FPL Verification System

General idea
Configuration technologies
Organization of hardware resources
Commercial aspects
Extensions of the basic idea
The FPL design flow
Field-Programmable Logic
Prof. Hubert Kaeslin
Microelectronics Design Center
ETH Z
urich
Morgan Kaufmann Top-Down Digital VLSI Design Chapter 2
last update: July 18, 2014
c Hubert Kaeslin Microelectronics Design Center ETH Z

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General idea
Commercial aspects
The FPL design flow
Content
You will learn
how field-programmable logic works and what variations are available.
I
Functioning and organization of field-programmable logic (FPL)

I
I
Configuration technologies (one-time vs. many-times programmable)

FPGAs vs. CPLDs architectures
Commercial aspects
I
I
Overview on FPL device families

The price of electrical configurability
Design flow for FPL devices
The benefits and limitations of FPL

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General idea
Commercial aspects
The FPL design flow
Introduction
The term programmable is a misnomer as there is no program,

no instruction sequence to execute.
As opposed to mask-programmed ICs, field-programmable logic (FPL)

uses neither custom layout structures, nor proprietary photomasks,
nor bespoke wafer processing steps to create the circuit to be.
Instead, pre-manufactured subcircuits get configured into the target

circuit via purely electrical means.
Sounds too good to be true. Think of how this might be achieved!

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General idea
Commercial aspects
The FPL design flow
General idea I: Hardware resources before configuration
(reprinted with permission from D. Strukov, K. Likharev: Reconfig. Nano-Crossbar

Architectures in Nanoelectronics and Information Technology, Wiley-VCH, 2012)
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General idea
Commercial aspects
The FPL design flow
General idea II: Target functionality

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General idea
Commercial aspects
The FPL design flow
General idea III: Circuit after configuration

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General idea
Commercial aspects
The FPL design flow
First understanding
Observation
Field-programmable devices are best understood as soft hardware.
As opposed to this, firmware must be viewed as hard software.

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General idea
Commercial aspects
The FPL design flow
A closer look
Key properties of any FPL device depend on choices along two dimensions.
What are the prefabricated hardware resources made available
to customers? 1
How can they be made to form a larger circuit?
Configuration technology
What are the programmable links?
How is the configuration stored?
How many times can it be changed?
Can this be done without removing the device from the board?
1 Customers
= designers who want to implement their own circuits in an FPL device.

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
Subject

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
Configuration technologies for field-programmable logic

have their roots in memories:
static memory cell
SRAM 7! a)
Flash memory 7! b)
PROM 7! Fuse c) and Antifuse d)
control gate
(used for programming only)
floating gate
(acting as charge trap)
metal
source
electronic
switch
metal
thin dielectric layer

(to be ruptured or not
during programming)
narrow constriction
(to be blown or not
during programming)
metal
drain
layout view
cross section
metal
base material
cross section
a)
b)
c)
d)
Figure: Electrical connections that can be done and undone by electrical means.
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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
a) SRAM-based FPL devices

I
Configuration data stored in static memory cells steer MOSFET switches.
Pros and cons:

+ Unlimited in-circuit reprogrammability
Huge overhead in terms of transistor count and area
Volatile (configuration gets lost whenever circuit is powered down)
The need to (re-)obtain the configuration from outside at power-up
is solved in one of three possible ways:
by reading from a dedicated o-chip ROM (bit-serial or bit-parallel),
by downloading a bit stream from a host computer, or
by long-term battery backup.

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
Operation principles of flash memory I

I
A floating gate is sandwiched between bulk material and a control gate.
The electrical charge trapped there governs MOSFET conductivity.
Programming
metal
metal
+
e e
Hot electron
injection
source
+
drain
a)
Programming occurs by way of hot electron injection from the channel.
A strong lateral field accelerates electrons to the point where
they get injected through the thin dielectric layer into the
floating gate. The necessary programming voltage on the order
of 5 to 20 V is generated by an on-chip charge pump.
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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
Operation principles of flash memory II

I
A floating gate is sandwiched between bulk material and a control gate.
The electrical charge trapped there governs MOSFET conductivity.
Erasure
Fowler-Nordheim
tunneling
metal
metal

e e
source
drain
b)
Erasure removes trapped electrons by having them tunnel through the
oxide layer underneath by way of Fowler-Nordheim tunneling
that occurs when a strong vertical field ( 8 ... 10 MV/cm)
is applied across the gate oxide.

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
b) Flash-based FPL devices

I
Electrical charges trapped on floating gates turn MOSFET switches

permanently on or o.
Pros and cons:

+ Non-volatile (no need to be configured following power-up)
+ Reconfigurable through package pins (no need for UV exposure)
+ Data retention times 10 to 40 years
Endurance 100 to 1000 configure-erase cycles (less than for flash memory)

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
d) Antifuse-based FPL devices

I
Thin dielectrics are selectively ruptured to establish conductive paths.
Pros and cons:

Programming is permanent
+ No need to be configured following power-up

New part required for each bug fix or design update
+ Higher layout densities than with reprogrammable links

(antifuses are only about the size of a contact or via)
+ Less sensitive to radiation
+ Superior protection against unauthorized cloning
1 Fuse-based
programming was a historical episode in FPL technology.

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General idea
Commercial aspects
The FPL design flow
Static memory
Flash memory
Antifuses
FPL configuration technologies compared
Configuration
technology
SRAM
Flash memory
Antifuse PROM
Ideal
Non
volatile
no
yes
yes
yes
Live at
power
up
no
yes
yes
yes
Reconfigurable
in circuit
in circuit
no
in circuit

urich
Unlimit.
endurance
yes
no
n.a.
yes
Area
occupation
per link
large
small
smallest
zero
Extra
fabr.
steps
0
>5
3
0
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General idea
Commercial aspects
The FPL design flow
Simple programmable logic devices (SPLD)

Field-programmable gate arrays (FPGA)
Subject

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General idea
Commercial aspects
The FPL design flow

Complex programmable logic devices (CPLD)

OR
plane
inputs
outputs
PLA
equivalent to
one SPLD
technological
evolution
AND
plane
programmable
logic
flip-flops & feedback
programmable
feedback
SPLD
programmable
interconnect
technological
evolution
OR
plane
inputs
b)
configurable
I/O cell
programmable
logic
OR
plane
AND
plane
flip-flops & feedback
a)
Overall organization has evolved from purely combinational devices.
AND
plane
outputs
c)
CPLD
Figure: General architecture of CPLDs (c) along with precursors (a,b).

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General idea
Commercial aspects
The FPL design flow


Overall organization patterned after mask-programmed gate-arrays.
configurable
I/O cell
config.
logic
cell
wires
conf.
wires switch
box
FPGA
Figure: General architecture of FPGAs.

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General idea
Commercial aspects
The FPL design flow

Fine-grained FPGAs
I
A few logic gates and/or one bistable per configurable logic cell.
Actel logic tile
subcircuits
controlled by
configuration bits
INP1
OUP1
to local routing
INP2
may serve
as clock
OUP2
to long routing
INP3
may serve
as reset
a)
Figure: Example: logic tile from Actel ProASIC.

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General idea
Commercial aspects
The FPL design flow

Xilinx slice
Coarse-grained FPGAs
YB
FXINA
FXINB
FX
YMUX
G4
G3
G2
Y
config.
LUT
SR
REV
ENA
CLK
G1
or
Combinational
functions of
four or more
variables.
Two or more
bits stored per
configurable
logic cell.
YQ
BY
XB
F5
XMUX
F4
F3
F2
X
config.
LUT
SR
REV
ENA
CLK
F1
or
D
XQ
BX
CE
CLK
SR
b)
CIN
Figure: Example: logic slice from Xilinx Virtex-4 (2 4-input LUTs, 2 bistables).
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General idea
Commercial aspects
The FPL design flow

There has been a trend towards even coarser granularities
Figure: LUT granularity trade-os at the 65 nm technology node.
The optimum trade-o for LUTs has shifted from 4 to 6 inputs

over the last couple of generations.
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General idea
Commercial aspects
The FPL design flow

Coarsegrained
FPGAs
2nd example:
logic slice
(slicel)
from Xilinx
Virtex-6

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General idea
Commercial aspects
The FPL design flow

Coarsegrained
FPGAs
3rd example:
adaptive logic
module (ALM)
from Altera
Stratix V

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General idea
Commercial aspects
The FPL design flow
An overview on FPL device families

The price and the benefits of electrical configurability
Subject
Commercial aspects

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General idea
Commercial aspects
The FPL design flow


Configuration
technology
Static
memory
(SRAM)
Flash
memory
Antifuse
(PROM)
Overall organization of hardware resources

CPLD
FPGA
coarse grained
fine grained
Xilinx Virtex, Kintex,
Atmel AT6000,
Artix, Spartan.
AT40K.
Lattice SC, EC, ECP.
Altera Stratix,
Arria, Cyclone.
eASIC Nextreme SL.
Achronix Speedster.
Xilinx XC9500,
Lattice XP
Actel ProASIC3,
CoolRunner-II.
MACH XO.
ProASIC3 nano,
Altera MAX.
Igloo,
Lattice MACH 1,...,5.
Fusion.
Cypress Delta39K,
Ultra37000,
PSoC 1,...,5LP.
QuickLogic Eclipse II,
Actel MX,
PolarPro.
Axcelerator AX.

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General idea
Commercial aspects
The FPL design flow

The benefits of electrical configurability
+ Agility. Being able to (re)define a parts functionality after fabrication

is extremely valuable in the marketplace.
+ Simpler design flow. Many issues that must be addressed in extenso
when designing a custom IC are implicitly solved in an FPL device.
+ Applications that mandated a custom ASIC a few years ago
fit into a single FPL device today, and this trend is to carry on.

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General idea
Commercial aspects
The FPL design flow

The price of electrical configurability I

To provide for configurability, FPL must accommodate extra
I
I
I
transistors, programmable links,

interconnect lines, vias,
lithographic masks, and wafer processing steps.
The required and the prefabricated hardware resources never quite match,
leaving part of the manufactured gates unused.
Field-programmable logic is unlikely to rival hardwired logic
on the grounds of integration density, unit costs and energy efficiency.
From comparisons of SRAM-based FPGAs against cell-based ASICs:
Overhead factors for
area
timing
power source
35
3.4...4.6
14
Kuon & Rose (2007, 90 nm CMOS)
27
5.1
n.a.
Ho et al. (2013, 130 nm CMOS)
Antifuse technology, hardwired multipliers, etc. improve the situation,
but a penalty remains.
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General idea
Commercial aspects
The FPL design flow

The price of electrical configurability II

I
Huge area overhead 7! large FPGAs continue to be rather expensive.
Figure: In an attempt to compensate for this, FPL vendors use the most advanced
fabrication processes (source: Altera White Paper WP-01199).
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General idea
Commercial aspects
The FPL design flow

FPL compared to semi- and full-custom ICs

production
volume
10M
full-custom
IC
towards highly
optimized implementation
(asks for commitment)
1M
fieldprogrammable
logic based on
two-level logic
(SPLD)
100k
10k
1k
semi-custom
IC
towards highly
agile implementation
(implies circuit and
energy overheads)
field-programmable
logic
(FPGA or CPLD)
technology
push
100
1
10
SSI
100
MSI
1k
LSI
10k
100k
VLSI
1M
10M
100M
1G
[GE]
circuit
size
ULSI
Figure: Implementation techniques as a function of circuit complexity and volume.

I
Each technique has its niche where it is the best compromise.

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General idea
Commercial aspects
The FPL design flow
Subject

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General idea
Commercial aspects
The FPL design flow
Providing only as much configurability as needed

Configurable logic cells are
+ designed to implement small LUTs and random logic functions,
extremely wasteful (in terms of area, delay and energy) when used
to implement
I
I
I
datapaths (that include multiplications and related arithmetic-logic

operations) on wide data words,
instruction-set processors (where the software aords flexibility), or
fixed functions (that do not ask for flexibility),
unsuitable for implementing analog subfunctions.

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General idea
Commercial aspects
The FPL design flow
Providing only as much configurability as needed

Configurable logic cells are
+ designed to implement small LUTs and random logic functions,
extremely wasteful (in terms of area, delay and energy) when used
to implement
I
I
I
datapaths (that include multiplications and related arithmetic-logic

operations) on wide data words,
instruction-set processors (where the software aords flexibility), or
fixed functions (that do not ask for flexibility),
unsuitable for implementing analog subfunctions.

Second stage of evolution
FPL gets combined with less malleable but more cost-eective
and more efficient hardware resources.
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General idea
Commercial aspects
The FPL design flow
Some FPGAs include wide datapath units (MAC)
Figure: Example: DSP48E1 slice from Xilinx Virtex-6

(25x18bit multiply, 48bit accumulate).
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General idea
Commercial aspects
The FPL design flow
Some real-world numbers

Vendor
Product
Year introduced
Technology
Configurable logic cells [k]
Block RAM [Mbit]
DSP48 slices
I/O pins
Serial transceivers
PCI Express blocks
100G Ethernet blocks
Mem. bandwidth [Mbit/s]
Xilinx
Virtex-7
Virtex Ultrascale
2013
2014
20 nm CMOS
16 nm CMOS
planar
finFET
1995
4407
68
115
3600
2880
1200
1456
96
104
4
6
0
7
1866
2400
Table: Maximum resources in two of the most advanced FPGA families.

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General idea
Commercial aspects
The FPL design flow
Almost all FPGAs mix-in hardwired units

Common subblocks SRAMs, FIFOs, clock recovery circuits, SerDes, etc.
Industry-standard functions and interfaces such as PCI, USB, FireWire,
Ethernet, WLAN, JTAG, LVDS, etc.
Analog-to-digital and digital-to-analog converters
Entire microprocessor and DSP cores (e.g. PowerPC, ARM)
Weakly configurable analog subfunctions such as filters or PLLs
Countless combinations are commercially available.

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General idea
Commercial aspects
The FPL design flow
Almost all FPGAs mix-in hardwired units

Common subblocks SRAMs, FIFOs, clock recovery circuits, SerDes, etc.
Industry-standard functions and interfaces such as PCI, USB, FireWire,
Ethernet, WLAN, JTAG, LVDS, etc.
Analog-to-digital and digital-to-analog converters
Entire microprocessor and DSP cores (e.g. PowerPC, ARM)
Weakly configurable analog subfunctions such as filters or PLLs
Countless combinations are commercially available.
And then there exist
Field-programmable analog arrays (FPAA) built from OpAmps, capacitors,
resistors and switchcap elements.

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General idea
Commercial aspects
The FPL design flow
Block diagram of Cypress mixed-signal PSoC 5LP device

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General idea
Commercial aspects
The FPL design flow
Capacity figures of FPL devices may be confusing ...

Manufactured gates Total number of GEs physically present on a die.
Usable gates Maximum number of GEs that are usable under typical or
best case conditions. The exact percentage depends on the
application, advertisements tend to exaggerate.
Actual gates GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanuf > GEusable > GEactual

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General idea
Commercial aspects
The FPL design flow
Capacity figures of FPL devices may be confusing ...

Manufactured gates Total number of GEs physically present on a die.
Usable gates Maximum number of GEs that are usable under typical or
best case conditions. The exact percentage depends on the
application, advertisements tend to exaggerate.
Actual gates GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanuf > GEusable > GEactual
4 Numbers frequently muddled up in an attempt to make one product look
better than competition.

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General idea
Commercial aspects
The FPL design flow
... and this is just the tip of the iceberg

Certainly one of the problems with FPGA technology is that youre
constantly comparing dierent things. Apples and oranges, Xilinx
CLBs and Altera ALMs, field-programmable elements and largely
hardwired datapath units, total negative slack and fastest clock,
dynamic power at 20 C and quiescent power at 85 C, prices today
for quantity 1000 and prices for 9 months from now at quantity
250 000. The list is almost endless, and useful comparison data is
virtually impossible to gather. (after Kevin Morris, 2005)
Hint
Carry out benchmarks with representative designs as this helps to
I
I
make better cost calculations,

obtain realistic timing figures,
avoid misguided choices.

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General idea
Commercial aspects
The FPL design flow
Subject
The FPL design flow

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General idea
Commercial aspects
The FPL design flow
FPL design flow

Front-end is essentially the same as for ASICs:
1. Architecture design.
2. HDL coding.
3. Functional verification (mostly by way of simulations).
4. HDL synthesis 7! Gate-level netlist.

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General idea
Commercial aspects
The FPL design flow
FPL design flow

Front-end is essentially the same as for ASICs:
1. Architecture design.
2. HDL coding.
3. Functional verification (mostly by way of simulations).
4. HDL synthesis 7! Gate-level netlist.
Back-end diers considerably.
5. Gate-level netlist is mapped onto the configurable cells
available in the target device.
6. Interconnect gets implemented using the wires,
switches and drivers available there.
7. Result is converted into a configuration bit stream
for download into the FPL device.
FPL vendors make available proprietary tools.
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General idea
Commercial aspects
The FPL design flow
Particularities of coarse-grained FPGAs

Look-up tables cheap and typically avail in chunks of 64 entries.
Routing dominates over gate delay due to conf. switches and larger die.
Routing resources limited.
+ Flip-flops come in generous numbers
pipelining is essentially free.
One-hot, Gray, or Johnson encoding sometimes better than min. bit count.
+ On-chip clock preparation circuits (nets, drivers, PLLs).
Asynchronous reset compete for global interconn. resources with clocks.

+ Sophisticated input/output circuits (adjustable, LVDS, synchronization).
+ On-chip block RAMs (depending on product).
+ Many parts include weakly configurable datapath units.
Datapaths, multipliers, adders, and memories come with fixed widths.
+ Available with on-chip microcontroller (depending on product).
Parts come in fixed sizes.
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General idea
Commercial aspects
The FPL design flow
FPL versus ASIC design
Advice
The cost matrix is not the same as for ASICs. Be aware of the realities
of the target platform before writing RTL synthesis code.

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General idea
Commercial aspects
The FPL design flow
FPL versus ASIC design
Advice
The cost matrix is not the same as for ASICs. Be aware of the realities
of the target platform before writing RTL synthesis code.
Hierarchy of required skill sets

Field-programmable logic Semi-custom ICs Full-custom ICs

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General idea
Commercial aspects
The FPL design flow
What keeps designers awake at night

FPL design
this volume
ASIC design
platform selection
limited and slow
routing resources
granularities
limited package options
and pinout constraints
mapping on target device
bit stream preparation
architecture design
clock domains
synchronization
process and library

selection
macrocell generation
HDL modeling
integration of
virtual components
functional verification
I/O subcircuits
HDL synthesis
floorplanning,
place and route
clock distribution
power distribution
electrical overstress
protection
testability
manufacturing and
testing partners
process migration
product-dependent
Figure: Primary concerns of FPL customers and full-custom ASIC designers.

The VLSI I course covers those topics that matter independently of fabrication depth,
VLSI II and III then specialize on ASIC design and VLSI technology.
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General idea
Commercial aspects
The FPL design flow
Pros and cons of field-programmable logic

+ Easy and extremely fast to modify (in minutes instead of months).
+ Designers can focus on functionality right away.
No need to agonize over subordinate details such as
I
I
I
I
I
I/O subcircuits,
clock distribution,
power distribution,
embedded memories,
testability, etc.
+ Low initial eort, lower than any other hardware alternative.

+ Aordable design tools.

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General idea
Commercial aspects
The FPL design flow
Pros and cons of field-programmable logic

+ Easy and extremely fast to modify (in minutes instead of months).
+ Designers can focus on functionality right away.
No need to agonize over subordinate details such as
I
I
I
I
I
I/O subcircuits,
clock distribution,
power distribution,
embedded memories,
testability, etc.
+ Low initial eort, lower than any other hardware alternative.

+ Aordable design tools.
Devices come in thousands of variations, may be confusing.
Huge overhead in terms of area, delay (performance), and energy.

Cost-eective for small volumes, not economic for large quantities.

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General idea
Commercial aspects
The FPL design flow
Conclusions
Field-programmable logic is ideal for
I
Prototyping and other
Situations where specs are subject to change at any time
Products that sell in modest quantities,
Products where time to market is paramount,
Products that need to be reconfigured or updated from remote.
Cost structure to be examined in chapter 16 VLSI Economics and Project Management.
Owing to their more scalable and flexible organization,

FPGAs prevail over CPLDs.

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General idea
Commercial aspects
The FPL design flow
Outlook
I
I
The trend towards (re)configuring larger, more powerful entities

(ALUs, datapath units, memories, etc. rather than gates and LUTs)
and towards mixing
I
I
I
reconfigurable logic with

processor cores and
fixed function blocks
is expected to continue.
This will naturally lead to the concept of platform ICs
as a next stage of evolution for FPL.
To be introduced in chapter 3 From Algorithm to Architectures.

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FPL Verification System

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General idea

Morgan Kaufmann Top-Down Digital VLSI Design Chapter 2

last update: July 18, 2014

c Hubert Kaeslin Microelectronics Design Center ETH Z

Functioning and organization of field-programmable logic (FPL)

Configuration technologies (one-time vs. many-times programmable)

Overview on FPL device families

Extensions of the basic idea

Design flow for FPL devices

The benefits and limitations of FPL

The term programmable is a misnomer as there is no program,

As opposed to mask-programmed ICs, field-programmable logic (FPL)

Instead, pre-manufactured subcircuits get configured into the target

Sounds too good to be true. Think of how this might be achieved!

c Hubert Kaeslin Microelectronics Design Center ETH Z

General idea I: Hardware resources before configuration

(reprinted with permission from D. Strukov, K. Likharev: Reconfig. Nano-Crossbar

General idea II: Target functionality

c Hubert Kaeslin Microelectronics Design Center ETH Z

General idea III: Circuit after configuration

c Hubert Kaeslin Microelectronics Design Center ETH Z

As opposed to this, firmware must be viewed as hard software.

= designers who want to implement their own circuits in an FPL device.

c Hubert Kaeslin Microelectronics Design Center ETH Z

c Hubert Kaeslin Microelectronics Design Center ETH Z

Configuration technologies for field-programmable logic

static memory cell

thin dielectric layer

a) SRAM-based FPL devices

Configuration data stored in static memory cells steer MOSFET switches.

Pros and cons:

c Hubert Kaeslin Microelectronics Design Center ETH Z

Operation principles of flash memory I

A floating gate is sandwiched between bulk material and a control gate.

The electrical charge trapped there governs MOSFET conductivity.

Operation principles of flash memory II

A floating gate is sandwiched between bulk material and a control gate.

The electrical charge trapped there governs MOSFET conductivity.

c Hubert Kaeslin Microelectronics Design Center ETH Z

b) Flash-based FPL devices

Electrical charges trapped on floating gates turn MOSFET switches

Pros and cons:

c Hubert Kaeslin Microelectronics Design Center ETH Z

d) Antifuse-based FPL devices

Thin dielectrics are selectively ruptured to establish conductive paths.

Pros and cons:

+ No need to be configured following power-up

+ Higher layout densities than with reprogrammable links

programming was a historical episode in FPL technology.

c Hubert Kaeslin Microelectronics Design Center ETH Z

FPL configuration technologies compared

c Hubert Kaeslin Microelectronics Design Center ETH Z

Simple programmable logic devices (SPLD)

Organization of hardware resources

c Hubert Kaeslin Microelectronics Design Center ETH Z

Simple programmable logic devices (SPLD)

Complex programmable logic devices (CPLD)

flip-flops & feedback

flip-flops & feedback

Overall organization has evolved from purely combinational devices.

Figure: General architecture of CPLDs (c) along with precursors (a,b).

Simple programmable logic devices (SPLD)

Field-programmable gate arrays (FPGA)