Inf3430 Xilinx Timing Constraints

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Design Entry
Synthesis
Constraints
Implementation
Constraints
Synthesis
Simulation
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Place & Route
Floor-Planning
Delay Simulation
Timing Analysis
Silicon
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Fundamental Timing Constraints
V9_2_2_0
What Needs Constraining?
Internal clock speed for one or more clocks

I/O speed
Logic using multi-cycle clocks
Pad to Pad timing
Pad Locations & Logic Locations
Clk & CE Speed
I/O Speed
X
I/O Speed
OUT1
CLK
Y
Logic
Locations
Z<0:9>
Pin
Locations
1 Level of Logic
2 Levels of Logic
OUT2
Pin
Locations
Pin 2 Pin Speed

29
Most Common Timing Constraints
PERIOD
Constrain all paths, sync element to sync element
OFFSET
Constrain I/O paths, ie. pad to sync element, sync element to pad
(these are not covered by PERIOD constraints)
FROM-TO
Specify Slow/Fast paths and Multi-Cycle paths
FROM-THRU-TO
Constrain specific path thru logic between sync elements
TIG (Timing Ignore)
Remove slow or static paths from Timing Analysis
30
Timing Constraint Precedence
Within a particular source

Highest Priority
TIG (Timing Ignores)

FROM-THRU-TO specs
FROM-TO specs
OFFSET specs
Lowest Priority
PERIOD specs
32
Constraint Entry Methods
Constraint Editor
Preferred method
Tools manage constraint syntax
Text Editor
User must manage syntax
PACE
Physical constraints only
33
Xilinx Constraints Editor (Old style)
IO Timing
Clock
Timing
PAD to PAD
Timing
Generated UCF
Constraints:
PERIOD,
OFFSET,
PAD TO PAD
34
New Constraints editor GUI (9.2 ->)
35
PERIOD Constraint
FLOP1
ADATA
D Q
FLOP2
FLOP3
D Q
D Q
OUT1
CLKA
BUFG
BUS [7..0]
CLKB
CDATA
FLOP4
D Q
FLOP5
D Q
OUT2
= Unconstrained Data Path

G
= Constrained Data Path

Period = 10 ns
HIGH = 45%
LOW = 55%
PERIOD accounts for data path delay

PERIOD accounts for duty cycle in this case 45/55
PERIOD accounts for first clock edge in this case HIGH
PERIOD is specified with the clock period
PERIOD accounts for clock skew on global and local clocks
PERIOD accounts for clock phase including DCM phase and negative edge clocking
UCF Example:
NET CLKA" TNM_NET = CLKA_Group";

TIMESPEC "TS_CLKA_Group_Spec " = PERIOD CLKA_Group" 10 ns HIGH 45%;
36
Basic Period Report

Slack equation
Clock
names
and time
of active
edge.
Includes
Clock
Phase
Web link to
graphical
picture of
delay type!
(In Timing
Analyzer)
BasicUpdated!
element
type is listed
Logic Levels
Only levels of logic, not
Clock to Out and Setup
Data path with
Cross Probing
Links to
Floorplanner or
Synthesis Tool
(In Timing
Analyzer)
37
OFFSET IN Constraint
The OFFSET IN constraint covers paths from the input pads to

synchronous elements taking clock delay into account
The OFFSET IN constraint does NOT optimize paths clocked by
internally generated clocks (including DCMs)
OFFSET IN only covers PAD to registered element data paths
OFFSET IN does not constrain the delay or skew of clock path itself
FLOP1
ADATA
D Q
FLOP2
FLOP3
D Q
D Q
OUT1
CLKA
BUFG
BUS [7..0]
CLKB
CDATA
FLOP4
D Q
FLOP5
D Q
OUT2

BUFG
44
OFFSET IN Constraint
OFFSET IN is used to constrain input data paths

OFFSET IN clock is specified to the clock PAD
OFFSET IN clock can not be an internal clock DCM output
OFFSET IN only covers PAD to registered element data paths
OFFSET IN does not constrain the delay or skew of clock path itself
45
OFFSET IN BEFORE Constraint

FPGA
External
Data
TData
TSU / TH
External
Clock
OFFSET IN BEFORE
REG
CLK
External
Clock
TClk
External
Data
Valid Data
VALID
OFFSET IN BEFORE Is time data is VALID prior to capture clock

VALID Duration is time data remains VALID data eye width
VALID is required for hold time analysis and error reporting
Without explicit VALID, implied VALID = OFFSET
In this example, implied VALID is not correct
Without VALID, hold time can be reported with TRCE fastpaths
-fastpaths reports delays only and does not check for hold errors
46
OFFSET IN Report Example
Slack equation
Clock
name
and time
of active
edge
Data Path Delay
Clock Path Delay
47
System Synchronous Interface
Source Device
TSU/ TH
TCKO
D
REG
CLK
FPGA
TDataTrace
TData
TData
REG
CLK
DCM
TSrcClk
TDestClk
System Clock
One common system clock for both source and destination

Board level skew and data path delays limits performance
Typically Single Data Rate (SDR) applications
49
System Synchronous Inputs

Transmit
Edge
Capture
Edge
PERIOD = 10 ns
SysClk
OFFSET IN BEFORE = 9 ns
DataIn
Valid Data
VALID = 8 ns
This example shows Data Valid Window less than PERIOD

Start of data is 9 ns before the capture clock edge
Data remains VALID for 8 ns
OFFSET IN 9 ns VALID 8 ns BEFORE SysClk;
50
System Synchronous Data Sheet
51
OFFSET OUT Constraint
The OFFSET OUT constraint covers paths from synchronous

elements to output pads taking clock delay into account
The OFFSET OUT constraint does NOT optimize paths clocked by

internally generated clocks
FLOP1
ADATA
D Q
FLOP2
FLOP3
D Q
D Q
OUT1
CLKA
BUFG
BUS [7..0]
CLKB
CDATA
FLOP4
D Q
FLOP5
D Q
OUT2

BUFG
56
OFFSET OUT Constraint
Defines maximum time in which data can leave the chip

Used for destination device setup time verification
OFFSET OUT clock is specified to the clock PAD
OFFSET OUT clock can not be an internal clock
Best used for system synchronous interfaces
OFFSET = OUT 10 ns AFTER "SYS_Clk";
57
OFFSET OUT Report
Slack equation
Clock
name
and time
of active
edge
Clock Path Delay
Data Path Delay
60
Constraining Specific Delays
A FROM-TO constraint defines the delay between two groups of logic

Logic paths typically start and stop at pads, registers, latches, RAM,
multipliers, CPUs and high speed IOs (MGT)
It is used to constrain the following types of paths (more details later):
Multi-cycle paths --If not expected to meeting the original single
cycle clock period
Data paths between unrelated clocks
False Paths --If paths/net that are known not to have a timing
requirement
No HOLD violation check is done for FROM:TO paths
62
Basic FROM-TO Examples
A FROM-TO constraint defines the delay between two groups of logic

Logic paths typically start and stop at pads, registers, latches, RAM, multipliers,
CPUs and high speed IOs (MGT/GTP)
UCF TIMESPEC command using default keywords
TIMESPEC
TIMESPEC
TIMESPEC
TIMESPEC
TS_C2S=FROM FFS TO FFS 30;

TS_P2S=FROM PADS TO FFS 25;
TS_P2P=FROM PADS TO PADS 26;
TS_C2P=FROM FFS TO PADS 9;
TS_P2S
TS_C2S
TS_C2P
D
OUT1
CLK
OUT2
TS_P2P
63
FROM:TO Report
Slack equation
Requirement is < twice

TS_clk (40ns)
Data Path Delay
64
PAD to PAD Constraint
Purely combinatorial delay paths start and end at I/O pads

and are often left unconstrained by users
Placing a FROM:TO constraint on pads-to-pads is necessary
if there is a timing requirement
TIMESPEC TS_P2P = FROM PADS TO PADS 15 ns;
FLOP1
ADATA
D Q
FLOP2
FLOP3
D Q
D Q
OUT1
CLKA
BUFG
BUS [7..0]
CLKB
CDATA
FLOP4
D Q
FLOP5
D Q
OUT2

BUFG
65
PAD to PAD Report
Slack equation
Source and Destination

elements are PADS
Data Path Delay
66
Pre-Defined Groups
Timing constraints are applied to logic paths

Logic paths typically start and stop at pads, and synchronous elements
The tool recognizes the following keywords to define endpoints or time groups:
PADS
All I/O pads
FFS
All flip-flops
LATCHES
All latches
RAMS
All RAM elements
BRAMS_PORTA
All Port A Dual Block RAM elements
BRAMS_PORTB
All Port B Dual Block RAM elements
HSIOS
All High Speed I/O elements (RocketI/O)
CPUS
All PowerPC elements
MULTS
All Multiplier elements
DSPS
All DSP48 and derivatives (DSP48A, DSP48E)
Keywords can be used globally, and to create design sub-groups
71
Using TNM_NET to create Groups on Nets
NET clock TNM_NET=clk_group;

TNM_NET is equivalent to TNM on a net except for pad nets.
If you place a TNM on a pad net, it will trace backwards to the pad and not
trace forward through the buffer to the next synchronous element.
TNM_NET was created for this purpose.
If you place a TNM_NET on a pad net, it will trace through the buffer to the
next synchronous element.
TNM_NET is extremely useful for synthesis designs. The ports are directly
connected to pads.
TNM_NET can be used in UCF or NCF only.
74
Auto-Related DCM Paths
PERIOD constraint applied to CLKIN

CLK2X Period automatically defined as related to CLK1X
Cross-clock paths are automatically analyzed
FROM-TO constraints are not required !

95
ISE Tool Flow Review
Design Entry
Synthesis
Constraints
Implementation
Constraints
Synthesis
Simulation
Translate
Map
Place & Route
Floor-Planning
Delay Simulation
Timing Analysis
Silicon
133
Source Code Changes to Improve Timing
Pipeline
Reduce combinatorial delays
Register block outputs
Register duplications
In general, source code changes have greater effect in

improving performance than software switches
134
Timing-Driven MAP
MAP -timing (Use Timing-Driven Packing and Placement
Algorithm)
MAP runs normally, then examines timing
If timing is not met, MAP tries to re-pack and place critical logic in order to
meet constraints
Runtime for MAP increases but this should be offset by a reduction in the
PAR runtime
Greatest benefit is seen in high density designs with unrelated logic packing
Typical performance improvement of 5 percent is achievable

Maximum performance improvement of 30 percent is possible
135
Timing-Driven MAP Options
Other options used with -timing option

Set -ol overall effort level {std | med | high}
Extra effort -xe {n | c}
Register duplication: -register_duplication
Allows MAP to duplicate registers to improve timing
Starting placer cost table: -t {1-100}
136
Timing-Driven MAP Options GUI

Right click Implement Design and pick Properties
Pick Map
Properties
Pick
Advanced
137
Timing-Driven MAP Options GUI

Enable advanced placement options
Check Timing
Driven
Packing and
Placement
Advanced
Options enabled
Set High to
enable Extra
Effort
138
Timing Constraints
In order to enable timing optimization you must set

Optimization Goal to Speed in XST synthesis
options
205

Inf3430 Xilinx Timing Constraints

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Inf3430 Xilinx Timing Constraints

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The essence of FPGA technology

Avnet SpeedWay Design Workshop

ISE Tool Flow Overview

Avnet SpeedWay Design Workshop

Support Across The Board

What Needs Constraining?

Internal clock speed for one or more clocks

Clk & CE Speed

Pin 2 Pin Speed

Most Common Timing Constraints

Avnet SpeedWay Design Workshop

Timing Constraint Precedence

Within a particular source

TIG (Timing Ignores)

Avnet SpeedWay Design Workshop

Constraint Entry Methods

Avnet SpeedWay Design Workshop

Xilinx Constraints Editor (Old style)

Avnet SpeedWay Design Workshop

New Constraints editor GUI (9.2 ->)

Avnet SpeedWay Design Workshop

= Unconstrained Data Path

= Constrained Data Path

PERIOD accounts for data path delay

NET CLKA" TNM_NET = CLKA_Group";

Basic Period Report

The OFFSET IN constraint covers paths from the input pads to

= Unconstrained Data Path

= Constrained Data Path

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OFFSET IN is used to constrain input data paths

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OFFSET IN BEFORE Constraint

OFFSET IN BEFORE Is time data is VALID prior to capture clock

OFFSET IN Report Example

Data Path Delay

Clock Path Delay

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System Synchronous Interface

One common system clock for both source and destination

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System Synchronous Inputs

This example shows Data Valid Window less than PERIOD

System Synchronous Data Sheet

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OFFSET OUT Constraint

The OFFSET OUT constraint covers paths from synchronous

The OFFSET OUT constraint does NOT optimize paths clocked by

= Unconstrained Data Path

= Constrained Data Path

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OFFSET OUT Constraint

Defines maximum time in which data can leave the chip

OFFSET OUT Report

Clock Path Delay

Data Path Delay

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Constraining Specific Delays

A FROM-TO constraint defines the delay between two groups of logic

Avnet SpeedWay Design Workshop

Basic FROM-TO Examples

A FROM-TO constraint defines the delay between two groups of logic

UCF TIMESPEC command using default keywords

TS_C2S=FROM FFS TO FFS 30;