Assignment Sheet

Gokaraju Rangaraju Institute of Engineering and Technology
(Autonomous)
Bachupally, Kukatpally, Hyderabad 500 090, A.P., India. (040) 6686 4440
ASSIGNMENT SHEET 1
Academic Year
: 2012
Semester
Date:.
Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

Course/Subject: Integrated Circuit Applications..
Name of the Faculty: R. Anil Kumar..Dept.:EEE.
Designation
: ASST.PROFESSOR
This Assignment corresponds to Unit No. / Lesson 1.

Q1. For an op-Amp, PSRR=70dB(min), CMRR=105, differential mode gain Ad=105, The output voltage
changes by 20v in 4seconds. Calculate
i. Numerical value of PSRR
ii. CMRR
iii. Slew rate.
Q2. (a) What is a level translator circuit? Why it is used with the Cascaded Differential amplifier?
(b) What is a cascode amplifier? List the characteristics of Cascode amplifier.
Q3. Explain the various techniques used to compensate for thermal drift in Op-Amps.
Q4. Calculate
(i)
Maximum output offset voltage caused by the input offset voltage Vios.
(ii)
Maximum output offset voltage caused by the input bias current IB, for an inverting amplifier
with R1=100K and Rf =10K. Here 741 Op-amp is used with Vios=6mV and IB=500nA.
Q5. Draw and explain the practical circuit for offset voltage measurement of Op-Amps.
Objective Nos.: 1,2 and 3.
Outcome Nos.: 1 and 3.
Signature of HOD
Signature of faculty
Date:
Date:

(Autonomous)
ASSIGNMENT SHEET 2
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1. In the circuit of figure shown below, R1=100, Rf =4.7K CMRR=90 db. If the amplitude of the
induced 60-Hz noise at the output is 5mv (rms), calculate the amplitude of the common-mode input
voltage Vcm:
Q2. (a) Explain the current limiting feature of 723 regulator.

(b) If a 741 IC is configured as an I-to-V converter, what is the lowest value of current that may be
measured.
Q3. For the strain gauge bridge circuit as shown in figure below, given that V ab=
Assume that
under the strained conditions the resistances RT1and RT3 decreases and that of RT2 and RT4 increases by the
same amount
. Also RT1= RT2 = RT3 = RT4 = R, under unstrained conditions.
Q4. Calculate
(i)
Maximum output offset voltage caused by the input offset voltage Vios.
(ii)
Maximum output offset voltage caused by the input bias current IB, for an inverting amplifier
with R1=100K and Rf =10K. Here 741 Op-amp is used with Vios=6mV and IB=500nA.
5Q. For the integrator circuit as shown in below figure, the input is a sine wave with a peak-to-peak
amplitude of 5V at 1kHz. Draw the output voltage waveform if R 1CF= 0.1ms and RF=10R1. Assume that the
voltage across CF if initially zero.

Outcome Nos.: 1,2 and 3.
Signature of HOD
Date:
Date:

(Autonomous)
ASSIGNMENT SHEET 3
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1. A certain narrow band-pass filter has been designed to meet the following specifications: fC=2kHz,
Q=20, and Ap=10. What modifications are necessary in the filter circuit to change the center
frequency `fc ' to 1kHz , keeping the gain and band-width constant?
Q2. (a)Define the conditions on the feedback circuit of an amplifier to convert it into an oscillator?
(b) Design a 60Hz Active Low Pass Filer (LPF)
Q3. Design a second order IGMF band pass filter with the following specifications: f o=500Hz, gain at
resonance=-5 and band width=50Hz. Use the circuit shown in figure below, assume necessary data
Q4. Consider the circuit shown next

(a) Calculate the output voltages of the circuit.
(b) Explain the effect of C' on stability of the OP-Amp connection.
Q5. F or a second order butter worth filter given C2 = C3 = 0:047F ;

R2 = R3 = 3.3k; R1 = 27k; and RF = 15.8k
4
(a) Determine the lower cutoff frequency fL of the filter.

(b) Draw the frequency response plot of the above filter.
Signature of HOD
Date:
Date:

(Autonomous)
5
ASSIGNMENT SHEET 4
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1.(a) Explain the importance of 555 timer in designing a monostable multivibrator
(b) If RA = 6.8 k, RB= 3.3 k, c = 0.1F in 555 astable multivibrator, Calculate:
i. thigh
ii. tlow
iii. Free running frequency
iv. Duty cycle.
Q2. Design a monostable multivibrator using 555 timer to produce a pulse width of 100msec.
Q3. (a) Write about voltage controlled frequency shifter using 555 timer.
(b) For the frequency shifter, calculate:
i. The charge current I for input E = 0V
ii. The centre frequency when E = 0V
iii. The frequency shift fout for E = 1V.
Q4. What are passive loop filters in PLL consider the PLL shown in below figure
Q5.(a) Explain the terms Lock range, Capture range and Pull-in time of a PLL. How are Lock ranges and
Capture range determined?
(b) Draw the internal circuit diagram and pin diagram (DIP) of 566 VCO. Explain its operation and
derive expression for output frequency fo.
6
Signature of HOD
Date:
Date:

(Autonomous)
ASSIGNMENT SHEET 5
Academic Year
: 2012
Semester
Date:.
Name of the Program: B.Tech Electrical Year: III..... Section: A/B/C

Designation
: ASST.PROFESSOR

Q1. (a) What are the advantages of R-2R adder type D/A converter over weighted resister type?
(b) In an inverted R-2R ladder, R=Rf=22kohms and VR=12V. Calculate the total current delivered to
the op-amp and the output voltage when the binary input is 1110.
Q2. (a) Write short notes on multiplying DACs?
(b) List the specifications of a DAC IC 1408.
Q3. (a) What are the sources of analog errors in an ADC?
(b) What is meant by differential linearity an ADC?
Q4. Design a 4 - bit weighted resistor DAC whose full-scale output voltage is 10volts. Assume R f = 10 k
and logic `1' level as +5 volts and also logic `0' level as 0 volts. What is the output voltage when the input
is 1011?
Q5. Give the schematic circuit of an A/D converter widely used in digital volt-meters and explain its
operation. Derive expression for output voltage.
Signature of HOD
Date:
Date:

(Autonomous)
ASSIGNMENT SHEET 6
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1. Explain the features of the TTL logic family.
Q2.(a) Draw the CMOS circuit diagram of tri-state buffer. Explain the circuit with the help of logic
diagram and function table.
(b) Design a CMOS transistor circuit that realizes the following Boolean function.
: Also explain its functional operations.
Q3. Compare the various Logic Families.
Q4. Explain the following terms:
(a) VOL(max)
(b) VOH(min)
(c) VIL(max)
(d) VIH(min)
Q5.(a) Draw the circuits of NAND and NOR gates using CMOS logic and explain their operation with
truth tables.
(b) Compare the performance of various logic families with reference to power dissipating,
propagation delay, Fan-in and Fan-out
Outcome Nos.: 1 and 2.
Signature of HOD
Date:
Date:

(Autonomous)
ASSIGNMENT SHEET 7
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1. (a) What is the need for a parity checker?
(b) Design an odd parity generator for an 8 bit binary word.
Q2. (a) Design a digital comparator for 2-bit numbers?
(b) With the help of logic diagram explain 74X157 multiplexer.
Q3. With the help of logic circuits explain a Multiplexer and a Demultiplexer also give their circuit
symbols and give their applications?
Q4. (a) Using two 74X138 decoders design a 4 to 16 decoder.
(b) Realize the following expression using 74X151 IC
Q5.(a) Give the logic diagram of 74X139? Explain with the help of truth table? Using this device design a
3 to 8 decoder and provide the truth table?
(b) Design a 16-bit comparator using 74X85 ICs.
Outcome Nos.: 1, 2 and 3.
Signature of HOD
Date:
Date:
10

(Autonomous)
ASSIGNMENT SHEET 8
Academic Year
: 2012
Semester
Date:.

Designation
: ASST.PROFESSOR

Q1. (a) Design a 3-bit LFSR counter using 74X194? List out the sequence assuming that the initial state is
10.
(b) Design a Modulo-12 ripple counter using 74X74.
Q2. (a) Draw the D-flip flop and T-flip flop and explain the operation with truth table.
(b) Draw the J-K flip flop and explain its operation with truth table.
Q3. With the help of logic circuits explain a Multiplexer and a Demultiplexer also give their circuit
symbols and give their applications?
Q4. (a) With neat circuit diagram explain a master-slave Flip-flop and also draw the timing diagram
(b) Explain about asynchronous Flip Flops.
Q5. Implement the following functions using a multiplexer.
(a) F (A,B,C) =m(1,3,5,6)
(b) F (A,B,C) =m(0,1,3,4,8,9,15)
Outcome Nos.: 1, 2 and 3.
Signature of HOD
Date:
Date:
11

Assignment Sheet

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Assignment Sheet

Загружено:

Авторское право:

Доступные форматы

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 1.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 2.

Q2. (a) Explain the current limiting feature of 723 regulator.

Objective Nos.: 1,2 and 3.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 3.

Q4. Consider the circuit shown next

Q5. F or a second order butter worth filter given C2 = C3 = 0:047F ;

(a) Determine the lower cutoff frequency fL of the filter.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 4.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III..... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 5.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 6.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 7.

Gokaraju Rangaraju Institute of Engineering and Technology

Name of the Program: B.Tech Electrical Year: III...... Section: A/B/C

This Assignment corresponds to Unit No. / Lesson 8.

Вам также может понравиться