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AL

RN

MIC
R

TECHNICAL FEATURE

AVE JOU
OW

OR

ED

IT

REVIEWED

IAL B O

EFFECTIVE CIRCUIT DESIGN


TECHNIQUES TO INCREASE
MOSFET POWER
AMPLIFIER EFFICIENCY

Fig. 1 Ideal class


F voltage and
current waveforms.

Vds

Eds

Ids

Is

TIME (t)

ewly developed low cost and highly


linear, high gain and high power laterally diffused metal oxide semi-conductor (LDMOS) and vertically diffused metal oxide semiconductor (VDMOS) field-effect
transistors are attractive devices for many applications including commercial FM broadcasting and TV power transmitters, cellular
and paging communication systems, and military RF and microwave hand-held transceivers. In all cases, along with high quality
transmission of radio signals resulting from
the high linearity of the amplifier transfer
characteristic, it is necessary to provide high
reliability and low overall dimensions of the
power amplifiers along with an increase in total operating efficiency.
To obtain high efficiency of the power amplifier, it is advisable to use a tuned class B or Class
F operating mode. 1,2 In such
amplifiers, the fundamental and
harmonic load impedances are
optimized by short-circuit terminations and open-circuit peaking
in order to control the voltage
and current waveforms at the
drain of the device to obtain
maximum efficiency.
CLASS F OPERATION
The impedance conditions at
the drain of the device for 100

percent idealized drain efficiency must be1


Z1 = R 1 =

8 Eds
,
Is

Zn = 0 for even n,
Zn = for odd n,

(1)

where
Eds = drain supply voltage
Is = peak drain current
n = harmonic component
These impedance conditions correspond to
the class F operating condition, the ideal voltage
and current shapes for which are shown in Figure 1. Here a sum of odd harmonics produces a
square voltage waveform and a sum of even harmonics approximates a half-sinusoidal current
shape. In reality, both extrinsic and intrinsic transistor parasitic elements have a substantial effect
on the efficiency, especially at high frequencies.
By using only the active device die it is possible
to reduce the influence of the parasitic elements
in the power amplifier module. However, in this
case it is necessary to take into account the main
influence of the device output capacitance Cout.

ANDREY V. GREBENNIKOV
Institute of Microelectronics
Singapore

Reprinted with permission of MICROWAVE JOURNAL from the July 2000 issue.

2000 Horizon House Publications, Inc.

TECHNICAL FEATURE

( )

Im Yout = j Cout j

1 2L 2C 2

L 1 1 2L 2C 2 + L 2

(2)

Applying the previously mentioned three harmonic impedance conditions, open-circuited for the fundamental
and third harmonic and short-circuited for the second
harmonic, equation (2) can be rewritten in the form

)(

2
2
1 2L C
0 1 out 1 0 L 2 C 2 0 L 2 Cout = 0,

L 1 1 4 02L 2C 2 + L 2 = 0,

1 9 02L 1Cout 1 9 02L 2C 2 9 02L 2Cout = 0

)(

(3)

12.8 nH, C2 = 5.3


0
pF) with a quality
factor Q of 20 for
10
the inductances at
the fundamental
20
frequency f = 0.5
GHz, and a device
30
output resistance
Rout of 200 and
40
0
0.5
1.0
1.5
2.0
2.5
output capacitance
FREQUENCY (GHz)
C out of 2.2 pF is
shown in Figure Fig. 4 The lumped impedance peaking
4. To increase the circuits frequency response.
total efficiency of Fig. 5 The microstrip amplifiers output
the amplifier, the impedance peaking circuit.
element of the outEds
put matching cirCbypass
cuit adjacent to the
drain of the transistor must be se1
2
ries and inductive

2
in order to provide
a high impedance
TO OUTPUT
Rout
Cout
MATCHING
for odd harmonic
CIRCUIT
components.1
To
increase
maximum drain efficiency up to 88.4 Fig. 6 The microstrip impedance forming
percent, it is nec- circuits frequency response.
essary to provide a
0
short-circuit termination for all even10
harmonic voltages
and an open-cir20
cuit impedance for
third-harmonic
30
currents.3 Class F
40
operation mode is
0
0.5
1.0
1.5
2.0
2.5
easy to realize by
FREQUENCY (GHz)
using transmission
lines in the output circuit. For a microstrip amplifier, it is
enough to provide transmission lines with electrical
lengths at the fundamental frequency of
S21 (dB)

Cbypass

S21 (dB)

The ideal class


F amplifier with a
voltage secondharmonic shortcircuit termination
L2
and current thirdC2
harmonic peaking
allows realization
of the maximum
L1
drain efficiency of
75 percent.3 For a
lumped-circuit
TO OUTPUT
Rout
Cout
amplifier, in order
Yout
MATCHING
CIRCUIT
to approximate
ideal class F oper Fig. 2 An output impedance
ation with the harpeaking circuit.
monic impedance
conditions of Z1 =
Fig. 3 The two-port passive circuits
Z3 = and Z2 =
schematic for simulation.
0 at the drain by
d
d
compensating for
IMPEDANCE
the influence of
INPUT
OUTPUT
PEAKING
Cout it is advisable
CIRCUIT
to use an additional parallel circuit.
An equivalent output impedance peaking circuit for a
lumped-circuit amplifier is shown in Figure 2. The reactive part of the output admittance of this circuit is given
by
Eds

1 =

where
0 = 2 f0
f0 = fundamental frequency

1
6 02Cout

, L2 =

(5)

where

As a result, the elements of the output impedance


peaking circuit are
L1 =

1
1

, 2 = tan 1
, 3 =
2
3
6
3Z0 0Cout

5
12
L1, C2 =
Cout
3
5

(4)

Linear analysis, which is sufficient to compute the response of a two-port passive circuit with lumped or distributed parameters, has been accomplished using the Serenade 7.5 CAD simulator. Simulations were performed according to the schematic shown in Figure 3 regarding the
drain of the device. The frequency-response characteristic
of a lumped impedance-peaking circuit (L1 = 7.7 nH, L2 =

Z0 = characteristic impedance of the microstrip line


The equivalent output impedance peaking circuit of
microstrip amplifier is shown in Figure 5. The frequencyresponse characteristic of the microstrip impedance-forming circuit on a substrate with dielectric loss tangent tan
= 0.0001 featuring a device output resistance Rout of 50
and an output capacitance Cout of 2.2 pF, with a characteristic impedance of the microstrip lines Z0 of 50 and
electrical length 2 of 15 is shown in Figure 6. It follows
from the data that if the short-circuited conditions for all
even voltage harmonics and current third-harmonic peaking are in place, then additional output matching is required at the fundamental frequency f0 = 0.5 GHz taking

TECHNICAL FEATURE
24 V
+
13.7 0.029 pF

100 pF

9.1

56.9 pH

0.73 pF

4.5 nH
10 pF

500

3.6 nH

0.31 pF

0.28 pF

0.87

2 pF

0.26 pF

Rds = 4.37 k

25 nH

15 nH

3.5 pF
Pout

1.0 pH

22

80

20

60

18

40

16

20

14

0
10.0

20.0
15.0
Pin (dBm)

EFFICIENCY (%)

100

100

22

80

20

60

18

40

16

20

14

0
10.0

12
25.0

Fig. 9 Drain efficiency and gain


vs. input power.

20.0
15.0
Pin (dBm)

12
25.0

Fig. 11 Drain efficiency and gain


vs. input power when the inductances
have a Q of 30.

Fig. 10 The drain voltage waveform


approximation.

60

Vds (V)

60
40

40
20

20
0
0

2
TIME (ns)

circuits based on microstrip lines. In


a simulated 500 MHz one-stage microstrip power amplifier, the input
and output matching circuits are Tsection matching circuits, and each of
them consists of a series microstrip
line, parallel open-circuit stub and series capacitance. To provide even harmonic termination and third-harmonic peaking for class F operation, an
RF short-circuited quarter-wave microstrip line and combination of series microstrip line and open-circuit
stub of /12 electrical length for third
harmonic termination are used. Such
an output circuit configuration closely matches the square drain voltage
waveform, as shown in Figure 12
and a high value of drain efficiency
up to 80 percent with maximum output power Pout = 9 W is obtained, as

2
TIME (ns)

Fig. 12 The microstrip amplifiers drain


voltage waveform.
Fig. 13 The microstrip amplifiers drain
efficiency and gain vs. input power.
EFFICIENCY (%)

AMPLIFIER NONLINEAR CAD


SIMULATION
The small-signal equivalent circuit
of a high-power LDMOS FET cell
with channel length L = 1.25 m and
channel width W = 1.44 mm is shown
in Figure 7. The device model parameters were extracted from pulsed IV and S-parameter measurements.
The parameters of the equivalent circuit are given at a bias voltage for
class AB operation with quiescent
current Iq = 15 mA at Eds = 28 V.
The equivalent circuit of the simulated 500 MHz one-stage lumped
power amplifier is shown in Figure
8. The total channel width of the
high-voltage LDMOS FET is 7
1.44 mm. The drain efficiency and
gain of the amplifier versus input
power Pin for the case of ideal circuit
inductances are shown in Figure 9.
The obtained value of the drain efficiency of more than 80 percent is the
result of additional harmonic peaking
on higher components which allows a
shortened switching time from the
pinch-off region to the saturation region by better approximation of the
drain voltage square waveform, as
shown in Figure 10. However, the
amplifier drain efficiency as well as
the gain can reduce significantly in
the case of sufficiently small values of
a circuit inductance Q. For example,
the maximum drain efficiency is only
71 percent when an inductance Q of
30 at the fundamental frequency is
used, as shown in Figure 11.
Therefore, for high output power
level, it is preferable to use matching

EFFICIENCY (%)

into account the reactance introduced by the impedance peaking


circuit.

1.1 pF

Fig. 8 The simulated 500 MHz one-stage lumped power


amplifiers equivalent circuit.

The LDMOS FETs small-signal equivalent circuit.

Vds (V)

Fig. 7

GAIN (dB)

6 pF

Pin

GAIN (dB)

1.2
= 14.1 ps
gm = 21.1mS

1.5 k
300

100

22

80

20

60

18

40

16

20

14

0
10.0

20.0
15.0
Pin (dBm)

GAIN (dB)

58.7 pH

12
25.0

shown in Figure 13. The power amplifiers equivalent circuit is shown in


Figure 14.
However, a further increase of the
total LDMOS FET channel width
leads to an increase of Cout and, as a
result, to a decrease in electrical
length of the series microstrip line

EFFICIENCY (%)

28 V
+

2 pF

30
54

500

100 pF

30
65

30
58

50
63

Fig. 14

9 pF

50
46

30
54

500

Vds (V)

2 pF

100 pF

30
58

50
63

50
46

mum value. On the other hand, when


the transistor is turned off, the drain
current continues to flow, but now
only through the shunt output capacitance Cout. The appropriate required
reactive harmonic load impedance of
the external circuit is realized by the
open-circuit stub at the second harmonic whose electrical length is approximately 0.125 and by the RF
short-circuit microstrip line whose
3.6 V

18 k

6 pF

10 15 20
Pin (dBm)

12
25 30

60

40

20

0
2
1

2
TIME (ns)

9 pF

Fig. 15 The equivalent circuit of the simulated 500 MHz one-stage microstrip high-power
amplifier using an LDMOS FET with a channel width of 28 1.44 mm.
adjacent to the drain, the value of
which becomes too small to provide
appropriate third harmonic peaking.
In this case, in order to realize both
high efficiency and high power operation, the output circuit must be simplified to only a T-section for impedance matching. The equivalent circuit of the simulated 500 MHz
one-stage microstrip high-power amplifier with a total LDMOS FET
channel width W = 28 1.44 mm is
shown in Figure 15. As it turned out,
a significant improvement of drain efficiency up to 78 percent for an output power of approximately 30 W can
be realized by using the specific electrical length (less than quarter-wave
length) of parallel microstrip line, as
shown in Figure 16. Furthermore,
the analysis of the drain voltage and
current waveforms, shown in Figure
17, demonstrates that the operating
mode obtained is close to class E operation mode.5 As seen in the data,
when the transistor is turned on,
there is practically no voltage when
the drain current achieves its maxi-

14

20
0

30
65

Pout
Pin

16

20

Fig. 16 Drain efficiency and gain


vs. input power for the T-section impedance.

28 V

1.5 k

18

40

Fig. 17 Drain voltage and current waveforms


using the T-section impedance matching
configuration.

The simulated 500 MHz one-stage microstrip power amplifiers schematic.

300

20

60

0
0

Pout
Pin

22

80

Ids (A)

300

1.5 k

100

GAIN (dB)

TECHNICAL FEATURE

50
35

0.1 F

1 k

impedance is sufficiently small at the


third harmonic. At the same time this
output circuit configuration accomplishes effective fundamental impedance matching of the output transistor impedance with the load.
EXPERIMENTAL RESULTS
The experimental test structure of
a single-stage LDMOS FET power
amplifier with a device gate length of
L = 1.25 m and total gate width of
W = 4 cm is shown in Figure 18.
Two T-section transformers with series microstrip lines and parallel variable capacitors have been used as the
input and output matching circuits.
The matching circuits were fabricat28 V

0.1 F

+
50
45

10 F

50
35

9 pF

Pin
Pout
8.5 TO 40 pF

Fig. 18

4.5 TO 20 pF

The single-stage LDMOS FET power amplifiers experimental test structure.

100

22

80

20

60

18

40

16

20

14

0
0

10 15 20
Pin (dBm)

GAIN (dB)

EFFICIENCY (%)

TECHNICAL FEATURE

12
25 30

Fig. 19 Measured drain efficiency


and gain vs. power input.
ed on epoxy glass copper-clad laminate substrates and the characteristic
impedance of all microstrip lines is
equal to 50 . To avoid low-frequency parasitic oscillations, a 10 F electrolytic capacitor was connected in
parallel with the drain supply. The
parameters of the matching circuit elements and the length of the microstrip line in the drain supply circuit were chosen according to the results of the CAD simulation for a
high-efficiency operating mode of the
power amplifier. Only small fine tuning of the variable capacitors in the

input and output matching circuits


was required to realize excellent electrical characteristics of the given LDMOS FET power amplifier.
The drain efficiency and power
gain characteristics as a function of input power are shown in Figure 19.
An output power of 20 W max with a
drain efficiency of 76 percent and DC
collector current of 0.94 A has been
achieved. A practically constant smallsignal power gain of approximately 17
dB was achieved over a wide dynamic
range up to an input power of 25 dBm
as a result of the appropriate choice of
gate bias voltage.
ACKNOWLEDGEMENT
The author would like to thank
Fujiang Lin for on-wafer measurements and device modeling as well as
for helpful discussions and support.
The Serenade 7.5 simulator is a product of Ansoft Corp., Pittsburgh, PA.
References
1. D.M. Snider, A Theoretical Analysis and
Experimental Confirmation of the Optimally Loaded and Overdriven RF Power

2.
3.

4.

5.

Amplifier, IEEE Trans. Electron Devices,


Vol. 14, December 1967, pp. 851857.
H.L. Krauss, C.W. Bostian and F.H. Raab,
Solid State Radio Engineering, New York:
Wiley, 1980.
F.H. Raab, Class-F Power Amplifiers with
Maximally Flat Waveforms, IEEE Transactions on Microwave Theory and Techniques, Vol. 45, November 1997,
pp. 20072012.
C. Duvanaud, S. Dietsche, G. Pataut and J.
Obregon, High-efficient Class F GaAs
FET Amplifiers Operating with Very Low
Bias Voltages for Use in Mobile Telephones at 1.75 GHz, IEEE Microwave
and Guided Wave Letters, Vol. 3, August
1993, pp. 268270.
T.B. Mader, E.W. Bryerton, M. Markovic,
M. Forman and Z. Popovic, Switchedmode High-efficiency Microwave Power
Amplifiers in a Free-space Power-combiner Array, IEEE Transactions on Microwave Theory and Techniques, Vol. 46,
October 1998, pp. 13911398.

Andrey V. Grebennikov received his Dipl Ing


degree from Moscow Technical University of
Communication and Informatics in 1980 and
1991, respectively. In 1983, he joined the
scientific research department of Moscow
Technical University of Communication and
Informatics as a research assistant. Since
October 1998, he has been working with the
Institute of Microelectronics, Singapore.
Grebennikov can be reached via e-mail at
andrei@ime.org.sg.