2014 - 1

-- LIBRARIES COMMONLY USED

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- =========================================================================
-- * * ENTITY DECLARATION * *
-- * * ARCHITECTURE DECLARATION * *
ENTITY <entity_name> IS
GENERIC(<generic_name>: <type>
<other generics> ... ;
<generic_name> : <type>
PORT ( <port_name>
: <mode>
<other ports> ... ;
<port_name>
: <mode>
);
END <entity_name>;

ARCHITECTURE <architecture_name> OF <entity_name> IS

-- declarative items:
-component declarations
:= default_value );
-constant declarations
<type>;
-signal declarations
-etc.
<type>
BEGIN
-- architecture body
END <architecture_name>;
:= default_value;

-- ---------------------------------------------------------------------------------------------------- COMPONENT DECLARATION

-- CONSTANT DECLARATION
COMPONENT <component_name>
CONSTANT <name>: <type> := constant_value;
GENERIC(<generic_name>: <type>:= default_value;
<other generics> ... ;
<generic_name> : <type>:= default_value );
PORT ( <port_name>
: <mode> <type>;
-- SIGNAL DECLARATION
<other ports>
... ;
SIGNAL <name>: <type>;
<port_name>
: <mode> <type>
SIGNAL <name>: <type>:= initial_value;
);
END COMPONENT;

-- =========================== ARCHITECTURE BODY =============================

-- SIGNAL ASSIGNMENT

-- SELECT / WHEN STATEMENT

<signal_name> <= <expression>;

WITH <choice_expression> SELECT

<signal_name> <= <expression> WHEN <choices>,
<expression> WHEN <choices>,
<expression> WHEN OTHERS;

-- COMPONENT INSTANTIATION
<instance_label>: <component_name>
GENERIC MAP(<generic_name>
=> <value>,
<other generics>
... ,
<generic_name>
=> <value>
)
PORT MAP( <comp_port_name> => <signal_name>,
<other comp_ports>
... ,
<comp_port_name> => <signal_name>
);

-- WHEN / ELSE STATEMENT

<signal_name> <= <expression> WHEN <condition> ELSE
<expression> WHEN <condition> ELSE
<expression>;

-- ---------------------------------------------------------------------------------------------------- IF STATEMENT
-- PROCESS STATEMENT
IF <condition> THEN
PROCESS (<sensibility list>)
<statements>;
BEGIN
ELSIF (condition) THEN
<statements>;
<statements>;
END PROCESS;
ELSE
<statements>;
*** statements :
END
IF;
signal assignment,
if statement,
-- CASE STATEMENT
case statement.
CASE (<choice_expression>) is
WHEN <choices> => <statements>;
-- SIGNAL ASSIGNMENT
<signal_name> <= <expression>;

WHEN <choices> => <statements>;

WHEN OTHERS
END CASE;

=> <statements>;

2014 - 1

-- ========================== FINITE STATE MACHINE ============================

-- This is a sample state-machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY <entity_name>
PORT( clock, reset
<inputs >
<outputs>
);
END <entity_name>;

IS
: in std_logic;
: in <type>;
: out <type>;

ARCHITECTURE FSM OF <entity_name> IS

-- Insert the following in the architecture BEFORE the begin keyword
-- Use descriptive names for the states, like st1_reset, st2_search
TYPE estados IS (default_state, <name_state>, <name_state>, ...);
SIGNAL presente : estados := default_state;
SIGNAL futuro
: estados;
BEGIN
-- Insert the following in the architecture AFTER the begin keyword
NEXT_STATE_DECODE: process (presente, <input_name>)
begin -- statements to decode next_state
CASE (presente) IS
WHEN <default_state> => if <input_name> = '1' then
futuro <= <name_state>;
else
futuro <= <name_state>;
end if;
WHEN <name_state> =>

WHEN <name_state> =>

if <input_name> = '0' then

futuro <= <name_state>;
else
futuro <= <name_state>;
end if;
futuro <= <name_state>;

WHEN OTHERS
=>
futuro <= <name_state>;
END CASE;
end process NEXT_STATE_DECODE;

SYNC_PROC: process (clock)

begin -- statements to decode outputs
if rising_edge(clock) then
if (reset = '1') then
presente <= <default_state>;
else
presente <= futuro;
end if;
end if;
end process SYNC_PROC;
OUTPUT_DECODE: process (presente)
begin
CASE (presente) IS
WHEN <default_state> => <outputs><= <value>;
WHEN <name_state>
=> <outputs><= <value>;
WHEN OTHERS
=> <outputs><= <value>;
END CASE;
end process OUTPUT _DECODE;
END FSM;

-- ===========================================================================
-------

The following operators can be used on two single bits to

produce a single bit output or on two equivalents sized
bused signals where the operations are performed on each
bit of the bus.
In the case of the Invert, only one signal or bus is
provided and the operation occurs on each bit of the signal

NOT
AND
OR
XOR
XNOR

------

Invert a
AND two
OR
two
XOR two
XNOR two

single-bit signal or each bit in a bus

single bits or each bit between two buses
single bits or each bit between two buses
single bits or each bit between two buses
single bits or each bit between two buses

-- The following logical operators are used

-- in conditional TRUE/FALSE statements in
-- order to specify the condition for the
-- operation.
NOT -- Not True
AND -- Both Inputs True
OR -- Either Input True
=
-- Inputs Equal
/= -- Inputs Not Equal
<
-- Less-than
<= -- Less-than or Equal
>
-- Greater-than
>= -- Greater-than or Equal