Microelectronic Design: LAB4

CMOS Inverter Layout

I Introduction:
A vital part of any IC design is the physical layout of the circuit components as this can have
significant impacts on the performance of the circuit. Good physical design depends on merging an
understanding of the processes involved in IC fabrication with those of electrical design.
This laboratory introduces the back-end or physical design aspects of a CAD system and examines
processes such as design-rule checking (DRC), layout extraction and layout versus schematic checking
(LVS). As an example, the student is expected to initially layout NMOS and PMOS transistors
separately before combining these cells to realise a CMOS inverter.

II Colour and Layer Key:

Red=polysilicon
Green=active
Blue=metal1
Light grey=N-select
Dark grey=N-well
Pink=P-select
III nMOS Layout: Procedure:
1.

The layout program within the Tanner suite is called L-Edit. This serves as a layout editor,
DRC checker and circuit extraction tool. The most important first step is to set up the
technology file which details the layers used by a particular fabrication process (e.g. Orbit
2.0um CMOS). This is done from the File>Replace Setup command which should load:
C:\Tanner\LEdit85\Samples\tech\mosis\morbn20.tdb

2.

The next step is to save the blank layout with any given name in your home account. All
layout is governed by a set of design rules which are particular to a given process. To get
access to a text-file version of this, use the ALT-W command.

3.

Create a layout of a NMOS transistor with a gate length of 2um and a width of 5um. The first
layer to be defined in the active area of the MOSFET, whose width will be defined as 5um.
The minimum length will depend on the active contact design rules.

4.

Next the polysilicon (poly) gate is defined with a length of 2um. This must overhang the
active area on both ends.

5.

Active contacts are defined which will contact the drain and source regions. These connect to
the metal1 (M1) layer, which is the lowest metal layer. Finally metal1 pads are drawn as
squares to define the drain and source connections.

6.

Although the active region is now defined, it is still necessary to define the MOS as either ntype or p-type. This is done by surrounding the active region with an N-select layer since:
ndiff=(ACTIVE) AND (NSELECT).

7.

In order to complete the NMOS layout, it is still necessary to define the substrate or bulk
connection. This is defined by drawing a minimum sized p+ region close to the transistor and
can be seen below connected to the source of the MOSFET.

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8.

Note that it is necessary to use an active region definition to ensure that the substrate region
remains free from the field oxide layer, which would not permit the implantation of p+-ions.

9.

Run a DRC check to ensure that the layout is free from design rule violations.

10. Within the layout file, define this device as a cell with a suitable name such as
NMOS_5u2u. This can be achieved using the Close As command from the Cell menu. In
this way the cell can be instanced in larger layouts.

IV pMOS Layout: Procedure:

1.

Define a new cell with a name such as PMOS_9u2u. Create a layout of a PMOS having a
width of 9um and a length of 2um using the same techniques as those used for the NMOS.

2.

Rather than using a NSELECT layer, the p-type transistor requires a PSELECT layer instead.
Remember also that a PMOS device requires a surrounding n-type well.

3.

Finally, an n+ substrate contact to the n-well is added and connected to the PMOS source as
shown below.

4.

Run a DRC check to ensure that the layout is free from design rule violations.

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V CMOS Inverter Layout: Procedure:

1.

Instance the NMOS and PMOS cells developed above into a new cell (named Inverter).
Wire up the circuit using polysilcon and metal interconnects as shown below.

2.

Insert ports with suitable names as shown to indicate to the layout tool where the equivalent
electrical ports are defined.

3.

Run a DRC check to ensure that the layout is free from design rule violations.

VI CMOS Inverter Extraction: Procedure:

1.

While the inverter cell is open, select Tools>Extract and select the extraction definition file as:
C:\Tanner\LEdit85\Samples\tech\mosis\morbn20.ext

2.

Select a suitable name for the SPICE netlist file such as Inverter.spc and click Run. The
extracted netlist can be examined using any text editor.

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3.

To extract the circuit complete with its parasitic components, open the Extraction dialog box
again and tick Write Node Capacitances. Select another SPICE netlist file name such as
Inverter_parasitics.spc and rerun the extraction. Upon examination, this file will reveal
several parasitic capacitances in addition to the inverters MOS devices.

VII CMOS Inverter Layout Versus Schematic (LVS) Check: Procedure:

1.

Using S-Edit create a netlist from the inverter module designed in Lab3. Exit S-Edit and
launch the LVS program.

2.

Create a new LVS Setup and input both the Layout netlist which has been created from the
layout extraction (without parasitics) and the Schematic netlist which refers to that created
in step 1.

3.

On the Output tab of the setup dialog box, define a file to write the output file, which should
be included in the practical report. Once the LVS is run, the verification window will
determine whether the layout correctly matches the desired electrical circuit. This process is
often known as analog verification.

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