NTUEE IC Design

Tutorial of HW3
Hung-Chi Kuo
Advisor: Tzi-Dar Chiueh
2015/11/27

Version 1 : Chun-Hao Liu

Version 2 : Xin-Yu Shih
Version 3 : Yi Chen
Version 4 : Hung-Chi Kuo

Outline
Introduction to Verilog
Module
Value & Number
Data Type

Simulation : NC-Verilog and nWave

Flow Chart
4bits>>>4circuits

Paper Works
Truth
Table

K-map: Design
each bit of
output

Draw a gatelevel circuit

diagram

lib.v

Verilog code:
build circuit

Test:
testbench
ncverilog

lib.v

Truth
Table

K-map: Design
each bit of
output

Draw a gatelevel circuit

diagram

Verilog code:
build circuit

Introduction to Verilog
Module
Value & Number
Data Type

Test:
testbench
ncverilog

Top-Down Design Flow

Front-End

C/C++/Matlab

NC-Verilog

Design Vision
(DV)

NC-Verilog

Astro/
SE

Back-End

Cadence

HSPICE/Nanosim

What is Verilog ?
Verilog is a Hardware Description Language
Describe digital electronic system at multiple
levels of abstraction
Model the timing
Express the concurrency of the system operation
Test the system

Levels of Abstraction
System
concept

Algorithm
Increasing
behavioral
abstraction

Behavior Level

Increasing
detailed
realization &
complexity

Register Transfer Level

Gate Level

Transistor Level
7

Levels of Abstraction in Verilog

Behavioral

High

Structural and procedural like the C programming

language, ex. ifelse, case.

Register Transfer Level (RTL)

Describe the flow of data between registers and how
a design process these data.

Structural (Gate Level)

Describe gate-level and switch-level circuits.
Low
8

Verilog Syntax
Create an Verilog file *.v
Edit with text editors such as WordPad or Notepad++

Comments: //(single row) or /* */(multiple row)

Case sensitive
; at the end of each row
module ADDER (out, in1, in2); //need ;
output [2:0] out;
input [1:0] in1, in2;
wire c;
FA1 fa0 (c, out[0], in1[0], in2[0], 1b0);
FA1 fa1 (out[2], out[1], in1[1], in2[1], c);
endmodule //doesnt need ;

Verilog Module
Basic building blocks .
Begin with module, end with endmodule
module <module name> (<port lists>);
//module description
endmodule

module ADDER (out, in1, in2);

endmodule
10

Module Ports
Modules communicate through ports
Input port
Output port
module FD2 (Q, D, CLK, RESET);
output
input

Q;
D, CLK, RESET;

endmodule

11

4-Value Logic System

0
zero, false, low

1
one, true, high

Z
high impedance, floating

X
unknown, occurs at un-initialized storage elements or
un-resolvable logic conflicts

12

Value and Number

<size><radix><value>
Size
The size in bits
Default size is 32 bits

Radix
b (binary), o (octal), d (decimal), h (hexadecimal)
Default radix is decimal

Value
Any legal number in selected radix
13

Value and Number Examples

4b1001
5D31
12h7ff
7

// 4-bit binary
// 5-bit decimal
// 12-bit hexadecimal
// 32-bit decimal

underline usage
16b0001_0101_0001_1111
32h12ab_f001

14

Data Type : Wire

wire

wire [MSB:LSB] variables;

Need to be declared before calling
Input, output are default to be wire
Default as one bit

output [2:0] out; //3 bits: out[2], out[1], out[0]

input [1:0] in; //2 bits: in[1], in[0]
wire [3:0] c; //4 bits: c[3], c[2], c[1], c[0]
wire d; //1 bit
assign c = 4d10; //c=4b1010, c[3]=1, c[2]=0, c[1]=1, c[0]=0
15

Wire Assignment
assign , output port
wire a;
wire b;
assign b = 1b0;
NOT n0(a, b);

Every wire can be only assigned once!!!

wire a;
wire b;
assign b = 1b0;
NOT n0(a, b);
assign a = 1b0; //Wrong!!!
16

Module Instances (1/2)

Create a higher-level system by connecting
lower-level components

Module Instances (2/2)

18

Net Concatenations
Representation
{b[3:0],c[2:0]}

Meaning
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}

{a,b[3:0],w,3b101} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1}

{4{w}}

{w,w,w,w}

{b,{3{a,b}}}

{b,a,b,a,b,a,b}

Ex.
wire [1:0] a;
wire [1:0] b;
wire [5:0] c;
assign c = {2{a[1]}, a, b}; // c = {a[1],a[1],a[1],a[0],b[1],b[0]}
19

Call by Order vs Call by Name

module FD2 (Q, D, CLK, RESET);
output
input

Q;
D, CLK, RESET;

Call by Order
Call by Name

20

Example : Adder
module ADDER (out, in1, in2);
output [2:0] out;
input [1:0] in1, in2;
wire c;

FA1 fa0 (c, out[0], in1[0], in2[0], 1b0);

FA1 fa1 (out[2], out[1], in1[1], in2[1], c);
endmodule
21

IC
Des

Standard Cell Library (lib.v)

Choose what you need
Compose your circuit according to I/O
connections
module AN3(Z,A,B,C);
output Z;
input A,B,C;

// netlist
and g1(Z,A,B,C);
// specify block, declare local
// timing constant
specify

// delay parameters
specparam Tp_A_Z = 0.275;
specparam Tp_B_Z = 0.275;
specparam Tp_C_Z = 0.275;
// path delay (full connection)
( A *> Z ) = ( Tp_A_Z );
( B *> Z ) = ( Tp_B_Z );
( C *> Z ) = ( Tp_C_Z );
endspecify
endmodule
22

Standard Cell Library (lib.v)

IV
AN3
AN4
AN2
EN
EN3
EO
EO3
FA1
FD1
FD2

// not
//and

// xnor
// xor
// full adder
// DFF

ND2
ND3
ND4
NR2
NR3
OR2
OR3
OR4
HA1
MUX21H

// nand

// nor
// or

// half adder
// 2-to-1 MUX
23

IC
Des

Notification of HW3!!
In this HW, all the logic operation MUST consist
of standard cell (defined in lib.v). You can NOT
use logic operators(&,|,^,~) or arithmetic
operators(+,-,*,/) or behavioral statement(if, else).

24

IC
Des

Notification of HW3!!
Do NOT change any module name and port name
in ADC_EADC.v, just modifiy the module
description, otherwise you cant pass testbench.

Dont Change

25

lib.v

Truth
Table

K-map: Design
each bit of
output

Draw a gatelevel circuit

diagram

Verilog code:
build circuit

Test:
testbench
ncverilog

NC-Verilog Simulation and nWave

Test and Verify Your Circuit

By applying input patterns and observing
output responses
Testbench: tb_*.v
in.dat

*.v

Test
patterns

*.vcd / out.dat

Output
response

Device Under Test (DUT)

27

Testbench
Put input into circuit you design in ADC_EADC.v
Check if the output is the same as golden output

28

NC-Verilog Simulation
Put all files in the same directory on Workstation
ADC_EADC.v, tb_ADC.v, tb_EADC.v, lib.v, in.dat, out.dat

Source files before simulation:

run.f

source /usr/cadence/cshrc
source /usr/spring_soft/CIC/verdi.cshrc

Test ADC
ncverilog tb_ADC.v ADC_EADC.v lib.v +access+r

Test EADC
ncverilog tb_EADC.v ADC_EADC.v lib.v +access+r
29

NC-Verilog Simulation Results

Pass all test pattern

Errors

30

nWave: Source File and Execute

Source
source /usr/spring_soft/CIC/verdi.cshrc

Execute nWave
nWave &

31

Select Output File ADC/EADC.vcd

(2)

*.vcd

(3)

Cancel the filter

(1)
(4)

32

Select Desired Signal

33

Reminder
If theres any workstation account/password
problem, please directly contact workstation
administrator
- d01943010@ntu.edu.tw

If you have any questions, please contact TA

EE2-232r04943027@ntu.edu.tw

34

Thanks for your attention!

Q&A