Chapter 5

Arithmetic Functions and

Circuits
J.J. Shann

Arithmetic ckt:

a combinational ckt that performs arithmetic ops w/ binary

numbers or w/ decimal numbers in a binary code

E.g.: addition, subtraction, multiplication, and division

Develop arithmetic ckts by means of hierarchical,

iterative design

J.J. Shann 5-2

Chapter Overview
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9

Iterative Combinational Circuits

Binary Adders
Binary Subtraction
Binary Adder-Subtractors
Binary Multiplication
Other Arithmetic Functions
HDL Representations VHDL ()
HDL Representations Verilog ()
Chapter Summary
J.J. Shann 5-3

Recall: Design Procedure of a

Combinational Circuit (3-3)

Design procedure of a combinational ckt:

1. Specification:

Write a specification for the ckt.

2. Formulation:

Derive the truth table or initial Boolean eqs that define the
required relationships b/t inputs and outputs.

3. Optimization:

Apply two-level and multiple-level optimization.

Draw a logic diagram or provide a netlist for the resulting ckt
using ANDs, ORs, and inverters.

4. Technology Mapping:

Transform the logic diagram or netlist to a new diagram or

netlist using the available implementation technology.

5. Verification:

Verify the correctness of the final design.

J.J. Shann 5-4

5-1 Iterative Combinational Circuits

Arithmetic block:
is typically designed to operate on
binary input vectors and produce
binary output vectors.
The function implemented often
requires that the same subfunction
be applied to each bit position.
A function block can be designed
for the subfunction and then used
repetitively for each bit positions
of the overall arithmetic block.

An-1 Bn-1

cell

A0 B0

Cn-1

cell
C0

cell: a subfunction block

the overall implementation is an

array of cell
iterative array

C
J.J. Shann 5-5

Iterative array

Iterative array:

a special case of hierarchical ckts

is useful in handling vectors of bits
has the repetitive nature of the ckt & the association of a
vector index w/ each of the ckt cells.
The cell in the array are often, but not always, identical.
E.g.: Block diagram of an iterative ckt

J.J. Shann 5-6

5-2 Binary Adders

Half adder: add 2 bits

Full adder: add 2 input bits and a carry-in bit
Binary ripple carry adder: add two n-bit binary
numbers
Carry-lookahead adder

J.J. Shann 5-7

A. Half Adder

Half adder (HA): adds 2 bits

<Design Procedure>
Step 1: Specification
The basic rule for binary addition:
0+0=
0
0+1=
1
X
Half Adder
Y
1+0=
1
1+1= 1 0
Input variables: 2; augend and addend bits; X, Y
Output variables: 2; sum and carry bits; S, C

S
C

J.J. Shann 5-8

Step2: Formulation
Truth
table

Step 3: Optimization
S = xy + xy = x y
C = xy

Step 4: Technology mapping

J.J. Shann 5-9

B. Full Adder

Full adder (FA): add 3 bits

<Design Procedure>
Step 1
Input variables: 3; 2 significant bits X, Y & a carry-in bit Z
Output variables: 2; sum and carry bits S, C

Step 2
X
Y
Z

S
Full Adder

J.J. Shann 5-10

Step3

Step 4

J.J. Shann 5-11

C. Binary Ripple Carry Adder

Parallel adder:

a digital ckt that produces the arithmetic sum of 2 binary

numbers using only combinational logic
uses n full adders in parallel, w/ all input bits applied
simultaneously to produce the sum
Design method: hierarchical, iterative design

J.J. Shann 5-12

Binary addition:

E.g.: 1011 + 0011

Truth table:
9 inputs; 2 4-bit numbers & a carry-in bit
512 entries (impractical)
J.J. Shann 5-13

Implementation of binary ripple carry adder:

The FAs are connected in cascade, w/ the carry output

from one FA connected to the carry input of the next FA.
E.g.: 4-bit adder

* Hierarchy &
Iterative design

Si = Ai Bi Ci
Ci+1 = Ai Bi + Ci(Ai Bi)
J.J. Shann 5-14

Carry Propagation

Propagation time of a combinational ckt:

(the propagation delay of a typical gate) (the # of gate
levels in the ckt)

Propagation time of the binary adder:

the time it takes the carry to propagate through the full

adders: 2n + 2 gate delays, n: # of bits of the input numbers

Assumption: delay of XOR gate = 2

J.J. Shann 5-15

B2 A2

B3 A3

B1 A1

B0 A0 C0

critical
path
C4

S3

C3

S2

C2

S1

C1

S0

J.J. Shann 5-16

Full adder (FA)

J.J. Shann 5-17

Methods of Speeding Addition

Method 1:

employ faster gates w/ reduced delays

Method 2:

increase the equipment complexity to reduce the carry

delay time
most widely used technique: carry lookahead

J.J. Shann 5-18

D. Carry Lookahead Adder

Ripple carry adder (RCA):

simple
has a long ckt delay in the carry path from LSB to MSB

Carry lookahead adder (CLA):

reduce delay at the price of more complex hardware

J.J. Shann 5-19

Carry Lookahead

Full adder:

Carry lookahead:

RCA

Define 2 new binary variables:

Pi = Ai Bi carry propagate function
propagate the carry from Ci to C i+1
Gi = Ai Bi
carry generate function
produce an output carry regardless of the input carry
Si = Pi Ci
Ci+1 = Gi + PiCi
J.J. Shann 5-20

RCA

Ci+1 = Gi + PiCi , C0 = input carry

C1 = G0 + P0C0
C2 = G1 + P1C1
= G1 + P1(G0 + P0C0)
= G1 + P1G0 + P1P0C0

Pi = Ai Bi
Gi = Ai Bi

C3 = G2 + P2C2
= G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 =
= G?3 + P3C3
= G3+P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

J.J. Shann 5-21

E.g.: 3-bit carry lookahead generator

C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

P2 = A2 B2
G2 = A2 B2
P1 = A1 B1
G1 = A1 B1
P0 = A0 B0
G0 = A0 B0

J.J. Shann 5-22

E.g.: 4-bit adder

Ripple carry

Carry lookahead
* Propagation delay = 6
2
Ai 2 Pi 2

Ci S i
Bi
Gi
J.J. Shann 5-23

Pi = Ai Bi
Gi = Ai Bi

C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

Si = Pi Ci
(2-level)

* Propagation delay = 6

J.J. Shann 5-24

CLA Expansion

Use the same method: single level CLA

Ci+1 = Gi + PiCi , C0 = input carry

C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = ?

max fan-in = 5

excessive fan-in

Multi-level CLA
J.J. Shann 5-25

Multi-Level CLA

4-bit groups:

Purpose: reuse the carry lookahead ckt for each group of 4

bits and for 4 4-bit groups as if they were individual bits.
produce the carries in positions 4, 8, and 12 as fast as
possible w/o using excessive fan-in.

C4 = G3+P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

Group propagation function:

propagate a carry from C0 to C4

P03 = P3 P2 P1 P0

C4 = G0-3 + P0-3C0

Group generate function:

G03 = G3 + P3G2 + P3 P2G1 + P3 P2 P1G0

J.J. Shann 5-26

4-bit CLA
w/ group
functions:

C4
S3

S2

S1

S0

Group
functions
J.J. Shann 5-27

For 4-bit group:

C4 = G0-3 + P0-3C0
C8 = G4-7 + P4-7C4
= G4-7 + P4-7G0-3 + P4-7P0-3C0
C12 = G8-11 + P8-11G4-7 + P8-11P4-7G0-3
+ P8-11P4-7P0-3C0
C16 = ?

J.J. Shann 5-28

16-bit CLA: 5 carry lookahead ckts, 2-level

B7~4

B3~0

B15~12 A15~12

B11~8 A11~8

4-bit CLA

4-bit CLA

4-bit CLA

4-bit CLA

Carry lookahead ckt

Carry lookahead ckt

Carry lookahead ckt

Carry lookahead ckt

G15-12

C16, S15~12

P15-12

G11-8

S11~8
C12

A7~4

G7-4

S7~4

P11-8

C8

A3~0
C0

G3-0

S3~0

P7-4

P3-0

C4

Carry lookahead ckt

G15-0 P15-0
J.J. Shann 5-29

Propagation delay:
2
2
Ai 2 Pi 2 P(4j+3)-4j 2

C4k Ci Si
Bi
Gi
G(4j+3)-4j

J.J. Shann 5-30

Delays:

Assumption: XOR = 2 gate delays

Ripple
carry
adder
(RCA)
Carry
lookahead
adder
(CLA)

4-bit adder

16-bit adder

64-bit adder

10

34

130

(2n + 2, n: # of bits of input numbers)

10
(5 copies in
2 levels of
lookahead)
(4 + 1)

14
(21 copies in
3 levels of
lookahead)
(16 + 4 +J.J.1)Shann 5-31

5-3 Binary Subtraction

(for Unsigned Numbers)

Unsigned number subtraction:

Method 1: (1-3)

Compare the subtrahend w/ the minuend and subtract the smaller

from the larger.
Disadv.: The comparison op results in inefficient and costly ckt.

Method 2: by 2s complement subtract (B.)

Method 3: by 2s complement addition (C.)

J.J. Shann 5-32

A. Complement

Two types of complements for each base-r system:

radix complement: rs complement

e.g.: 2s complement for binary numbers

10s complement for decimal numbers

diminished radix complement: (r 1)s complement

e.g.: 1s complement for binary numbers

9s complement for decimal numbers

J.J. Shann 5-33

1s Complement

1s complement of an n-bit binary number N:

(2n 1) N
11 1
(n 1s)

subtracting each digit from 1

changing all 1s to 0s and all 0s to 1s
(applying the NOT op to each of the bits)

E.g.s:

1011001
1s comp
0100110

0001111
1s comp
1110000

E.g.: the 9s complement of a decimal number is obtained

by subtracting each digit from 9
J.J. Shann 5-34

2s Complement

2s complement of an n-bit binary number N:

2n N for N 0 &
(2n 1) N
0
for N = 0
adding 1 to the 1s complement of N
leaving all least significant 0s and the 1st 1 unchanged
and then replacing 1s w/ 0s and 0s w/ 1s in all other
higher significant bits

E.g.s:

1101100
2s comp
0010100

The complement of the complement restores the number to its original

value.
J.J. Shann 5-35

B. Unsigned Binary Subtraction by 2s

Complement Subtract

Unsigned number subtraction by 2s complement

subtract :
Subtract the subtrahend from the minuend directly: M N
If no end borrow occurs : M N
the result (M N) is positive and correct
If an end borrow occurs: M < N
the result (M N + 2n) must then be negative and
the magnitude needs to be corrected by 2s complement
2n (M N + 2n ) = N M
[2n (M N + 2n )] = (N M)
Subtract a binary number from 2n
J.J. Shann 5-36

E.g.:

end borrow

Borrows into:
11100
Minuend:
10011
Subtrahend:
11110
Difference:
10101
Correct Difference: 01011

2s complement

negative

J.J. Shann 5-37

Example 5-11: Perform the binary subtraction

01100100 10010110
end borrow
<Ans.>
Borrows into:
Minuend:
Subtrahend:
Initial Result:

10011110
01100100
10010110
11001110

28
Initial Result:
Final Result

1 00000000
11001110
00110010
J.J. Shann 5-38

Block diagram of binary adder-subtractor:

Subtraction by 2s complement
subtract:
Subtract the subtrahend N
from the minuend M.
If no end borrow occurs, the
result is nonnegative and
correct.
If an end borrow occurs, the
difference is subtracted from
2n, and a minus sign is
appended to the result.

* This ckt is more complex than necessary.

Share logic b/t adder & subtractor.
J.J. Shann 5-39

C. Unsigned Binary Subtraction by 2s/1s

Complement Addition

Subtraction of 2 n-digit unsigned numbers by 2s

complement addition: M N = M + ( N)
1. Add the 2s complement of the subtrahend N to the

minuend M: M + (2n N) = M N + 2n
2. If M N, the sum produces an end carry, 2n. Discard the
end carry, leaving result M N .
3. If M < N, the sum does not produce an end carry since it
is equal to 2n (N M). Perform a correction, taking the
2s complement of the sum and placing a minus sign in
front to obtain the result (N M).
{2n [2n (N M)]} = (N M)

J.J. Shann 5-40

Example 5-12: Unsigned binary subtraction by 2s

complement addition
Given the two binary numbers X = 1010100 and Y =
1000011, perform the subtraction X Y and Y X using
2s complement ops.

<Ans.>

XY

X=
1010100
2s complement of Y = + 0111101
Sum = 1 0010001
Discard end carry 27 = 1 0000000
Answer: X Y =
0010001

YX
Y=
1000011
2s complement of X = + 0101100
Sum =
1101111
(No end carry)
Answer: Y X = (2s comp of sum)
= 0010001
J.J. Shann 5-41

Subtraction of 2 n-digit unsigned numbers by 1s

complement addition: M N = M + ( N)
1. Add the 1s complement of the subtrahend N to the

minuend M: M + (2n 1 N) = M N + 2n 1
2. If M > N, the sum produces an end carry, 2n. Discard the
end carry and add one to the sum for the correct result of
M N . (end-around carry)
3. If M N, the sum does not produce an end carry.
Perform a correction, taking the 1s complement of the
sum and placing a minus sign in front to obtain the
result (2n 1 ( M N + 2n 1)) = (N M).

J.J. Shann 5-42

Example 5-13: Unsigned binary subtraction by 1s

complement addition
Given the two binary numbers X = 1010100 and Y =
1000011, perform the subtraction X Y and Y X using
1s complement ops.

<Ans.>
X=
2s complement of Y =
Sum =
End-around carry
Answer: X Y =

XY
1010100
+ 0111100
1 0010000
+1
0010001

YX
Y=
1000011
2s complement of X = + 0101011
Sum =
1101110
(No end carry)
Answer: Y X = (1s comp of sum)
= 0010001
J.J. Shann 5-43

Summary:

Either using the 2s or 1s complement, we have

eliminated the subtraction op
need only the appropriate complementer and an adder.

J.J. Shann 5-44

Binary Adder-Subtractor for Unsigned Binary

Numbsers

Subtraction: (5-3, for unsigned binary numbers)

A B = A + (the 2s-complement of B)
= A + (the 1s-complement of B) + 1

Adder-subtractor: based on a parallel adder

Selection input S:
S=0A+B
S = 1 A + B + 1

S
0
1

X Y Cin
A B 0
A B 1

X=A
Y = SB + SB
= SB
Cin = S

Cout Parallel Cin

adder
Sum
4

J.J. Shann 5-45

S
0
1

X Y Cin
A B 0
A B 1

X=A
Y = SB
Cin = S

CoutParallel

adder

Cin

Sum
4

J.J. Shann 5-46

5-4 Binary Adder-Subtractors

(for Signed Numbers)

Signed binary number representation

Signed binary addition and subtraction
Overflow

J.J. Shann 5-47

A. Signed Binary Numbers

Signed binary numbers:

Represent the sign w/ a bit placed in the most significant

position of an n-bit number:

Convention: Sign bit = 0 for positive numbers

= 1 for negative numbers

* The user determines whether a string of bit is a number

or not & whether the number is signed or unsigned.

Representations of signed numbers:

i. Signed-magnitude
ii. Signed-1s complement
iii.Signed-2s complement
J.J. Shann 5-48

Signed-Magnitude Representation

Signed-magnitude representation:

The number consists of

a magnitude and
a symbol (+/) or a bit (0/1) indicating the sign.
Negate a number: change its sign.

Signed-magnitude addition/subtraction for n-bit

numbers:

The single sign bit in the leftmost position and the n 1

magnitude bits are processed separately.
The magnitude bits are processed as unsigned binary
numbers. Subtraction involves the correction step.
J.J. Shann 5-49

Signed-Complement Representation

Signed-complement representation:

A negative number is represented by its complement.

Negate a number: take its complement
can use either 1s or 2s complement
(most common)

E.g.: Represent +9 and 9 in binary w/ 8 bits

Signed-magnitude
Signed-1s complement
Signed-2s complement

+9
00001001
00001001
00001001

9
10001001
11110110
11110111
J.J. Shann 5-50

Comparison of Different Representations

E.g.: 4-bit signed binary numbers

* The positive numbers in all

3 representations are
identical and have 0 in the
leftmost position &
all negative numbers have a
1 in the leftmost bit
position.

(a)

(b)

(c)

* (a): 7 positive numbers

1 zero
8 negative numbers
* (b) (c): 7 positive numbers
2 zeros
8 negative numbers

J.J. Shann 5-51

Signed-magnitude system:

Signed-1s complement system:

is used in ordinary arithmetic

is awkward when employed in computer arithmetic
separate handling of the sign &
the correction step required for subtraction
is useful as a logical op
is seldom used for arithmetic ops
2 representations of 0 &
end-around carry

Signed-2s complement system (9)

is used in computer arithmetic

J.J. Shann 5-52

B. Signed Binary Addition & Subtraction

Signed-magnitude system:

Addition of 2 numbers: M + N

Follow the rules of ordinary arithmetic:

If the sign are the same, add the 2 magnitudes and
give the sum the sign of M.
If the sign are different, subtract the magnitude of N from the
magnitude of M. The absence or presence of an end borrow then
determines the sign of the result, based on the sign of M, and
determines whether or not a 2s complement correction is performed.

E.g.: (0 0011001) + (1 0100101)

Two signed bits are different.
0011001 0100101 = 1110100 & an end borrow of 1 occurs
The sign of the result = 1 (is opposite to that of M) &
take the 2s complement of the magnitude of the result
1110100 0001100
The result = 1 0001100

J.J. Shann 5-53

Signed-2s Complement System

Addition for signed-2s complement system:

(Negative numbers are represented in signed-2s
complement form.)
Add the 2 numbers, including their sign bits. A carry out
of the sign bit position is discarded.

Negative results are automatically in 2s complement form.

Example 5-4:

+ 6 00000110
+ 13 00001101
+ 19 00010011

11111010
+ 13
00001101
+ 7 1 00000111

+6

00000110

13 11110011
7 11111001

6 11111010
13 11110011
19 1 11101101
J.J. Shann 5-54

Subtraction for signed-2s complement system:

(Negative numbers are represented in signed-2s
complement form.)
Take the 2s complement of the subtrahend (including the
sign bit) and add it to the minuend (including the sign bit).
A carry out of the sign bit position is discarded.
( A) (+ B ) = ( A) + ( B)
( A) ( B) = ( A) + (+ B)

6
( 13)
+7

Example 5-5:
11111010

11111010

11110011

+ 00001101
1 00000111

+6
( 13)
+ 19

00000110

00000110

11110011

+ 00001101
00010011
J.J. Shann 5-55

Summary:
In the signed-complement system, binary numbers are
added and subtracted by the same basic addition and
subtraction rules as are unsigned numbers.
Computers need only one common HW ckt to handle
both types of arithmetic.
The same adder-subtractor designed for unsigned
numbers can be used for signed numbers.

J.J. Shann 5-56

* For 2s complement: no correction step required

* For 1s complement: the input from S to C0 must be
replaced by an input from Cn to C0.
J.J. Shann 5-57

C. Overflow

Overflow: signed or unsigned

When 2 n-bit numbers are added &

the sum occupies n + 1 bits

Detection of an overflow:

For unsigned numbers: end carry out of the MSB

An overflow is detected from the end carry out of the MSB.

For signed numbers: carry into the sign bit carry out of the sign bit

An overflow may occur if the 2 numbers added are both positive or

both negative.
Examples: 8-bit numbers (+127 ~ 128)
carries: 0 1
carries: 1 0
+70
0 1000110
70
1 0111010
+80
0 1010000
80
1 0110000
Shann 5-58
+150
1 0010110
150
0 J.J.
1101010

Adder-subtractor ckt w/ overflow detection:

For unsigned numbers: C = Cn

detects a carry after addition or a borrow after subtraction

For signed numbers: V = Cn-1 Cn

detects an overflow: the (n+1)th bit is the actual sign, but it cannot occupy
the sign bit position in the result.
J.J. Shann 5-59

Decimal Adder
(p.5-59~5-62)

Decimal adder:

Employ arithmetic ckts that accept coded decimal

numbers and present results in the same code.

Design method:

Classic method
Add the numbers w/ FA ckts

J.J. Shann 5-60

BCD Adder

Addend
digit

Augend
digit

BCD adder:

Cout BCD

Add two BCD digits in parallel &

produces a sum digits also in BCD
9 inputs: two BCD digits and one carry-in
5 outputs: one BCD digit and one carry-out

adder

Cin

Sum
4

Design approaches
i. Classic method: a truth table with 29 entries
ii. Add the numbers w/ FA ckts

the sum <= 9 + 9 + 1 = 19

Binary results to BCD

J.J. Shann 5-61

Addend Augend
digit
digit
4

1-digit
BCD adder

4-bit
Binary Adder
K

Carry
in

Z8Z4Z2Z1

Carry
out
S8S4S2S1

J.J. Shann 5-62

BCD Adder w/ FA ckts

Binary results to BCD:

J.J. Shann 5-63

Modifications are needed if the sum > 9:

C = K + Z8Z4 + Z8Z2
S8S4S2S1 Z8Z4Z2Z1
when C = 0
Z8Z4Z2Z1 + 0110 when C = 1
J.J. Shann 5-64

Magnitude Comparator
(p.5-63~5-65)
A

Magnitude comparator:

Compares two numbers, A and B,

and determines their relative magnitude:
A > B, A = B, A < B

Design Approaches

B
4

Magnitude
Comparator

A>B

A=B A<B

Classic method: truth table

2n

Two n-bit numbers 2 entries too cumbersome for large n

Use inherent regularity of the problem: algorithm

reduce design efforts

reduce human errors
J.J. Shann 5-65

Algorithm logic:
A = A3A2A1A0 ; B = B3B2B1B0
A=B

if A3 = B3, A2 = B2, A1 = B1, and A1 = B1

equality: xi = AiBi + Ai'Bi' = (Ai'Bi + AiBi')' for i = 0, 1, 2, 3

(A=B) = x3x2x1x0
(A>B) = A3B3' + x3A2B2' + x3x2A1B1' + x3x2x1 A0B0'
(A<B) = A3'B3 + x3A2'B2 + x3x2A1'B1 + x3x2x1 A0'B0

J.J. Shann 5-66

Example: 4-bit Magnitude Comparator

A = A3A2A1A0 ; B = B3B2B1B0
xi = (AiBi'+Ai'Bi)'
(A=B) = x3x2x1x0
(A>B) = A3B3'
+ x3A2B2'
+ x3x2A1B1'
+ x3x2x1 A0B0'
(A<B) = A3'B3
+ x3A2'B2
+ x3x2A1'B1
+ x3x2x1 A0'B0

J.J. Shann 5-67

5-5 Binary Multiplication

Binary multiplication:

The multiplicand is multiplied by each bit of the multiplier, starting from

the LSB.
Each such multiplication forms a partial product.
Successive partial products are shifted one bit to the left.
The final product is obtained from the sum of the partial products.
E.g.: multiplication of two 2-bit numbers

multiplicand
multiplier
partial product
partial product
J.J. Shann 5-68

Example: A 2-bit by 2-bit binary multiplier

A0B1

A1B1

A0B0

A1B0

J.J. Shann 5-69

Example:
A 4-bit by 3-bit
binary multiplier
B3

B2
A2

B1
A1

B0
A0

A0B3 A0B2 A0B1 A0B0

A1B3 A1B2 A1B1 A1B0
A2B2 A2B1 A2B0

A2B3
C6 C5

C4

C3

C2

C1

C0

* 12 AND gates & two 4-bit adders

J.J. Shann 5-70

Construction of Comb. Binary Multiplier

General rule:
A bit of the multiplier is ANDed w/ each bit of the
multiplicand in as many levels as there are bits in the
multiplier.
The binary output in each level of AND gates is added w/
the product.
For J multiplier bit & K multiplicand bits:
Need (J K) AND gates & (J 1) K-bit adders
to produce a product of J + K bits.

E.g.: A 4-bit by 3-bit binary multiplier (p.5-70)

K = 4 & J = 3 12 AND gates & two 4-bit adders

J.J. Shann 5-71

5-6 Other Arithmetic Functions

Other important arithmetic functions:

Incrementing
Decrementing
Multiplication by a constant
Division by a constant
Greater than comparison
Less than comparison

Design approaches:
i. Each of these functions can be implemented for multiple-bit ops by
using an iterative array of 1-bit cells.
ii. Use a combination of rudimentary functions and contraction
technique.

Contraction: a new design technique

simplifies design by converting existing ckts into useful, lesscomplicated ckts (instead of designing the latter ckts directly)
J.J. Shann 5-72

A. Contraction

Contraction:

converting existing ckts into useful, less-complicated ckts

Goal: accomplish the design of a logic ckt or functional
block by using results from past designs
Methods:

Contraction based on ckt inputs:

Simplify an initial ckt w/ value-fixing, transferring, and
inverting on its inputs to obtain a target ckt
Contraction based on unused outputs:
Based on unused outputs to simplify a source ckt to a target ckt

can be applied to Boolean equations or on ckt diagrams

J.J. Shann 5-73

Contraction based on Inputs

Example 5-6: Contraction of Full Adder Equations

Design a ckt Add1 to form the sum Si and carry Ci+1 for the
single bit addition Ai + 1 + Ci .
Ai
Si
Add1
1
Ci+1
C
i
<Ans.>
Full adder equations: Ai + Bi + Ci
Si = Ai Bi Ci

Ci +1 = Ai Bi + Ai Ci + Bi Ci
Contraction by setting Bi = 1 and simplifying the results:

Si = Ai 1 Ci = Ai Ci
Ci +1 = Ai 1 + Ai Ci + 1 Ci = Ai + Ci
J.J. Shann 5-74

* Use Add1 ckt in place of each FA in a ripple carry adder:

S = A + B + C0

S = A + 111 + C0
= A 1 + C0 (in 2s complement)
=A1
(if C0 = 0; decrement op)
Si = Ai Ci

Ci +1 = Ai + Ci
Add1

Add1

Add1

Add1

J.J. Shann 5-75

Contraction Based on Unused Outputs

Contraction based on unused outputs:

Place an unknown value, , on the output of a ckt to

mean that the output will not be used.
The output gate and any other gates that drive only that
output gate can be removed.

Rules for contracting eqs w/ s on outputs:

1. Delete all eqs w/ s on the ckt outputs.
2. If an intermediate variable does not appear in any

remaining eq, delete its eq.

3. If an input variable does not appear in any remaining eq,
delete it.
4. Repeat 2 and 3 until no new deletions are possible.
J.J. Shann 5-76

Rules for contracting a logic diagram w/ s on

outputs:
1. Beginning at the outputs, delete all gates w/ s on their

outputs and place s on their input wires.

2. If all input wires driven by a gate are labeled w/ s,
delete the gate and place s on its output.
3. If all input wires driven by an external input are labeled
w/ s, delete the input.
4. Repeat 2 and 3 until no new deletions are possible.

J.J. Shann 5-77

E.g.: Contract the following logic diagram if Y is a

unused output.
A

C
Z
A
B
C
Z

J.J. Shann 5-78

B. Incrementing

Incrementing:

adding a fixed value to an arithmetic variable

most often a fixed value of 1

n-bit incrementer that performs A + 1 :

Contracting an adder to incrementer

A + 1 = A + B + C0 with B = 001 & C0 = 0 or
B = 000 & C0 = 1
E.g.: contracting a 3-bit adder to incrementer

J.J. Shann 5-79

Example

E.g.: contracting a 3-bit adder to incrementer

A + 1 = A + B + C0 with B = 001 & C0 = 0
C3 is unused output
0

B = 001, C0 = 0, C3 =

S1 = A1 C1
C2 = A1C1

J.J. Shann 5-80

C. Decrementing

Decrementing:

adding a fixed negative value to an arithmetic variable

most often a fixed value of 1

n-bit incrementer that performs A 1 :

Approach1: Example 5-6 (p.5-74)
Approach2: Contracting an adder-subtractor to decrementer:
0

S=1
B = 001

1
1

J.J. Shann 5-81

Incrementer/Decrementer:

Contracting an adder-subtractor to
incrementer/decrementer:

Applying B = 001 &

letting S remain a variable ( = 0 for increment; = 1 for decrement)

J.J. Shann 5-82

D. Multiplication by Constants

Multiplication by a
constant:

apply the constant as

the multiplier A:
If the value for a
particular multiplier
bit position is 1, then
the multiplicand will
be applied to an adder.
If the value for a
particular bit position
is 0, then the adder
will be removed.
* The AND gates will
all be removed.

J.J. Shann 5-83

E.g.: Multiplier = 101

B3

B2
1

B1
0

B0
1

B1
0

B3

B2
0
B0

B0

0
B2

B3
0
B1

C5

C4

C3

C2

B1

B0

J.J. Shann 5-84

Multiplication by a constant equal 2i: 2i B

Only one 1 appears in the multiplier.

All logic is eliminated from the ckt resulting in only wires.
For the 1 in position i:
the result = B followed by i 0s
Function block: a combination of skewed transfers and
value fixing to 0
(left shift by i bit positions with zero fill)

adding 0s to the right (or left) of an operand

E.g.: 100 B

J.J. Shann 5-85

E. Division by Constants

Division by powers of 2:

remove the i LSBs of the dividend

The remaining bits are the quotient &

the discarded bits are the remainder
Right shift by i bit positions

E.g.: B 100

quotient

remainder

J.J. Shann 5-86

F. Zero Fill and Extension

Zero fill:

adding 0s to the right (or left) of an operand

E.g.: Use a byte 01101011 as an input to a ckt that
requires an input of 16 bits.
Zero fill w/ 8 0s on the left 0000000001101011
Zero fill w/ 8 0s on the right 0110101100000000

Sign extension:

increase the # of bits in an operand represented by using a

complement representation for signed numbers

preserve the complement representation for signed numbers

E.g.: Signed-2s number numbers

01101011 0000000001101011 (+107)
10010101 1111111110010101 (107)

J.J. Shann 5-87

5-7 HDL Representations VHDL

J.J. Shann 5-88

5-8 HDL Representations Verilog

J.J. Shann 5-89

5-9 Chapter Summary

Binary adder:

Carry ripple adder

Carry lookahead adder (for improving performance)

Subtraction of unsigned binary numbers

Addition/subtraction of signed binary numbers
Adder/subtractor
Binary multiplication
Additional arithmetic ops:

incrementing, decrementing, multiplication and division

by a constant, shifting, zero fill, sign extension
J.J. Shann 5-90

Problems
Sections
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8

Exercises
5-1, 5-2
5-3, 5-4
5-5~5-8, 5-12, 5-13,
5-15~5-17
5-18
5-9~5-11, 5-14,
5-19~5-20
5-21~5-24
5-25~5-28
J.J. Shann 5-91

Homework

5-1 -->chapter 5-2, adder

5-7 -->chapter 5-4, signed-2s complement

5-11 -->chapter 5-2 and 5-6, carry lookahead

adder
5-12 -->compare
5-20 -->chapter 5-5 and 5-6,

J.J. Shann 5-92