International Journal of Advanced Engineering Research and Technology (IJAERT) 253

Volume 3 Issue 7, July 2015, ISSN No.: 2348 8190

IMPLEMENTATION AND ANALYSIS OF ONE BIT SRAM MEMORY

Kirti Bushan Bawa*, Dr. Sukhwinder Singh**
*ME VLSI Department, PEC, Chandigarh
** Supervisor/Assistant Professor ECE Department, PEC, Chandigarh

ABSTRACT
From the last few decades, the scaling down of CMOS
devices have been taking place to achieve better
performance in terms of speed, power dissipation, size
and reliability. The main area of concern now a day is
Data retention, delay and leakage current reduction in
CMOS technology. SRAM (Static Random Access
Memory) is memory used to store data. For an SRAM
memory design Static Access time, speed, and power
consumption are the three key parameters. The single
SRAM cell, along with the precharge, sense amplifier
and drive circuit are designed and simulated. The
integrated SRAM is operated with input voltage of 0 to
1.8v. In this paper one bit SRAM memory cell has been
designed, implemented & analyzed in standard
UMC180nm technology library using Cadence tool. We
also analyzed the read and write operation of the
designed memory cell.
Keywords SRAM, SNM, 6T, 8T, 9T, delay, PRE, SE,
WE.

I.

sense that data is eventually lost when the memory is not

powered. The stability and area of SRAM need to be
concern in designing SRAM cell. SRAM cell must be
able to write and read data and keep it as long as the
power is applied. For nearly 40 years CMOS devices
have been scaled down in order to achieve higher speed,
performance and lower power consumption. Due to their
higher speed SRAM based Cache memories and Systemon-chips are commonly used. In order to obtain higher
noise margin along with better performance new SRAM
cells have been introduced. In most of these cell read and
write operation are isolated to obtain higher noise
margin. SRAM represents a large portion of the chip,
and it is expected to increase in the future in both
portable devices and high-performance processors. To
achieve longer battery life and higher reliability for
portable application, low-power SRAM array is a
necessity [3]. SRAM is significant component used as a
cache memory in microprocessors, main frame
computers, engineering workstations and memory in
hand-held devices due to low power consumption and
high speed.

INTRODUCTION
II.

Technology and supply voltage scaling continues to

improve the logic circuit delay with each technology
generation. However, the speed of the overall circuit is
increasingly limited by the signal delay over long
interconnects and heavily loaded bit-lines due to
increased capacitance and resistance [1]. Static randomaccess memory (SRAM) is a type of semiconductor
memory that uses bi-stable latching circuitry to store
each bit. Because they are fast, robust, and easily
manufactured in standard logic processes, they are
nearly universally found on the same die with
microcontrollers and microprocessors. SRAM based
Cache memories and System-on-chips are commonly
used due to their higher speed. As the integration density
of transistors increases, power consumption has become
a major concern in todays processors and SoC designs.
Considerable attention has been paid to the design of
low power and high-performance SRAMs as they are
critical components in both handheld devices and high
performance processors. [2] SRAM exhibits data
remanence, but it is still volatile in the conventional

SRAM ARCHITECTURE

SRAMs can be organized as bit-oriented or wordoriented. In a bit-oriented SRAM, each address accesses
a single bit, whereas in a word-oriented memory [4] each
address addresses a word of n bits (where the popular
values of n include 8, 16, 32 or 64). Column decoders or
column MUXs (YMUXs) addressed by Y address bits
allow sharing of a single sense amplifier among 2,4or
more columns. A SRAM cell must be designed such that
it provides a non-destructive read operation and a
reliable write operation. These two requirements impose
Contradicting requirements on SRAM cell transistor
sizing [4].
SRAM cell transistor sizing must be observed for
successful read and write operation. For the simulation
of one bit SRAM cell the main building blocks are as
follows
SRAM cell.
Pre-Charge Circuit.
Write Driver Circuit.
Sense Amplifier.

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International Journal of Advanced Engineering Research and Technology (IJAERT) 254

Volume 3 Issue 7, July 2015, ISSN No.: 2348 8190

III.

DESIGN AND IMPLEMENTATION

This section deals with implementation of five

Components as discussed above.
1. Precharge circuit
The pre charge circuit is one of the essential component
used in SRAM. The function of SRAM is to charge the
bit and bitbar lines to Vdd=1.8v.The pre charge circuit
enables the bit lines to be charged high at all times
except during read and write operation. Here 3 pmos
transistors are used.

Figure 2: 6T SRAM cell

3. Driver circuit
The job of the driver is to bring the bit line and bit
line bar to ground potential for the further job.
Before this the bit line and bit line are being charged
maximum supply voltage Vdd. Its main job is to
provide low impedance path to the ground. So that
the voltage difference between bit line and ground,
bit line bar and ground is zero.
Figure 1: Precharge schematic
2. SRAM cell
SRAM cell design considerations are important for a
number of reasons. The design of an SRAM cell is
key to ensure stable and robust SRAM operation.
Here in this paper 6 transistor SRAM cell is used. It
has both read and write capabilities. The word line
defines operational modes [5]. When wl=0 both
access transistors are off and cell is isolated. To
perform read or write operation the word line is
brought upto a value of 1 which turns on both
access transistors. A typical SRAM cell uses two
cross-coupled inverters forming a latch and access
transistors.

Figure 3: Driver circuit

4. Sense amplifier
The cross paired stage make curtains a full
strengthening of the input signal. This type of
amplifier uses less amount of power and delay as
some timing margin is required for the generation of
the sense clock signal. As shown in figure circuit is
having two transistor M1 and M2 as current source
load, M3 and M4 as driver transistor, M5 as current
source, M6 and M7 are forming inverter (amplifier).

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International Journal of Advanced Engineering Research and Technology (IJAERT) 255

Volume 3 Issue 7, July 2015, ISSN No.: 2348 8190

40 ns during which bit lines are charged to vdd after that

it is made off. Then driver circuit is made on by enabling
write enable, if data to be stored is 1 BL discharges to 0
,if data to be stored is 0 then BLB discharges to 0.

Figure 4: Schematic of sense amplifier

5. Read and write operation of 1 bit SRAM cell
Figure below shows the reading and writing operation of
SRAM cell where both the operations are carried out in
100ns. It includes precharge circuit, driver circuit, sense
amplifier and SRAM cell. When PRE signal goes low
precharge charges the bit lines to vdd, After some time
PRE signal is made high and driver circuit is activated so
that it charges or discharges the bit lines. Tafter that
word line is made on so that value in bit lines can be
stored in SRAM cell. When the value is stored during
read operation sense amplifier is made high and it gives
the desired output.

Figure 6: Simulation result of driver circuit

Figure 7: Simulation result of sense amplifier

Figure 5: read and write operation of 6T SRAM cell

IV.

SIMULATION RESULTS

This Section clearly discuss about the simulation results

of one bit memory cell, precharge, driver circuit and
sense amplifier. Figure 6 shows the simulation result of
driver circuit and precharge. Precharge circuit is on for

The above figure shows the simulation result of sense

amplifier when it is on by making the SE high it senses
the difference between bit lines from SRAM cell and is
OUT is high if data stored is 1 and is low if data stored is
0. The delay of sense amplifier is 326 ps. Figure 8 shows
the shows the simulation result of one bit memory cell
where in write cycle with the help of driver circuit 1 is
stored in SRAM cell and during read cycle sense

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International Journal of Advanced Engineering Research and Technology (IJAERT) 256

Volume 3 Issue 7, July 2015, ISSN No.: 2348 8190

amplifier is made on and it senses the difference between

bit lines from SRAM cell.

journal of solid-state circuits, Vol. 42,April 2007,

pp820 -829
[6] Mr. Viplav A. SOliv, Dr. Ajay A. Gurjar, An
analytical approach to design VLSI implementation
of low power , high speed SRAm cell using submicron technology, International Journal of
Enterprise Computing and Business Systems, 2(1),
2012.

Figure 8: Simulation result of one bit memory cell

V.

CONCLUSION

In this paper we have analyzed and simulated one bit

SRAM cells for read and write operation. The complete
memory cell which includes peripheral components such
as memory bit cell, write driver circuit, pre-charge
circuit, Sense amplifier are designed, integrated and
simulated. The proposed work is operated with analog
input voltage of 0 to 1.8v, supply voltage 1.8v, and
consumes 49.94mW power. The SRAM is designed and
implemented in standard UMC (united microelectronics
limited) 180nm technology of version 5.14 using
Cadence virtuoso tool for schematic.

REFERENCES
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[3] A.V Gayatri, Efficient Current Mode Sense
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