LOGIC DESIGN

First Year - Computer Eng. Dept.

Dr. Ihab Talkhan

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Dr. Ihab Talkhan

Cairo University
Faculty of Engineering
Computer Engineering Department

Introduction to Logic Design

Sunday/Tuesday 2012/2013
Course Description:
Digital Logic Design, The nature of digital logic, numbering system, Boolean
algebra, karnaugh maps, decision making elements, memory elements, latches,
flip-flops, design of combinational and sequential circuits, integrated circuits and
logic families, shift registers, counters and combinational circuits, adders,
substraters ,multiplication and division circuits, memory types. Exposure to logic
design automation software.

Credit: This course consists of 1 1 /2 lectures per week

Text book: M. Morris Mano, Digital Design , Fourth edition, Prentice Hall, 2007
References:
M. Morris Mano, Digital Design , third edition, Prentice Hall, 2002
M. Mano and C. R. Kime , Logic and Computer Design Fundamentals, Prentice
Hall, 2000.
Daniel Gajski, Principles of Digital Design, Prentice Hall, 1997.
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Instructor(s):

Dr. Ihab E. Talkhan

This course is designed to introduce the student to the basic techniques

of design and analysis of digital circuits

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Course contents:
#

Title

Number Systems, 1s and 2s complements

Basic Gates

Boolean Algebra

Analysis of Combinational Circuits

Synthesis of Combinational Circuits using Karnaugh maps

NAND/NOR networks, dont care conditions, duality

Design Automation Software (PSPICE A/D)

Multiplexers, demultiplexers, decoders, encoders and parity circuits

Arithmetic circuits

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Latches and Flip-Flops

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Design of clocked sequential circuits using counters as examples

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Shift registers and different types of counters

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Semiconductor memories

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Design of circuits using ROMs and PLAs

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Introduction to PLDs , CPLDs, & FPGAs and also VHDL (brief)

Assignments
#1

#2

#3

#4

 Grading:

20 point (MID-Term - no make-ups)

5 points Attendance
25 point Assignments/ Labs / Projects (all
assignments from the text book, end of chapter
selected problems
+ FINAL
to be announced later
refer to First term Schedule
to be announced later
to be announced later

Testing dates:
Final test date:
Assistant:
Office hours:
italkhan@cu.edu.eg
italkhan@aucegypt.edu
italkhan@mcit.gov.eg
italkhan@mohp.gov.eg

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Design Cycle
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The Packaging Sequence

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ASIC Design Flow

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Course Ouline
Course Outline
Digital Circuits

Digital Design

Analysis & Design

Hardware & Microprogram method

Hardware Components

Gates

Register Transfer Level

CPU (Central Processing

Flip-Flops

Various components of a

Unit)

Combinational

computer Hardware

I/O

Sequential

Control Logic

Memory

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Binary Logic
AND

OR

-Represented by any of
the following notations:

-Represented by any of
the following notations:

NOT

(inverter)

-Represented by a bar
over the variable

X .AND. Y

X .OR. Y

X.Y

X+Y

-Function definition:

XY

XvY

Z is what X is not

-Function definition:
Z = 1 only if X=Y=1

0 otherwise

-Function definition:
Z = 1 if X=1 or Y =1
or both X=Y=1

-It is also called

complement operation ,
as it changes 1s to 0s
and 0s to 1s.

0 if X=Y=0
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Binary Logic
AND

OR

NOT

(inverter)

-Symbol:

-Symbol

-Symbol

-Truth Table

-Truth Table

-Truth Table

0
0
1
1

0
1
0
1

0
0
0
1

0
0
1
1

0
1
0
1

0
1
1
1

0
1

1
0

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Important Notes
Various binary systems suitable for representing information
in digital components [ decimal & Alphanumeric].
Digital system has a property of manipulating discrete
elements of information, discrete information is contained in
any set that is restricted to a finite number of elements, e.g. 10
decimal digits, the 26 letters of the alphabet, 25 playing cards,
and other discrete quantities.

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Important Notes (cont.)

Early digital computers were used mostly for numeric
computations, in this case the discrete elements used were the
digits, from which the term digital computer has emerged.
Discrete elements of information are represented in a digital
system by physical quantities called signal [voltages &
currents] which have only two discrete values and are said to
be binary.

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 Electrical Signals [ voltages or currents ] that exist throughout a digital

system is in either of two recognizable values [ logic-1 or logic 0 ]

Voltage
5

Intermediate
region,
crossed only
during state
transition

Logic 1 range
2

Transition , occurs
between the two limits

0.8

Logic 0 range
0

time
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Important Notes (cont.)

Digital computers use the binary number system that has two digits 0 and
1, a binary digit is called a bit, thus information is represented in
digital computers in groups of bits.
By using various coding technique, groups of bits can be made to represent
not only binary numbers but also any other group of discrete symbols.
To simulate a process in a digital computer, the quantities must be
quantized, i.e. a process whose variables are presented by continuous realtime signals needs its signals to be quantized using an analog-to-digital
(A/D) conversion device.

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 The memory unit: stores programs,

inputs, outputs and other
intermediate data.
The processor unit: performs
arithmetic and other data-processing
operations as specified by the
program.
The control unit: supervises the flow
of information between the various
units. It also retrieves the
instructions, one by one, from the
program stored in memory and
informs the processor to execute
them

Memory or Storage Unit

CPU
Central Processing Unit
Control
Unit

Processor
Unit

Input devices

Output devices

Block Diagram of a Digital Computer

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Important Notes (cont.)

A CPU enclosed in a small integrated circuit package is called
a microprocessor.
The program and data prepared by the user are transferred into
the memory unit by means of an input devices such as a
keyboard.
An output device, such as a printer, receives the results of the
computations and the printed results are presented to the user.

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Numbering Systems
A number is base r contains r digits 0,1,2,..(r-1) and is expressed with a
power series in r.

An r n An1r n1 .... A1r1 Ao r o A1r 1 A2 r 2 ...

A number can also be expressed by a string of coefficients [positional
notation].

Least significant digit

Most significant digit

An An1.... A1 Ao . A1 A2 ...
Radix point
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Numbering Systems (cont.)

The Ai coefficients contain r digits, and the subscript i
gives the position of the coefficient, hence the weight ri by
which the coefficient must be multiplied.
To distinguish between numbers of different bases, we enclose
the coefficients in parentheses and place a subscript after the
right parenthesis to indicate the base of the number.

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Decimal Numbers
The decimal number system is of base or radix r = 10, because the
coefficients are multiplied by powers of 10 and the system uses ten distinct
digits [0,1,2,9].
Decimal number is represented by a string of digits, each digit position has an
associated value of an integer raised to the power of 10.
Consider the number (724.5)10

724.5 7 10 2 10 4 10 5 10
2

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Conversion from Any numbering System to

Decimal System
To convert any numbering system to decimal, you expand the number to
a power series with its base.
Example:
Convert (312.4)5 to its equivalent decimal, note that the number is in
base 5.

312.45 3 5

1 5 2 5 4 5
1

75 5 2 0.8
Radix 5

82.810

Conversion
from base 5
number to its
equivalent
decimal
number

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Computer Numbering Systems

Binary
Base 2

Octal
Base 8

- It is a base 2 system
with two digits 0 &
1

- It is a base 8 system
with eight digits from
0-7

- The decimal
equivalent can be
found by expanding
the binary number to
a power series with a
base of 2.

- The decimal
equivalent can be
found by expanding
the Octal number to a
power series with a
base of 8.

Hexadecimal
Base 16

- It is a base 16 system
with sixteen digits
from 0 9 plus
A,B,C,D,E,F letters
from the alphabet.
- The decimal
equivalent can be
found by expanding
the Hexadecimal
number to a power
series with a base of
16.

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Binary Numbers
Converting a Binary number to its equivalent Decimal:
(11010.11)2

11010.112 1 24 1 23 0 22 1 21 0 20 1 21 1 22
16 8 2 0.5 0.25
26.7510
Note that, when a bit is equal to 0, it does not contribute to the sum
during the conversion. Therefore, the conversion to decimal can be
obtained by adding the numbers with powers of two corresponding to
the bits that are equal to 1.
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Computer Units
210 = 1024 is referred to as Kilo K
220 = 1,048,567 is referred to as Mega M
230 is referred to as Giga G
Example: 16M = 224 = 16,777,216

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Conversion from Decimal to Binary

(Integer numbers only)
The conversion of a decimal number to binary is achieved by a
method that successively subtracts powers of two from the
decimal number, i.e. it is required to find the greatest number
(power of two) that can be subtracted from the decimal
number and produce a positive difference and repeating the
same procedure on the obtained number till the difference is
zero.

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Example
Find the binary equivalent of (625)10
625 512 = 113
113 64 = 49
49 32 = 17
17 16 = 1
1 1= 0

512 = 29
64 = 26
32 = 25
16 = 24
1 = 20
MSB

LSB

(625)10 = 29 + 26 + 25 + 24 + 20 = (1001110001)
Position 10
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General Method
If the number includes a radix point, it is necessary to separate it into an
integer part and a fraction part, since each part must be converted
differently.
The conversion of a decimal integer to a number in base r is done by
dividing the number and all successive quotients by r and
accumulating the remainders.
The conversion of a decimal fraction to base r is accomplished by a
method similar to that used for integer, except that multiplication by r
is used instead of division, and integers are accumulated instead of
remainders.

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Example
Find the binary equivalent of (41.6875)10
Separate the number into an integer part & a fraction part.

Integer Part:
2
2
2
2
2
2

remainder

41
20 +
10
5
2+
1
0+

=1
=0
=0
=1
=0
=1

(41)10 = (101001)2

Fraction Part:
Integer

LSB

0.6875 x 2 = 1.3750
0.3750 x 2 = 0.7500
0.7500 x 2 = 1.5000
0.5000 x 2 = 1.0000

MSB
1
0
1
1

LSB

MSB

( .6875)10 = ( .1011)2
Thus: (41.6875)10 L (101001.1011)2
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Important Note
The process of multiplying fractions by r does not
necessarily end with zero, so we must stop at a certain
accuracy , i.e. number of fraction digits, otherwise this process
might go forever.

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Octal Numbers
Octal number system is a base 8 system with eight digits [
0,1,2,3,4,5,6,7 ].
To find the equivalent decimal value, we expand the number in
a power series with a base of 8 .
Example:
(127.4)8

= 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1
= (87.5)10

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Hexadecimal Numbers
The Hexadecimal number system is a base 16 system with the
first ten digits borrowed from the decimal system and the
letters A,B,C,D,E,F are used for digits 10,11,12,13,14 and 15
respectively.
To find the equivalent decimal value, we expand the number in
a power series with a base of 16 .
Example:
(B65F)16

= 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160

= (46687)10
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Note
It is customary to borrow the needed r digits for the
coefficients from the decimal system, when the base of the
numbering system is less than 10.
The letters of the alphabet are used to supplement the digits
when the base of the number is greater than 10.

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Decimal

Binary

Octal

Hexadecimal

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
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Important Property
The Octal & Hexadecimal systems are useful for representing
binary quantities indirectly because they posses the property
that their bases are powers of 2.
Octal base = 8 = 23 & Hexadecimal base = 16 = 24, from
which we conclude:
Each Octal digit correspond to three binary digits
Each Hexadecimal digit correspond to four binary digits.

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Conversion from Binary to

Octal/Hexadecimal
The conversion from Binary to either Octal or Hexadecimal is
accomplished by partitioning the Binary number into groups of
three or four digits each respectively, starting from the binary
point and proceeding to the left and to the right. Then, the
corresponding Octal or Hexadecimal is assigned to each
group.
Note that, 0s can be freely added to the left or right to the
Binary number to make the total number of bits a multiple of
three or four.

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Example
Find the Octal equivalent of the Binary number:
( 10110001101011.11110000011)2
Added 0s

010 110 001 101 011 . 111 100 000 110

2

(010110001101011.111100000110)2 L(26153.7406)8

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Example
Find the Hexadecimal equivalent of the Binary number:
( 10110001101011.11110000011)2
Added 0s

0010 1100 0110 1011 . 1111 0000 0110

2

(10110001101011.11110000011)2 L(2C6B.F06)16

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Conversion from Octal/Hexadecimal

to Binary
Conversion from Octal or Hexadecimal to Binary is done by a
procedure reverse to the previous one.
Each Octal digit is converted to a three-digit binary equivalent.
Each Hexadecimal digit is converted to its four-digit binary
equivalent.

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Example
Find the Binary equivalent of (673.12)8
6

. 1

110 111 011 001 010

(673.12)8 = (110111011.001010)2

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Example
Find the Binary equivalent of (3A6.C)16
3

0011 1010 0110 1100

(3A6.C)16 = (001110100110.1100)2

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Important Note
The Octal or Hexadecimal equivalent representation
is more convenient because the number can be
expressed more compactly with a third or fourth of
the number of digits.

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Carry

Two digits

Arithmetic

1 + 1 = 10

Binary

1+1=1

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Arithmetic Operations
Arithmetic operations with numbers in base r follow the same rules
as for decimal numbers

Addition

Subtraction
1 1

Augend

0 1 1 0

Minuend

Addend

0 0 1 1

Subtrahend

Sum

1 0 0 1

Result

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Arithmetic Operations (cont.)

Multiplication
Multiplicand
Multiplier

1 0 1 1

Division

divisor

1 0 1

1110

1 0 1 1

1101

1 1 1

subtract

1 0 0

1 1

0 1

0 1

0 0

1 0

0 1

1 1

1 0

1 0 1 1
0 0 0 0
1
Product

dividend

0 1 1
1 0 1 1 1

186
4
100
13 1101
14
14
1110
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0 1

remainder
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Notes
The rules for subtraction are the same as in decimal, except
that a borrow from a given column adds 2 to the minuend
digit.
In division, we have only two choices for the greatest multiple
of the divisor Zero and the divisor itself.

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Arithmetic Operations with

Base r Systems
Arithmetic operations with Octal , Hexadecimal or any other
base r system is done by using the following methods:
Formulation of tables from which one obtains sums and
products of two digits in base r.
Converting each pair of digits in a column to decimal , add
the digits in decimal, and then convert the result to the
corresponding sum and carry in base r system.

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Example
Add :

(59F)16 + (E46)16
Equivalent Decimal

Hexadecimal

5 9 F
+

E 4 6

3 E 5

15

14

19

14

21

Carry 1

=16+5

=16+3
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Note
The idea is to add F+6 in hexadecimal, by adding the
equivalent decimals 15+6 = 21, then converting (21)10 back to
hexadecimal knowing that;
21 = 16+5 gives a sum digit of 5 and a
carry 1 to the next higher
order column digit

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Multiplication
The multiplication of two base r numbers is done by
performing all arithmetic operations in decimal and converting
intermediate results one at a time.

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Example
Multiply (762)8 x (45)8

carry
Octal

Octal

Decimal

Octal

762

5x2

10=8+2

12

5 x 6 +1

31=24+7

37

5 x 7 + 3 38=32+6

46

3710

4x2

8=8+0

10

43772

4 x 6 +1

25=24+1

31

4 x 7 + 3 31=24+7

37

45
4672

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Complements
Complements are used to simplify the subtraction operation and for logical
manipulation.
Types
Radix Complement

Diminished radix Complement

rs complement

(r-1)s complement

Given n-digit number N in base r,

its rs complement is;

rn N

N 0

N 0

Given n-digit number N in base r,

its rs complement is;
(r n 1) N

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Important Notes
The rs complement is obtained by adding 1 to the (r-1)s
complement.
rs complement of N can be formed by leaving all least
significant 0s unchanged, then subtracting the first nonzero
least significant digit from r, and subtracting all higher
significant digits from (r-1).
(r-1)s complement of N can be formed by subtracting each
digit from (r-1).

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Examples
106-246700

10s complement of :
9s complement of :

246700 753300
246700 753299
(106-1)-246700

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Binary 1s & 2s Complements

Note that ; 2n = a binary number which consists of a 1
followed by n 0s.
2n 1= a binary number represented by n 1s.
2s complement is formed by leaving all least significant 0s
and the first 1 unchanged, then replacing 1s with 0s and
0s by 1s in all other higher significant bits.
1s complement is obtained by changing 1s to 0s and 0s to
1s.

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Note
The (r-1)s complement of Octal or Hexadecimal numbers is
obtained by subtracting each digit from 7 or f (15)
respectively.
If the number contains a radix point, then the point should be
removed temporarily in order to form the rs or (r-1)s
complement. The radix point is then restored to the
complemented number in the same relative position.
The complement of the complement restores the number to its
original value.

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Subtraction with Complements

The subtraction method that is based or uses the borrow concept is less efficient
than the method that uses complements, when subtraction is implemented with
digital hardware.
The subtraction of two n-digit unsigned numbers, M-N in base r is done as
follows:
1.
Add the minuend M to the rs complement of the subtrahend N;
M + (rn N) = M- N + rn
2.
If MN, the sum will produce an end carry rn, which is discarded, what is
left is the result M-N .
3.
If M < N, the sum does not produce an end carry and is equal to
rn (N-M)
which is the rs complement of (N-M). to obtain the answer in a familiar
form, take the rs complement of the sum and place a negative sign in front.

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Example (using 10s complement)

Consider the two numbers 72532 & 3250, it is required to apply the rules
for subtraction with complements with these two numbers, thus we have
two cases:
Case # 1:
M = 72532 & N = 3250, required M-N.
In this case M > N
Note that M has 5-digits and N has only 4-digits, rule number 1: both
numbers must have the same number of digits.
Note also,, the occurrence of the end carry signifies that M > N and the
result is positive.

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M N = 72532 03250
72532
-03250

72532
+ 96750
1 69282

10s Complement
sum

Discard the
end carry

69282 is the required answer

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Example (using 10s complement)

Case # 2:
M = 3250 & N = 72532, required M-N.
In this case M < N
Note that M has 5-digits and N has only 4-digits, rule
number 1: both numbers must have the same number of
digits.
Note also,, the absence of the end carry signifies that M <
N and the result is negative.

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M N = 03250 - 72532
03250
-72532
no carry

03250
+ 27468
30718

10s Complement
sum

The required answer = - ( 10s complement of 30718)

= - 69282
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Notes
When subtracting with complements, the negative answer is
recognized by the absence of the end carry and the
complemented result.

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Subtracting with (r-1)s Complements

The (r-1)s complement can be used when subtracting two
unsigned numbers as the (r-1)s complement is one less than
the rs complement. Thus the result of adding the minuend to
the complement of the subtrahend produces a sum which is
one less than the correct difference when an end carry occurs.
Removing the end-carry and adding one to the sum is referred
to as an end-around carry.

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1s Complement
Example:
X Y = 1010100 1000011
1010100
-1000011

1010100
+ 0111100
1 0010000
1
0010001

1s Complement
sum
End-around carry
answer (X-Y)

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1s Complement (cont.)
Example (cont.):
Y X = 1000011 1010100
1000011
-1010100

1000011
+ 0101011

1s Complement

1101110
sum
Note that, there is no carry in this case
Answer = Y X
= - ( 1s complement of 1101110)
= - 0010001
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Signed Binary Number

Positive integers including zero can be represented as unsigned
numbers.
Because of hardware limitations, computers must represent
everything with 1s & 0s, including the sign of a number.
The sign is represented with a bit, placed in the left-most
position of the number, where:
0 = positive sign
&
1 = negative sign

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Binary number
Binary Number
Signed number

The left most bit represents the

sign and the rest of the bits
represent the number

X = 0 +ve
X = 1 -ve

The left
most bit

Unsigned number

The left most bit is the most

significant bit of the number

X1010101011
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Signed & Unsigned numbers

Unsigned

01001
Signed

+9

Unsigned

25

Signed

-9

Signedmagnitude
System

11001

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 In computers, a signed-complement system is used to

represent a negative number, i.e. negative number is
represented by its complement.

8-bit representation
+9

-9

0 0001001

Signed-magnitude representation

10001001

Signed-1s complement representation

11110110

Signed-2s complement representation

11110111
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 The addition of two signed numbers, with negative numbers

represented in signed 2s complement form, is obtained from
the addition of the two numbers including their sign bits. A
carry out of the sign bit position is discarded.
Note that the negative numbers must be initially in 2s
complement and the sum obtained after the addition, if
negative, is in 2s complement form.

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+ 6

0000 0110

+ 6

0000 0110

+ 13

0000 1101

- 13

1111 0011

+ 19

00010011

- 7

1111 1001

2s complement

We must ensure that the result has sufficient number of bits to

accommodate the sum, if we start with two n-bit numbers and
the sum occupies n+1 bits, we say that an overflow occurs.
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 Note that binary numbers in the signed-complemented system are added

and subtracted by the same basic addition and subtraction rules as unsigned
numbers, therefore, computers need only one common hardware circuit to
handle both types of arithmetic.
The user / programmer must interpret the results to distinguish between
signed and unsigned numbers

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Decimal Codes
n

The binary code is a group (string) of n bits that assume up to 2 distinct

combinations of 1s and 0s, with each combination representing one
element of the set that is being coded, the bit combination of an n-bit
code is determined from the count in binary from 0 to 2 n -1.
Each element must be assigned a unique binary combination and no two
elements can have the same value

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Binary Coded Decimal BCD

Decimal

BCD

0
1
2
3
4
5
6
7
8
9

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

23 22 21 20

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Dr. Ihab Talkhan

 Note , a number with n decimal digit will require 4n bits

in BCD.
Note also, a decimal number in BCD is the same as its
equivalent binary number, only when the number is between 0
9. A BCD number > 10 looks different from its equivalent
binary number.
The binary combinations 1010 1111 are not used and have
no meaning in the BCD.

75
Dr. Ihab Talkhan

18510 00011000 0101BCD 101110012

12 bit

8 bit

It is important to realize that BCD numbers are decimal numbers and not
binary numbers.

76
Dr. Ihab Talkhan

BCD Addition
Each digit in a BCD does not exceed 9, the sum can not be
greater than 9+9+1 = 19, where the 1 being a carry.
The binary sum will produce a result in the range from 0 to 19,
in binary it correspond to 0000 10011, but in BCD
0000 1 1001, thus when the binary sum is equal to or less
1001 (without a carry) the corresponding BCD is correct.

77
Dr. Ihab Talkhan

BCD Addition (cont.)

When the binary sum is 1010 , the result is an invalid
BCD digit.
To correct this problem, add binary 6 (0110) to the sum, which
converts the sum to a correct BCD digit and produces a carry
as required.
The value 6 corresponds to the 6 invalid combinations in the
BCD code (1010 1111).

78
Dr. Ihab Talkhan

Examples
4

0100

0100

1000

+ 5

0101

+ 8

1000

+ 9

1001

1001

12

1100

17

1 0001

Sum greater than 9

0110

0110

1 0010

1 0111

Add 6

Sum greater than 16

carry

79
Dr. Ihab Talkhan

Example (2)
1

184

0001 1000 0100

+ 576

0101 0111 0110

0111 0000 1010

0110 0110
760

0111 0110 0000

BCD carry

Binary sum
add 6
BCD sum

80
Dr. Ihab Talkhan

BCD Multiplication
Multiply 15 x 16 in BCD
15
5x6
= 30
x 16
6x1+3=9
1001 0000
1x5
=5
1
0001 0101
1x
=1
0010 1110 0000
0110
0010 0100 0000

L0011 0000
L1001
L0101
L0001

81
Dr. Ihab Talkhan

 For signed decimal numbers, the sign is represented with

Four bits to conform with the 4-bit code of the decimal
digits, where:
-ve sign
=
1001 (9)
+ve sign
=
0000 (0)
Many computers have special hardware to perform arithmetic
calculations directly with decimal numbers in BCD.

82
Dr. Ihab Talkhan

Other Decimal Codes

Binary codes for decimal digits require a minimum 4-bits per digit.
BCD
8421
Repeated code
2421
3 2 1 0
2
2 2 2
Excess-3 code
Negative code
8 4 -2 -1
Weighted
codes
Always add 3 (0011) to the
original binary number, e.g
0000

0011

0001

0100 and so on

Note, some
digits can be
coded in two
possible ways
83

Dr. Ihab Talkhan

Other Decimal Codes (cont.)

The 2421 & Excess-3 codes are self-complementing codes, i.e.
the 9s complement of a decimal number is obtained directly
by changing 1s to 0s and 0s to 1s.
BCD is not a self-complementing code
The 84-2-1 accepts positive & negative weights.

84
Dr. Ihab Talkhan

Notes
You should distinguish between conversion of a decimal
number to binary and the binary coding of a decimal number.
It is important to realize that a string of bits in a computer
sometimes represents a binary number and at other times it
represents information as specified by a given binary code.

85
Dr. Ihab Talkhan

Alphanumeric Codes
ASCII = American Standard Code for
Information Interchange
ASCII consists of 7-bits to code 128 characters

26 upper-case letters [ A,B,C,]

26 lower-case letters [a,b,c,.]
128
characters

10 decimal numbers [ 0- 9]
32 special printable characters [ #,$,%,&,*,..]
34 control characters

(non-printing C/Cs)
86

Dr. Ihab Talkhan

 Note that, binary codes merely change the symbols not the
meaning of the element of information.
The 34 control characters are used for routing data and
arranging the printed text into the prescribed format

87
Dr. Ihab Talkhan

The 34 control Characters

Control Characters

Format effectors

Information separators

Communication
Control characters

Layout of printing

Separate data into

paragraphs & pages

Transmission of text
between remote
terminals

88
Dr. Ihab Talkhan

Parity bit
ASCII code was modified to 8-bits instead of 7-bits. (ASCII is
1 byte in length)
1 byte = 8 bits
The extra bit, whose position is in the most significant bit [
default is 0] , is used for:
Providing additional symbols such as the Greek Alphabet
or italic type formatetc
Indicating the parity of the character when used for data
communication.

89
Dr. Ihab Talkhan

Parity bit (cont.)

The parity bit is an extra bit included to make the total number of 1s in a row
either even or odd.
The bit is helpful in detecting errors during the transmission of information
from one location to another.

Even parity

0
1
1
1

0011101
0011010
0101001
0011001

90
Dr. Ihab Talkhan

Other Alphanumeric Codes

EBCDIC = Extended BCD Interchange Code, used in IBM. It
is 8-bits for each character and a 9th bit for parity.

91
Dr. Ihab Talkhan

Binary Logic
Digital circuits are hardware components that manipulate
binary information.
Gates are circuits that are constructed with electronics
components [ transistors, diodes, and resistors]
Boolean algebra is a binary logic system which is a
mathematical notation that specifies the operation of a gate [
Boolean => the English mathematician George Boole 1854 ]

92
Dr. Ihab Talkhan

 Electrical Signals [ voltages or currents ] that exist throughout a digital

system is in either of two recognizable values [ logic-1 or logic 0 ]

Voltage
5

Intermediate
region,
crossed only
during state
transition

Logic 1 range
2

Transition , occurs
between the two limits

0.8

Logic 0 range
0

time
93
Dr. Ihab Talkhan

 You should distinguish between binary logic and binary

arithmetic. Arithmetic variables are numbers that consist of
many digits. A logic variable is always either 1 or 0.
A Truth Table is a table of combinations of the binary
variables showing the relationship between the values that the
variables take and the result of the operation.
The number of rows in the Truth Table is 2 n, n = number of
variables in the function.
The binary combinations are obtained from the binary
n
number by counting from 0 to 2 1

94
Dr. Ihab Talkhan

Carry

Two digits

Arithmetic

1 + 1 = 10

Binary

1+1=1

95
Dr. Ihab Talkhan

Binary Logic
AND

OR

-Represented by any of
the following notations:

-Represented by any of
the following notations:

NOT

(inverter)

-Represented by a bar
over the variable

X .AND. Y

X .OR. Y

X.Y

X+Y

-Function definition:

XY

XvY

Z is what X is not

-Function definition:
Z = 1 only if X=Y=1

0 otherwise

-Function definition:
Z = 1 if X=1 or Y =1
or both X=Y=1

-It is also called

complement operation ,
as it changes 1s to 0s
and 0s to 1s.

0 if X=Y=0
96
Dr. Ihab Talkhan

Binary Logic
AND

OR

NOT

(inverter)

-Symbol:

-Symbol

-Symbol

-Truth Table

-Truth Table

-Truth Table

0
0
1
1

0
1
0
1

0
0
0
1

0
0
1
1

0
1
0
1

0
1
1
1

0
1

1
0

97
Dr. Ihab Talkhan

 AND and OR gates may have more than two inputs.

Timing diagrams illustrate the response of any gate to all
possible input signal combinations.
The horizontal axis of the timing diagram represents time and
th vertical axis represents the signal as it changes between the
two possible voltage levels

98
Dr. Ihab Talkhan

Timing Diagram
input 1

input 2

AND

X.Y

OR

X+Y

NOT

99
Dr. Ihab Talkhan

Logic Function Definition

Language description
Function description
Boolean Equation
Graphic Symbols
Truth Table
Timing Diagram
Coding (HDL)

100
Dr. Ihab Talkhan

Other Gates
NAND = AND-Invert

NOR Invert-OR

XOR ( odd )

XNOR (even )

-Symbol:

-Symbol

-Symbol

-Symbol

-Truth Table

-Truth Table

-Truth Table

-Truth Table

0
0
1
1

0
1
0
1

1
1
1
0

0
0
1
1

0
1
0
1

1
0
0
0

0
0
1
1

0
1
0
1

0
1
1
0

0
0
1
1

0
1
0
1

1
0
0
1

Z=X.Y

Z XY

Z=X+Y

Z XY
101

Dr. Ihab Talkhan

Building the Basic Functions

from Other gates
Using NAND Gates
A

Using NOR Gates

Basic Function

NOT (inverter)

A
AB

AND

AB

B
B
A
A+B

OR

A
B

A+B
102

Dr. Ihab Talkhan

Boolean Algebra
It is an algebra that deals with binary variables and logic
operations:
A Boolean function consists of:
An algebraic expression formed with binary variables.
The constants 0 and 1
The logic operation symbol ( . , +, NOT)
Parentheses and an equal sign

103
Dr. Ihab Talkhan

Example
Given a logic function F, defined as follows:

F=

1 if X = 1 or if both Y & Z are equal to 1

0 otherwise
The logic equation that represents the above function is given
by:

F X YZ
104
Dr. Ihab Talkhan

 The truth table for the given function is

as shown.
The Boolean function can be transformed
from an algebraic expression into a
circuit diagram composed of logic gates.

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
0
1
1
1
1

105
Dr. Ihab Talkhan

Logic Circuit Diagram

OR

F X YZ

AND

output
Complement = need an inverter

F X YZ

Y
Z

Note : the number of inputs equal the number of variables

106
Dr. Ihab Talkhan

Notes
There is only one way to represent a Boolean function in a
Truth Table, where there are a variety of ways to represent the
function when it is in algebraic form.
By manipulating a Boolean expression according to Boolean
Algebra rules, it is sometimes possible to obtain a simpler
expression for the same function, thus reducing the number of
gates in the circuit.

107
Dr. Ihab Talkhan

Basic Identities of Boolean Algebra

description

Commutative
Associative
Distributive
DeMorgan

Duality

X + 0 =X
X+1=1
X+X=X
X+X=1
X = X
X + Y = Y +X
X+(Y+Z) = (X+Y)+Z
X(Y+Z) = XY + XZ

X Y X.Y

X.1=X
X.0=0
X.X=X
X.X=0
XY = YX
X(YZ) = (XY)Z
X+YZ=(X+Y)(X+Z)

X.Y X Y

108
Dr. Ihab Talkhan

Duality
The dual of an algebraic expression is obtained by
interchanging OR and AND operations and replacing
1s by 0s and 0s by 1s.
Notice that when evaluating an expression, the
complement over a single variable is evaluated first ,
then the AND operation and the OR operation
( )
NOT
AND
OR

109
Dr. Ihab Talkhan

Extension of DeMorgans Theorem

X1 X 2 X 3 ... X n X1 .X 2 .X 3 ..X n
X1 .X 2 .X 3 .....X n X1 X 2 X 3 .. X n

110
Dr. Ihab Talkhan

Algebraic Manipulation
F XYZ XY Z XZ

XYZ Z XZ using X(Y Z) XY XZ

XY.1 XZ

using X X 1

XY XZ

using X.1 X

111
Dr. Ihab Talkhan

F XYZ XYZ XZ
X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

F
0
0
1
1
0
1
0
1

F XY XZ

112
Dr. Ihab Talkhan

The Consensus Theorem

XY XZ YZ XY XZ
Which Shows that the term YZ is redundant and can be eliminated
Proof:

XY XZ YZ XY XZ YZ ( X X )
XY XZ XYZ XYZ
XY XYZ XZ XYZ
XY(1 Z) XZ(1 Y)
XY XZ
113
Dr. Ihab Talkhan

The Dual of Consensus Theorem

X YX ZY Z X YX Z
Notice that, two terms are associated with one variable and its
complement and the redundant term is the one which not contain the
same variable.

114
Dr. Ihab Talkhan

Complement of a Function F
The complement of a function F is obtained by
interchanging 1s to 0s and 0s to 1s in the values of F in
the Truth Table.
OR, it can be derived algebraically by applying DeMorgans
Theorem.
The complement of an expression is obtained by interchanging
AND and OR operations and complementing each variable.

115
Dr. Ihab Talkhan

Example
F XY Z X YZ
F XY Z X YZ

XY Z
. X YZ

X Y Z
. X Y Z

Or by taking the dual of the expression:

F XY Z X YZ
The original function
Fdual X Y Z
. X Y Z
The dual of F
Complement each literal
F X Y Z X Y Z
The complement of a function is done by taking the dual of the function
and complement each literal.

116
Dr. Ihab Talkhan

Standard Forms
Standard Forms
Product terms

Sum Terms

AND operation among several variables

OR operation among several variables

0 = complemented variable

1 = complemented variable

1 = uncomplemented variable

0 = uncomplemented variable

A product term in which all the variables appear exactly once either
complemented or uncomplemented is called a minterm, note that there are
2 n distinct minterm for n-variables.

117
Dr. Ihab Talkhan

 An algebraic expression representing the function is derived from the

Truth Table by finding the logical sun of all product terms for which the
function assumes the binary value of 1.
A symbol for each minterm m j , where j denotes the decimal
equivalent of the binary number of the minterm.
A sum term that contain all the variables in complemented or
uncomplemented form is called maxterm, symbol M j
Note that

Mj mj

118
Dr. Ihab Talkhan

Example

X Y
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Product
Z
term symbol
0 X Y Z m0
1 X YZ m1
0 XY Z m 2
1 X YZ m3
0 XY Z m4
1 XYZ m5
0 XYZ m6
1 XYZ m7

SUM
sum
symbol
M0
XYZ
M1
XYZ
M2
XYZ
M3
XYZ
M4
XYZ
M5
XYZ
M6
XYZ
M7
XYZ

F
1
0
1
0
0
1
0
1
119

Dr. Ihab Talkhan

Example
Sum of Product

SOP

F X Y Z XY Z X YZ XYZ
m0 m 2 m5 m7
m0,2,5,7

F m1,3,4,6

Product of Sum

POS

F M1 M 3 M 4 M 6
m1 m 3 m 4 m 6
m1 m 3 m 4 m 6

X Y Z X Y Z X Y Z X Y Z
M1,3,4,6

Note that the decimal numbers included in the product of maxterms

will always be the same as the minterm list of the complement
function
120
Dr. Ihab Talkhan

Properties of minterm
1.
2.
3.
4.

There are 2 minterm for n-Boolean variables which can be evaluated

n
from the binary numbers 0 to 2 1
Any Boolean function can be expressed as a logical sum of minterms.
The complement of a function contains those minterms not included in the
original function
n
A function that includes all 2 minterms is equal to logic-1.

121
Dr. Ihab Talkhan

 AND gates followed by OR gate forms a circuit configuration

that is referred to as a Two-Level implementation (SOP).
Two-Level implementation is preferred as it produces the least
amount of delay time through the system.
Delay is defined as the time that a signal spends to propagate
from input to output.
Also, Product of Sum (POS) is a two-level implementation, as
it consists of a group of OR gates followed by an AND gate.

122
Dr. Ihab Talkhan

Example
F AB CD E AB CD CE

123
Dr. Ihab Talkhan

Karnaugh map (k-map)

Each square corresponds to a row of the Truth-Table and to one minterm of
the algebraic equation.
Only one digit changing value between two adjacent rows and columns.
One square represent one minterm, giving a term of four variables (in case
of 4-varaiable map).
Two adjacent squares represent a term of three literals
Four adjacent squares represent a term of two literals.
Eight adjacent squares represent a term of one literal.
Sixteen adjacent squares represent F=1.
When a variable appears within a group in both inverted and non-inverted
state, then the variable can be eliminated.

124
Dr. Ihab Talkhan

K-map Procedure
Fill the map from the Truth-Table.
Look at 1s (where F=1).
Make the biggest group possible:

Squares in a group = 2 n , n=0,1,2,

Adjacent cells
Cover all 1s

Any square can appear in more than one group.

Get expression for each group.
OR all expressions.

125
Dr. Ihab Talkhan

One digit change value at a time

CD
AB

00
01
11
10

00

01

11

10

Cell

12

13

15

14

ABCD 8

11

10

A BC D

SOP
Dr. Ihab Talkhan

POS
126

 Note that there are cases where two squares in the map are considered to
be adjacent,, even though they do not touch each other.

YZ

00

0
1

01
0
4

11
1
5

10
3
7

2
6

127
Dr. Ihab Talkhan

Example
FA, B, C, D m0,1,2,4,5,6,8,9,12,13,14
AB CD

00
01
11
10

00

01

11

10

12

13

15

14

11

10

F C AD BD
128
Dr. Ihab Talkhan

Example 2
FA, B, C, D ABC BCD ABCD ABC

AB CD

00
01
11
10

00
1

01
1

11

10

12

13

15

14

11

1 10

F BD BC ACD
129
Dr. Ihab Talkhan

Prime Implicant
A prime implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map.
If a minterm in a square is covered by only one prime
implicant , that prime implicant is said to be essential.

130
Dr. Ihab Talkhan

YZ

00

0
1

01
0
4

1
1

11
1
5

10
3
7

2
6

F XZ X Z X Y
XZ X Z YZ
XZ & X Z essential prime implicants
X Y & YZ non - essential prime implicants
131
Dr. Ihab Talkhan

Example 1
AB

CD

00
01
11
10

00
1

01

11

10

1 12
8

13

15

11

2
1
1

6
14
10

F AD BD AB
essential prime
implicants

Non-essential prime
implicant

132
Dr. Ihab Talkhan

 Note that, once the essential prime implicants are taken, the third term is not
needed (redundant), as all the minterms are already covered by the essential
prime implicants, thus:

F AD BD
133
Dr. Ihab Talkhan

Example 2
AB CD

00

00
01
11
10

01

11

10

1 12
8

13

1 15
1 11

14

10
Non-essential

F A BCD BCD ABC A BC ACD

or

ABD
Dr. Ihab Talkhan

134

Complement of a Function
The complement of a function is represented in the K-map by
the squares (cells) not marked by 1s.

135
Dr. Ihab Talkhan

Product of Sums (POS)

To represent any function as a product of sums (POS), we take the dual of
and complementing each literal, i.e. we get: F

FF

136
Dr. Ihab Talkhan

Example
FA, B, C, D 0,1,2,5,8,9,10

F AB CD BD

CD
AB

dual F A BC D B D 0 0
complement ing each literal
01
F A BC D B D
11
10

00

01

13

15

14

11

12
1

11

10
1

10
137

Dr. Ihab Talkhan

Dont Care Terms

There are applications where the function is not specified for
certain combinations of variables, e.g. the four-bit binary code
(BCD code) where there are six combinations from 10 15
which are not used and consequently are considered as
unspecified.
These unspecified minterms are called dont care terms and
can be used on a map to provide further simplification of the
function by considering it as 1s or 0s (depending on the
situation).
Dont care terms are represented by a cross X in the map.

138
Dr. Ihab Talkhan

Example
AB CD

00
01
11
10

00
X

01

11

10

12

13

15

14

11

10

F1 CD AB F2 CD AD
Algebraically these two functions are not equal , as both covers
different dont care minterms, but the original function is satisfied as
dont care terms will not affect the original function
Dr. Ihab Talkhan

139

K-map with more than 4-variables

Five-variable map needs 32-cell
Six-variable map needs 64-cell & so on.
In general, maps with six or more variables needs too many
cells and they are impractical to be analyzed manually, there
special program (simulation programs) that can handle such
situation.

140
Dr. Ihab Talkhan

5-variables Map
We use two four-variables maps, the first one has a the variable A=0 as a
common factor, and the second has a common factor A=1.
Each cell in the A=0 map is adjacent to the corresponding cell in the A=1
map, e.g.

Any adjacent cells , k=0,1,2,3,4, in the 5-variable map represents a product

term of 5-k literals.

m 4 m 20 & m15 m31

141
Dr. Ihab Talkhan

5-variables map
DE
BC

00
01
11
10

00

01

11

DE
BC

10

12

13

15

14

11

10

00
01
11
10

A=0

00

01

11

10

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26

A=1

142
Dr. Ihab Talkhan

Example
F ( A, B, C, D, E) m(0,2,4,6,9,13,21,23,25,29,31)
DE
BC

00
01
11
10

00

01

11

DE
BC

10

12

13

15

14

11

10

A=0

00

00
01
11
10
common

F ABE BDE ACE

Dr. Ihab Talkhan

01
16

11
17

10
19

18

20

21

23

22

28

29

31

30

24

25

27

26

A=1
143

Other Gates
NAND = AND-Invert NOR Invert-OR

Buffer

-Symbol:

-Symbol

-Symbol

-Truth Table

-Truth Table

-Truth Table

0
0
1
1

0
1
0
1

1
1
1
0

0
0
1
1

0
1
0
1

1
0
0
0

Z=X.Y

Z=X+Y
Dr. Ihab Talkhan

0
1

0
1

ZX

144

 NAND and NOR gates are more popular than AND and OR gates, as they are
easily constructed with electronic circuits and Boolean functions can be
easily implemented with them.

XY

X Y XY

Invert-OR

AND-invert

Two Graphic Symbols for a NAND gate

145
Dr. Ihab Talkhan

XY

XY X Y

OR-invert

invert-AND

Two Graphic Symbols for a NOR gate

146
Dr. Ihab Talkhan

 The implementation of Boolean functions with NAND gates requires that the
function be in the SOP form.

F AB CD

Double inversion

AND & OR gates

NAND gates

Mixed notation, both

AND-invert & invertOR are present

147
Dr. Ihab Talkhan

Example
F(X, Y, Z) m1,2,3,4,5,7

X
Y

00
X
Y

0
1

01
0
4

1
1

11
1
5

1
1

10
3
7

2
6

Note that Z must have a one-input NAND

gate to compensate for the small circle in
the second level gate

F XY XY Z
X
Y
X
Y

Z
148
Dr. Ihab Talkhan

Steps to Configure SOP with NAND gates

1.
2.

3.
4.

Simplify the function (SOP)

Draw a NAND gate for each product term and the inputs to
each NAND gate are the literals of the product term. (group
of the first-level gates)
Draw a single gate using AND-invert or invert-OR graphic
symbol in the second level.
A term with a single literal requires an inverter in the first
level.

149
Dr. Ihab Talkhan

Another Rule for converting

AND/OR into NAND
1.
2.

Convert all AND/OR using AND-invert/invert-OR.

Check all the small circles in the diagram. For every small
circle that is not counteracted by anther small circle along
the same line, insert an inverter (one-input NAND gate) or
complement the input variable.

150
Dr. Ihab Talkhan

Example
F A B ABC D

A
B

A
B

A
B

A
B

C
D

C
D

151
Dr. Ihab Talkhan

Exclusive-OR Gate / Equivalence gate

XOR ( odd ) XNOR (even )
-Symbol

-Symbol

XOR is equal to 1
if only one variable
is equal to 1 but
not both

XNOR is equal to 1
if both X & Y are equal
to 1 or both are
equal to 0
-Truth Table

-Truth Table

0
0
1
1

0
1
0
1

0
1
1
0

0
0
1
1

0
1
0
1

1
0
0
1

Z XY
X Y XY
Dr. Ihab Talkhan

Z XY
XY X Y

152

XOR/XNOR identities
X0 X
X 1 X
XX 0
X X 1
XY XY
XY XY
Commutativ e : X Y Y X
Associative : (X Y) Z X (Y Z) X Y Z

X Y Z X Y XY Z (XY X Y) Z
X Y Z XY Z X YZ XYZ
Dr. Ihab Talkhan

153

Parity Generation & Checking

It used for error detection.
The circuit that generates the parity bit in the transmitter is
called a parity generator.
The circuit that checks the parity in the receiver is called a
parity checker.

154
Dr. Ihab Talkhan

Even parity generator/checker

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

P
0
1
1
0
1
0
0
1

C
0
0
0
0
0
0
0
0

P XYZ
C XY ZP

Parity Checker

Parity generator
Dr. Ihab Talkhan

155

Transmission Gates
This gate is available with CMOS type electronic circuits.

C
X

TG

C 1

X & Y are inputs

C0

C0

C & C are control inputs

C 1
Open Switch

Pass signal

156
Dr. Ihab Talkhan

Using Transmission gates to construct An

Exclusive-OR gate (XOR)
Z XY
X Y XY
TG1

TG2

TG1

TG2

0
0
1
1

0
1
0
1

Close
Close
Open
Open

Open
Open
Close
Close

0
1
1
0

Dr. Ihab Talkhan

157

Integrated Circuits
It is a small silicon semiconductor crystal, called a chip,
containing the electronic components for the digital gates.
Number of pins may range from 14 in a small OC package to
64 or more in a large package.

158
Dr. Ihab Talkhan

Levels of Integration
Small Scale
Integration
SSI

Medium Scale
Integration
MSI

No. of gates < 10

10 -100 gates

Inputs & outputs

are
connected
directly to the pins

Decoder
Adders

Registers

Large Scale
Integration
LSI

Very Large Scale

Integration
VLSI

100

few
thousands gates

Thousands for
gates

Processors

Large memory
arrays

Memory chips
Programmable
modules

Ultra Large Scale

Integration
ULSI

Complex
microprocessors

159
Dr. Ihab Talkhan

Logic Circuits Technology

Basic circuits in each technology is a NAND, NOR or an inverter.

Digital Logic Families

DTL

TTL

Diode-Transistor
Logic

TransistorTransistor Logic

ECL
Emitter-Coupled
Logic

Diodes/transistors High speed

operation
Power supply 5 V
Super computers
Two logic levels
Signal processors
[0V - 3.5V]
Standard
Dr. Ihab Talkhan

MOS

CMOS

Metal-Oxide
Semiconductor

High component
density
Simple processing
technique during
fabrication

Complementary
Metal-Oxide
Semiconductor
Low power
consumption

160

Notes
There are many type of the TTL family
High-speed TTL
Low-power TTL
Schottky TTL
Low-power Schottky TTL
Advanced Low-power Shcottky TTL
ECL gates operates in a nano-saturated state, a condition that
allows the achievement of propagation delays of 1-2
nanoseconds.

161
Dr. Ihab Talkhan

Important Parameters that are evaluated and

compared

Fan-out
Power-dissipation
Propagation delay
Noise margin

162
Dr. Ihab Talkhan

Fan-out
It specifies the number of standard loads that the output of a
typical gate can drive without impairing its normal operation.
A standard load is usually defined as the amount of current
needed by an input of another similar gate of the same family.

163
Dr. Ihab Talkhan

Power Dissipation
It is the power consumed by the gate which must be available
from the power supply.

164
Dr. Ihab Talkhan

Propagation Delay
It is the average transition delay time for the signal to
propagate from input to output when the binary changes in
value. The operating speed is inversely proportional to the
propagation delay.

165
Dr. Ihab Talkhan

Noise Margin
It is the maximum external noise voltage that causes an
undesirable change in the circuit output.

166
Dr. Ihab Talkhan

Positive & Negative Logic

Choosing the high-level H to represent logic 1 defines a positive logic
system.
Choosing the low-level L to represent logic 1 defines a negative logic
system.

Logic value

Signal value

Logic value

Signal value

Negative logic

Positive logic

167
Dr. Ihab Talkhan

Notes
The signal values H & L are usually used in the
components data sheets
The actual truth table is defined according to the definition of
H and L in the data sheet.

168
Dr. Ihab Talkhan

Data
Sheet

L
L
H
H

L
H
L
H

L
L
L
H

X
TTL
Gate

Depending on the definition of H &

L in the data sheet

0
0
1
1

0
1
0
1

0
0
0
1

X
Y

X
Y

0
0
1
1

0
1
0
1

1
1
1
0

These small triangle in the

inputs & output designate a
polarity indicator
169
Dr. Ihab Talkhan

Logic Circuits
Logic Circuits
Combinational

Sequential

Consists of logic gates whose It involves storage elements (FlipFlops).

outputs at any time are determined
directly from the values of the Outputs are a function of inputs
present inputs.
and the state of the storage
elements, where the state of the
No feedback or storage elements
storage elements is a function of
are involved.
the previous inputs.
Circuit behavior must be specified
by a time sequence of inputs and
internal states.

170

Dr. Ihab Talkhan

Logic Circuits
Logic Circuits

Combinational

n
inputs

Sequential
Outputs

Inputs

Combinational
Circuit

m
outputs

Combinational
Circuit

Next
state

2 n possible input
combination

One possible
output for each
binary
combination of
input variables

Storage
elements
Present state

171
Dr. Ihab Talkhan

 A sequential circuit is specified by a time sequence of inputs, outputs and internal

states. It contain memory and thus can remember the changes of input signals that
occurred in the past.
Inputs for the sequential circuit are functions of external inputs and the present state
of the storage elements.
Both external inputs and the present states determine the binary value of the outputs
and the condition for changing the state of the storage state.

Outputs = f( external inputs , present states)

Next state = f( external inputs , present states)
172
Dr. Ihab Talkhan

Analysis Procedure

To obtain the output Boolean functions from a logic diagram:

1. Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean functions for each gate.

2.

3.

Label the gates that are a function of input variables and previous
labeled gates with different arbitrary symbols. Find the Boolean
functions for these gates.
Repeat step 2 until the outputs of the circuit are obtained in terms
of the input variables.

173
Dr. Ihab Talkhan

Example

174
Dr. Ihab Talkhan

T1 BC

, T2 AB

T3 A T1 A BC
T4 T2 D (AB) D ABD AD BD
T5 T2 D AB D
Thus the Boolean functions of F1 and F2 are:

F1 T3 T4 A BC ABD AD BD
A BC BD BD
F2 T5 AB D
175
Dr. Ihab Talkhan

Another Way using the Truth Table

1. Determine the number of input variables in the circuit for ninputs, list the binary number from 0 to 2n-1 in a table.
2. Label the outputs of the selected gates with arbitrary symbols.
3. Obtain the Truth Table for the outputs of those gates that are a
function of the input variables only.
4. Proceed to obtain the Truth Table for the outputs of those
gates that are a function of previously defined values until the
columns for all outputs are determined.

176
Dr. Ihab Talkhan

T1

T2

T3

T4

T5

F1

F2

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0

0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1

0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0

0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1

0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1

0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1

177
Dr. Ihab Talkhan

Design Procedure
1. Form the specifications of the circuit, determine the required
number of inputs and outputs and assign a letter (symbol) to
each.
2. Derive the Truth Table that defines the required relationship
between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a
function of the input variables.
4. Draw the logic diagram.

178
Dr. Ihab Talkhan

Need to Accomplish
1.
2.
3.
4.

Minimum number of gates

Minimum number of inputs to a gate
Minimum propagation delay of the signal through the gates
Minimum number of interconnections

179
Dr. Ihab Talkhan

Example
Design a combinational circuit with three
inputs and one output. The output must
equal 1 when the inputs are less than
three and 0 otherwise. [use only NAND
gates]

0
1
2
3
4
5
6
7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
0
0
0
0
0

180
Dr. Ihab Talkhan

YZ

00

0
1

01
0

11

10

2
6

F XY X Z
X
Y

F XY X Z

Mixed-symbol notation
Dr. Ihab Talkhan

181

Note
When a combinational circuit has two or more outputs, each output must
be expressed separately as a function of all the input variables.

182
Dr. Ihab Talkhan

Code Converter Example

Decimal
Digit

0
1
2
3
4
5
6
7
8
9

BCD code

Excess-3 code

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
1
1
1
1
1

0
1
1
1
1
0
0
0
0
1

1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0

183
Dr. Ihab Talkhan

CD

00

01

11

10

CD

AB

AB

00

00

01

00

01

1
X

11

11

10

10

01

11

10

W A BC BD
A B(C D)

X BC BD BCD
B(C D) BCD
Dr. Ihab Talkhan

184

CD

00

01

11

10

CD

00

01

11

10

AB

AB
00

00

01

01

11

10

11

10

Y CD CD

ZD

CD

185
Dr. Ihab Talkhan

Logic Diagram of BCD to Excess-3

code Converter

186
Dr. Ihab Talkhan

BCD to Seven-Segment Decoder

Digital read-out found in electronic caculators and digital watches use
display devices such as light emitting diodes LED or liquid crystal display
LCD, each digit of the display is formed from seven segments.
Each consists of one LED or one crystal which can be illuminated by
digital signals.

187
Dr. Ihab Talkhan

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

Not valid (dont care)

All other input combinations

7-outputs
a
f
e

g
d

b
c

188
Dr. Ihab Talkhan

 We cannot use the dont care condition here for the six binary
combinations 10101 1111, as the design will most likely
produce some arbitrary and meaningless display of the
unused combinations.

a AC ABD BC D A BC
b A B AC D ACD A BC
c AB AD BC D A BC
d AC D A BC BC D A BC ABC D
e AC D BC D
f ABC AC D AB D A BC
g AC D A BC ABC A BC
14 AND gate and 7 OR
189
Dr. Ihab Talkhan

Arithmetic Circuits
An arithmetic circuit is a combinational circuit that performs
arithmetic operations such as addition, subtraction,
multiplication and division with binary numbers or with
decimal numbers in a binary code.
0+0=0
One digit
0+1=1
Carry is added to
the next higher
1+0=1
order pair of
significant bits
Two digits
1 + 1 = 10
A combinational circuit that performs the addition of two bits
is called a Half Adder.
190
Dr. Ihab Talkhan

 A combinational circuit that performs the addition of three bits

(two significant bits and a previous carry) is called a Full
Adder.
Two Half Adders are employed to implement a Full Adder.
The Full adder circuit is the basic arithmetic component from
which all other arithmetic circuits are constructed.

191
Dr. Ihab Talkhan

Half-Adder
It is an arithmetic circuit that generates the sum of two binary digits.

S XY X Y X Y
C XY
Ouputs

Inputs

Half-Adder

0
0
1
1

0
1
0
1

0
0
0
1

0
1
1
0

192
Dr. Ihab Talkhan

Full-Adder
It is a combinational circuit that forms the arithmetic sum of three input bits.

Carry from the previous

lower significant position
193
Dr. Ihab Talkhan

S X Y Z
C XY Z ( X Y )
Inputs

Outputs

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

YZ
X
0

00

01

11

10
1

S X Y Z XY Z X Y Z XYZ
X Y Z
YZ
X
0

00

01

11

10

C XY XZ YZ
XY Z ( X Y X Y )
XY Z ( X Y )

Dr. Ihab Talkhan

194

Binary Parallel Adder

The sum of two n-bit binary numbers can be generated in serial or parallel
fashion.
The serial addition method uses only one Full Adder and a Storage device to
hold the output carry.
The parallel method uses n-Full Adders and all bits are applied
simultaneously to produce the sum.
B3

A3
FA

C4

S3

B2

C3

B1

A2
FA

C2

S2

FA

S1
4-bit Parallel Adder
Dr. Ihab Talkhan

B0

A1

C1

A0
FA

C0

S0
195

Binary Adder/Subtractor
The subtraction of binary number can be done most
conveniently by means of complements
The subtraction A-B is done by taking the 2s complement
of B and adding it to A .
The 2s complement can be obtained by taking the 1s
complement and adding 1 to the least significant bit.
The 1s complement can be implemented easily with inverter
circuit and we can add 1 to the sum by making the initial
input carry of the parallel adder equal to 1.

196
Dr. Ihab Talkhan

Example
A = 1011

B = 0011

Input Carry

Augend A

Addend B

Sum

Output Carry

197
Dr. Ihab Talkhan

B3

A3

B2

B1

A2

B0

A1

A0

FA

C4

S3

C3

FA

C2

S2

FA

S1

C1

FA

C0

S0
S = C0 = 0
S = C0 = 1

addition
Subtraction

Adder/Subtractor Circuit
198
Dr. Ihab Talkhan

BCD Adder
An adder that perform arithmetic operations directly with decimal number
system employ arithmetic circuit that accept decimal numbers and present
results in the same code.
It requires a minimum of nine inputs and five outputs, Four bits to code
each decimal digit and the circuit must have an input and output carry.
When C=0 , nothing is added to the binary sum
When C=1, binary 0110 is added to the binary sum through the second 4bit adder.
Any output carry from the second binary adder can be neglected.
A decimal parallel adder that adds two n-decimal digits needs n BCD
adders, the output carry from each BCD adder must be connected to the
input carry of the adder in the next higher position.
199
Dr. Ihab Talkhan

Addend

Augend

4-bit binary adder

Z 3 Z 2 Z1 Z 0

input

carry

Condition for correction:

C K Z1Z3 Z 2 Z3

0
4-bit binary adder

Detect the binary

output from 1010 - 1111
Output carry from the
first Adder
Output carry

S3

S2

S1

BCD sum
Dr. Ihab Talkhan

S0
200

Binary Multiplier
The multiplicand is multiplied by each bit of the multiplier,
starting from the least significant bit.
Such multiplication forms a partial products.
Successive partial products are shifted one position to the left.
The final product is obtained from the sum of the partial
products.
For j multiplier bits and k multiplicand bits , we need jxk
AND gates and (j-1)k bit adders to produce a product of j+k
bits.

201
Dr. Ihab Talkhan

A0
B1

B0

A1

A0

B1

A1

B1

B0

B0

A0 B1 A0 B0

A1 B1 A1 B0
C3

C2

C1

HA

C0

C3 C 2
2-bit by 2-bit binary multiplier
Dr. Ihab Talkhan

HA

C1

C0
202

Decoders
Discrete quantities of information are represented in digital
computers with binary codes.
A binary code of n-bits is capable of representing up to 2n
distinct elements of coded information.
A decoder is a combinational circuit that converts binary
information from n-coded inputs to a maximum of 2n unique
outputs.
A decoder has n inputs and m outputs and is referred to as
nxm decoder

203
Dr. Ihab Talkhan

Z
Y
X

20
21
22

C
3x8 Decoder

208
Dr. Ihab Talkhan

Encoders
An Encoder has 2n (or less) input lines and n output lines.

209
Dr. Ihab Talkhan

Priority Encoder
It is a combinatinal circuit that implements the priority function.
The operation of the priority Encoder is such that, if two or more inputs are
equal to 1 at the same time, the input having the highest priority will take
precedence.
The input D3 in the following Truth Table has the highest priority,
regardless of the values of the other inputs.
Thus, if D3 is 1 , the output will indicate that A1A0 = 11, i.e. the code
A1A0 = 11 means that any data appears on line D3 will have the highest
priority and pass through the system irrespective of the other inputs.
If D2 = 1 and D3 = 0 the code A1A0 = 10 and this means that D2 has the
highest priority in this case.

210
Dr. Ihab Talkhan

Inputs

D1D0
D3D2

00

Outputs

D3

D2

D1

D0

A1

A0

0
0
0
0
1

0
0
0
1
X

0
0
1
X
X

0
1
X
X
X

0
0
0
1
1

0
0
1
0
1

0
1
1
1
1

01

11

10

D1D0
D3D2

00

01

00

00

11

10

01

01

11

11

10

10

1
211

Dr. Ihab Talkhan

A 0 D3 D1 D 2
A1 D 2 D3
V D 0 D1 D 2 D3
D3

A0

D2

A1
D1
V
D0

4-input Priority Encoder

212
Dr. Ihab Talkhan

Multiplexers
It is a combinational circuit that selects binary information
from one of many lines and directs it to a single output line.
The selection of a particular input line is controlled by a set of
selection variables.
Normally, there are 2n input lines and n selection variables
whose bit combinations determine which input is selected.
As in decoders, multiplexers may have an enable input to
control the operation of the unit.
When the enable input is in the active state, the outputs are
disabled.
The enable input is useful for expanding two or more
multiplexers onto a multiplexer with a larger number of inputs.
213
Dr. Ihab Talkhan

S0

S1
D0
D1

D2

D3
Function Table
S0

S1

0
0
1
1

0
1
0
1

D0
D1
D2
D3

4-to-1 line Multiplexer ( MUX )

[ Data Selector ]
Dr. Ihab Talkhan

214

Implementing a Boolean Function of n

variables with a Multiplexer that n-1
Selection Inputs
The first n-1 variables of the function are connected to the
selection inputs of the multiplexer.
The remaining single variable of the function is used for the
data inputs.
If the single variable is Z, the data input of the multiplexer
will be either ;

Z, Z,1 or 0

215
Dr. Ihab Talkhan

Example
FX, Y, Z m1,2,6,7
X

0
0

0
0

0
1

0
1

FZ

0
0

1
1

0
1

1
0

FZ

1
1

0
0

0
1

0
0

F0

1
1

1
1

0
1

1
1

F 1

Y
X

4 x 1 MUX

F
Z
Z
0
1
216

Dr. Ihab Talkhan

General Steps
The Boolean function is first listed in a truth table.
The first n-1 variables listed in the table are applied to the
selection inputs of the MUX.
For each combination of the selection variables, we evaluate
the output as a function of the last variable.
This can be 0, 1, the variable or the complement of the
variable.

217
Dr. Ihab Talkhan

Demultiplexer
It is a digital function that performs the inverse operation of a
MUX.
It receives information from a single line and transmits it to
one of 2n possible output lines.
The selection of the specific output is controlled by the bit
combination of n-selection lines.

218
Dr. Ihab Talkhan

E
S0

D0

D1

S1

D2

D3

1-to-4 Demultiplexer
219
Dr. Ihab Talkhan

Sequential Circuits

220

Logic Circuits
Logic Circuits
Combinational

Sequential

Consists of logic gates whose outputs It involves storage elements (FlipFlops).

at any time are determined directly
from the values of the present inputs. Outputs are a function of inputs and
the state of the storage elements,
No feedback or storage elements are
where the state of the storage
involved.
elements is a function of the previous
inputs.
Circuit behavior must be specified by
a time sequence of inputs and internal
states.
221
Dr. Ihab Talkhan

Logic Circuits
Logic Circuits

Combinational

n
inputs

Sequential
Outputs

Inputs

Combinational
Circuit

m
outputs

Combinational
Circuit

Next
state

2 npossible input
combination

One possible
output for
each binary
combination
of input
variables

Storage
elements
Present state

222
Dr. Ihab Talkhan

 A sequential circuit is specified by a time sequence of inputs,

outputs and internal states. It contain memory and thus can
remember the changes of input signals that occurred in the
past.
Inputs for the sequential circuit are functions of external inputs
and the present state of the storage elements.
Both external inputs and the present states determine the
binary value of the outputs and the condition for changing the
state of the storage state.
Outputs = f( external inputs , present states)
Next state = f( external inputs , present states)
223
Dr. Ihab Talkhan

Sequential Circuits
Sequential Circuits
Synchronous

It is a system whose
behavior can be defined
from the knowledge of its
signals at discrete instants of
time

Asynchronous

It is a system whose
behavior depends upon the
order in which the inputs
change, and the state of the
circuit can be affected at any
instant of time

224
Dr. Ihab Talkhan

 An asynchronous sequential circuit may be regarded as a

combinational circuit with feedback, thus the system may
operate in an unpredictable manner and sometimes may even
become unstable.
The various problems encountered in asynchronous systems
impose many difficulties on the designer, and for this reason
they are seldom used.
A synchronous sequential circuit employs signals that affect
the storage elements only at discrete instant of time, as
synchronization is achieved by a timing device called a Clock
Generator that produces a periodic train of clock pulses.

225
Dr. Ihab Talkhan

 The clock pulses are distributed throughout the system in such

a way that storage elements are affected only upon the arrival
of each pulse, the outputs of the storage elements change only
when clock pulses are present.
The storage elements employed in clocked sequential circuits
are called Flip-Flops.
A Flip-Flop is a binary storage device capable of storing one
bit of information.
When a clock pulse is not active, the feedback loop is broken
because the Flip-Flop outputs cannot change even if the
outputs of the combinational circuit change in value, thus the
transition from one state to the other occurs only at
predetermined time intervals dictated by the clock pulses.
226
Dr. Ihab Talkhan

inputs

Combinational
Circuit

Outputs

Next
state
FLIP-Flop

Next state
change only
during a clock
pulse
transition

Clock pulses

Present state

Synchronous clocked sequential circuit

227
Dr. Ihab Talkhan

 A Flip-Flop circuit has two outputs, one for the normal value
and the other for the complemented value of the bit that is
stored in it.

228
Dr. Ihab Talkhan

Latches
A Flip-Flop circuit can maintain a binary state indefinitely (as
long as power is delivered to the circuit), until directed by an
input signal to switch states.
Latches are the basic circuit from which all Flip-Flops are
constructed.

229
Dr. Ihab Talkhan

SR-Latch (NOR gates)

Action that must
be taken

Action

Set
state

reset

Reset
State
Undefined
set

No change

SR-Latch with NOR gates

230
Dr. Ihab Talkhan

SR-Latch (NAND gates)

Action that must
be taken

Action

Set
state

set

Reset
State
Undefined
reset

No change

SR-Latch with NAND gates

231
Dr. Ihab Talkhan

 Notice that, the S input in the SR NOR-Latch must go back to

0 before any other changes can occur.
There are two input conditions that cause the circuit to be in
the SET state, the first is the action that must be taken by input
S to bring the circuit to the SET state, the second is the
removing of the active input from S leaving the circuit in the
same state.
When S=R=1 (NOR-gate latch), both outputs go to 0, this
produces an undefined state and it also violates the
requirement that output Q and Q be the complement of each
other.

232
Dr. Ihab Talkhan

 Comparing the SR NAND-Latch and the SR NOR-Latch, we

note that the input signals for the NAND required the
complement values of those used for the NOR-Latch.
Because the NAND-Latch require a 0 signal to change its
state, it is sometimes referred to as an S-R Latch, the bar above
the letters designates the fact that the inputs must be in their
complement form to activate the circuit.

233
Dr. Ihab Talkhan

SR-Latch (NAND gates)

set
C

Next state of Q

No change

No change

Q=0 : reset state

Q=1 : set state

undetermined

reset

SR-Latch with NAND gates

and a control input

Dr. Ihab Talkhan

234

 An additional control input which determines when the state of

the latch can be changed is added to the basic SR-Latch to
improve its operation
The control input C acts as an enable signal for the other two
inputs.

235
Dr. Ihab Talkhan

D-Latch

Next state of Q

No change

Q=0: reset state

Q=1: set state

236
Dr. Ihab Talkhan

 One way to eliminate the undesirable condition of the

indeterminate state in the SR-Latch is to insure that inputs S &
R are never equal to 1 at the same time.
As long as the control input is at 0, the cross-coupled SR
latch has both inputs at the 1 level and the circuit can not
change regardless of the value of D.

237
Dr. Ihab Talkhan

JK Flip-Flop
C

Next state of Q

No change

No change

Q=0 : reset state

Q=1 : set state

Complement
(toggle)

238
Dr. Ihab Talkhan

T Flip-Flop
C

Next state of Q

No change

No change

complement

239
Dr. Ihab Talkhan

Flip-Flops Characteristic
Tables & Equations
JK Flip-Flop

SR Flip-Flop
S

Q(t+1)

Operation

Q(t+1)

Operation

0
0
1
1

0
1
0
1

Q(t)
0
1
N/A

No change
Reset
Set
Indeterminate

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)

No change
Reset
Set
Complement

Q( t 1) S RQ,

Q( t 1) JQ KQ

SR 0

D Flip-Flop

T Flip-Flop

Q(t+1)

Operation

Q(t+1)

Operation

0
1

0
1

Reset
Set

0
1

Q(t)
Q(t)

No change
Complement

Q( t 1) D

Q( t 1) TQ TQ
Dr. Ihab Talkhan

240

Analysis Procedure
Obtain the binary values of each Flip-Flop input equation in
terms of the present state and input variables
Use the corresponding Flip-Flop characteristic table to
determine the next state.

241
Dr. Ihab Talkhan

 The characteristic tables are a shorter version of the truth table,

it gives for every set of input values and the state of the FlipFlop before the rising-end (edge) the corresponding state of
the Flip-Flop after the rising edge of the clock signal.
By using K-map we can derive the characteristic equation for
each Flip-Flop

242
Dr. Ihab Talkhan

Flip-Flop Excitation Tables

SR Flip-Flop Excitation Table

JK Flip-Flop Excitation Table

Q(t)

Q(t+1)

Q(t)

Q(t+1)

0
0
1
1

0
1
0
1

0
1
0
X

X
0
1
0

0
0
1
1

0
1
0
1

0
1
X
X

X
X
1
0

D Flip-Flop Excitation Table

T Flip-Flop Excitation Table

Q(t)

Q(t+1)

Q(t)

Q(t+1)

0
0
1
1

0
1
0
1

0
1
0
1

0
0
1
1

0
1
0
1

0
1
1
0
243

Dr. Ihab Talkhan

 The excitation for each Flip-Flop, is used during the analysis

of sequential circuits. It is derived from the characteristic table
by transposing input and output columns.
It gives the value of the Flip-Flops inputs that are necessary to
change the Flip-Flops present state to the desired next state
after the rising edge of the clock signal.

244
Dr. Ihab Talkhan

 In addition to graphical symbols, tables, or equations, FlipFlops can also be described uniquely by means of State
diagrams or State graphs, in which case each state would be
represented by a circle , and a transition between state would
be represented by an arrow.

245
Dr. Ihab Talkhan

State Diagram for various Flip-Flops

SR =00 or 01

Q=
0

SR = 10

SR = 01

SR =00 or 10

Q=
1

SR Flip-Flop
JK =00 or 01

Q=
0

JK = 10 or 11

JK = 01or 11

JK =00 or 10

Q=
1

JK Flip-Flop
246
Dr. Ihab Talkhan

State Diagram for various Flip-Flops

D=1

D=0

Q=
0

D=0

D=1

Q=
1

D Flip-Flop
T=1

T=0

Q=
0

T=1

T=0

Q=
1

T Flip-Flop
247
Dr. Ihab Talkhan

The State Diagram

The state diagram can be obtained directly from the state table.
The state is represented by a circle and the transition between
state is indicated by a directed lines connecting the circles.
The directed lines are labeled with two binary numbers
separated by a slash, the input value during present state and
the second is the output during the present state.
Same state can represent both the source and destination of a
transition.
Each state can be thought of as a time interval between two
rising edges of the clock signal.

248
Dr. Ihab Talkhan

The State Diagram (cont.)

During
present state
Input / output

Q=
1

Q=
0

State of a
Flip-Flop

Directed line

249
Dr. Ihab Talkhan

Example
Consider a sequential circuit with two JK Flip-Flops (A & B)
and one input X, specified by the following input equations:

JA B

K A BX

JB X

K B A X AX

250
Dr. Ihab Talkhan

JA B

K A BX

JB X

K B A X AX
Dr. Ihab Talkhan

251

State Table
Present State

Input

Next State

Flip-Flop
Inputs

JA

KA

JB

KB

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1
1
1
0
1

1
0
1
0
1
0
0
1

0
0
1
1
0
0
1
1

0
0
1
0
0
0
1
0

1
0
1
0
1
0
1
0

0
1
0
1
1
0
1
0

JK Flip-Flop Excitation Table

JK Flip-Flop Characteristic Table

Q(t)

Q(t+1)

Q(t+1)

Operation

0
0
1
1

0
1
0
1

0
1
X
X

X
X
1
0

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)

No change
Reset
Set
Complement

Dr. Ihab Talkhan

252

Steps
Find J A , K A , J B , K B from the equations
Find the next state from the corresponding J & K inputs using the
characteristic table of the JK Flip-Flop.

253
Dr. Ihab Talkhan

State Diagram
Value of
input X

01

00
0

11

10
0

254
Dr. Ihab Talkhan

Master-Slave Flip-Flop
It consists of two Latches and an inverter.
When clock pulse input C=1, then the output of the inverter is 0. Thus
the Master is enabled and its output Y is equal to the external input D and
the Slave is disabled.
When clock pulse input C=0, then the output of the inverter is 1. Thus
the Slave is enabled and its output Q is equal to the Master output Y and
the Master is disabled.
Any changes in the external D input changes the master output Y but
cannot affect the Slave output Q.

255
Dr. Ihab Talkhan

MASTER

SLAVE

External D
Y

256
Dr. Ihab Talkhan

Master-Slave with a JK Flip-Flop

Replacing the Master D Latch with an SR Latch with control
input, the result is a Master-Slave SR Flip-Flop. But the SP
Flip-Flop has the undesirable condition of producing an
indeterminate next state when S=R=1.
A modified version of the SR Flip-Flop that eliminates the
undesirable condition is the JK Flip-Flop, in this case when
J=K=1, it causes the output to complement its value

257
Dr. Ihab Talkhan

Master-Slave with a JK Flip-Flop (cont.)

MASTER

SLAVE

258
Dr. Ihab Talkhan

Flip-Flips with Asynchronous Inputs

Each Flip-Flop is usually available with and without asynchronous inputs,
that are used to preset and clear the Flip-Flops independently of other FlipFlop inputs.
These inputs are used to set the Flip-Flops into initial state for their
standard operation, as when power is turned on, the state of each Flip-Flop
is not predictable, thus we must use asynchronous inputs to set the FlipFlop properly.
Asynchronous means, inputs do not depend on the clock signal and
therefore have precedence over all other operations.

259
Dr. Ihab Talkhan

Flip-Flips with Asynchronous Inputs

CLR & PRS are asynchronous inputs

260
Dr. Ihab Talkhan

Active-high CLR & PRS

Active-low CLR & PRS

261
Dr. Ihab Talkhan

Edge Triggered Flip-Flop (Latch)

It is divided into three Latches:
The SET latch
The Reset Latch
The Output Latch
A low value of asynchronous signals affects the FLIP-Flop:
The Latch is preset by the signal PRS = 0
The Latch is cleared by the signal CLR = 0
Note that, the preset and clear signals force all the latches into proper states
that correspond to Q = 1 & Q = 0 respectively.

262
Dr. Ihab Talkhan

SET Latch

OUTPUT Latch

263

RESET Latch
Dr. Ihab Talkhan

Edge Triggered Flip-Flop (Latch) (cont.)

Active-low preset and clear signals are more frequently found
in practice.
Note that, the SET latch follows the changes in the CLK signal
if D is equal to 1 at the rising edge of the CLK signal, while
the RESET latch follows the CLK signal if D=0 at the rising
edge of the CLK signal.

264
Dr. Ihab Talkhan

Registers
The simplest of the storage components.
Each register consists of n-Flip-Flops driven by a common
clock signal.
SET (Preset) and RESET (Clear) inputs are independent of the
clock signal and have priority over it.
The register store any new data automatically on every rising
edge of the clock.

265
Dr. Ihab Talkhan

Preset

4-bit register

I3

CLK

Clear
Dr. Ihab Talkhan

Q3

Q2

I2
Q1

I1

I0
Q266
0

Register with a Selector (Mutliplexer)

To control the input data of a register, a selector (Multiplexer
[MUX]) unit is used, where a selector is a device that accepts
many inputs and selects only one of them at a time to represent
the output [ 2n-inputs, n-control and one output ].
A control signal LOAD or Enable is used, which allows
loading the data into the register [parallel-load register].
The selector, selects either input data or data already stored in
the register.

267
Dr. Ihab Talkhan

Load =
0

enter new data (Ii , i = 0,1,2,3)

enterDr.previous
Ihab Talkhan stored data (Qi , i = 0,1,2,3)

268

Shift Register
It shifts its contents one bit in the specified direction when the
control signal SHIFT is equal to 1.
It is used to convert a serial data stream into a parallel stream.

269
Dr. Ihab Talkhan

4-bit serial-in/parallel-out
Shift-right register

270
Dr. Ihab Talkhan

A Multi-Functional Register
By using a 4-to-1 Selector, you can combine the SHIFT and LOADING
functions into one unit.
It either shift its contents or load new data.
It could shift one-bit either to the left or to the right depending on the
selection mode.

Present state
S1

S0

0
0
1
1

0
1
0
1

Operation

No change
Load input
Shift Left
Shift Right

Next State
Q3

Q2

Q1

Q0

Q3
I3
Q2
IL

Q2
I2
Q1
Q3

Q1
I1
Q0
Q2

Q0
I0
IR
Q1
271

Dr. Ihab Talkhan

A Multi-Functional Register (cont.)

D 0 S1 S0Q 0 S1S0 I 0 S1 S0 I R S1S0Q1

Di S1 S0Qi S1S0 Ii S1 S0Qi1 S1S0Qi1

1 i 2

D3 S1 S0Q3 S1S0 I3 S1 S0Q 2 S1S0 I L

272
Dr. Ihab Talkhan

3 2

3 2

3 2

3 2

273
Dr. Ihab Talkhan

Counters
A counter is a special type of a register.
It incorporates an incremental, which allows it to count upward or downward.
The incremental consists of a series of Half-Adders [HA] arranged such that an HA
in bit position i will have two inputs connected to the output of the Flip-Flop Qi
and the carry Ci from he HA in position i-1.
The counter equation is as follows:

Di Qi Ci
Ci 1 Qi Ci
As long as E=1, the counter will count-up modulo 4, adding 1 to its content on
every rising edge of the clock.

274
Dr. Ihab Talkhan

Enable

Present

Next

>

F.F.

Q2 Q1 Q0

Clear

Q2

Q1

Q0

Q2

Q1

Q0

D2

D1

D0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

0
1
2
3
4
5
6
7

Counter

Enable = 0 no change
= 1 count
D Flip-Flop Excitation Table
Q(t)

Q(t+1)

0
0
1
1

0
1
0
1

0
1
0
1

Three states
3 Flip-Flops, we
will use D F.F. as an example
275
Dr. Ihab Talkhan

Q1Q0
00
Q2
0
1
1

01

11

Q1Q0
00
Q2
0

10
1

01

11

10

D1 Q1Q0 Q0 Q1

D0 Q0
Q1Q0
00
Q2
0
1

01

11

10

Q0 Q1

1
1

D2 Q2 Q1 Q2 Q0 Q2Q1Q0

Q2 Q1 Q0 Q2Q1Q0
Q2 Q1Q0 Q2Q1Q0
Q2 Q1Q 0
276
Dr. Ihab Talkhan

Half-Adder
E
C0

C1
C2
C3
carry

D2

D1

Q2

D0

Q1

3-bit up-counter
Dr. Ihab Talkhan

Q0
277

278
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279
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280
Dr. Ihab Talkhan

Up/Down Counter
The previous counter can be extended to represent an up/down counter, if
we replace the Half-Adder with a Half-Adder/Subtractor [HAS], which can
increment or decrement under the control of a direction signal D , in this
case the counter equation will be:

Di Qi Ci
Ci 1 DQi Ci DQi Ci

281
Dr. Ihab Talkhan

Direction signal ,

D=0

count up, D = 1

count down

D
E

C3

C0

C1
C2

Carry

D1

D2

CLK
E

0
1
1

X
0
1

D0

CLEAR

No change
Count-up
Count-down

Q2

Q1

4-bit up/down Binary Counter

Dr. Ihab Talkhan

Q0
282

Half-Adder/Subtractor
[ HAS ]
D
Qi
E = Ci

Ci+1

Qi

Di
283
Dr. Ihab Talkhan

3-bit up/down Counter with Parallel Load

[ Presetable Counter ]
I2

I1

I0

E
Output carry

HAS

HAS

Selector

HAS

Selector

Selector

Load

CLK

Clear
Q2

Q1
Dr. Ihab Talkhan

Q0 284

4-bit up/down Counter with Parallel Load

[ Presetable Counter ] [cont.]

Load

Operation

0
0
0
1

0
1
1
X

X
0
1
X

No change
Count-up
Count-down
Load input

285
Dr. Ihab Talkhan

BCD Counter
It can be constructed by detecting when the counter reaches a count of 9
and loading 0 instead of 10 in the next clock cycle.
The detection is accomplished by an AND gate whose output is equal to
1 when the content of the counter is equal to 1001.
The output of the AND is connected to the Counter's Load input, which
allows the counter to load 0 at the next rising edge of the clock.
In the up direction we must load 0 into the counter when it reaches a
count of 9, while in the down direction we must load 9 when the
counter reaches a count of 0.

286
Dr. Ihab Talkhan

Up/Down Counter

BCD up-counter
Dr. Ihab Talkhan

287

Up/Down BCD Counter

S

Selector

Up/Down Counter

288
Dr. Ihab Talkhan

Asynchronous Counter
All Flip-Flops are not all clocked by the same clock signal
There is no need to use an incremental or decremental, counting is
achieved by toggling each Flip-Flop at half the frequency of the preceding
Flip-Flop.
The Flip-Flop will change its state on every 0-to-1 transition of its clock
input.
Note, the clock signal CLK is used to only clock the Flip-Flop in the
least significant position.
The clock-to-output delay of the ith Flip-Flop is equal to i .
The maximum counting frequency of an n-bit asynchronous counter is:

1
f
n
Dr. Ihab Talkhan

289

4-bit Asynchronous Up-Counter

Dr. Ihab Talkhan

290

CLK

Q3

Q2

Q1

Q0

t0

t1

t2

t3

t4

t5

t6

t7
291

Dr. Ihab Talkhan

Mixed-mode Counters
To speed up an asynchronous counter, we must make it partly
synchronous.
To do this, we divide a large counter into n-bit slices, so that
the operation within each slice is asynchronous, while the
propagation between slices is synchronous, or vice versa.

292
Dr. Ihab Talkhan

Asynchronous
Counter

Asynchronous
Counter

Synchronous Counter with 4-bit Asynchronous Slices

8-bit Mixed-mode Counter
Dr. Ihab Talkhan

293

Synchronous
Counter

Synchronous
Counter

Asynchronous Counter with 4-bit Synchronous Slices

8-bit Mixed-mode Counter
Dr. Ihab Talkhan

294

Memory & Programmable Logic

295

Major Units
For any system, there are three major units:
Central processing unit CPU
Memory unit
Input/Output unit
In digital system, memory is a collection of cells capable of
storing binary information (permanent or temporary).
It contains electronic circuits for storing and retrieving
information.
It interacts with the CPU and input/output units.

296
Dr. Ihab Talkhan

Memory types
Random Access Memory
RAM

Read Only Memory

ROM

It is a programmable logic
devices PLDs, which are
integrated
circuits
with
internal
logic
gates
connected
through
electronic fuses.

Accept new information for

storage to be available later
for use (write)

Transfer stored information

out of memory (read)
RAMs may range on size
from hundreds to billions of
bits.

Programming is done by
blowing these fuses to
obtain the desired logic
function.

It is volatile

297
Dr. Ihab Talkhan

Conventional
Symbol

Array Logic
Symbol

298
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299
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300
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301
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302
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303
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304
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305
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306
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Example of a PLD Chip

307
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308
Dr. Ihab Talkhan

Programming Technology
To establish the programmable connections the following
technologies are used:
EPROM
EEPROM
FLASH

309
Dr. Ihab Talkhan

EPROM
used to create a wired AND function. The transistor has two gates, a
select gate and a floating gate, charge can be accumulated and trapped on
the floating gate by a mechanism called avalanche injection or hot electron
injection. These transistors are referred to as FAMOS (Floating gate
Avalanche-injection MOS). Note that without a charge on the floating gate
the FAMOS acts as a normal n-channel transistor in that when a voltage is
applied to the gate, the transistor is turned on. EPROM cells provide a
mechanism to hold a programmed state, which is used in PLDs or CPLDs
to establish or not establish a connection. To erase the cell remove charge
from the floating gate by exposing the device to ultraviolet light. (typical
erasure time is about 35 minutes under high-intensity UV light.

310
Dr. Ihab Talkhan

311
Dr. Ihab Talkhan

EEPROM
E2PROM, used to create a wired AND-function. It consists of two
transistors (select & storage transistors). These transistors are referred to as
FLOTOX (Floating gate Tunnel Oxide transistors). It is similar to the
FAMOS except that the oxide region over the drain is considerably smaller,
less than 10 Ao (Angstroms) compared to 200 Ao for the FAMOS. This
allows charges to be accumulated and trapped on the floating gate by a
mechanism called Fowler-Nordheim tunneling. E2PROM cells require a
select transistor because when the floating gate does not hold a charge, the
threshold voltage of the FLOTOX transistor is negative.

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FLASH
like E2PROM, FLASH cells consist of two transistors (select
& storage transistors). They create a wired AND function.
The storage Transistor is a FAMOS, so programming is
accomplished via hot electron injection. However the floating
gate is shared by an eraser transistor that take charge off it via
tunneling.

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RAM
Random access from any random location.
It stores information in groups of bits (called words.
A word is a group of 1s & 0s (represents numbers,
instructions, alphanumeric characters, binary coded
information).
Normally, a word is a multiples of 8 bits (1 byte) in length,
where 1 byte = 8 bits.
Capacity of memory = total number of bytes.

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Communications between Memory &

Environment
Communications between memory and environment is done
through:
In/Out lines
Address selection lines
Control lines

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Memory Unit Block Diagram

n data-in lines

K-address

K-address = specify particular

lines
Read
Write

Memory Unit

2k words
n bits/word

word chosen
R/W Control = Direction of transfer

n data-out lines

Computer range from 210=1024 words (requiring address of 10-bits) to

232 (requiring 32 address bits)
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Units

Kilo K = 210
Mega M = 220
Gega G = 230
64 K = 216
(26 x 210 )
2 M = 221
4 G = 232

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Memory Address
Binary

Decimal

Memory Content

0000000000

1101100101011100

1111111111

1023

Content of 1024 x 16 Memory L 1K x 16bit

i.e. 10 address lines & 16-bit word
Note: 64K x 10 16 bits in address , 10-bits word

2k = m , m total number of words, K number of address bits (lines)

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Write & Read

Write
Transfer binary address of desired word to address lines.
Transfer data bits that must be stored to data-in lines
Activate write-in
Read
Transfer binary address to address lines.
Activate read-in

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Memory Chip Control

Select

IN

Out
S
R

R/W

Basic Cell
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Memory Select

Read/Write

Operation

None

Write

Read
Select

R/W =

read path from F.F to output

In to F.F.

IN

Basic

OUT

Cell

R/W
m words of n-bits/word consists of n x m binary storage cells
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Addresslines

RAM
16 x 4

Memory Select

R/W

DataIN

DataOUT

Memory Chip Symbol

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3-State Buffer
It exhibits three distinct states, two of the states are the logic 1
and logic 0 of conventional logic. The third state is the highimpedance (Hi-Z) state.
The high-impedance state behaves like an open circuit, i.e.
looking back into the logic circuit, we would find that the
output appears to be disconnected.

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IN

OUT

ENABLE ) EN)

EN

IN

OUT

0
1
1

X
0
1

Hi-Z
0
1

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Properties of Memory
Integrated circuit RAM may be either Static or Dynamic

RAM
Static RAM (SRAM)

Dynamic RAM (DRAM)

It consists of internal latches that

store the binary information.

The stored information remain valid

as long as power is applied to the
RAM

It stores the binary information

in the form of electric charges
on capacitors, the capacitors
are accessed inside the chip
by n-channel MOS transistors.

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RAM
Static RAM (SRAM)
SRAM is easier to use and
has shorter read/write cycles.
No refresh is required

Dynamic RAM (DRAM)

The stored charge on the
capacitors tends to discharge
with time, and the capacitors
must be periodically recharged
by refreshing the DRAM. This is
done by cycling through the
words every few milliseconds,
reading and rewriting them to
restore the decaying charge.
It
offers
reduced
power
consumption and larger storage
capacity in a single DRAM chip
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 Memory units that lose stored information when power is

turned-off are said to be Volatile.
Both SRAM & DRAM are of this category, since the binary
cells needs external power to maitain the stored information.
Magnetic disks, CDs as well as ROM are non-volatile
memories, as they retain their stored information after the
removal of power.

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Array of RAM Chips

Combine a number of chips in an array to form the required
memory size.
Capacity = number of words & number of bits/word
increase in words increase in address
Usually input and output ports are combined, to reduce the
number of pins on the memory package.

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4 x 4 memory

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4 x 4 Memory
It consists of 16 memory cells MCs.
For each memory access, the address decoder decodes the address and
selects one of the rows.
If RWS & CS are both equal to 1 the new content will be written into
each cell of the row selected. Note that the output drivers are disabled to
allow the new data to be written-in
If RWS = 0 & CS = 1 the data from the row selected will be passed
through the tri-state drivers to the IO pins.

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Design Flow Diagram

Design description
Synthesis
Placement
Routing
Test Benches for design verification

Design flow diagram

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Design Constraints

Time-to-market
Cost
Design Features
Performance
Manufacturing capabilities

Design constraints

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System Design Requirements

Increasing Functionality
Higher performance
Lower cost
Lower power consumption
Smaller dimensions

Need to create
highly integrated,
complex systems
with fewer IC
devices and less
printed-circuitboard PCB area.

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Technologies available
PCB technology
Surface mounting Devices (SMD)
Multi-chip Modules MCMS
Custom Design
Application Specific Integrated Circuit ASIC (SC, GA,
PLD, CPLD, FPGA)

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How to Define your Hardware

Function description
Algorithms
Equation
Symbols (schematic capture)
Data from graphs
Netlist
Truth table
Waveforms (timing diagrams)
VHDL

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Future Integrated CAD

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Schematic Capture
(Small Designs)

It provides a graphical view of the design

It uses software tools that support schematic hierarchy
Design modularity ( )

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But Capturing
difficult:

Large

designs

is

Control logic must still be generated using traditional design

techniques
Schematic is difficult to maintain
Schematic capture environment are proprietary ( ) , so a
designer who works in a schematic capture environment for one
project may not be able to reuse material when working on a new
project that requires the use of a new schematic capture environment
The simulation environment supported by PLD schematic capture tool
may not fit with the system design environment, making design
verification difficult at best.

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Bottleneck with increasing complexity of

designs

Electronic Design Automation (EDA) tools

Accelerated time-to-market schedules

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Appropriate Design Methodologies

Increase the efficiency of designers
Facilitate capturing, understanding and
maintaining a design
Not open to interpretation
Open, not proprietary, standard accepted by
industry
Allow designs to be ported from one EDA
environment to another, thus modules can be
packaged and reused

VHDL
&
Verilog
Languages
satisfy
These
requirements

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Appropriate Design Methodologies

(cont.)

Support complex designs and hierarchy and

gate-level to system-level design
May be used for description, simulation
and synthesis of logic circuits
Support different design entries
Supports multiple levels of design
description

VHDL
&
Verilog
Languages
satisfy
These
requirements

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Modern Methodologies
in design and test
Semi-custom & Full-custom Application
Specific Integrated Circuit ASIC
High-density Programmable Logic Devices
PLDs
Complex High-density Programmable Logic
Devices CPLDs
Field Programmable Gate Arrays FPGAs
Hardware Description Language VHDL
Very High Speed Integrated Circuit VHSIC
Hardware Description Language

Dr. Ihab Talkhan

500 to more
than 100,000
gates, thus
Boolean
equations or
gate-level
descriptions are
no longer
efficient to
quickly
complete a
design 346

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VHDL History
VHDL ( a product of the VHSIC (Very High Speed
Integrated Circuit) program funded by the Department of
Defense (US government) in 1970s & 1980s) is well suited
for designing with programmable logic devices (it is one
language for design & simulation).
It was endorsed by IEEE in 1986 in its attempt at
standardization.
By December 1987 the IEEE 1076.1 standard for VHDL was
approved and a VHDL Language Reference Manual (LRM)
was published.

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VHDL properties
it provides high-level language constructs that enable
designers to describe large circuits and bring products to
market rapidly.
It supports the creation of design libraries for reuse in
subsequent designs.
It is a standard language (IEEE standard 1076), thus it
provides portability of code between synthesis and simulation
tools as well as technology-independent design.

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VHDL properties (cont.)

Reduction of a design description to lower-levels (such as
netlist), and it serves the needs of designers at any level
It facilitates converting a design from programmable logic to
an ASIC implementation.

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VHDL Advantages

Standard
Government Support
Industry Support
Portability
Modeling Capability (Power & Flexibility)
Reusability
Technology & Foundry independence
Documentation
New Design methodology

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Standard
VHDL is an IEEE standard (such as graphic X-windows
standard, bus communication interface standard, and so on).
It reduces confusion and makes interfaces between tools,
companies, and products easier.
Any development to the standard would have better chances of
lasting longer and have less chance of becoming obsolete due
to incompatibility with others.

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Government Support
VHDL is a result of the VHSIC program, so it is clear that the
US government supports the VHDL standard for electronic
procurement.

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Industry Support
Companies use VHDL tools not only with regard to defense
contractors, but also for their commercial designs.

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Portability
VHDL permits you to simulate the same design description
that you synthesized, simulating a several-thousand-gate
design description before synthesizing can save a considerable
amount of time & effort.
VHDL is standard, design description can be taken from one
simulator to another, one synthesis tool to another, and one
platform to another, i.e. VHDL design descriptions can be
used in multiple projects.

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VHDL Portability property

VHDL
CODE

Compiler
A

Compiler
B

One design

Compiler
C

Any Synthesis tool

PCB

Custom

ASIC
Any vendor/device

VHDL provides portability between compilers &

Device independent design
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Modeling Capability
(Power & Flexibility)
It has powerful language constructs (code description of
complex control logic)
It has multiple levels of design description for controlling
design implementation
It supports design libraries & the creation of reusable
components
It provides for design hierarchies to create modular designs

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Device-independent Design
You can create a design without having to first choose a
device for implementation, with one design description you
can target many device architecture.
It permits multiple styles of design description, i.e. it permits
several classes of design description.

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Device-independent Design
aeqb (a(0) XOR b(0)) NOR (a(1)
XOR b(1));

U1: xor2 port map(a(0),b(0),x(0)));

U2: xor2 port map(a(1),b(1),x(10);
U3: nor2 port map(x(0),x(1),aeqb);

Netlist

Boolean equationst

If a = b then aeqb `1`;

Else aeqb `0`;
End if;

aeqb `1` when a = b else `0`;

Concurrent statements

Sequential statements

2-bit Comparator
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Benchmarking Capabilities
Device-independent design & portability allow you
benchmark a design using different architectures and different
synthesis tools.

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ASIC Migration
The efficiency the VHDL generates allows your product to hit the market
quickly.
When production volumes reach appropriate levels, VHDL facilitate the
development of an ASIC, sometimes the exact code used with the PLD can
be used with the ASIC.

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Quick time-to-market & Low Cost

VHDL & programmable logic pair facilitate a speady design
process, as VHDL permits designs to be described quickly and
Programmable logic eliminates NRE expenses and facilitates
quick design iterations.
VHDL & programmable logic combine as a powerful vehicle
to bring your products to market in record time.

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