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DynamicRandomAccessMemory

DynamicRandomAccessMemory(DRAM)memory

cycles

The timing diagrams for the read, write and refresh‐only cycles are shown in the Figure below. For a read cycle /WE must be inactive before the CAS pulse is applied and remain inactive until the /CAS pulse is over. After the column address is strobed, /RAS is raised and with /RAS high and /CAS low the data bit is made available on DOUT.

For a write cycle the DIN signal should be applied by the time /CAS goes low, but after the /WE pin goes low. The write is performed through the DIN pin while /RAS /CAS and /WE are all low. The DOUT pin is held at its high‐impedance state throughout the write cycle. For the refresh‐only cycle, only the row address is strobed and the /CAS pin is held inactive. The DOUT pin is kept in its high‐impedance state.

Note the address lines are A0 to A7 which provide 2 8 choices. However the memory is arranged

as a

the /CAS line is used to select the column of the DRAM.

2 8 x

2 8 matrix, giving 2 16 = 64K choices. The /RAS line is used to select the row and then

choices. The /RAS line is used to select the row and then DRAM Read Cycle: In

DRAM Read Cycle:

In terms of timing, the following steps must occur:

1. The row address must be applied to the address input pins on the memory device for the

prescribed amount of time before RAS goes low and held after RAS goes low.

2. RAS must go from high to low and remain low.

3. A column address must be applied to the address input pins on the memory device for the

prescribed amount of time and held after CAS goes low.

4. WE must be set high for a read operation to occur prior to the transition of CAS, and remain

high after the transition of CAS.

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DynamicRandomAccessMemory

5. CAS must switch from high to low and remain low.

6. OE goes low within the prescribed window of time.

7. Data appears at the data output pins of the memory device. The time at which the data

appears depends on when RAS , CAS and OE went low, and when the address is supplied.

8. Before the read cycle can be considered complete, CAS and RAS must return to their inactive

states.

complete, CAS and RAS must return to their inactive states. DRAM Write Cycle: DRAM READ CYCLE

DRAM Write Cycle:

DRAM READ CYCLE

To write to a memory cell, the row and column address for the cell must be selected and data must be presented at the data input pins. The chip's on‐board logic either charges the memory cell's capacitor or discharges it, depending on whether a 1 or 0 is to be stored. In terms of

7/7/2015

DynamicRandomAccessMemory

timing, the following steps must occur:

1. The row address must be applied to the address input pins on the memory device for the

prescribed amount of time before RAS goes low and be held for a period of time.

2. RAS must go from high to low.

3. A column address must be applied to the address input pins on the memory device for the

prescribed amount of time after RAS goes low and before CAS goes low and held for the

prescribed time.

4. WE must be set low for a certain time for a write operation to occur. The timing of the

transitions are determined by CAS going low.

5. Data must be applied to the data input pins the prescribed amount of time before CAS goes

low and held.

6. CAS must switch from high to low.

7. Before the write cycle can be considered complete, CAS and RAS must return to their inactive

states.

complete, CAS and RAS must return to their inactive states. DRAM WRITE CYCLE

DRAM WRITE CYCLE