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ENERGY SOURCES
K.SUDHEER
N.MANOJ KUMAR
Assistant Professor
Sudheerk_115@inbox.com
Assistant Professor
manojkumar.neela@gmail.com
P.PRADEEP KUMAR
Researcher
pradeepp226@gmail.com
alone renewable power system, where several dcdc converters are conventionally employed with
the drawback of high cost and low efficiency due
to multiple-stage conversion. To better interface
the renewable source, storage elements and load,
an integrated three-port full bridge converter
Abstract:
A systematic approach to generate three port
full bridge converters(TPFBCS) interfacing a
renewable source,a storage battery and a load
is proposed for a stand-alone renewable power
system application.Allowing dc bias current in
the transformer,the primary circuit of a half
bridge converter can function in such a way
that a power flow path can be configured
between
the
renewable
source
and
battery,which is connected in parallel with one
of the dividing capacitors.To make voltage on
any two of the three ports independently
regulated,a synchronous regulation with
various implementations are proposed.As a
result,a family of TPFBCS with merits of
simple topologies and control,reduced number
of devices and single stage power conversion
between any two of the three ports is
presented.A TPFBC with a synchronous
regulation is thus presented to validate the
above operation and theories.
III.
Proposed circuit
Conventional circuit
IV.
Block diagram
-2-
V.
In this project, a three-port bidirectional seriesresonant converter is proposed with the following
features:
All ports are bidirectional, including the
load port for applications, such as motor
loads with regenerative braking.
Centralized control of power flow by
phase shifting the square wave outputs of
the three bridges.
Higher switching frequencies with
realizable component values when
compared to three-port circuits with only
inductors.
Reduced switching losses due to softswitching operation and voltage gain
increased by more than two times due to
the phase-shifting between input and
output bridges as opposed to a diode
bridge at the load side.
Simulation
Hardware control
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9
P3.0/R XD
P3.1/TXD
P3.2/IN T0
P3.3/IN T1
P3.4/T0
P3.5/T1
P3.6/W R
P3.7/R D
XTAL1
XTAL2
EA/VPP
R ST
ALE/ PR OG
PSEN
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22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
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GND
19
18
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
20
1
2
3
4
5
6
7
8
P0.0/AD 0
P0.1/AD 1
P0.2/AD 2
P0.3/AD 3
P0.4/AD 4
P0.5/AD 5
P0.6/AD 6
P0.7/AD 7
VCC
40
The
AT89C51
provides
the
following standard
features: 4K bytes
of Flash, 128 bytes
of RAM, 32 I/O
lines, two 16-bit
timer/counters, five
vector
two-level
interrupt
architecture, a full duplex serial port, on-chip
oscillator and clock circuitry. In addition, the
AT89C51 is designed with static logic for
operation down to zero frequency and supports
two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port and interrupt
system to continue functioning. The Power-down
Mode saves the RAM contents but freezes the
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34
33
32
Conclusion
AT89C 51
IX.
References
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