Fault models

1 Stuck-at-1

11

Transition /1

1
0

Set coupling

10

1
0

Inversion coupling

11

0
1

OR bridging

1
1

Neighborhood
pattern sensitive
faults (passive)

Transition /0

Reset coupling

1
0

Inversion coupling

0
1

AND bridging

Neighborhood
pattern sensitive
faults (active)

0
1

1
0

1
Address decoder
faults

ADR
ADR

Stuck-at-0

0
0

ADR
ADR

ADR
ADR

ADR
ADR

ADR
ADR

Elements of march test

(w0)

(w1)

(r1,w0)

(r0,w1)

1
0

1
0

1
0

1
0

1
0

0
1

1
0

0
1

1
0

1
0

1
0

1
0

0
1

1
0

0
1

0
1

C - algorithm
(w0) (r0,w1)

(r0,w1)

(r1,w0)

(r1,w0)

(r0)

0
0

0
0

0
0

1
0

0
1

1
0

0
1

0
1

0
1

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

0
1

1
0

0
1

1
0

0
1

1
0

0
1

1
0

1
0

1
0

1
0

1
0

0
1

1
0

1
0

0
1

0
1

0
1

Number of steps: 10n

Fault coverage: AFs, SAFs, TFs, CFins , CFids

0
0

Checkerboard test and data retention

1

Designed to test refresh

operations of DRAMs
Maximizes leakage current
and detects leakage faults
Used as data retention test
To be effective it must
consider address
scrambling and layout

Data backgrounds for word memories

Multiple
Multipledata
databackgrounds
backgroundsto
todetect
detectcoupling
couplingand
andbridging
bridgingfaults
faultsbetween
betweencells
cellsof
ofthe
thesame
sameword
word
For
Forevery
everypair
pairof
ofcells
cellsall
allfour
fourcombinations
combinationsare
arechecked
checked

22(log
(log2ww++1)
1)backgrounds
backgrounds

16

16backgrounds
backgroundsfor
for
128-bitwide
widememory
memory

128-bit

Normal
Normaland
andinverse
inverse

D0 D1 D2 D3 D4 D5 D6 D7
0
1
0
1
0
1
0
1

0
1
0
1
0
1
1
0

0
1
0
1
1
0
0
1

0
1
0
1
1
0
1
0

0
1
1
0
0
1
0
1

0
1
1
0
0
1
1
0

0
1
1
0
1
0
0
1

0
1
1
0
1
0
1
0

Data in word-oriented memory

(w0)

(r0,w1)

(r1,w0)

(r0,w1)

Parallel memory BIST

Clock

FF
S
S
M
M

Start

Hold

System logic

Data
Data generator
generator
Address
Address generator
generator
Control
Control generator
generator

Done

BIST
mode

Memory

Fail

Serial memory BIST

System logic
Data output
Serial input

Serial output

Memory

Minimal logic and routing

Longer test time

r0
w1
r0
w1
r0
w1
r0
w1
r1

Address M
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 0
1 1 0 0
1 1 0 0
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1

Serial-parallel data interface trade-offs

Memory

Memory

Memory

Memory

Memory BIST collar

Functional logic
Memory
Memory BIST
BIST
controller
controller
Memory controller at the top level
To / From
TAP controller

TAP controller as test engine

Memory
array

Embedded memory BIST collar

mux address / control bus and data lines
local comparator with single pass/fail
local data generator to reduce routing
area and timing problems
local address validation

Shared controller and parallel test

Functional logic
Memory
Memory BIST
BIST
controller
controller

To / From
TAP controller

Insert collars
Connect them
through memory test
bus

to memory BIST
controller
to TAP

Memory
array

Memory
array

Sin

BIST control

BIST address
Functional address

Functional control

Parallel memory BIST collar

BIST data
Functional data
Pass / Fail

MBIST mode

=?

Sout

Address

Ctrl

Data in

Memory array
Clock

Data out

Full-Speed test application

Runs at system clock speeds with single cycle

read/write operations
Uncovers speed-related defects
Reduce test application time.
Clock
Cycle 1

Clock
Cycle 2

Clock
Cycle 3

Clock
Cycle 4

Clock
Cycle 5

Setup
Setup
Read
Read 11

Setup
Write 1

Setup
Read 2

Setup
Read 3

Setup
Write 2

Clock
Addr/Cntrl/
Data
Memory
Output

Read 1

Read 2

Read 3

Compare
Circuitry

Compare
Read 1

Compare
Read 2

Compare
Read 3

Circuit
Output
Write

Pass/Fail
Read 1
Write 1

Pass/Fail
Read 2

Diagnostics

Detect failing location/data during test

Should diagnose speed related defects
Two types - Hold and resume, Hold and restart
How it works?

BIST controller stops after 1 (or 2) failures

Fail data is scanned out
BIST session resumes from where it stops (Hold and
resume)
BIST session restarts after fail data is scanned out
(Hold and restart)

Full-speed diagnostics

MBIST
controller

+
Restart

Memory
Memory
array
array

Diagnostic monitor

ATE

Yield improvement with memory redundancy

Memory percentage, defect rate, and redundancy
amount affect yield
Redundancy Yield Improvement
100
90

Memory Yield

Optimal

80
70

Level 3
Redundancy

60
50

Level 2
Redundancy

40
30
20

Level 1
Redundancy

10

No Redundancy

0
0

10

20

30

40

50

60

70

80

90 100

Chip Memory Percentage

Source: Zorian, Rodgers, DATE 2002

Redundancy and repair

Memory
Memory BIST
BIST
controller
controller

Memory
Memory
Array
Array

Extra columns, rows, or rows

and columns
At the end of test - good,
repairable, or non-repairable
Repair data scanned out at
the end of test

Full-Chip memory BIST integration

Read in SOC netlist
Identify memories

BIST GENERATION
Assign memories to
controller
(BIST Scheduling)

Memory BIST Generation

(Generate Controller/Collars)

BIST INSERTION
Insert controllers in the design
Stitch controllers to top-level

Full Chip Memory BIST Control

SOC
TM S
TCK
TRST

Block
TAP Controller

Memory 1

rst_l
BIST
Controller

CLK

BIST Block

test_done

BIST Block
Memory 2

fail_h
test_h
MBIST Data
Register
TDI

TDO
Boundary Scan Register

Programmable algorithms

Selection of algorithms

Synthesizable algorithms

March1, March2, March3, Unique Address, Checkerboard,

address jumping
user defined prior to synthesis
simple language
number of sequences, backgrounds, sequence elements etc.,

Programmable algorithms

defect mechanisms may not be known before fabrication

memory BIST controller implements a class of algorithms
field programmable parameters define active elements of test
sequences

Summary
Key

components of a BIST controller

algorithm controller
data background generator
address generator
comparator

Very

high quality test of embedded arrays

BIST controller shared across a number of memory
arrays to reduce area
BIST diagnostics helps in gathering failure
information
Built-in repair results in yield improvement