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Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel.

, AP/ECE

NAME :
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SEM / YEAR : VI / III
SUBJECT CODE :
SUBJECT NAME : VLSI LABORATORY
LABORATORY MANUAL
Prepared by
B.SAKTHIKUMAR., M.E., ASSISTANT PROFESSOR / ECE P.SUNDARAVADIVEL., M.E., ASSISTANT
PROFESSOR / ECE
070290076 - VLSI DESIGN LAB 1

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE

VIDYAA VIKAS COLLEGE OF ENGINEERING AND


TECHNOLOGY
TIRUCHENGODE - 637214
Register No
Certified that this is the bonafide record of work done by
Selvan / Selvi ............................................................................ of
the ......................
Semester ........................................................................ branch during the
Year........................ in the .........................................Laboratory.
Staff in Charge Head of the Department
Submitted for the University Practical Examination on.................................
Internal Examiner External Examiner
EXTRACT OF ANNA UNIVERSITY COIMBATORE SYLLABUS
070290076 - VLSI DESIGN LAB 2

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE

I- Design and simulation of Combinational Logic Circuit using VHDL


1. Adder
2. Multiplexer and Demultiplexer
3. Encoder and Decoder
4. Multiplier
II- Design and simulation of Sequential logic circuit using VHDL
5. Flip Flops
6. Counter
7. Shift registers
8. Frequency Divider
III- CMOS Circuit design using SPICE (DC and Transient Analysis)
9. CMOS Inverter
10. CMOS NAND and NOR Gates
11. CMOS D Latch
IV- FPGA Implementation
12. 4 bit Adder
070290076 - VLSI DESIGN LAB 3

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


Introduction to VHDL
A digital system can be described at different levels of abstractions and from different points of
view. As the design process progresses, the level and view are changed, either by human designers or by
software tools, It is desirable to have a common framework to exchange information among the designers
and various software tools, Hardware description languages (HDLs) serve this purpose. In this chapter we
provide an overview of the design, use and capability of HDLs.
Limitations of traditional programming languages:
A programming language is characterized by its syntax and semantics. The syntax comprises the
grammatical rules used to write a program, and the semantics is the meaning associated with language
constructs. When a new computer language is developed, the designers first study the characteristics of
the underlying processes and then develop syntactic constructs and their associated semantics to model
and express these characteristics.
Most traditional general-purpose programming languages, such as C, are modeled after a
sequential process. In this process, operations are performed in sequential order, one operation at a time.
Since an operation frequently depends on the result of an earlier operation, the order of execution cannot
be altered at will. The sequential process model has two major benefits.
At the abstract level, it helps the human thinking process to develop an algorithm step by step.
At the implementation level, the sequential process resembles the operation of a basic computer model
and thus allows efficient translation from an algorithm to machine instructions. The characteristics of
digital hardware, on the other hand, are very different from those of the sequential model. A typical digital
system is normally built by smaller parts, with customized wiring that connects the input and output ports
of these parts. When signal changes, the parts connected to the signal are activated and a set of new
operations is initiated accordingly. These operations are performed concurrently, and each operation will
take a specific amount of time, which represents the propagation delay of a particular part, to complete.
After completion, each part updates the value of the corresponding output port. If the value is changed,
the output signal will in turn activate all the connected parts and initiate another round of operations. This
description shows several unique characteristics of digital systems, including the connections of parts,
concurrent operations, and the concept of propagation delay and timing. The sequential model used in
traditional programming languages cannot capture the characteristics of digital hardware, and there is a
need for special languages (i.e., HDLs) that are designed to model digital hardware.
VHDL:
VHDL and Verilog are the two most widely used HDLs. Although the syntax and appearance of
the two languages are very different, their capabilities and scopes are quite similar. Both are industrial
standards and are supported by most software tools.
VHDL stands for VHSIC (Very High Speed Integrated Circuit) HDL. The development of VHDL
was sponsored initially by the US Department of Defense as a hardware documentation standard in the
early 1980s and then was transferred to the IEEE (Institute of Electrical and Electronics Engineers). IEEE
ratified it as IEEE standard 1076 in 1987, which is referred to as VHDL-87. Each IEEE standard is
reviewed every few years and is revised as needed, IEEE revised the VHDL standard in 1993, which is

referred to as VHDL-93, and made minor modifications and bug fixes in 2001, which is referred to as
VHDL-2001. Since no new language construct is added in the new version, there is no significant
difference between VHDL-93 and VHDL-2001. A suffix is sometimes added to the IEEE standard to
indicate the year the standard was released. For example, VHDL-87 and VHDL-2001 are known as IEEE
standards 1076-1987 and IEEE 1076-2001 respectively.
070290076 - VLSI DESIGN LAB 4

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


After the initial release, various extensions were developed to facilitate various design and modeling
requirements. These extensions are documented in several IEEE standards:
IEEE standard 1076.1-1999, VHDL Analog and Mixed Signal Extensions (VHDLAMS): defines the
extension for analog and mixed-signal modeling.
IEEE standard 1076.2-1996, VHDL Mathematical Packages: defines extra mathematical functions for
real and complex numbers.
IEEE standard 1076.3- 1997, Synthesis Packages: defines arithmetic operations over a collection of bits.
IEEE standard 1076.4-1995, VHDL Initiative Towards ASK Libraries (VITAL): defines a mechanism to
add detailed timing information to ASIC cells.
IEEE standard 1076.6-1999, VHDL Register Transfer Level (RTL) Synthesis: defines a subset that is
suitable for synthesis.
IEEE standard 1164- 1993 Multivalue Logic System for VHDL Model Interoperability (stdlogicJl64): defines new data types to model multivalue logic.
IEEE standard 1029.1-1998, VHDL Waveform and Vector Exchange to Support Design and Test
Verification (WAVES): defines how to use VHDL to exchange information in a simulation
environment
Advantages of VHDL:
VHDL offers the following advantages for the digital design
Standard
Technology / Vendor independent
Portability
Modeling Capability
Reusability
Case Insensitive
Basic VHDL Statement Syntax:
Library
Entity
Architecture
Component
Signal
Variable
Constant
Simple When

Selected When
Process
If statement
Case Statement
While loop
For loop
Wait statement
070290076 - VLSI DESIGN LAB 5

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


Library Syntax:
Library <Library_Name>; Use <Library_Name>.<Package_Name>.<Package_Parts>;
Entity Syntax:
Entity <Entity_Name> is Port (<Port_name> : <Signal_Mode> <Signal_Type>); End <Entity_Name
(optional)>;
Architecture Syntax:
Architecture <Architecture_Name> of <Entity_Name> is <Declarations>; Begin <Concurrent
Statements>; End <Architecture_Name (optional)>;
Component Declaration Syntax:
Component <Component_Name> Port (<Port_name> : <Signal_Mode> <Signal_Type>); End
Component;
Component Instantiation Syntax:
Label: <Component_Name> Portmap (Signal mapping);
Signal Declaration Syntax:
Signal <Signal_Name>: Signal_Type (Range):= Initial Value;
Variable Declaration Syntax:
Variable <Variable_Name>: Variable_ Type (Range):= Initial Value;
Constant Declaration Syntax:
Constant <Constant_Name>: Constant_ Type (Range):= Initial Value;
Simple When/Else Syntax:
Assignment When Condition Else Assignment When Condition Else;
With/Select/When:
With <identifier> Select Assignment When Value, Assignment When Value; (Whenever
With/Select/When is used, all permutations must be tested.)
Process Syntax:
Label: Process (Sensitivity List) <Variable Declaration>; Begin <Sequential Statements>; End Process
label;
070290076 - VLSI DESIGN LAB 6

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


If Statement Syntax:
If <Condition> Then <Assignments>; Elsif <Condition> Then <Assignments>; ....... Else
<Assignments>; End If;
Case Statement Syntax:
Case <identifier> is When value => assignments; When value => assignments; End Case;
While Loop Statement;
Label: While <Condition> Loop <Sequential Statements>; End Loop;
For Loop Statement:
Label: For <identifier> In < range>Loop <Sequential Statements>; End Loop;
Wait Statement Syntax:
Wait Until <Signal_Condition>; Wait On Signal<Signal1, Signal2...>; Wait For <time>; Wait statement
when used inside process statement does not need sensitivity list in process statement.
070290076 - VLSI DESIGN LAB 7

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


Creating a New Project in ISE
In this section, you will create a new ISE project. A project is a collection of all files necessary to
create and to download a design to a selected FPGA or CPLD device.
XILINX ISE Quick Start Tutorial
To create a new project for this tutorial:
1. Select File > New Project. The New Project Wizard appears.
2. First, enter a location (directory path) for the new project.
3. Type tutorial in the Project Name field. When you type tutorial in the Project Name field, a
tutorial subdirectory is created automatically in the directory path you selected.
4. Select HDL from the Top-Level Module Type list, indicating that the top-level file in your
project will be HDL, rather than Schematic or EDIF.
5. Click Next to move to the project properties page.
6. Fill in the properties in the table as shown below
Device Family : CoolRunner XPLA3 CPLDs Device : xcr3128xl Package : TQ144 Speed Grade : 7 TopLevel Module Type : HDL Synthesis Tool : XST (VHDL/Verilog) Simulator : ModelSim Generated
Simulation Language: VHDL or Verilog, depending on the language you want to use when running
behavioral simulation.
When the table is complete, your project properties should look like the following:
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the
next section, your new project will be created.
Creating an HDL Source
In this section, you will create a top-level HDL file for your design. Determine the language that you wish
to use for the tutorial. Then, continue either to the Creating a VHDL Source section below.
070290076 - VLSI DESIGN LAB 8

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


This simple AND Gate design has two inputs: A and B. This design has one output called C
1. Click New Source in the New Project Wizard to add one new source to your project.
2. Select VHDL Module as the source type in the New Source dialog box.
3. Type in the file name andgate.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Define the ports for your VHDL source.
In the Port Name column, type the port names on three separate rows: A, B and C. In the Direction
column, indicate whether each port is an input, output, or inout. For A and B, select in from the list. For
C, select out from the list.
7. Click Next in the Define VHDL Source dialog box.
8. Click Finish in the New Source Information dialog box to complete the new source file template.
9. Click Next in the New Project Wizard.
10. Click Next again.
11. Click Finish in the New Project Information dialog box.ISE creates and displays the new project
in the Sources in Project window and adds the andgate.vhd file to the project.
070290076 - VLSI DESIGN LAB 9

Prepared by: B. Sakthikumar., AP/ECE & P. Sundaravadivel., AP/ECE


12. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL file in
the ISE Text Editor. The andgate.vhd file contains:
Header information.
Library declaration and use statements.
Entity declaration for the counter and an empty architecture statement.
13. In the header section, fill in the following fields:
Design Name : andgate.vhd Project Name : andgate Target Device : xcr3128xl- TQ144 Description : This
is the top level HDL file for an up/down counter. Dependencies : None Note: It is good design practice to
fill in the header section in all source files.
14. Below the end process statement, enter the following line:
C <= A and B;
15. Save the file by selecting File -> Save.
Check the Syntax of New Counter Module.
When the source files are complete, the next step is to check the syntax of the design. Syntax
errors and typos can be found using this step.
1. Select the counter design source in the ISE Sources window to display the related processes in
the Processes for Source window.
2. Click the + next to the Synthesize-XST process to expand the hierarchy.
3. Double-click the Check Syntax process.
When an ISE process completes, you will see a status indicator next to the process name.
If the process completed successfully, a green check mark appears.
If there were errors and the process failed, a red X appears.
A yellow exclamation point means that the process completed successfully, but some warnings
occurred.
An orange question mark means the process is out of date and should be run again.
4. Look in the Console tab of the Transcript window and read the output and status messages produced by
any process that you run.
Caution! You must correct any errors found in your source files. If you continue without valid syntax, you
will not be able to simulate or synthesize your design.
070290076 - VLSI DESIGN LAB 10