On chip switched capacitor based DCDC converter for low ripple and Fast

Response

Submitted in partial fulfilment of the requirements

for the degree of

Master of Technology
in
VLSI Design
by

AHIRE SHASHANK VISHWANATH

(12MVD0030)

VIT
UNIVERSITY
(Estd. u/s 3 of UGC Act 1956)

Vellore - 632 014, Tamil Nadu, India

May, 2014

CERTIFICATE

This is to certify that the Project work titled On chip switched capacitor based DCDC converter for low ripple and Fast Response that is being submitted by Ahire
Shashank Vishwanath is in partial fulfilment of the requirements for the award of
Masters of Technology [VLSI Design], is a record of bonafide work done under my
guidance. The contents of this Project work, in full or in parts, have neither been taken
from any other source nor have been submitted to any other Institute or University for
award of any degree or diploma and the same is certified.

Prof. K. Jagannadha Naidu

Internal Guide

The thesis is satisfactory / unsatisfactory

Prof. John Ruben

Dr.Gopala Krishna

Internal Examiner

External Examiner

Approved by
Program Chair

ABSTRACT
In recent years, many portable devices are introduced in the market which are
having on chip DC-DC converters. These chips are having multiple function modules
which require different dc power supply depending on the technology used. As the
feature size of MOSFET transistor scales down, the power supply voltage required in
digital systems also decreases .For this purpose Switch capacitor (SC) based DC-DC
converters are used because they dont need any inductor and can be integrated on one
chip to reduce cost, weight and area. In this project the input voltage is step down to
the three different voltage levels depend upon input signal frequency. The input
voltage is 1.8V which is then step down to the 0.6V, 0.8V.Main objective of this
project is to achieve minimum output voltage ripple and fast transient response.

ACKNOWLEDGEMENT
First and foremost, I praise and hearts full thank the Almighty-god, from the bottom
of my heart, which has been the unfailing source of strength, comfort and inspiration
in the completion of this project work.
I owe my thanks to our respectable, Chancellor, Dr. G.VISHWANATHAN
and to our beloved Vice Presidents, Mr. SANKAR VISHWANATHAN, Mr.
SEKAR VISHWANATHAN, Mr.G.V. SELVAM. I also express my heartfelt
thanks to our Vice Chancellor, Prof. V. RAJU and Pro-Vice Chancellor (Vellore
Campus),Prof. S.NARAYANAN, for giving this wonderful opportunity for carrying
out my course in this University.
I am greatly indebted to Dr. G. RAMCHANDRA REDDY, Dean, School of
Electronics Engineering, VIT University, Vellore for his support. I express my
heartfelt gratitude to Dr. HARISH KITTUR, M.Tech (VLSI Design) Program Chair,
School of Electronics Engineering, VIT University, Vellore for his help during the
course of project. I express my sincere thanks to Prof. S.RAVI, M.Tech (VLSI
Design) Project Coordinator, School of Electronics Engineering, VIT University,
Vellore for his valuable support in completing this project successfully.
I take immense pleasure and very deep sense- of gratitude in conveying my
special, sincere and heartfelt thanks to my project guide Prof. K. JAGANNADHA
NAIDU, Assistant Professor, School of Electronics Engineering, VIT University,
Vellore, for his consistent motivation, guidance, support and having faith in me for
completing this project successfully.
It is with deep sense of reverence, I thank my Family, who constantly
encouraged and continuously supported my entire academic life. I also acknowledge
my Friends all those who have contributed either directly or indirectly for the
successful completion of project.

TABLE OF CONTENTS
LIST OF FIGURES.7
LIST OF TABLES...9
LIST OF ABBREVATION..10
Chapter 1 INTRODUCTION.11
1.1 Introduction and Motivation.11
1.2 Background literature survey.12
1.3 Thesis contribution...16
Chapter 2 ARCHITECTURE DESCRIPTION..17
2.1 Introduction..17
2.2 Working of switched capacitor.17
2.3 Proposed architecture19
2.3.1 Analog to digital converter20
2.3.2 Gain select21
2.3.3 Counter..22
2.3.4 Phase Trigger Unit...23
2.3.5 Phase Control Logic24
Chapter 3 SCHEMATIC AND TRANSIENT RESPONSE27
3.1 Analog to digital converter..27
3.2 Counter....30
3.3Phase Control Logic.32
3.4 Gain select.....34
3.5 Proposed architecture36

Chapter 4 RESULTS AND DISCUSSION.42

Chapter 5 CONCLUSION...44
REFERENCS...45

LIST OF FIGURES
Fig. 2.1 Switched capacitor..17
Fig. 2.2 Switched capacitor with gain a) 1 on, b) 2 on..18
Fig.2.3 Switched capacitor with 2/3 gain configuration..............18
Fig.2.4 switched capacitor with 2/3 gain during a) 1 on, b) 2 on...19
Fig.2.5 Block diagram of proposed dc-dc architecture....19
Fig. 2.6 Two stage CMOS comparator....................20
Fig. 2.7 Analog to digital converter with reference select logic.....21
Fig. 2.8 Gain select block....22
Fig. 2.9 4-bit counter.......22
Fig. 2.10 Phase trigger unit.....24
Fig. 2.11 Phase control logic block....24
Fig.2.12 Phase control logic......25
Fig.2.13 Phase signal logic for low voltage......26
Fig.3.1 Schematic of ADC and reference select logic..27
Fig.3.2Schematic of two stage comparator...28
Fig.3.3 Transient response of ADC and reference generator block.....29
Fig.3.4 Schematic of 8-bit counter.......30
Fig.3.5 Transient response of counter.......31
Fig.3.6 Schematic of phase control logic.32
Fig.3.7 Transient response of phase control logic33
Fig.3.8 Schematic of gain select block..........34
Fig.3.9 Transient response of gain select block...35

Fig.3.10 Schematic of proposed architecture...36

Fig.3.11 Transient response of proposed architecture for variable input frequency....37
Fig.3.12 Transient response of converter for 0.6V output voltage...38
Fig.3.13Transient response of converter for high frequency...39
Fig.3.14 Transient response of converter for low frequency...39
Fig.3.15 Transient response of converter (rising edge)40
Fig.3.16 Transient response of converter (falling edge)..41

LIST OF TABLES
Table 1 Truth table for gain signals.23
Table 2 Comparison with previous work43

LIST OF ABBREVATIONS
SC

Switched Capacitor

ADC

Analog to Digital Converter

PTU

Phase Trigger Unit

PFM

Pulse Frequency Modulation

PDWM

Pulse Density and Width Modulation

DCpM

Digital Capacitance Modulation

10

Chapter1
INTRODUCTION AND BACKGROUND
1.1 Introduction and Motivation
Recently many portable devices introduced in the market are having
multifunction modules which require different power supply levels. And also as size
of the MOSFET transistor reduces the power supply voltage is also scaled down
below 1V.Conventional DC-DC converters suffer from electromagnetic interference
noise due to presence of inductor component and off chip converter increases the area.
SC based DC-DC converters can be integrated on single chip because they dont have
any inductor. Step down SC DC-DC converters are mainly used in most of the
systems but step up converters are also required in some of the systems because for
many high precision analog and mixed-signal circuits, higher supply voltages are
required. For step up converters voltage doubler circuit and close loop system is used
not only to reduce ripple in output voltage but also to get fast transient response
[1,7].Similarly some step down converters also use close loop system to reduce ripple
and fast transient response[2,4,6,9]. In SC DC-DC converter different non
overlapping signals are used to control the switches. Output voltage ripple depends
upon the switching frequency fsw, load capacitor CL and IL current as described below.

Vripple

IL
2 CL fsw

.. (1)

The ripple can be reduced by increasing switching frequency fsw but it reduces
the power efficiency. To overcome this limitation some of the converters vary the
switching frequency depending upon the output [2, 3, 6, 9,10] but still some
converters use fixed switching frequency architecture [4,5,8].To change the switching
frequency some converters uses different modulation technique such as pulse density
and

width modulation(PDWM),digital capacitance modulation(DCpM) or pulse

frequency modulation(PFM). Also as load on the converter varies the output current
and voltage also varies hence the transient response of the converter should be fast
otherwise ripple at the output voltage increases.

11

1.2 Background Literature Survey

In step up switched capacitor DC-DC converters cross coupled voltage
doubler circuit is popular because of its high efficiency [1,7]. A fully digital
interleaving scheme is used to control the phase signals which help to reduce ripple in
output voltage [1,7].All the phase signals generated by interleaving scheme are nonoverlapping. Main charge pump circuitry is having a parallel connection of two cross
coupled cells. To detect the error in output, feedback from output to the digital
hysteretic controller is given. Digital hysteretic controller consists of ring oscillator
based A/D converter. Close loop system with hysteretic controller is help to regulate
the output voltage. The system is more robust to the noise and device failure but if
there is a large variation in the load, the output ripple increases. And also PMOS in
the charge pump circuit requires double voltage than NMOS to switch on or off hence
additional voltage boosting circuit is required. For step down SC converter double
bound hysteretic regulation scheme is used in [2].The main block of this design is 4phase 2:1 SC converter. Hysteretic controller uses a lower bound and upper bound
comparator in order to control SC converters switching frequency and reconfigure
the number of interleaved phases respectively. When the output voltage is less than
the reference voltage then the switching frequency increases and output ripple
decreases. Similarly, when the output voltage is greater than the reference voltage
then number of interleaved phases is decreases. This converter gives very low ripple,
high switching frequency as well as fast transient response. But to decide lower and
upper bound three different DC reference voltages are required.
Switched capacitor DC-DC converter with pulse frequency modulation (PFM) is
described in [3]. In this design n-stage SC converter are connected in series each
having capacitor C1-Cn-1.This capacitor has n modes in one cycle. Initially all
capacitors C1-Cn-1 are charged serially, then by discharging capacitor one by one to
the load at a different time lower output ripple is achieved. Switching frequency is
controlled through PFM control scheme. An error amplifier is used in PFM control
scheme to sense the output voltage and produce error signal. With this error signal
PFM oscillator circuit changes the switching frequency. Besides, a separate digital
circuit is use to get fix duty cycle for optimum efficiency. Previously input current
12

control scheme is use to get fix duty cycle but it makes the switches work in
saturation region which increases conduction loss and reduces efficiency. The
advantage of this design is, the switches can work in triode region to reduce the
conduction loss and get a wider load region. A SC DC-DC converter with dual-cell
power stage is explained in [4].In this architecture SC converter consists of two
identical sub-cells connected parallel in between input and output. Each cell has two
pumping capacitors and the gain of cells can be adjust to 1, 2/3, and 1/3 with the
switches. Digital controller is use to control the phase signals to the sub-cells, this
controller is combination of adaptive gain control (AG) and adaptive pulse control
(AP) which is explain later. The two sub-cells operates alternately, when one cell is
charging phase and disconnected from output other is in discharging phase and
regulates the output. In charging phase pumping capacitors are in parallel with input
and output, the current flows from input to the capacitors and in discharging phase
capacitors are in series with the output. The efficiency of the converter can be
decreased due to the variation in input power supply. To overcome this adaptive gain
control (AG) is introduced in the feed forward path of the converter. If load is heavy
then supply voltage can not provide sufficient energy that time AG converts the gain
of cell to higher level. And if the load is light fast switching frequency increases the
power consumption which reduces efficiency hence adaptive pulse control (AG) is
used in feed back path. AG controls the pulses to the converter which reduces the
switching frequency in case of light load. But due to presence of the dual cells
component required are double as compare to the single cell design.
A dual switched capacitor based DC-DC converter is explained in [5]. These
two SC circuits are connected in parallel. Switches in the SC circuits are controlled by
the two non overlapping phase signals. A pass transistor is connected between the SC
circuits and the output. A negative feedback is given to the gate of pass transistor
through an error amplifier. In this design a flying capacitors of an equal size are use
instead of charge storing capacitors which are use in typical SC circuits. Switching
these flying capacitors in opposite phases helps to maintain output voltage at half of
the input voltage. Also use of the dual switched capacitor helps to keep input supply
current steady state. To avoid the short circuit current through various switches a non
overlapping phase signals are used but due to this there is a momentary inflow current
deficiency at the pass transistor terminal. To overcome this, another transistor is
13

connected between input and pass transistor terminal which is controlled by the pulse
generator. The disadvantage of this design is its low efficiency and also if there is
slight variation in the input voltage the output ripple increases drastically. To reduce
output ripple a pulse density and width modulation (PDWM) is also use in converters
[6]. The core of this scheme is switch matrix which consists of charge transfer
capacitors and charge transfer switches. The pulse density modulation (PDM) based
scheme is use to generate non overlapping clock signals which regulate the output
voltage. A comparator is use to compare a reference voltage and output voltage. If
output voltage is above reference voltage the clock signals are paused and if output is
below reference voltage clock signals are transferred to the switch matrix which
charge up the load capacitors. To reduce output ripple a pulse width control block and
look up table are introduced to control circuit. Only one switch connected to the input
is controlled by the PDM controller. By controlling the pulse width to switch power
transferred from input to the capacitor can be controlled precisely. A LUT gives 4-bit
control signal to pulse width controller which determines the pulse width according to
the values of output current and voltage. In low voltage region above design reduces
output ripple by 57% but efficiency also reduces by 2%.
A digital capacitance modulation (DCpM) technique is used instead of pulse
frequency and width modulation to maintain regulation in output [8]. In this scheme
width of the charge transfer switches can be change as the capacitance scaled. The
output regulation is maintained by the changing the capacitance that takes part in
charge transfer process. Total charge transfer capacitances are broken into binary
weighted banks of sizes 8X, 4X, 2X, 1X which are course controlled and 1X FINE
which is fine controlled .In each bank, size of the charge capacitor as well as width of
the switch changes such that every bank has equal charge and discharge time .1X
FINE is further divided to the three capacitance values from which one capacitance is
always engaged and other two are select by fine signal .Course and fine control
signals are generated by the DCpM mode controller. Course signal is of 4 bit which is
use to select course bank and 2 bit fine signal selects fine bank. By controlling 4 bit
course signal and 2 bit fine signal the converter changes the amount of capacitor used
for charge transfer. The switching frequency is constant in this scheme. The DCpM
scheme is helps to get the fast transient response but the switch corresponds to
capacitor banks are switching on and off constantly hence switching losses can not be
14

brought down below certain level. Another disadvantage is that when load current
decreases, due to constant switching frequency efficiency of the design also
decreases. To overcome this, the controller switches to the PFM scheme whenever the
load current goes down below certain level to reduce switching loss and to improve
efficiency.
Another method in which number of interleaved phases is change to reduce
output ripple is described in [9]. In this scheme four 2:1 SC DC-DC converters are
used. Each SC converter is consists of 2 NMOS, 2 PMOS and a charge transfer
capacitor C. Two non overlapping switching signals are used to control the switching
of the transistors. 2:1 SC converter operates in two phases in phase one charge
transfer capacitor get charged through input and in phase two it get discharged to the
load capacitor CL making output voltage half of the input if C and C L are equal. The
relation between output ripple and switching frequency is given in equation 1, as the
switching frequency increases output ripple decreases. In this architecture four such
2:1 SC converters and a controller is use to regulate the output. The controller use to
turn on or off the SC converter depending upon the output current. In controller a
comparator is used to compare output voltage with the reference voltage. When
output voltage is less than reference voltage then the controller increases the number
of interleaved phases, and if output is lager than reference, number of interleaved
phases is reduced. Controller also changes the switching frequency depending upon
interleaved phases. If interleaved phases are less then controller increases the
switching frequency to reduce output ripple. Due to load variation if output load
current decreases the controller turn on the single SC converter unit output current get
strong enough. In the controller flash A/D converter and look up table generates the
control signals. Look up table has pre characterized data for regulated output.
Capacitor used in this converter is metal-insulator-metal capacitor (MIM). Output
voltage generated by this converter is not exactly half of the input because of the
parasitic of switches and capacitors.
Switched capacitor DC-DC converter with dual output voltage is discussed in
[10]. In this architecture combination of two conventional 2 to 1 step down topology
is used to generate 4 to 3 step down topology. 2 to 1_up converter gives the upper
voltage and 2 to 1_down converter gives lower voltage. To control the switch
capacitor non overlapping phase signals are used. MIM and MOS types of capacitors
15

are used in this design. 2 to 1_up converter is discharged to the load due to which it is
less sensitive towards bottom plate parasitic capacitance loss hence MOS capacitors
are used in this converter. 2 to 1_down converter is discharged to the ground hence it
is more sensitive to the bottom plate parasitic loss. To reduce this loss MIM
capacitors are used in down converter. The output of converter is regulated by pulse
frequency modulation (PFM) technique which consists of 18 bit registers and digitally
controlled oscillator (DSO). This architecture gives two different voltages at the same
time and its switching frequency is also very high.

1.3 Thesis Contribution

The working principle, advantages and drawbacks of the switched capacitor
based dc-dc converter is understood. A architecture is proposed to achieve low output
ripple and fast transient response. The proposed design down converts input supply of
1.8V to the 0.6V and 0.8V output voltages depending upon the input signal frequency.

16

Chapter 2
ARCHITECTURE DESCRIPTION
2.1 Introduction
This chapter includes basic working principle of the switched capacitor circuit
with different gain circuitry. PMOS and NMOS transistors are used as a switch to
charge and discharge the capacitor respectively. The load capacitor of 1pf is used. The
proposed architecture is explained in the next section.

2.2 Working of switched capacitor

The switched capacitor circuit made up of a fly capacitance and switches as shown
in figure below.
Vin

Cout

C
2

Vout

Fig. 2.1 Switched capacitor

The gain of above circuit is i.e the capacitors charges up to half of the Vin. The
phase signals 1 and 2 are two non overlapping signals which are used to charge
and discharge the flying capacitor respectively. When 1 is on the flying capacitor
and load capacitor are in series, both gets charge up to the Vin/2 voltage. When 2 is
on the flying capacitor and load capacitor both gets discharge in series. When 1 is
on 2 is off and vice a versa. This charging and discharging of capacitor results in the
ripple at the output voltage which can be reduced by increasing switching frequency
of phase signals. The charging and discharging of switch capacitor is as shown in
figure below.

17

Vin

Vout
Cout

Cout

C
2

Vin

Vout

Fig. 2.2 Switch capacitor with gain during a) 1 on, b) 2 on

The gain of the switch capacitor can be adjusted with the different configurations of
flying capacitors and switches. A configuration of switch capacitor for gain of 2/3 is
as shown in figure below.

Vin

C
3

1
Vout
5
Cout

C
2

Fig. 2.3 switch capacitor with 2/3 gain configuration

In this configuration the charging and discharging of the flying capacitor is takes
place with phase signals 1 and 2 respectively. The switch 3 and 4 are always at
off state. During charging phase signal 1 is on and flying capacitors get connected in
parallel. This combination is in series with load capacitance Cout. The phase signal
5 and 2 are on during the discharging phase and all capacitors get discharged in
series. The charging and discharging phase are as shown in figure below.

18

Vin

2
Vin

C
3

Vout

Vout

Cout
1

Cout

C
2

Fig. 2.4 Switch capacitor with 2/3 gain during a) 1 on, b) 2 on

2.3 Proposed Architecture

Vout

Switched
Capacitor

Vin

2
1
Phase control
logic

Phase Trigger
Unit

ADC
And
reference
select logic

Gain
select

Counter

clk

Fig. 2.5 Block diagram of proposed dc-dc converter

19

Block diagram of the proposed dc-dc converter architecture is as shown in figure 2.5
above. The architecture is mainly consists of

Analog to digital converter

Gain select

counter

Phase trigger unit

Phase control circuit

2.3.1 Analog to digital converter

A 2 bit analog converter is used in feedback to control the switching activity of
the phases. This ADC block consist of a resistance network which helps to generate
reference voltages, a digital logic which gets the input from gain select block and
comparators which generates output bits. The digital logic in this block gets input
from the gain select and changes the reference voltage at the input of the comparator.
This reference select logic consists of the multiplexers which generates required
reference voltages with the help of resistance network. The resistance network is
arranged so that the difference in the voltage at the input of the comparator is around
7 mV which helps to reduce the output ripple. The comparator is consists of
differential amplifier followed by the common source amplifier. The schematic of the
comparator is as shown in figure below.
Vdd

Vn
Vout

Vp

Vbias

Gnd

Fig. 2.6 Two stage CMOS comparator

20

To operate this circuit as comparator all transistors must be in saturation region

hence a bias voltage of 0.5 V is applied which puts all transistors in saturation region.
Two such comparators are used in ADC to generate two bit output. A digital circuit
and resistance network is use to sense the output voltage. As soon as the required
voltage level reached at the output the ADC generates two bit output which is then
given to digital circuit block as shown in fig 2.5. The block diagram of two bit ADC
is as shown in fig 2.7.
Vout

Reference select logic

Fig. 2.7 ADC with reference select logic

2.3.2 Gain select

The gain select block takes the 4 bit input from the counter and generates output
G. The block diagram of gain select logic is as shown in figure below. If the input
signal frequency is high the number of pulses count by the counter is low and for the
output signal G sets to high. For high number of count the signal G sets to low. This
signal acts as an input to the ADC block which helps to select reference voltage
through the reference voltage select circuit.

21

Q0-Q3

Gain Select

Fig. 2.8 Gain select block

2.3.3 Counter
The counter is use to count the number of the pulses in one cycle of the input
signal which decides the frequency of the input signal X. Counter gives 4-bit output
(Q0-Q3)which is then acts as an input to the gain select block. The system clock is
given to the counter and input signal X acts as reset signal to the counter. At the end
of input signal pulse the counter is reset and the count is stored in D flip flop register.
For high frequency signal the count is low and hence the output voltage is high. When
input frequency is low the counter value is high and the output is low. The input
signal frequency varies from 12.5MHz to 25MHz and the centre frequency is 15MHz.
For all the signal frequency above 15MHz the output is 0.8V and for output is 0.6V
for all the frequencies below 15MHz. By increasing the number of output bit the
range of the frequency can be increases.
The block diagram for counter and the truth table for counter and gain select block
is as shown in table below.

Q0
X
Q1
4-bit Counter
Q2
clk
Q3

Fig. 2.9 4-bit counter

22

Table.1.1 Truth table for gain signals

Counter output

Gain signal

Q3

Q2

Q1

Q0

2.3.4 Phase Trigger Unit

The Phase Trigger unit (PTU) block consists of trigger signal generator logic
which drives the phase control unit. The output from the ADC block is given to this
phase trigger unit and two input nand gate. Two bits signal generated by ADC, U and
L is MSB and LSB respectively. When the output signal reaches to the lower
threshold L bit goes high and as soon as the output reaches to the upper threshold the
U bit goes high. The voltage difference of 7 mV is adjusted by the resistance network
and comparator itself. As soon as the both signal goes high the triggering takes place
and triggering signals are then send to the phase control. The block diagram of phase
trigger unit is as shown in figure below.

23

To Phase control unit

Input from ADC
Phase Trigger Unit

Fig. 2.10 Phase Trigger Unit

2.3.5 Phase Control Logic

Phase control block is a simple 2:1 multiplier which takes the select line input
from the phase trigger unit. One input to this multiplexer is simple high frequency
pulses from the counter and other is NAND of the both output of analog to digital
converter (U and L bits). The phase signals 1 and 2 generated by this block use to
control the charging and discharging of the switched capacitor. Phase signal 1 is
connected to the PMOS and 2 is connected to the NMOS of the switched capacitor
.The block diagram of phase control logic is shown in figure below.

Phase control logic

Trigger signal
Fig. 2.11 Phase control logic block

24

The Phase control logic block mainly consist of a network of 2:1 muxs one after the
other. As mentioned earlier the two bits from ADC are NANDed together and acts as
the select line input to the lower mux. The logic diagram of the Phase control block is
as shown in figure 2.12.

Phase signal

2:1

2:1

i/p from PTU

2:1

Fig. 2.12 Phase control logic

Initially when the output is low both U and L signals from ADC are low and the
signal from PTU selects the upper and lower voltage. For high voltage output the
upper mux selects pin is low and the phase signal is connected to the ground and
hence PMOS is switched on in SC hence charges the flying capacitor. When the
output reaches to the threshold voltage level both U and L pins goes high and pulse
signal of 1ns period is connected to the SC which keeps the output voltage to the 0.8V
level with the ripple of 7mV. For the lower output voltage the SC circuit try to reach
the half of the input voltage (0.8V) hence to keep the voltage lower than the 0.8V the
phase signal of different pulse width is given to the SC circuit. The charging and
discharging of the SC circuit is different. Discharging of the capacitor is much slower
than charging hence a phase signal with duty cycle of 75% is applied to the converter.
25

When the U and L bits are low the phase signal of 1ns is applied as soon as both
signals goes high a pulse of 75% duty cycle is applied to keep output voltage to 0.6V.
This pulse is generated by ORing a 1ns and 2ns period signal generated from the
counter is as shown in figure 2.13 below.

2ns
2ns

1ns

Fig. 2.13 Phase signal logic for low voltage

As mentioned above when the phase signal is low the PMOS is on and the charging
takes place. When the output reaches to the 0.6V the phase signal of 75% duty cycle
is applied to the converter. The off period is 0.5ns and on period is 1.5ns hence the
proper discharging takes place and gives the output ripple of 7mV.

26

Chapter 3
SCHEMATICS AND TRANSIENT RESPONSES
3.1 Analog to digital converter
As mentioned in chapter 2 ADC block is mainly consist of comparator and
resistance network. Resistances are of value 1K ohm and 2k ohm in R-2R ladder
structure. This network helps to generate a reference voltage for the comparator. The
arrangements of these networks are such that the difference in the voltages is of 7mV
which helps to reduce the ripple in output voltage. The reference select logic circuit is
use to select reference voltage to the comparator through the mux. The schematic of
ADC and reference select block is as shown in figure 3.1 below.

Fig. 3.1Schematic of ADC and reference select logic

27

The comparator used in this ADC is simple two stage amplifier in which
differential amplifier is first stage followed by the common source amplifier as second
stage. First stage gives amplifies the difference of the input signals and second stage
is just to increase the intermediate signal strength. A schematic diagram of two stage
comparator is as shown in figure 3.2 below. To operate this circuit as a comparator all
transistors must be in saturation region hence a bias voltage source of 0.5V is
connected which helps to put all transistors in saturation region. A current mirror
circuit can also use but for this purpose other current source is required for bias
current generation instead of voltage source. The offset voltage of comparator is
30mV which can be reduced by increasing the number of stages. Offset voltage can
also be reduced by using preamplifier stage.

Fig. 3.2Schematic of two stage comparator

28

Analog output of the converter and gain signal acts as input to the ADC block.
ADC block generates two bit output U and L where U is MSB and L acts as LSB bit.
The transient response of ADC and reference select block is as shown in figure 3.3.

Fig. 3.3Transient response of ADC and reference generator block

During a charging phase the output charges rapidly and the ADC converts it to the
digital value. When it reaches to the threshold value both of the bits goes high and
conversion stops. The transient response in figure 3.3 shows that the upper bit of the
ADC stats to rise later than the lower bit. The voltage difference of 7mV is adjusted
between these two bits with the help of resistance network. Transient response shown
in figure 16 is for low voltage. The output voltage shows a ripple of 7mV and it is not
stable at 0.6V due to discharging of the capacitors.

29

3.2 Counter
8-bit counter is used for gain selection and to generate multiple of a clock
frequency signal. In gain select block pulses of the variable input signal frequency is
counted by the counter. Another 8 bit counter is used to give multiple of the clock
frequencies to the phase control block. Clock frequency for the counter is 1GHz. A
schematic of 8-bit up-down counter is as shown in figure 3.4. Counter consists of
simple one bit adder, one bit subtracter, mux ,D flipflop and inverters. A cntrl signals
is use for up (cntrl=0) and down (cntrl=1) count. A default output value of D flipflop
is high hence an inverter is connected after each of the flip flop to start the counter
with zero value.

Fig. 3.4Schematic of 8-bit counter

Transient response of the counter is as shown in figure 3.5. The cntrl pin is low
hence the counter is in up count mode. The clock frequency of counter is 1GHz,
30

counter acts as a frequency divider hence the minimum output frequency of counter is
3.9 MHz. Two outputs of the counter q0 and q1 are use by the phase control unit to
change the duty cycle of the phase signal as discussed in chapter 2. These two signals
are ORed together to get a phase signal of 75% duty cycle. In gain select block an
input signal X acts as a reset signal to the counter. For frequency divider reset signal
is not necessary. A positive edge triggered D flip flop used in the counter is made up
of a simple master slave negedge trigger D latch and posedge triggered D latch
respectively.

Fig. 3.5Transient response of counter (up)

31

3.3 Phase Control Logic

The charging and discharging time of the SC circuit is different because of the
different resistance values of PMOS and NMOS transistors. Also phase control logic
block is necessary for switching the output from different level. Phase control logic is
mainly consists of series of 2:1 multiplexers in series. Phase trigger block gives the
input to the phase control logic which gives the output as phase 1 and 2.
Multiplexers used in this design are made up of transmission gate logic. The phase
signal generated by this block is connected to both PMOS and NMOS transistors.
When the phase signal is low PMOS is on and SC circuit is in charging mode. For
high value of the signal NMOS is on which discharges the capacitor. The OR gate is
used in the same block to generate a phase signal of 75% duty cycle for the low
output voltage. The NANDed signal of upper and lower bit of the ADC is one of the
select line input to multiplexer. The schematic of phase control logic is as shown in
the figure 3.6.

Fig. 3.6Schematic of Phase control logic

32

Transient response of the phase control logic block for output voltage of 0.6V is
shown in figure 3.7.As mentioned earlier for lower output voltage a phase signal of
75% duty cycle is used. When the output voltage is low the multiplexer gives the
phase signal as low which turn on the PMOS of SC circuit and it charges the flying
capacitor. The signal r in the figure below is generated by NANDing upper and lower
bit of the ADC hence when the threshold voltage reaches both the bits are high and
signal r goes low .When this event occurs the multiplexer gives the phase signal of
75% duty cycle. The variation of the phase signal can be observed in the figure 3.7.
The clock frequency of 1GHz as well as the multiple of the signal of 0.5 GHz
frequency from the counter is applied to the phase control logic.

Fig. 3.7Transient response of phase control logic

33

3.4 Gain select

Output of this block is depends upon the frequency of input signal X. For the high
frequency output is high and for the low frequency signal output is low. The gain
select block is consists of 8 bit counter and PIPO registers. Input signal X acts as a
reset to the counter but it acts as a clock signal to the PIPO registers. The schematic of
gain select is shown in figure 3.8. When the input frequency is low the count is high
and as soon as the input signal X reaches to its positive edge the PIPO register holds
the value of the counter. For signal frequency above 15MHz the output is high and all
frequency below 15MHz the gain signal is low. By considering higher bits of the
PIPO register the range of the frequency can be extended. But the maximum limit of
the input frequency can be 500MHz because the clock frequency of the counter is
1GHz if the input signal frequency goes higher than 1GHz counter will give wrong
count for every cycle.

Fig. 3.8 Schematic of gain select block

34

The input signal X for the gain select block is generated by variable frequency
generator which is explained in this chapter later in section 3.6. Transient response of
the gain select logic is shown in figure 3.9. The input signal frequency from the
variable frequency generator changes from 12.5MHz to 20MHz. As the shown in
figure 3.9 for frequency below 15MHz i.e for 12.5 MHz the gain output is low and for
frequency above 15 MHz i.e for 20 MHz gain signal is high. To select the gain r3 bit
of PIPO register is used. If the higher bits are used for gain select the range of the
input signal frequency can be increased. As the logic goes for the higher bits the lower
frequency range reduces and the operating range of the frequency increases. The
transient response shows that when the input signal frequency changes the gain select
block takes only half of the cycle of input signal to change the gain. As soon as the
next positive edge of the signal is received the gain changes.

Fig. 3.9 Transient response of Gain select block

35

3.5 Schematic of proposed architecture

The schematic of dc-dc converter is designed in 90 nm technology and the input
supply voltage is of 1.8V. Schematic diagram of the proposed architecture is as shown
in figure 3.10 below. Capacitance of 1pf is used in switched capacitor circuit for
flying as well as load capacitor. Input to the design is signal of variable frequency,
clock and power supply voltage. As discussed in chapter 2 by using different
combinations of the switches the gain of SC circuit can be adjusted. The gain setting
of 1:2 is used in proposed architecture hence maximum output of 0.8V is available at
the output. By changing gain setting to the 2:3 output voltage can go up to 1.2V. The
number of switched capacitor circuit used in the converter can be increases to increase
the output current. If the output load current increase the voltage at the output
decreases to restore the value of the output number of the SC circuit can be changed.
The output ripple is also depends upon the output load current IL as discussed in
chapter 1 equation 1.

Fig. 3.10 Schematic of Proposed architecture

36

In the proposed architecture the duty cycle of the phase signal is changed to reduce
the output ripple. The relation between the switching frequency of the phase signal
and ripple is as shown in equation 1. As the switching frequency increases the output
ripple decreases and vice a versa. But for the low voltages the duty cycle of the phase
signal should be changed to reduce ripple in output voltage. The proposed architecture
is tested with variable input signal frequency changing from 12.5 MHz to 20 MHz.
Transient response of the architecture is as shown in figure 3.11. The discharging time

Fig. 3.11 Transient response of proposed architecture for variable input frequency

of SC circuit capacitance is higher than the charging time hence output takes more
time to fall from higher voltage level to lower level. But the rise time of the output
voltage is very high and can be seen in transient response above. The output ripple of
the converter is about 7mV. The transient response for 0.6V is as shown in figure
37

3.12. The maximum and minimum variation of output voltage is marked by the cursor
which shows that the output voltage ripple is around 7mV.

Fig. 3.12 Transient response of converter for 0.6V output voltage

Fig. 3.13 Transient response of converter for high frequency

38

Transient response of the design for the higher voltage i.e 0.8V is as shown in
figure 3.13. In this response the gain signal is high and the input signal frequency is
above 15MHz.

Fig. 3.14Transient response of converter for low frequency

Figure 3.14 shows the total response for the 0.6V output voltage along with the 2bits of the ADC. The slew rate of the comparator used in ADC block is very slow.
Because of this reason the transient response of ADC output shown in figure 3.3 takes
time to rise. A buffer circuit is connected to the output of the ADC U and L bit which
increases the rise time of the signal.

A buffer circuit consists of two inverters

connected back to back fashion.

Transient response of the converter for variable input frequency is show in figure
3.11. It can be observed from the response that the discharging time of the converter
is higher than the charging time. Figure 3.16 shows the transient response of converter
for changing output voltage from higher voltage to the lower voltage.

39

Fig. 3.15 Transient response of converter (rising edge)

The converter takes 18ns to changes from lower voltage level to higher level.
Transient response of converter for variable frequency is as shown in figure 3.15.
Charging and discharging time of converter is different because of the resistance of
the PMOS and NMOS transistors during on state. By increasing the width of the
transistor the resistance can be reduced which is then reducing the rc time constant of
the converter

40

Fig. 3.16 Transient response of converter (falling edge)

Figure 3.16 shows the transient response of converter for changing output
voltage from higher voltage to the lower voltage. As mentioned earlier the dischrgibg
time of the convert is more. It takes about 20ns to discharge from 0.8V to 0.6V. The
gain signal is changing according to the input signal frequency.

41

Chapter 4 RESULTS AND DISCUSSION

The dc-dc converter with proposed architecture gives dual output voltage of 0.6V
and 0.8V with input voltage of 1.8V. The voltage doubler dc-dc converter in [1] gives
two output voltages of 1.6V and 2.7V from 1.5V but the results for output ripple and
transient response of this converter is better. Converter mentioned in [9] reduces the
ripple voltage but the transient response of the converter is very slow as compared to
the proposed architecture. Converter in [4] gives the single output voltage of 1.5V
from the input voltage of 3.3V which reduces the output ripple up to 7mV but the
transient response of converter is 13s.Architecture in [6] gives two output voltages
of 0.2V and 0.47V but gives the output ripple of 23mV which is very high as
compared to this design.
The comparison of different SC based dc-dc converter is listed in Table 1. The
proposed architecture supports the step down conversion with minimum output ripple
of 7.3mV and transient response of 18ns.
Table 2 Comparison with previous work

Design

[1]

[7]

[8]

[9]

[10]

This
work

Technology

350nm

350nm

45nm

45nm

350nm

90nm

Output ripple

20mV

40mV

50mV

15mV

40mV

7.3mV

Transient
response

2000ns

2000ns

120ns

200s

450ns

18ns

Switching
Frequency

0.5MHz 0.5MHz 8.33MHz 5KHz 2.22MHz 55.5MHz

42

Chapter 5 CONCLUSION
The switched capacitor DC-DC converter architectures are reviewed and the
results are compared. The switch capacitor DC-DC converters with the fixed
switching frequency scheme give the low efficiency but the switching frequency is in
the range of MHz. Also the output ripple in these schemes is high. The converter with
variable switching frequency architecture give high efficiency with low output ripple
and switching frequency is in the range of MHz. The step up switched capacitor
converters gives moderate efficiency and output ripple. In this project a switched
capacitor based dc-dc converter with dual output voltage of 0.6V and 0.8V from input
voltage of 1.8V is designed. As the input signal frequency changes the output voltage
also switches to different values. While switching from high to low voltage phase
control block change the duty cycle of the phase signal to reduce ripple in output
voltage. The minimum output ripple if converter is 7.3mV with the transient response
of 18ns.

43

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[9] Jung, I. -. Kim, Y. -., & Choi, M. (2011). The novel switched-capacitor DC-DC
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