Design Guidelines to Implement Six Sigma in Assembly Process

Yield of Area Array Solder Interconnect Packages

Chunho Kim and Daniel F. Baldwin, Ph.D
Packaging Research Center and
Advanced Assembly Process Technology (AdAPT) Laboratory
The George W. Woodruff School of Mechanical Engineering
Georgia Institute of Technology
813 Ferst Dr. NW, Atlanta, GA 30332-0405
Phone: 404-894-4135, Fax: 404-894-9342,
Email: Daniel.Baldwin@me.gatech.edu

Abstract
Area array solder joints are difficult to visually inspect
because solder joints are very tiny and covered by the chip. It
may result in the increase of the interconnect defects passing
the inspection step. Those defects become evident in later
process steps or in the testing of the finished product. Since
reworking of area array interconnects is very difficult and
costly, interconnect yield is the crucial issue that determines
the final product cost. The significance of interconnect yield
becomes obvious as the demand on area array packages is
growing. Therefore, it is essential to reduce the yield defects
as close to zero as possible. The objective of this paper is to
suggest design guidelines to implement Six Sigma, i.e., llss
than 3.5 defects per million in the assembly process of area
array solder interconnect packages. For that purpose, the
parameters impacting on interconnect yield are identified, the
cause and effect relationships of design and process
parameters to interconnect yield are analyzed, and the process
design rules to statistically achieve Six Sigma are developed
in general and explicit forms.
Introduction
The past decade has witnessed continual miniaturization,
performance growth and cost reduction of electronic
components. As the trend toward small size, high performance
and low cost continues, a paradigm shift from wire bonding
and TAB to area array interconnect has become inevitable in
electronic interconnects [ 13. According to the Semiconductor
Industry Association (S1A)s techology roadmap, chips with
2400 I/Os and 1400MHz clock speed are forecast to be in
volume by the year 2001. The IlO count and the frequency
demanded are beyond current wire bonding or TAB
capabilities. To make these types of ICs possible, area array
solder bumped interconnect technology provides a viable
answer to the needs. In comparison with the popular wirebonding technology, area array solder bumped interconnect
technology provides greater 1/0 density and shorter electrical
path with less propagation delay.
Electronic packages using area array interconnect have
been rapidly growing. According to the source provided by
Prismark, the number of packages using area array
interconnect including DCA Flip chip, BGA, CSP and PGA is
forecast to be more than 10 billion by the year 2003. In
addition, area package units are estimated at 87% of all
electronics packages with more than 209 I/Os. As the demand
on area array interconnect increases, interconnect yield
0-7803-7430-4102/$17.0002002 IEEE

becomes a crucial issue that could affect the economic success

or failure in cost competition.
Area array solder joints are difficult to visually inspect
because solder joints are very tiny and covered by the chip.
Although x-ray microscopy and electrical continuity tests are
employed to detect solder interconnect defects, the detection
capability for area array interconnects seems to be limited. It
may result in the increase of the interconnect defects passing
the inspection step. Those defects become evident in later
process steps or in the testing of the finished product. Since
reworking of area array interconnects is very difficult and
costly, interconnect yield is the crucial issue that determines
the final product cost. The significance of interconnect yield
becomes obvious as the product volume increases. Assuming
the total product volume is 10 billions, only 1% interconnect
failure rate would give rise to a huge economic loss.
Therefore, it is essential to obtain close to 100% interconnect
yield for the area array interconnect packages being in
growing demand.
The objective of this paper is to suggest design guidelines
to implement Six Sigma, i.e., less than 3.5 defects per million
in the assembly process of area array solder interconnect
packages. For that purpose, the parameters impacting on
interconnect yield are identified, the cause and effect
relationships of design and process parameters to interconnect
yield are analyzed, and the process design rules to statistically
achieve Six Sigma are developed in general and explicit
forms.

Assembly Process of Area Array Solder Interconnect

Packages
.
The assembly process starts with a bare board entering the
placement tool. The chip is first picked from a feeder medium,
such as waffle pack feeders, tape and reel, surf tape or a direct
wafer feeder. The chip then taken over to stationary camera or
imaged by an on-board camera located in the placement head
chassis. The relative position and rotation of the chip are
recognized by processing the image taken. The chip is then
either dipped into a thin film flux bath, or flux is dispensed on
to the chip bond site (Fig. 1). Next, the chip is taken to the
board, the local fiducial for the chip bond site is imaged, and
the reference position for the chip alignment with the substrate
pads is computed based on the image. Then the chip is placed
on the bond pad position at the programmed distance off the
reference position. The assembly is next reflowed in a reflow
oven where the eutectic solder bumps melt and wet the

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substrate pads. In the reflow over, the eutectic solder bumps

reach 183C in which the state changes from solid to liquid.
During this change of state, the solder wets out the substrate
pads and the chip self aligns driven by the surface tension
force of the liquid solder. After reflow, the assembly is
cleaned to remove flux residues and can be functionally tested
at this point. Next, underfill is dispensed along the side of the
chip. Capillary action draws the underfill under the chip.
Finally, the assembly is taken offline and placed in a batch
oven to cure the underfill. Aitematively, an in-line convection
oven can be used to cure the underfill.

(a) fluxing (dip/dispense)

(c) reflow

(b) placement

(d) test

(e) underfill

Figure 1. Assembly process of area array solder

interconnect

Interconnect Yield Definition

Interconnect yield may be defined as the ratio of the
number of good interconnected chips produced to the total
number of chips started in assembly process. Good
interconnected chips in this definition may be defined in terms
of either functionality or reliability. The former means having
no fatal defects that would cause immediate rejection and the
latter means having no potential defects that would be evident
afterward. Electrical continuity test may be employed to detect
functional defects and burn-in test or shear strength test to
detect potential defects.
It can be shown that functional interconnect success in the
assembly process of area array packages is obtained only
when all of the following three steps are successfully
accomplished; (1) contact of some solder bumps on the
substrate pads in the placement process, (2) contact of all
solder bumps on the substrate pads during the reflow process
and (3) wetting of the solder bumps in contact with substrate
pads in the reflow process. The three steps happen in series
and the success of a previous step is the necessary condition
for the success of the next step. Designating the success rate of
each step as horizontal contact yield (Yh),vertical contact
yield (YJ and wetting yield (Y,) respectively, the success rate,
i.e., interconnect yield (Y) of the whole assembly process can
be written as equation (1).

Y =Y, XU"

XY,

More clearly, the horizontal contact yield can be defined

as the probability that some of the solder bumps make contact
with the substrate pads in the placement process prior to the

reflow process; the vertical contact yield can be defined as the

probability that all solder bumps of a chip make contact with
the corresponding substrate pads during the reflow process
based on the horizontal contact condition; and the wetting
yield can be defined as the probability that all solder bumps of
a chip wet the substrate pads successfully during the reflow
process based on the vertical contact condition.
Breaking the interconnect yield into three in this way
makes yield analysis easier because geometric factors
dominantly affecting the contact yields and chemical factors
dominantly affecting the wetting yield can be decoupled.

Cause and Effect Analysis

Fig. 2 shows the cause and effect analysis for the
interconnect yield. The horizontal contact yield is basically
affected by the misalignment between the solder bumps and
the pads in the placement step. If the misalignment is so large
that none of the solder bumps makes contact with the pads,
the chip will not be interconnected throughout the following
steps. The misalignment is attributed to the placement
misalignment, and the solder mask misregistration depending
on the solder mask definition of the local fiducial; if the solder
mask definition of the local fiducial is solder mask defined
(SMD), the reference position for the alignment synchronizes
with the solder mask misregistration and thus the the
placement positions of the chip bumps when no misalignment
in the placement exists will be on the center of the solder mask
openings. In this case, the solder mask misregistration is not a
factor impacting on the misalignment. On the other hand, if
the solder mask definition of the local fiducial is non-solder
mask defined (NSMD), the reference position for the
alignment is not affected by the solder mask misregistration
and the placement position of the chip bumps will be deviated
from the center of the solder mask openings by the solder
mask misregistration.The total misalignment due to the solder
mask misregistration and the placement misalignment should
not exceed the maximum allowable misalignment to ensure the
horizontal contact of the chip bumps on the pads. The
maximum allowable misalignment is geometrically determined
by the solder bump size, the solder mask thickness, the solder
mask opening size and the pad size [2]. Moreover, when there
exists the variation of the solder bump size, it turns out that
the variation of the solder bumps size and the number of
solder bumps in a chip also affect the maximum allowable
misalignment; at the horizontal contact step, only three biggest
solder bumps can make contact with the corresponding pads.
As the variation of the solder bump size and the number of the
solder bumps increase, the expected biggest solder bump size
in a chip increases reducing the expected maximum allowable
misalignment. If considering the rotational misalignment, the
chip size is a factor impacting on the horizontal contact yield
since as the chip size increases the misalignmentt from the
center of the pad located at the perimeter due to the roational
misalignment increaeses.
The vertical contact yield is affected by the solder bump
height variation, the substrate warpage, the standoff height, the
pad height variation, etc. The solder bumps shorter than the
standoff height between the chip and the pad surface cannot
make contact with the pads [3]. To ensure that all solder

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solder mask

solder mask

placement accuracy

number of solder bumps

solder mask thickness
solder mask opening size
solder bump size
convection flow rate

/application method

profile

Figure 2. Cause and effect analysis of interconnect yield in assembly process of area array packages
bumps make contact with the pads during reflow process, the
variation of the solder bump height should be controlled
within the limit. At this point, the standoff height is the critical
factor impacting on the vertical contact yield. The standoff
gap is determined by the balance between the molten solder
forces and the chip weight. The molten solder forces is
comprised of the surface tension and the pressure difference
due to the miniscus of the solder joint shape, which is affected
by the pad size and pattem, the solder bump size, the
convection flow rate, the chip weight, the p-via on the pad,
etc. By increaseing the pad size, the standoff height may be
reduced to improve the vertical contact yield. However, the
increment of the pad size is usually limited by the pitch
requirement, and also short standoff height can increase the
bridging defect rate and decrease the solder joint reliability.
The substrate warpage which may be induced during reflow
and pre reflow gives a similar effect with the increased
variation of solder bump height on vertical contact yield.
Regarding to the wetting yield, the wetting of the solder
bump which is in contact with the pad is sensitive to the
reflow environment gas, the flux material and amount, the
reflow temperature profile, etc. Usually, the solder bumps and
pads are covered by the oxidation layer that prevents the
solder from initiating the wetting. The flux chemically breaks
the oxidation layer and enables the wetting of the solder.
Appropriate amount of flux should be applied. If it is too
small, the oxidation is not removed completely and thus
partial wetting occurs and if it is too much, then chip is likely
to fly out due to the high pressure underneath the chip induced
by the flux evaporation during reflow. Reflow temperature
profile may also be critical, particularly, the flux activation

temperature and its duration, and the duration above the

liquidus temperature of the eutectic solder. Those factors
should be well controlled to prevent the flux from being
exhausted before wetting is completed; if so, the solder can be
reoxidized under high temperature, and allow all solder bumps
to be heated above the melting point.

Interconnect Yield Model and Design Guidelines

In the paper, horizontal contact yield and vertical contact
yield are theoretcially investigated and design guidelines are
suggested to achieve Six Sigma in the two interconnect yields.
Horizontal Contact Yield
In general, two kinds of solder mask definition exist;
solder mask defined (SMD) and non-solder mask defined
(NSMD). If the solder mask definition is SMD, the pad size
exposed is equal to the opening size of the solder mask and
otherwise to the original pad pattem size. If the solder mask
definition of the fiducial pad is SMD, the reference position
for alignment will move along with the misregistration of the
solder mask since the placemen machine tries to seek the
reference position using the exposed pad area in the fiducial.
Otherwise, the reference position is not affected by the
misregistration of the solder mask. The effect of the solder
mask definitions for the bond pads and the fiducial pad on the
horizontal contact yield will be discussed.
Firstly, the yield prediction model will be described below
for the case that both of the bond pads and the fiducial pads
are SMD. The contact condition can be geometrically derived
as a function of the solder mask misregistration, the placement
misalignment and the solder bump size. Fig. 3 shows the
contact conditions for SMD where the shape of the pads and

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where RLI, and OR are the mean and the standard deviation
respectively of the radius of the solder bumps when the radius
is assumed to be normally distributed. The maximum
allowable misalignment is thus rewritten as equation (7). It is
noticeable that the maximum allowable misalignment
decreases as the number of solder bumps and the standard
deviation of the radius increase.
~

' R ,

ZR,

)i

the solder mask opening are assumed circular. The maximum

allowable misalignment (R,) of the solder bump from the
center of the pad is given by

R, = R, - , / A h( 2Rb - Ah)
where R, is the radius of the solder mask opening, Ah is
the thickness of the solder mask off the pad surface and Rb is
the radius of the solder bump. If there exists the placement
misalignment (r) from the center of the pad, the contact
condition can be written as

r I R,

4%)

R, = R, - d 2 A h p R+ oR

Figure 3. Geometrical limitation for horizontal contact

when the bond pad is solder mask defined.

The design rule to have less than 0.002 defects per million
that corresponds to the 60 for the normal distribution can be
derived from the yield prediction model (equation ( 5 ) ) by
replacing Y h with 1 - 0 . 0 0 2 ~ 1 0(equation
~~
(8)). According to
the origial concept of Six Sigma [5] it can be shown that ppm
level of defects can be obtained even with presence of the shift
of the chip placement mean up to 1.50 in both directions. The
design rule indicates that the maximum allowable
misalignment should be greater than 6.33 times the standard
deviation of the placment misalignment.

The horizontal contact yield seems not affected by the

misregistration of the solder mask as far as the reference point
movement due to the misregistration of the solder mask
synchronizes with the bond pad location movement like the
case above where the bond pads and the fiducial pads are both
SMD. However, if the solder mask definition is different for
the bond pads and the fiducial pads, e.g., the fiducial pads are
NSMD and the bond pads are SMD, the misregistration of the
solder mask is added to the total placement misalignment.
Thus, the effective standard deviation of the placement
misalignment ( oef)
is given by
2

0 =O,+Os
eff

-_
R,'
20;

If there exists the variation of solder bump size, only the

three biggest solder bumps make contact with the bond pads.
Thus, the allowable misalignment is determined by the biggest
solder bumps. Substituting the maximum radius
for Rb
in equation (2), the other two biggest solder bumps can be
guaranteed to make contact with the pads. The mean of the
maximum radius among n solder bumps can be approximated
by employing the Extreme Value Theory [4].
Rb,max

P R

+O

(7)

(3)

For horizontal alignment, the placement machine generally

adopts three independently controlled motors each of which is
for lateral, longitudinal and rotational alignment. Assuming
that position misalignment offsets in lateral direction (x) and
longitudinal direction (y) are independently and normally
distributed with zero mean and O, standard deviation, it can be
shown that the position misalignment offset in radial direction
(r) follows a weibull distribution as shown in equation (4).
Then, the probability that the contact condition (equation (3))
is met, i.e., horizontal contact yield (Yh) is given by equation
(5) under the assumptions that there is no rotational
misalignment.

Yh =1-e

- Ah2

d%

(6)

(9)

The horizontal contact yield model for the condition that

the bond pads and the fiducial pads are both NSMD can be
developed in the same way. Under this condition, it is
assumed that the reference point and the bond pad locations
are not affected by the solder mask misregistration. In Fig. 4,
the maximum allowable misalignment of the solder bump
from the center of the solder mask opening (not the center of
the pad in this case) is geometrically given by equation ( 2 ) and
the contact condition is given by equation (3) if the placement
offset ( r ) is measured from the center of the solder mask
opening. Since the placement misalignment (rp)and the solder
mask misregistration (rs) both from the center of the pad
linearly contribute to the placement offset (r), the standard
deviation of the placement offset (4) can be given by
equation (10). The yield model (equation ( 5 ) ) and the design
rule (equation (8)) can be still used by substituting or for
under this condition.
0,=
"0;+0,"

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2002 Electronic Components and Technology Conference

L
-!

2 6.33

Oeg

where oeg= upor

d z

for SMD in fiducial

+ 0, for NSMD in fiducial

oef=

The rotational placement misalignment is an additional

contributing factor that affects the horizontal contact yield. In
Fig. 5 , the lateral offset (Ax)and the longitudinal offset (Ay) at
a location (x, y) caused by the chip rotation (8, is given by
equation (13) assuming the chip rotation is small and thus its
variances are given by equation (14).

Figure 4. Geometrical limitation for horizontal contact

when the bond pad is non-solder mask defined.

If the fiducial pad is SMD and the bond pads are NSMD,
the solder mask misregistration results in the movement of the
reference point and also the center of the solder mask opening.
Thus, the expected placement position of the solder bump on
the pad is identical with the center of the solder mask opening
and the contribution of the solder mask misregistration (0,)to
o ; = y 02 , 2
is negligible in equation (10). The
the placement offset (0,)
horizontal contact yield under this condition is the same with
2
2 2
= x 0,
the case that the bond pads and the fiducial pads are both
SMD as discussed in the first case.
. It is assumed the chip rotation is normally distributed.
The standard deviation of the lateral placement offset (o,) Then, it shows that when the biggest solder bump is placed on
may be different from that of the longitudinal placement offset the pad at (x, y), the horizontal placement offsets from the
(0,)if the driving mechanism for the lateral movement in the
center of the pad are normally distributed with the variances
placement machine is different from that for the longitudinal proportional to 2 and y2. Noting the probability that the
movement, e.g., a rubber belt is adopted for the longitudinal biggest solder bump is placed at a pad is uniform throughout
driving mechanism. In that case, the horizontal contact yield all pads in the chip, averaging the variances over the chip area
model becomes complicated. However, if assuming qJqyis for convenience yields:
close to one, the horizontal contact yield model can be
approximated as
-_
R:

Yh =1-e

2 4

As a conclusion, the horizontal contact yield model and the

design rule can be expressed into one unified fashion,
equation (1 1) and (12) that are applicable for any. of four
combinations of the solder mask definition for the bond pads
and the fiducial pad. It seems that the horizontal contact yield
is not affected by the solder mask misregistration when the
fiducial pad is SMD. On the other hand, the placement
misalignment is a source of non-horizontal contact for any
cases.

where L is the chip side length. It is concluded that the lateral

offset (Ax) and the longitudinal offset ( A y ) caused by the chip
rotation at the location where the biggest chip is placed are
independently and normally distributed with variances given
by equation (15). In addition, since the chip rotation is
assumed to independent of the lateral and longitudinal chip
movement, the standard deviation of the offset due to the chip
rotational misalignment (equation (15)) can be added to the
effective standard deviation in equation (12), i.e.,

f o r SMD infiducial
(16)

oefl
=

L2
+ a,+-oj

0;

12

f o r NSMD infiducial

Figure 5. Rotational placement misalignment

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Vertical Contact Yield

Usually, the distribution of solder bump height measured
from all population of chips to be assembled can be
approximated closely as a normal distribution with a mean
&) and a standard deviation ( a b ) . The probability that any
solder bump makes contact with the corresponding pad (YJ is
equal to the probability that the solder bump height (hbi) is not
shorter than the contact distance (hSi-hpj)
in Fig. 6, i.e.,

Yvi= P (hbi 2 hSi- hpi)

Figure 6. Interconnect failure caused by solder bump

height variation

(17)

where h,; is the standoff height, hPiis the pad thickness and hb,
is the solder bump height.
Assuming that hpi is also normally distributed with a mean
&) and a standard deviation (ap),
a new random variable,
hbjf h p i is normally distributed with the effective mean, lu, and

the effective standard deviation,

Thus, vertical contact
yield for one solder bump can be rewritten as

Yvj= P (hbi + hpi 2 hSi)

100

io1

102
n (//Os)

lo4

Figure 7. The k factor versus the number of I/Os

where 4 is the accumulative normal distribution density

function. Since the vertical contact yield for each solder bump
of the chip can be assumed independent, the vertical contact
yield for one chip ( Y J , i.e., the probability that all solder
bumps of the chip make contact with the pads is given by

If Y, is close to one, it can be approximated as

It is shown that as the number of the solder joints

increases, the vertical contact yield linearly decreases. To
obtain the same level of the interconnect yield in the
interconnect assembly process of high I/O packages, the
variations of the solder bump size and the pad thickness
should be more tightly controlled.
The design rule to achieve Six Sigma in vertical contact
yield without presence of substrate warpage is given by
equation (23). k is the factor specifying the limit of the
allowable effective standard deviation with respect to the
difference between the effective mean and the standoff height
and it is a function of the number of I/Os as shown in Fig. 7.

or, since l-@(x)= Q(-x),

To simplify the yield model, the standoff height can be

approximated as a constant since when the number of solder
bumps in a chip is greater than 100 as such in most of area
array packages, the effect of the standoff height variation on
the yield is negligible [6]. The standoff height calculated
based on the averages of the random parameters [7] can be
approximately used for the constant standoff height ( h ,1.
Then, the vertical contact yield model becomes

As the trend toward high density, continues in electronics

packaging, the bridge between neighboring solder joints is a

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concem. The bridge defect in area array interconnect can

occur when the big solder joint of liquid state is compressed in
the relatively small standoff height between the chip and the
substrate and consequently swells in lateral direction to meet
the adjacent solder joint or when the solder joint of liquid state
wets out over the non-wettable mask beyond the bond pad to
the neighboring solder joint.
Non-bridge interconnect yield (YnJ is defined as the
probability that there is no potential bridge defect in the area
array interconnect. Being defined in this way, the non-bridge
yield depends on how the potential bridge is defined.
Comprehensively, the potential bridge may be defined as the
liquid solder joint whose shape is unstable so that it can easily
make a connection with a neighboring solder joint even by
trivial environmental change. In this study, a confined
definition of the potential bridge is suggested by determining
the instability condition of the solder joint based on the
geometry of the liquid solder joint; the potential bridge is
defined as the solder joint whose contact angle on the chip and
the substrate is 180" as shown Fig. 8. Under this condition, the
restoring force of the solder toward the stable shape is very
weak and thus the solder joint shape may change sensitively to
external disturbance. In addition, the solder touches the nonwettable layer (solder mask or dielectric layer) whose surface
can be chemically non-uniform and thus the solder joint is
likely to be unstable.
The solder joint volume (Vu)under the potential bridge
condition can be estimated by equation (24) by assuming the
meniscus of the solder joint is circular [8] and the maximum
thickness of the solder joint ( D ) by equation (25).

Figure 8. Definition of the potential bridge

bridge. Thus, the non-bridge interconnect yield as defined is
the probability that the height of every solder bump (hb;) in the
chip is shorter than the corresponding upper limit (hbui).
n

If it is assumed that the standoff height is a constant for

every solder joint and thus the upper limit of the solder bump
height for each solder bump is the same, the non-bridge
interconnect yield can be rewritten as

The design rule to achieve Six Sigma in non-bridge

interconnect yield is given by equation (29) where k is defined
in equation (23).
hbu-pb

when Ynb= 1

2k

Ob

When r is the pad radius in this equation, Vu can be the

lower limit of solder joint volume under the potential bridege,
i.e., if the solder joint volume is greater than Vuit is under the
potential bridge condition. The solder bump height (hbu)
corresponding to the lower limit of the potential bridge can be
found by equalizing equation (24) to equation (25) for the
solder bump volume (vb)pre reflow. Then, hbu becomes the
upper limit to avoid the potential defects. If the bond pad is
non-solder mask defined, the pad volume should be added to
the solder bump volume.

Vb=-hb(hi+3r2)
n
6
h:u + 3r2hb,- h, (h,' +3nrhs + 6 r 2 )= 0

(26)

FR4 substrate is being widely used to produce low cost

electronic products. At the same time, to meet the
requirements of small size and high performance, highly dense
circuits are designed on the multilayer FR4 substrates. The
substrate warpage cannot be avoided in the processing of
multi layers under multi processing temperatures. Even trivial
warpage may be critical in the interconnect yield of highly
dense electronics packages [9]. Ability to specify the tolerable
limit of the substrate warpage in terms of interconnect yield
would be substantial to manage the quality of the substrate and
reduce the economy waste caused by interconnect yield loss.
The vertical contact yield model with presence of substrate
warpage was developed. The model starts with the assumption
that the substrate warpage profile is known with respect to the
coordinate system in Fig.9. The offset of each substrate pad
(z;) from the base plane is known as such in equation (30)
where the pad is located at xiand yi in x-y plane. The offset of
each substrate pad can be rewritten using the average height (i
) of all the pads and the deviation (bi)
from the average
height as equation (31).

By solving the 3th order polynomial equation above, the

upper limit of the solder bump height to avoid the potential
bridge can be obtained. If a solder bump height is greater than
the upper limit, the solder bump can be considered a potential
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2002 Electronic Components and Technology Conference

Here, it is assumed that the offset of the active surface of the

chip from the level at the average height is equal to the
standoff height of the chip measured if the substrate were flat
and parallel to the chip. Then, the standoff height (h,J of each
solder joint can be expressed as
C

hsi = h, -hi
Thus, with presence of substrate warpage, the vertical
contact yield model (equation (20)) becomes

The vertical contact yield model can be calculated only

when the height offsets of all the pads due to the substrate
warpage are known. In general, the substrate warpage can be
characterized by the maximum height offset which usually is
measured at the comer of the substrate. To make the vertical
contact yield compatible with the conventional
characterization of the substrate warpage, the lower bound of
the vertical contact yield can be derived in terms of the
maximum height offset (Am) of the substrate warpage.

demanded in the future. The process models can be used to

evaluate the process capability with respect to the needs in the
future and help decide how the processes should be improved
to meet the needs unless the current processes are judged to be
capable.
Design rules to achieve ppm level of defects in assembly
process for area array solder interconnect packages are
presented in general and explicit forms. The parameter
variations cannot be avoided due to inherent imperfections in
the manufacturing processes [ 10-111. Rather, it is important to
control the manufacturing process so that the parameter
variations are limited to certain quantities within which the
desired yield is obtained. Therefore, to have an ability to
specify the parameter variation limits required is essential for
manufacturing process designers. It is expected that design
rules presented in the paper enable to efficiently achieve Six
Sigma in the assembly process combined with the
conventional statistical process control tools [121.

Figure 9. Substrate warpage

(34)

91

Defining Wand c a s
.
C

The lower bound of the vertical contact yield in terms of

the maximum offset of the substrate warpage can be expressed
by two dimensionless parameters as equation (36). v i s the
parameter representing the vertical contact yield without
substrate warpage and 5 is the parameter representing the
effect of the substrate warpage on the vertical contact yield.

10

11

12

13

14

15

w=- ph - hs
*h

The design rule to achieve Six Sigma can be obtained from

the lower bound of the vertical contact yield. Fig. 10 shows
the process window to have less than 0.002 defects per
million. It is shown that the effect of the number of I/Os on the
allowable limit of the substrate warpage is small, though the
higher number of I/Os requires the tighter tolerance of the
substrate warpage.

Conclusions
The cause and effect analysis and the yield prediction
models presented in the paper can provide an intuitive
engineering analysis capturing the process physics and enable
rapid design process evaluation. The current feasible
manufacturing processes may not meet the yield requirement
of the chip with high 1/0 count and small solder joints

Figure 10. Process window specifying the

allowable limit of the substrate warpage

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2002 Electronic Components and Technology Conference

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