tjniversiti

Malaysia
Q PAHANG

Engineering Technology Creativity

FACULTY OF MANUFACTURING ENGINEERING

FINAL EXAMINATION
COURSE

DIGITAL ELECTRONICS

COURSE CODE

BFM2313

LECTURER

WAN HASBULLAH BIN MOHD ISA

DATE

8 JUNE 2012

DURATION

3 HOURS

SESSION/SEMESTER

SESSION 2011/2012 SEMESTER II

PROGRAMME CODE

BFM

INSTRUCTIONS TO CANDIDATE:

1. Answer ALL questions.

2. All answers to a new question should start on new page.
3. All the calculations and assumptions must be clearly stated.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of EIGHT (8) printed pages including front page.

CONFJDENTIAL

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ANSWER ALL QUESTIONS

QUESTION 1 (20 MARKS)

(a) A storage tank system for a pancake syrup manufacturing process has four inputs A,
B, C, and P that control the whole tank system. The expression for the output Z, of
the system is given as:
Z = ABCD + ABCD + ABCD + A B C D + 4 C

i)

Sketch the logic circuit represented by the output Z expression.

(2 marks)

ii)

Develop a truth table for the output Z expression.

(5 marks)

iii)

Reduce the function specified in truth table in Question 1 a (ii) to its minimum
SOP form by using a Karnaugh map.

(3 marks)

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(b) The outputs of a Combinational Logic Circuits are only determined by the logical
function of their current input state, logic "0" or logic "1", at any given instant in time
as they have no feedback, and any changes to the signals being applied to their inputs
will immediately have an effect at the output. Figure 1 is a combinational logic
circuit with three inputs A, B, C, and an output X.

A
B

Figure 1: Combinational Logic Circuit

i)

Implement the logic circuits in Figure 1 using only "NAND" gates.

(4 marks)

ii)

Reiterate Question lb (i) using only "NOR" gates.

(4 marks)

iii)

NAND gates and NOR gates are holding universal property. Why both gates
are known as Universal Gates?

(2 marks)

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QUESTION 2 (20 MARKS)

The process of converting control objectives into a ladder logic program requires
structured thought. Boolean algebra provides the tools needed to analyze and design
these systems. By applying this technique design a burglar alarm system for a house.

When activated, an alarm and lights will be activated to encourage the unwanted
guest to leave. This alarm will be activated if an unauthorized intruder is detected by
window sensor and a motion detector. The window sensor is effectively a loop of wire
that is a piece of thin metal foil that encircles the window. If the window is broken,
the foil breaks breaking the conductor. This behaves like a normally closed switch.
The motion sensor is designed so that when a person is detected the output will go on.
As with any alarm an activate/deactivate switch is also needed.

The inputs and outputs are chosen to be;

A= Alarm and lighis switch (1 = on)
W WindoIDoor sensor (1 = OK)
M Motion Sensor
O)
S
1 arm Active switch (1 on)

The basic operation of the alarm canbe denbed with rules.

1.If alarm is on, check sensors.
2. lf window/door sensor is brcken(turns off),sound alarm and turn on lights
3. lfmotionseror goes on(detecis thiel)sound alarm and turn on lights.

Note: As the engineer, it is yourisponslbilityto define these items before starling

the vrk. If you do not do this first you are guaranteed to produce a poor
design. It is important to develop a good list of inputs and outputs, and give
the msimple names so that theyare easy to refer to. Most companies will use
re numbering schemes on their diagrams.

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a)

BFMII112II/BFM2313

Specify the behavior of the system using a truth table.

(5 marks)
b)

Derive the simplest sum of products (SOP).

(5 marks)
C)

Draw the logic circuit diagram to accomplish the design.

(5 marks)

d)

Implement the logic circuit diagram in Question 2(c) using either one of the
Universal Gates
(5 marks)

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QUESTION 3 (20 MARKS)

(a)

Figure 2, a dual NAND-gate circuit shown below is called a Set-Reset latch and has
the symbol shown at right. Complete the timing diagram by showing the waveforms
of Q and N assuming that Q is initially low.

SET -S
RESET

RESET

Figure 2: Dual NAND-gate I Set-Reset Latch

SET

RESET

(5 marks)

(b)

A general sequential circuit consists of a combinational logic section and a memory

section (flip-flops). Basic idea behind this type of design is to use flip flops to hold
the system's state and use combinational logic to make the system move from state to
state. By implementing this application, design a binary UP! DOWN counter with the
following sequence in Figure 3. The counter should be able to count up/down using
J-K flip-flops.

UP c0UNr

EEEK
DOWN COTJN

Figure 3: UP! DOWN Sequence

(15 marks)
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QUESTION 4 (20 MARKS)

(a) A 8-bit bidirectional shift register is shown below. A HIGH on this input enables a
shift to the right, and a LOW enables a shift to the left. Determine the state of the
register after each clock pulse for the RIGHT/LEFT control waveform given. Assume
that the register is initially storing the decimal numbers sixty-six in binary, with the
right-most position being the LSB. There is a LOW on the data-input line.

Data in
RIGHT! LEFT

Data out

CLK

CLK

RIGHT! LEFT

(6 marks)

(b) RAM or random access memory is the temporary memory that the computer uses to
perform its functions while being used. There are two major categories of RAM
which are:
Static RAM (SRAM)
Dynamic RAM (DRAM)

(i)

Explain the differences between SRAM and DRAM

(6 marks)

(ii)

Discuss the types of DRAM

(8 marks)
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QUESTION 5 (20 MARKS)

A digital signal processor (DSP) is a type of microprocessor - one that is incredibly
fast and powerful. A DSP is unique because it processes data in real time. This realtime capability makes a DSP perfect for applications where we won't tolerate any
delays. Digital cellular telephone is one of the applications how DSP has been used.

a)

Illustrate a simplified block diagram of a digital cellular phone.

(10 marks)

b)

Describe the functions performed by the DSP in cellular application to

improve the reception and transmission of a voice signal.
(10 marks)

END OF EXAMINATION PAPER

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