VLSI DESIGN

UNIT I
INTRODUCTION: Introduction to IC Technology - MOS, PMOS, NMOS, CMOS &
BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion implantation,
Metallization, Encapsulation, Probe testing, Integrated Resistors and Capacitors. Cmos
nanotechnology.

INTRODUCTION:
The expansion of VLSI is Very-Large-Scale-Integration. Here, the term Integration
refers to the complexity of the Integrated circuitry (IC). An IC is a well-packaged
electronic circuit on a small piece of single crystal silicon measuring few mms by few
mms, comprising active devices, passive devices and their interconnections. The
technology of making ICs is known as MICROELECTRONICS. This is because the
size of the devices will be in the range of micro, sub micrometers. The examples include
basic gates to microprocessors, op-amps to consumer electronic ICs. There is so much
evolution taken place in the field of Microelectronics, that the IC industry has the
expertise of fabricating an IC successfully with more than 100 million MOS transistors as
of today. ICs are classified keeping many parameters in mind. Based on the transistors
count on the IC, ICs are classified as SSI, MSI, LSI and VLSI. The minimum number of
transistors on a VLSI IC is in excess of 40,000.
The concept of IC was conceived and demonstrated by JACK KILBY of TEXAS
INSTRUMENTS at Dallas of USA in the year 1958.The silicon IC industry has not
looked back since then. A lot of evolution has taken place in the industry and VLSI is the
result of this. This technology has become the backbone of all the other industries. We
will see every other field of science and technology getting benefit out of this. In fact the
advancements that we see in other fields like IT, AUTOMOBILE or MEDICAL, are
because of VLSI. This being such important discipline of engineering, there is so much
interest to know more about this. This is the motivation for this course namely VLSI
CIRCUITS.
What is VLSI?
VLSI is Very Large Scale Integration. It is the process of designing, verifying,
fabricating and testing of a VLSI IC or CHIP.A VLSI chip is an IC, which has transistors
in excess of 40,000. MOS and MOS technology alone is used. The active devices used
are CMOSFETs. The small piece of single crystal silicon that is used to build this IC is
called a DIE. The size of this die could be 1.5cmsx1.5cms.
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This die is a part of a bigger circular silicon disc of diameter 30cms.This is called a
WAFR. Using batch process, where in 40 wafers are processed simultaneously, one can
fabricate as many as 12,000 ICs in one fabrication cycle. Even if a low yield rate of 40%
is considered you are liable to get as many as 5000 good ICs. These could be complex
and versatile ICs. These could be a PENTIUM Microprocessor IC of INTEL, or a DSP
processor of TI costing around Rs10,000. Thus you are likely to make Rs50 million
(Rs5crore) out of one process flow. So there is lot of money in VLSI industry. The initial
investment to set up a silicon fabrication unit (called FAB in short and also called
sometimes as silicon foundry) runs into a few $Billion. In INDIA, we have only one
silicon foundry-SCL at Punjab (Semiconductor Complex Ltd., in Chandigarh). Very
stringent and critical requirements of power supply, cleanliness of the environment and
purity of water are the reasons as to why there are not many FABS in India.
Producing a VLSI chip is an extremely complex task. It has number of design and
verification steps. Then the fabrication step follows. The complexity could be best
explained by what is known as VLSI design funnel as shown in the Figure1.1.

Figure1.1 The VLSI design tunnel

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Semiconductor technology:
Semiconductors can be made from crystalline silicon into which impurities have been
introduced: A high valency implant such as phosphorous gives free electrons, creating an
n-type region. A low valency implant such as boron gives free holes, creating a p-type
region. The junction of an n-type and a p-type region in a single crystalline lattice creates
a diode which only conducts if it is forward biased with the p-type region (the anode)
more positive than the n-type region (the cathode).
A light emitting diode has the additional property that it glows when current is flowing
through it. It is prudent to limit this current to a few milli-Amps by means of a kilohm
series resistor, or it glows very brightly, but only for a short time.

Digital switching:
Most digital logic is based on the idea of switching signals between a high voltage (which
we will usually treat as being 5V, although modern systems more commonly use 3.3V or
less) and a low voltage (0V, or ground). The sense may be determined by current flowing
or not (as in bipolar circuits) or by the presence or absence of charge (as in MOS
circuits). A logic function takes some input signals and computes an output function
using pull-up and pull-down circuits which may be passive (always switched on) or
active (selectively switched).

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The diagram shows a circuit with an active pull-down and a passive pull-up. The pulldown can be thought of as a remote-control switch, usually made from transistors but
possibly relays or valves. A further complexity with MOS circuits is that the charge on
wires persists after they have ceased to be driven; this means that the wires have a
memory (typically lasting a thousandth of a second or so) of the last value driven on
them.

Bipolar circuits:
A bipolar transistor is formed by a sandwich of n-type, p-type and n-type regions in a
single crystalline lattice. It can be thought of two diodes connected anode-to-anode such
that a current through the forward biased diode overwhelms the reverse biased diode.

A small current flowing from the base to the emitter of an npn transistor induces a large
current from the collector to the emitter. A pnp transistor has the opposite polarity. These
can be used to construct a AND gate using transistor-transistor logic (TTL).

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The two transistors on the left calculate the logical function and that on the right is simply
an inverter. Sometimes this is followed by an additional buffer for a totem pole output.
With a 1k7 Ohm pull-up, about 1 mA flows through the gate whenever an input is high
and the gate then dissipates 5 mW. There are also difficulties in finding the right sizes for
the transistors and resistor.

MOS circuits :An enhancement mode, n-channel, metal-oxide-silicon field-effect

transistor (nMOS FET) is formed on a crystal of p-type silicon. Two n-type regions
(known as diffusion) lie on either side of a region of the p-type substrate which is covered
by a thick layer of insulating silicon dioxide (or oxide) and a metal plate.

When the gate is positive with respect to the source, an n-type channel is formed under
the gate and current is conducted from drain to source. Even when turned on, a MOS
transistor has a resistance of about 10 k. The construction of the transistor is symmetric
with respect to the source and drain - the labels merely indicate the relative voltages. This
contrasts with the different processing used to make the collector and emitter of a bipolar
transistor. A p-channel MOS FET has the opposite polarity and conducts when its gate is
low. However, the resistance of a p-type channel is about 2 times that of an n-type
channel of the same size.

In integrated circuits, the metal gate is replaced by one made from polycrystalline silicon
(or polysilicon) for ease of fabrication. The nMOS transistor operate in three modes:
 off when Vgs <Vt
 saturated when Vgs >Vt and Vds >Vgs Vt

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 linear when Vgs >Vt and Vds <Vgs Vt

where Vt is the threshold voltage ( = 0.2 Vdd =1Vfora5Vsystem) Note that, even when
the transistor is turned on, the source voltage can not rise above the gate voltage less the
threshold voltage. The threshold voltage can be adjusted by implanting further impurities
into the channel regions. Itcanevenbemadenegative(Vt =-0.8Vdd = -4V), giving a
depletion mode nMOS FET which always conducts. This can be used as a compact way
of making a resistor.

nMOS
An nMOS NOR gate can be made with two n-type pull-down transistors in parallel and a
passive pull-up. There are three ways that the pull-up could be made:
A resistor using polysilicon (which is the most resistive material available in a
MOS process) this would have to be several hundred times the size of the pulldown transistor.
An enhancement mode transistor with its gate wired high this could never pull
the output above Vdd Vt.
A depletion mode transistor with its gate wired to its source is used in practice. So
far, we have treated transistors as ideal switches An ON transistor passes a finite
amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed

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CMOS:
A CMOS NOR gate can be made with two n-type pull-down transistors in parallel and
two p- type transistors in series as an active pull-up. The complementary Boolean circuits
in the pull- up and pull-down networks give the technology its name.

Current only flows when the gate is switched and the output signal (which may be
regarded as a capacitor) is charged or discharged, making the power consumption very
low. A further advantage of CMOS over nMOS and bipolar circuitry is that is does not
rely on the ratio of the resistances in the pull-up and pull-down networks to determine the
output voltage. The output switches between 0 V and 5 V rather than between about 1 V
and 5 V. The disadvantage is the additional complexity of the complementary circuit.

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BiCMOS :

A known deficiency of MOS technology is its limited load driving capabilities

(due to limited current sourcing and sinking abilities of pMOS and nMOS
transistors).

BiCMOS is a modified CMOS technology that includes bipolar junction

transistors as circuit elements. In digital design, BiCMOS stages are used to drive

high- capacitance lines more efficiently than MOSFET only circuits. BiCMOS
Circuits employ CMOS logic circuits that are connected a bipolar output driver stage,
as shown in fig. The CMOS network provides logic operations and bipolar transistors
are used to drive the output. Only one BJT is active at a time. BJT Q1 provides the
high output voltage while Q1 discharges the output capacitance and gives the low
output value.

Bipolar transistors have

higher gain
better noise characteristics
better high frequency characteristics

BiCMOS gates can be an efficient way of speeding up VLSI circuits

See table for comparison between CMOS and BiCMOS

CMOS fabrication process can be extended for BiCMOS

Example Applications
CMOS

- Logic

BiCMOS

- I/O and driver circuits

ECL - critical high speed parts of the system

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General form of a BiCMOS circuit

The inverting circuit shown in BELOW Fig illustrates the operational details. The
inversion is done by FETs Mp and Mn. The other two FETs M1 and M2 are used to
provide paths to remove charge from the base terminals of Q1and Q2 respectively. This
speeds up the switching of the circuit, enhancing its use as an output driver.

operational details of the BiCMOS driver circuit

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A BICMOS NAND2 circuit: The CMOS circuitry can be modified as shown in fig.23.
The logic is performed by the parallel pFETs driving Q1, and the series nFETs between
the collector and the base of Q2. The other FETs are used as pull-down devices to turn
off the output transistors. Other logic functions cazn be designed using this as a basis. In
general, the upper output transistor uses a standard-design CMOS circuit as a driver. The
nFET section is replicated and placed in between the collector and base of the
loweroutput transistor; adding a pull-down nFET to the base completes the design.

A BICMOS NAND2 circuit:

As additional devices are present, parasitic capacitance is larger in a BiCMOS circuit
than CMOS. BiCMOS is only effective for larger values of CL. A typical plot of time
delay V/S CL of fig shows that, due to the higher parasitic device capacitance, the CM
Design provides faster switching than a BiCMOS circuit. The speed increase is only
forloads where CL is much larger than Cx. This restricts the application of BiCMOS
circuits to applications such as driving long data buses. Moreover, the cost and problem
of VBE drops are important factors in using the technology in digital VLSI.OS and
BiCMOS behaviors cross at a value CL=Cx. For CL < Cx, a standard CMOS

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MOS TECHNOLOGY FABRICATION :

nMOS Fabrication

CMOS Fabrication
p-well process
n-well process
twin-tub process

All the devices on the wafer are made at the same time

After the circuitry has been placed on the chip

the chip is overglassed (with a passivation layer) to protect it
only those areas which connect to the outside world will be left uncovered
(the pads)

The wafer finally passes to a test station

test probes send test signal patterns to the chip and monitor the output of
the chip

The yield of a process is the percentage of die which pass this testing

The wafer is then scribed and separated up into the individual chips. These are
then packaged

Chips are binned according to their performance

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nMOS Fabrication:
The process starts with the oxidation of the silicon substrate (Fig. 4(a)), in which a
relatively thick silicon dioxide layer, also called field oxide, is created on the surface
(Fig. 4(b)). Then, the field oxide is selectively etched to expose the silicon surface on
which the MOS transistor will be created (Fig. 4(c)). Following this step, the surface is
covered with a thin, high-quality oxide layer, which will eventually form the gate oxide
of the MOS transistor (Fig. 4(d)).

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Figure-4: Process flow for the fabrication of an n-type MOSFET on p-type silicon.

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On top of the thin oxide, a layer of polysilicon (polycrystalline silicon) is deposited (Fig.
4(e)). Polysilicon is used both as gate electrode material for MOS transistors and also as
an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively
high resistivity. The resistivity of polysilicon can be reduced, however, by doping it with
impurity atoms. After deposition, the polysilicon layer is patterned and etched to form the
interconnects and the MOS transistor gates (Fig. 4(f)). The thin gate oxide not covered by
polysilicon is also etched away, which exposes the bare silicon surface on which the
source and drain junctions are to be formed (Fig. 4(g)). The entire silicon surface is then
doped with a high concentration of impurities, either through diffusion or ion
implantation (in this case with donor atoms to produce n-type doping). Figure 4(h) shows
that the doping penetrates the exposed areas on the silicon surface, ultimately creating
two n-type regions (source and drain junctions) in the p-type substrate. The impurity
doping also penetrates the polysilicon on the surface, reducing its resistivity. Note that
the polysilicon gate, which is patterned before doping actually defines the precise
location of the channel region and, hence, the location of the source and the drain regions.
Since this procedure allows very precise positioning of the two regions relative to the
gate, it is also called the self-aligned process.
Once the source and drain regions are completed, the entire surface is again covered with
an insulating layer of silicon dioxide (Fig. 4(i)). The insulating oxide layer is then
patterned in order to provide contact windows for the drain and source junctions (Fig.
4(j)). The surface is covered with evaporated aluminum which will form the
interconnects. Finally, the metal layer is patterned and etched, completing the
interconnection of the MOS transistors on the surface (Fig. 4(l)). Usually, a second (and
third) layer of metallic interconnect can also be added on top of this structure by creating
another insulating oxide layer, cutting contact (via) holes, depositing, and patterning the
metal.

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CMOS TECHNOLOGY:
Fabrication
Fabrication involves the implementation of semiconductor processes to build a
MOSFET transistor and compatible passive components as an integrated circuit.
N-Well CMOS Fabrication Major Steps
Start with blank wafer Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide),Remove layer where n-well
should be built, Implant or diffuse n dopants into exposed wafer Strip off SiO2

Oxidation:
Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation
furnace
Now shape/pattern it for n-well

Photoresist:
Spin on photoresist Photoresist is a light-sensitive organic polymer Softens
where exposed to light

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Lithography:
Expose photoresist through n-well mask
Strip off exposed photoresist

Etch:
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been Exposed

Strip Photoresist:
Strip off remaining photoresist Use mixture of acids called piranha etch

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n-well:
n-well is formed with diffusion or ion implantation
Diffusion: Place wafer in furnace with arsenic gas Heat until As atoms diffuse
into exposed Si
Ion Implanatation: Blast wafer with beam of As ions Ions blocked by SiO , only
enter exposed Si

Strip Oxide:
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

Polysilicon:
Deposit very thin layer of gate oxide < 20 > (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with
Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to
be good conductor

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Polysilicon Patterning:
Use same lithography process to pattern polysilicon

Self-Aligned Process:
Use oxide and masking to expose where n+ dopants should be diffused or
implanted
N-diffusion forms nMOS source, drain, and n-well contact

N-diffusion:
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesnt melt
during later processing

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Historically dopants were diffused Usually ion implantation today But regions are
still called diffusion

Strip off oxide to complete patterning step

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P-Diffusion: Similar set of steps form p+ diffusion regions for pMOS source
and drain and substrate contact

Contacts:
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

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Metallization:
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

Passive layer formation.

p-well process is similar but starts with a p-well implant rather than an n-well
implant.

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Twin-Tub (Twin-Well) CMOS Process :
This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the channel
transconductance of both types of transistors to be tuned independently. Generally, the
starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This
epitaxial layer provides the actual substrate on which the n-well and the p-well are
formed. Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the desired
device characteristics. The Twin-Tub process is shown below.

In the conventional p & n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among other
effects, results in unbalanced drain parasitics. The twin-tub process avoids this problem.

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Silicon-on-Insulator (SOI) CMOS Process:
Rather than using silicon as the substrate material, technologists have sought to use an
insulating substrate to improve process characteristics such as speed and latch-up
susceptibility. The SOI CMOS technology allows the creation of independent, completely
isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
The main advantages of this technology are the higher integration density (because of the
absence of well regions), complete avoidance of the latch-up problem, and lower parasitic
capacitances compared to the conventional p & n-well or twin-tub CMOS processes. A
cross-section of nMOS and pMOS devices using SOI process is shown below.

The SOI CMOS process is considerably more costly than the standard p & n-well CMOS
process. Yet the improvements of device performance and the absence of latch-up
problems can justify its use, especially for deep-sub-micron devices.

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Fabrication Technology :
Cleaning,
Oxidation,
Diffusion,
Ion Implantation,
Deposition,
Photolithography,
Etching.

Making of chip:

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Silicon of extremely high purity

chemically purified then grown into large crystals

Wafers
crystals are sliced into wafers
wafer diameter is currently 150mm, 200mm, 300mm
wafer thickness <1mm
surface is polished to optical smoothness

Wafer is then ready for processing

Each wafer will yield many chips

chip die size varies from about 5mmx5mm to 15mmx15mm
A whole wafer is processed at a time

Different parts of each die will be made P-type or N-type (small amount of other
atoms intentionally introduced - doping -implant)

Interconnections are made with metal

Insulation used is typically SiO2. SiN is also used. New materials being
investigated (low-k dielectrics)

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Starting Material and Wafer Preparation :
The starting material for modern integrated circuits is very high purity silicon. The
material is grown as a single crystal ingot.
It takes the shape of a steel gray solid cylinder 10 to 30 cm in diameter and about
one meter length.
This crystal is then sawed (like a loaf of bread) to produce wafers 10 to 30 cm in
diameter and 400 to 600m thick.
The sawed wafer surface must be both flat and smooth. This done by a two-steps
polishing.
Rough polishing using a conventional abrasive, slurry-lapping process. This is to
remove the surface damage leftover from the wafer-slicing process.
The wafer is polished to a mirror like finish using chemical and mechanical
polishing techniques combination of chemical etching and mechanical
buffing.
The wafers are mounted on rotating holders and lowered onto a pad surface
rotating in opposite direction. A slurry of silica suspended in a mild etchant (e.g.
KOH) is used during polishing.
Semiconductor manufacturers usually purchase ready-made silicon wafers and
rarely start their process in ingot form.
The basic electrical and mechanical properties of the wafer depend on the
orientation of the crystal growth, the concentration and the type of impurities.
The crystal orientation of the wafer is identified by means of primary and
secondary flats.
<100> wafers are usually used for MOS ICs.
<111> wafers are usually used for bipolar ICs.
The crystal orientation can be determined by etching, x-ray diffraction, or light
reflection.

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Typical 200 mm Wafer Specification

Diameter

200mm

Diam. Tolerance
Thickness

0.25mm
725 50m

Crystal Orientation

<100> 1

Resistivity

2.7-4 ?cm

Oxygen

25-29 ppm

Oxygen Gradient
Carbon

5%
0.3 ppm

Basic Processing Steps :

Cleaning :
Clean wafers (free of contaminants) are essential at all stages of the fabrication process,
especially before any high temperature operation. Cleaning procedures are needed prior
to any processing steps; consequently wafers spend most of their time in the cleaning
station.
Contaminants in the wafer surface include:
Particulates
Organic residues
Inorganic residues
Unwanted oxide layers
Particulate Removal:
Blow off using a spray of high pressure nitrogen.

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Wafer scrubbers: rotating brush and spray of de-ionized water (+ detergent if necessary).
Scrubbers are usually stand-alone units with automated loading and cleaning setup.High
pressure water cleaning using a small stream of water at 2000 to 4000 psi.A stream of
water is used to dislodge both surface particles.

Organic Residue Removal:

Contaminants that contain carbon, e.g. oil from finger prints. Can be removed using
solvent baths such as alcohol or acetone.
Inorganic Residue Removal:
Contaminants that do not contain carbon. A variety of solution can be used: Sulfuric
acid, Sulfuric acid + Hydrogen Peroxide or Ammonia Developed in the mid 60s by an
RCA engineer.
Oxide Removal:
Silicon can be oxidized very easily, whenever it is exposed to Oxidants. Oxides are often
grown in the baths. Typically 100 to 200 is thick enough to block the silicon surface
from reacting properly. Silicon surfaces with an oxide are called hydroscopic. Surfaces
without oxide are called hydrophobic. Hydrofluoric acid is often used to remove the
oxide. HF does not etch silicon.

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Oxidation :
Si + O2 SiO2 Dry oxidation
Si + 2H2O

SiO2 + H2 Wet Oxidation

Thermal oxidation is easily achieved by heating the wafer to a high temperature, typically
900 to 1200C in pure oxygen or steam environment. Oxygen diffuses to the silicon
surface, reacts and forms SiO2.

Thermal oxidation is carried out in a high temperature furnace tube. The tubes are
usually made of quartz or silicon

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Oxide Quality: thickness uniformity, breakdown voltage, trapped charges. Thin oxide is
usually grown using dry oxidation Thick oxide is usually grown using wet oxidation Dry
oxidation results in slower growth rate, but high density higher breakdown
voltage.MOS devices are usually fabricated using <100> wafers since the SiO2-Si
interface has the lowest number of dangling bonds. Sodium contamination results in
positive mobile charges which could lead to a shift in the threshold voltage of the MOS
devices.

Diffusion :
Diffusion is the process by which atoms move through the crystal lattice. This is very
much like a drop of ink disperses through a glass of water except that it occurs very
slowly in solids. The impurity atoms (dopants) changes the resistivity of the silicon. The
rate at which dopants diffuse in silicon is a strong function of temperature. Diffusion of
impurities is usually carried out at high temperatures (1000 to 1200C) to obtain the
desired doping profile. When the wafer is cooled to room temperature, the impurities are
essentially frozen in position.The diffusion process is performed in furnaces similar
to those used for oxidation. The depth to which the impurities diffuse depends on both the
temperature and time.

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The most common impurities used as dopants are boron, phosphorus and arsenic. Boron
is a p-type dopant while phosphorus and arsenic are n-type dopant. These dopants can be
effectively masked by thin silicon dioxide layers.Diffusion is usually carried out in two
steps: predeposition and drive-in. Predeposition is a constant source diffusion where a
continuous flow of impurity is dissolved into the wafer surface.Drive-in is used to move
the diffusion front to the desired depth (junction depth).

During this step, the source of impurity is removed. The only amount of impurity
available is from the predeposition step.

Ion Implantation :
Ion implantation is an alternate method used to introduce impurities into silicon.An ion
implanter produces ions of the desired impurity,accelerates them by an electric field, and
allows them to strike the silicon surface.The ions become embedded in the silicon. The
depth of penetration is related to the energy of the ion beam,which can be controlled by
the accelerating-field voltage (energy specified in keV).The dose of ions implanted
(specified in cm- 2) can be controlled by varying the beam current. Since both voltage
and current can be accurately measured and controlled, ion implantation results in much
more accurate and reproducible impurity profiles than can be obtained by diffusion. Ion
implantation can be performed at room temperature.Ion implantation normally is used
when accurate control of the dopant is essential for device operation.

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The impurity must be subjected to a high temperature activation (similar to drive-in,
except it is usually for a much shorter time) to reduce crystal lattice damage. The regular
arrangement of silicon lattice in <110> orientation leaves a large amount of open
space.The implanted ions may channel deep into the substrate.

Channeling can be

reduced by tilting the <100> silicon by approximately 7 relative to the ion beam.Tilted
implant can produce a doping profile with a junction depth that is closer to the theoretical
calculation.

CVD Deposition :
Chemical vapor deposition (CVD) is a process by which gases or vapors are chemically
reacted, leading to the formation of a solid on a substrate. CVD can be used to deposit
silicon dioxide on a silicon substrate. For instance, if silane gas and oxygen are mixed
above a silicon substrate, silicon dioxide deposits as a solid on the silicon.The quality of
the CVD oxide layer is not as good as a thermally grown oxide, but it is good enough to
act as an electrical insulator. The advantage of a CVD layer is that the oxide deposits at a
faster rate and a lower temperature (below 500C).

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Horizontal LPCVD Reactor

Exhaust

Metallization :
The purpose of metallization is to interconnect the various components of the integrated
circuit to form the desired circuit.Metallization involves the deposition of a metal
(aluminum) over the entire surface of the silicon. The required interconnection pattern is
then selectively etched.The aluminum is deposited by heating it in vacuum until it
vaporizes. The vapors then contact the silicon surface and condense to form a solid
aluminum layer.

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Sputtering

Si melts at 1412C, Al melts at 660C. When Si + Al are alloyed together, it exhibits a

eutectic characteristics such that the melting point of 577C is lower then either of the
element alone. Because of this low eutectic temperature, metallization is usually
performed at the very late stages of the fabrication process. After the deposition, the
aluminum is usually annealed in an inert atmosphere (e.g. 30 min, 450C).Although this
temperature is well below the melting point of aluminum, some silicon may diffuse into
the aluminum. Where ever aluminum comes into contact with silicon,some silicon will be
absorbed, leaving avoids behind.Since this is not a uniform process, random pits may
result. After the annealing, aluminum will fill up these voids, resulting in spikes
penetrating through the surface. Spikes may cause a short circuit in shallow junctions.
Use 1% Al-Si target. Metal silicide barriers T-Si, Pt-Si,etc.

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Photolithography :
The surface geometry of the various integrated-circuit components is defined
photographically. The silicon surface is coated with a photosensitive layer called
photoresist .To achieve uniform thickness, the photoresist is spin coated onto the silicon
wafer. The photoresist may be softened if exposed to light (positive resist) or soften if not
exposed (negative).The softened layer can then be removed using a chemical developer,
causing the mask pattern to appear on the wafer. Very fine surface geometries can be
reproduced accurately by this technique.

The photoresist layer forms an effective mask from the chemical etchants used for silicon
dioxide or aluminum. This allows windows to be etched in the oxide layer in
preparation for subsequent diffusion processes.

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The x10 mask is generated from computer layout. A step and repeat camera is used to
generate an array of dies on the final mask. The final mask is then used in the actual
patterning. Multiple masks must be aligned on top of each other.

Etching :
Chemical etching in liquid or gaseous form is used to remove any barrier material not
protected by hardened photoresist. The choice of chemicals depend on the material to be
etched (e.g. SiO2, nitride, poly, metal, etc.).
Wet Etch uses liquid chemical:
Buffered Hydroflouric Acid (BHF) for SiO2
Potassium Hydroxide (KOH) for Silicon
Phosphroic Acid for Aluminum
Hot Phosphroic Acid (180C) for Silicon Nitride

Wet Etch is usually non-direction. This phenomenon is called isotropic etching. In the
idea case, vertical sidewalls are expected. This type of etching is called anisotropic
etching. The etch time and temperature are critical such that over-etch can be avoided.

Wet Etch has various limitations for small geometries:

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Limited to pattern sizes of 3m or larger Isotropic, resulting in sloped sidewalls Requires
rinse and dry steps Wet chemicals are hazardous and/or toxic Potential for contamination
Failure of resist-wafer bond causes under cutting Dry Etch processes are more suitable
for small feature sizes.
Dry Etch is a generic term that refers to the etching techniques in which gases are the
primary etch medium. The wafers are etched without wet chemicals or rinsing. The
wafers enter and leave the etching system in dry state.There are three dry etching
techniques: plasma, ion-milling, and reactive ion etching (REI).Plasma etching uses
corrosive gases and plasma energy to cause the chemical reaction. Ion-milling uses ionbeam (inert gas, Ar) to physically bombard the wafer surface. Small amount of wafer
material is literally blasted out of the surface. The material removal is highly directional,
resulting in good definition of small openings. Being a physical process, ion-milling has
very poor selectivity, and may be prone to radiation damage. Reactive Ion Etching (RIE)
is a combination of plasma etching and ion-milling principles.

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Encapsulation
During Encapsulation, lead frames are placed onto mold plates and heated. Molten plastic
material is pressed around each die to form its individual package. The mold is opened,
and the lead frames are pressed out and cleaned.
Wafer Test
Upon completion of wafer fabrication, not all of the die on a wafer will be fully
functional. The yield loss at this step ranges from a few percent for mature processes, to
90% or more for new processes. In order to avoid adding additional value to defective
units during packaging, a 100% test of the die is performed.
Packaging
Silicon ICs in die form are difficult to handle, fragile even though they have a
protective layer, and the tiny bond pads are difficult to connect to. In order to further
protect the die and make the parts easier to handle and connect, packaging is
performed.
Probe testing:
Upon completion of wafer fabrication, not all of the die on a wafer will be fully
functional. The yield loss at this step ranges from a few percent for mature processes, to
90% or more for new processes. In order to avoid adding additional value to defective
units during packaging, a 100% test of the die is performed .Each die that has been
fabricated on the wafer has a series of pads referred to as bond pads where connections
will be made to the die during assembly. The die is covered with a protective passivation
layer everywhere except where the pads are located. For each type of die being tested a
specialized probe card is fabricated with a set of tiny needles spaced apart so they line
up with the bond pad openings - see figure 1.

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Figure 1. Simple probe card.

The wafer to be tested is held onto a chuck in a piece of equipment referred to as a wafer
prober - figure 2b. The prober also holds the probe card and mechanically positions the
probe card needles over the bond pads on a die, touches the needle down to make an
electrical connection for testing, and following testing lifts the needles and positions them
over the next die.The wafer prober is connected to a tester, an automated piece of
equipment that performs electrical tests on each die - see figure 2 .

Figure 2. Wafer test set-up.

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The tester is basically a computer and some power supplies, meters and function
generators that can be programmed to perform a variety of electrical measurements. The
tester communicates with the prober telling the prober when each die has been tested and
whether the die is good or not. When a die tests bad, a tiny ink dot may be dispensed
onto the die to mark it bad or an entry may be made in an electronic map to denote the
location of the bad die.
Wafer Test Terminology
Probe card - a card with tiny needles used to make electrical connections to IC die being
tested.
Bond pad - pads on the die where electrical connection may be made.
Tester - a computer controlled system that performs electrical tests automatically.
Prober - a piece of equipment that holds the probe card and wafer being tested and steps
the card across the wafer contacting each die. Operates under control of the tester.

Packaging
Silicon ICs in die form are difficult to handle, fragile even though they have a
protective layer, and the tiny bond pads are difficult to connect to. In order to further
protect the die and make the parts easier to handle and connect, packaging is performed.
Historically, the most common packing method is as follows.
After wafer test, the wafer is mounted onto sticky tape stretched over a metal frame.
The backside - non circuit side of the wafer is stuck to the tape. An automated - high
speed saw with a very thin diamond blade is used to saw apart the die. There is an area
between each die that has no circuitry referred to as a street so that sawing does not
damage the IC circuitry. The sticky tape serves to hold the individual die in place after
sawing, see figure 3 - 1a through 3.
Each good die on the wafer is now removed from the sticky tape and placed onto a
metal frame referred to as a lead frame. This operation is performed by automated pick
and place machines.

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The leadframe is etched or stamped into a pattern that will later become the electrical
connection pins that protrude from the package. The leadframe also includes a pad that
the die is epoxy mounted to, see figure 3 - 4a through 4c.
Tiny wires, typically gold, are now attached from each bond pad down to a
corresponding lead frame pin. This is the electrical connections from the die to the pins
that eventually connects the die to the outside world. Wire bonding is also performed by
automated systems referred to as wire bonders, see figure 3 - 5.
A rectangular area of black epoxy is now molded around the die and lead frame leaving
the lead frame pins sticking out. Molding is accomplished in large presses under heat and
pressure, see figure 3 - 6.
A mechanical tool now punches out each individual packaged IC from the lead frame
bars that held the units in rows. The tool also bends the leads forming them into their
final configuration.
The units are branded with a part number, company name, date, etc. on the epoxy plastic
to identify the part. Figure 4 illustrates the common package styles and their popularity.
Recently, newer techniques have been developed to produce smaller packages and also
enable higher frequency connections to ICs. The relatively large pins used to connect
plastic packages to the outside world degrade high frequency signals. The newer
techniques are generically referred to as chip scale packaging, the idea being that the
package is barely any bigger than the silicon chip. One technique is called flip chip.

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Figure 20. Plastic packaging process.

Figure 21. Common package styles and popularity

In flip chip processing, tiny solder balls are fabricated on the bond pads, the silicon chip
is then flipped over and soldered down to connecting pads on a substrate.

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The technique is compatible with high frequency, less expensive than wire bonding for
high connections counts, and results in a very small package. Additionally, for wire
bonding, pads need to be at or near the edge of the IC to minimize wire length. In some
cases the number of pads required for electrical connections exceeds the number that will
fit around the periphery of the IC. The IC size must be increased just to accommodate
pads increasing the IC size and cost. With a flip chip approach pads can be placed in an
array anywhere on the IC - see figure 22.
Integrated Resistors:
Resistors in integrated form are not very precise.
They can be made from various diffusion regions.
The basic technique for obtaining a resistor in integrated circuit is by utilizing the
bulk resistance of a define volume of semiconductor region
Four different methods are available for fabricating integrated resistors namely
Diffused resistor, Epitaxial resistor, pinched resistor and thin film resistor.

Integrated Capacitors:
Three types of capacitor structure are available in cmos process.Mos , Interpoly
(MIM-metal insulator metal ), Junction capacitor
Mos capacitor: The Mos gate capacitance is basically the gate to source
capacitance of a MOSFET.
The capacitance value is dependent on the gate area.
The oxide thickness is same as the gate oxide thickness in the MOSFETS.
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This capacitor exhibits a large voltage dependence. To eliminate this problem, an
additional n+ implant is required to form at the bottom plate of the capacitor.
Interpoly:
The inter poly capacitor exhibits near ideal characteristics but at the expense of
the inclusion of a second poly silicon layer to the cmos process.
Since the capacitor is placed on top of the thick field oxide, parasitic effects are
kept to a minimum.
Junction capacitor:
Any PN junction under reversed bias produces a depletion region that acts as a
dielectric between the P and N regions.
This type of capacitor is often used as a varactor for tuning circuits.
This capacitor works only with reverse bias voltages.

CMOS Nano Technology:

A lot of research effort has been devoted to developing the concept of molecule on
CMOS architecture (CMOL). These are hybrid CMOS / nanoelectronic systems that are
based on conventional CMOS devices connected to nanowire arrays with molecular
elements functioning as programmable diodes.

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These are predicted to have very attractive performance potential compared to scaled
CMOS systems, but no successful demonstrations have been realised so far. Perhaps the
first potential application is using the bistable behaviour of certain molecules to produce
memories with an extremely high density. Specific issues, such as contacting the
molecule, carrying enough current to provide noise immunity and a reasonable fan-out,
and the addressing and read out of specific blocks remain to be solved. In addition to
logic operations, molecular devices could potentially be used for several other
applications. For example, molecular schemes for combinatorial logic have been
envisaged.
Computing has been demonstrated using DNA molecules utilizing self-assembly to
perform computational steps in test-tubes. The key challenges for molecular devices
include the ability to electrically stimulate and measure response or the state. In some
systems, protons have been used to communicate signals. Optical signal communication
is also being investigated. Tunneling transport between molecular wires and devices is
actively being researched and may be a viable option.The subject of molecular and DNA
switches is also discussed in the report on Novel Biomaterials.

Nanophotonics
A promising alternative for information transfer is to use light in the visible or infrared
range. Nanophotonics allows the confinement and interaction of photons and electrons in
a small volume which opens up the possibility of processing data at high frequency.
This subject is discussed in detail in ICT subsector report Photonics.
Nanoelectromechanical systems (NEMS)
NEMS devices hold the promise to improve abilities to measure small displacements and
forces at a molecular scale. The ITRS 2007 edition contains NEMS memory as a new
entry for the Emerging Research Devices section.

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Nanosensors
Nanosensors are any type of sensors (biological, chemical or other) that convey
molecular-level information to the macroscopic world. Future multifunctional systems
are envisioned to integrate nanoscale computing devices with sensing capabilities for use
in various application areas ranging from communications to medical uses.
The potential of nanosensors as part of future computing systems lies in their capability
to provide the link between other forms of nanotechnology and the macroscopic world.
This would allow full exploitation of the potential of miniaturisation of computer chips
while vastly expanding their storage potential.
However, before widespread implementation to consumer products becomes feasible,
Developers must overcome several major issues related to reliability, compatibility with
CMOS technology, difficulties in mass manufacturing and high costs of production.
The topic of nanosensors and biosensors is also discussed in ICT sector report Integrated
circuits.

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