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home work and solution for OPAMP

home work and solution for OPAMP

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You are on page 1of 6

EE 42/100

Spring 2012

Prof. A. Niknejad

Problem Set 4

Solutions

Please note that these are merely suggested solutions. Many of these problems can be

approached in different ways.

1. (a) Notice that the first op amp is simply a noninverting amplifier with input vin and

the second is an inverting amplifier with the same input. Denoting the respective

2

vin and

outputs of the op amps by vo1 and vo2 , we immediately infer that vo1 = R1R+R

1

R4

vo2 = R3 vin . If you do not see this, you can also write nodal equations at the

noninverting inputs of the op amps after applying the golden rules. Now the output

vo is given by the difference of the above two voltages:

R1 + R2 R4

vin

+

vo = vo1 vo2 =

R1

R3

(b) Since the supply voltages are Vs , the maximum output that can be achieved

across RL is when vo1 = Vs and vo2 = Vs , giving us a total output of 2Vs . This can

be potentially useful because it allows us to achieve a greater gain than is normally

allowed by our supply voltages.

2. While the circuit looks intimidating, we can make massive simplifications by applying

the golden rules to each op amp. We are left with only two unknown voltages as

shown below:

8 k

v1

2 k

0

vx

20 k

40 k

0.5 k

vx

4 k

vx

vy

10 k

vo

10 k

v2

vy

vy

2 k

vy

0

16 k

40 k

vy

0.5 k

Firstly, the first two op amps have their inverting inputs at a virtual ground due to

the connection to ground at their noninverting inputs. Notice that the two 40 k

resistors dont induce any voltage drop between the first pair of op amps and the

second, as the currents into the op amp inputs are always 0. Because both of the

middle op amps are buffers, vx and vy get carried over to their outputs. Finally, there

is no voltage drop across the bottom 0.5 k resistor due to lack of current (note this

is NOT true for the one on the top).

With all this in mind, we can simply solve for vx and vy , and this will give us access

to vo . Both vx and vy are given by inverting amplifiers:

vx =

8 k

v1 = 4v1

2 k

16 k

v1 = 8v2

2 k

KCL at the inverting input of the last op amp gives us

vy =

vy vx vy vo

+

=0

0.5 k

4 k

Plugging in for our quantities previously solved gives us vo = 32v1 72v2 .

3. (a) Since the first pair of op amps are both buffers, their inputs carry over to their

respective output nodes. In addition, we can define one unknown node vx at both

inputs of the third op amp, by usage of the golden rules. KCL at the bottom

noninverting input node gives us vx due to voltage divider:

vx =

R3

v2

R2 + R3

vx v1 vx vo

+

=0

R2

R3

Plugging in for vx and solving for vo gives us vo =

R3

(v

R2 2

v1 ).

(b) The situation here is a bit more complex, as we do not know explicitly what the

outputs of the first pair of op amps are. Call them vo1 and vo2 . If we write nodal

equations at the noninverting inputs of these op amps, we get two plus the two from

the last part, giving us four equations.

v1 vo1 v1 v2

+

=0

R1

Rgain

v2 vo2 v2 v1

+

=0

R1

Rgain

vx =

R3

vo2

R2 + R3

2

vx vo1 vx vo

+

=0

R2

R3

Plug the third into the fourth equation to get rid of vx . Then solve the first two

equations for vo1 and vo2 and plug them in to obtain vo in terms of v1 and v2 .

vo =

vo1 =

R3

R3

R2 + R3

vx

vo1 =

(vo2 vo1 )

R2

R2

R2

R1

R1

(v1 v2 ) + v1 , vo2 =

(v2 v1 ) + v2

Rgain

Rgain

!

2R1 R3

vo = 1 +

(v2 v1 )

Rgain R2

4. (a) The circuit redrawn with the transconductance amplifier model looks like the

following (notice the placement of each of the components):

io

Rs

is

R in

+

vi

Gv i

R out

RL

(b) The output current io is simply given by the current divider of the current Gvi :

io =

So Gmsc =

io

vi

Rout

10 k

Gvi =

10000vi = 8333vi

Rout + RL

10 k + 2 k

= 8333.

(c) To calculate the output, we simply need to relate the input current is to vi :

io = 8333vi = 8333(Rs ||Rin )is = 8333(5 k||100 )(1 A) = 0.817 A

5. (a) The order of the amplifiers will matter due to the nonidealities of each and the

loading effects that they cause. For order AB, our circuit can be redrawn:

1 k

1

i in

1V

1 k

+

vin

10

8vin

10i in

1 M

100

The power input is given by the power through the input source vs :

1V

Pi = vs is = (1 V)

= 0.5 mW

1 k + 1 k

The power output can be found by using the current going through RL :

2

2

1 M

8vin

2

10iin (100 ) = 9998

Po = iL RL =

= 5288(0.5 V)2 = 1322 W

1 M + 100

1 + 10

Now consider the order BA:

1 k

1

i in

10i in

10

1V

1 M

Pi = vs is = (1 V)

v2

Po = L =

RL

1 k

1V

1 k + 10

+

vin

8vin

100

= 0.99 mW

2

100

8vin /(100 ) = 0.627[10iin (1 M||1 k)]2

1 + 100

2

1V

7

= 6.26 10

= 61.3 W

1 k + 10

Clearly, the power gain of AB is much greater, with 2.65 106 as opposed to 62000 of

BA. Without the amplifiers, the power gain is smaller than 1:

i2 RL

RL

vs

RL

100

GP =

=i

=

=

= 0.099

ivs

vs

RS + RL vs

100 + 1000

(b) Consider the power output in the absence of the second stage (replace the 10

resistor with a 100 ).

Po =

i2L RL

=

8vin

1 + 100

2

Clearly, the second stage delivers a lot more power to the load.

1k

(c) The voltage gain of the first stage is 1k +1k

A 10 = 3.64. The gain of the

v 1 +10

1k

Av

cascade amplifiers is 1k +1k

Ai 1M ||100 = 363.6. Since the cascade voltage

11

gain is larger than the gain of the first state, the second stage will clip first when the

V

input voltage is 10

= 27.5 mV.

363.6

6. (a) For the sequence BAC, we first have a noninverting amplifier, followed by an

inverting amplifier, and finally a voltage follower. The gain is thus

R2

8k

6k

R4

(1) = 1 +

= 9

G= 1+

R3

R1

4k

2k

The load resistance seen by the voltage input is infinite, since no current flows into

the noninverting input of op amp B.

(b) The gain here is the same, since it is order-independent (multiplication is

commutative). However, the input resistance is not 0 in this case; instead, it is

R1 = 2 k, since the source sees the inverting amplifier first. So in terms of overall

gain, both orderings are equally good. However, the former is better for voltage

amplification, as its input resistance is much higher.

(c) The voltage gain remains the same in both cases, since the third stage does not

affect it. It is usually useful to prevent loading effects at either the input or output of

an op amp, especially if it is non-ideal (although it doesnt play any role here since all

the op amps are ideal).

7. On the left side, we first combine the 10 F with the 5 F in series, followed by the

9 F in parallel:

Ceq1 = (10 F||5 F) + 9 F = 12.3 F

On the right side, the 9 F is in parallel with the 7 F, followed by a series connection

with the 8 F.

Ceq2 = (9 F + 7 F)||(8 F) = 5.33 F

These two equivalent capacitances are in parallel with each other, as seen by a and b.

Ceq = Ceq1 + Ceq2 = 17.7 F

8. Note that before t = 0, all the current shorts through the middle branch, since there

is no charge nor voltage on the capacitor. Once the switch opens, the capacitor must

sustatin a constant 20 mA current to satisfy KCL.

Z

Z 50 ms

1

(20 mA)(50 ms)

1 50 ms

v(t = 50 ms) =

i(t)dt =

20 mAdt =

= 20 V

C 0

50 F 0

50 F

p(t = 50 ms) = v(t = 50 ms)i(t = 50 ms) = (20 V)(20 mA) = 0.4 W

1

1

w(t = 50 ms) = Cv 2 (t = 50 ms) = (50 F)(20 V)2 = 0.01 J

2

2

9. The current is given by i(t) = C dv(t)

. Hence it is sufficient to differentiate the given

dt

graph of voltage in segments. We thus have i(t) = 50 A for 0 < t < 1, i(t) = 0 for

1 < t < 4, i(t) = 37.5 A for 4 < t < 6, i(t) = 0 for 6 < t < 9, and i(t) = 25 A for

9 < t < 10. Note that all times listed are in s.

The net charge and energy are both 0, since both are proportional to voltage, which

is itself 0 at the end time t = 10 s. (We are only concerned with net charge and

energy, which represents the total transferred.)

5

10. Since both capacitors are initially uncharged, conservation demands that the net

charge at each node remain 0 after the voltage source is connected. We apply this

principle to the node between the two capacitors. Since we are looking at the

negative plate of cap 1 and the positive plate of cap 2, we must have that

q1 + q2 = 0

Remember that the charge on parallel-plate capacitors are equal and opposite.

Another relation we can construct using KVL is the following:

15 V = v1 + v2 =

q1

q2

q1

q2

+

=

+

C1 C2

12 F 28 F

The above two equations give us a system that we can solve. The solutions are

q1 = q2 = 0.126 mC. With this we find that the voltages are v1 = 10.5 V and

v2 = 4.5 V.

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