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Big Picture
Many weeks ago + 1:
This week:
Synchronous pipelines
& data transactions
Asynchronous pipelines
& data transactions
{Synchronous, Asynchronous*} FIFOs
Motivation
We want to pass data across clock domains
Well, why not use a data/hold register?
footnote:
with as high a throughput as possible
Applications
Rate matching video interfaces
Communicating to off-chip components
Bulk data transfer/DMA across a chip
UCB EECS150 Spring 2010, Honors #14
an
We
w
Valid
Recall: Clock
Ready
e
We g
Synchronizer delay
The bad
Works badly when the FIFO is in the full/empty
state most of the time
Why? Every time the FIFO goes full/empty,
we impose the synchronizer delay
Proposal #1
Pulse based inc/dec
Resources
Clock Domain B
Clock Domain A
Write
2n counter FFs
2n pointer FFs
4 synchronizers FFs
Inc
Count
Dec
Pulse
Synch
1b
!= Depth
Incr
Write
Pointer
Output
Read
Pointer
Buffer
Incr
Input
!=0
1b
Pulse
Synch
Inc
Count
Read
Dec
Proposal #2
Clock Domain B
Clock Domain A
Binary pointers
Data
Level
Level
Sync
Synch
Synch
Direct comparison
Nb
!=Full
Resources
Write
2n pointer FFs
2n + 4 synchronizer FFs
Output
Write
Pointer
Buffer
Read
Pointer
Read
Input
!= Empty
Nb
Data
Level
Level
Sync
Synch
Synch
Synch
Handshake
Synch
Data
Synch
Handshake
Synch
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
0000
9
Proposal #3
Gray code pointers
Gray
Bin
Direct comparison
Requires GCBin
Resources
Level
Level
Level
Synch
Synch
Synch
Nb
!=Full
Write
2n pointer FFs
4n synchronizer FFs
GCBin converters
Buffer
Gray
Bin
Read
Pointer
Read
Input
Output
Gray
Bin
Write
Pointer
Clock Domain B
Clock Domain A
!= Empty
Nb
Level
Level
Level
Synch
Synch
Synch
Gray
Bin
10
11
UC Berkeley CS150 (Spring 2010): Components and Design Techniques for Digital Systems
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