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  • Mtech VLSI Projects List 2016

    Загружено:

    Nsrc Nano Scientifc
    56 просмотров4 страницы
    MTech VLSI IEEE Projects list, We arev Specialized on Btech/MTech/PHD Vlsi Designing (frontend & Backend)ss NVD-01 A DYNAMICALLY RECONFIGUBLE MULTI-ASIP ARCHITECTURE FOR MULTI STANDARD AND MULTIMODE TURBO DECODING 2015 NVD-02 LOW-COST HIGH-PERFORMANCE VLSI ARICTURE FOR MONTGOMERY MODULAR MULTIPLICATION 2015 NVD-03 FUNCTIONAL CONSTRAINT EXTRACTION FROM REGISTER FTRANSFER LEVEL FOR ATPG 2015 NVD-04 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES 2015 NVD-05 DSCANPUF:A DEALY-BASED PHYSICIAL UNCLONABLE FUNCTION BUILT INTO SCAN CHAIN 2015 NVD-06 PRE-ENCODED MULTIPLIERS BASED ON NON-REDUNDANT RADIX-4 SIGNED-DIGIT ENCODING 2015 NVD-07 QUANTUM COST REALIZATION OF NEW REVERSIBLE GATES WITH TRANSFORMATION BASED SYNTHESIS TECHINIQUE 2015 NVD-08 ON THE ANALYSIS OF REVERSIBLE BOOTH’S MULTIPLIER 2015 NVD-09 OPTIMIZED LOGARITHMIC BARREL SHIFTER IN REVERSIBLE LOGIC SYNTHESIS 2015 NVD-10 A NOVEL DELAY & QUANTUM COST EFFICIENT REVERSIBLE REALIZATION OF 2I*J RANDOM ACCESS MEMORY 2015 NVD-11 EXPLOITING SAME TAG BITS TO IMPROVE THE RELIABLITY OF THE CACHE MEMORIES 2015 NVD-12 HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS 2015 NVD-13 32 BIT*32 BIT MULTI PRECISION RAZOR-BASED DYNAMIC VOLTAGE SCALING MULTIPLY OPERATOR 2014(P) NVD-14 AN OPTIMIZED MODIFIED BOOTH RECODER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY OPERATOR 2014(P) NVD-15 HIGH-THROUGHPUT MULTI STANDARD TRANSFORM CORE SUPPORTING MPEG/H.264/VC-1 USING COMMON SHARING DISTRIBUTED ARITHMETIC 2014(P) NVD-16 IMPROVED 8-POINT APPORIXIMATE DCT FOR IMAGE AND VIDEO COMPRESSION REQUIRING ONLY 14 ADDITIONS 2014(P) NVD-17 AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER 2014(P) NVD-18 MULTIFUNCTION RESIDUE ARCHITECTURES FOR CRYPTOGRAPHY 2014(P) NVD-19 LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATD ENCODED WITH HARD SYSTEMATIC ERROR-CORRECTING CODES 2014(P) NVD-20 ENERGY-EFFICIENT HIGH-THROUGHPUT MONTGOMERY MODULAR MULTIPLIERS FOR RSA CRYPTOSYSTEMS 2014(P) NVD-21 A CLASS OF SEC-DED-DAEC CODES DERIVED FROM ORTHOGONAL LATIN SQUARE CODES 2014 NVD-22 EFFICIENT FFPGA AND ASIC REALIZATIONS OF A DA-BASED RECONFIGARABLE FIR DIGITAL FILTER 2014 NVD-23 LOW-POWER DIGITAL SIGNAL PROCESSOR ARCHITECTURE FOR WIRELESS SENSOR NODES 2014 NVD-24 ERROR DETECTION IN MAJIRITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK(EG-LDPC)CODES 2013(T) NVD-25 LOW-POWER HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC 2013(T) NVD-26 RADIX-4 AND RADIX-8 BOOTH ENCODED MULTI-MODULUS MULTIPLIERS 2013(T) NVD-27 DESIGN AND IMPLEMENTATION OF AN ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM-ON-CHIP 2013(T) NVD-28 MULTI OPERAND REDUNDANT ADDERS ON FPGAS 2013 NVD-29 GLOBAL BUILT-IN SELF-REPAIR FOR 3D MEMORIES WITH REDUNDANCY SHARING AND PARALLEL TESTING 2013 NVD-30 A PRACTICAL NOC DESIGN FOR PARALLEL DES COMPUTATIOM 2013 NVD-31 PARALLEL AES ENCRYPTION ENGINES FOR MANY-CORE PROCESSOR ARRAYS 2013 NVD-32 VLSI IMPLEMENTATION OF A HIGH SPEED SINGLE PRECISION FLOATING POINT UNIT USING VERILOG 2013 NVD-33 A VLIW ARCHITECTURE FOR EXECUTING MULTI-SCALAR/VECTOS INSTRUCTIONS ON UNIFIED DATAPATH 2013 NVD-34 A NOVEL MODULO ADDER FOR 2^n-2^k-1 RESIDUE NUMBER SYSTEM 2013(T) NVD-35 LOW-COST FIR FILTER DESIGNS BASED ON FAITHFULLY ROUNDED TRUNCATED MULTIPLE CONSTANT MULTIPLICATION/ACCUMUIATION 2013(T) NVD-36 LOW-POWER, HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC NVD-37 DESIGN AND IMPLIMENTATION OF 32 BIT UNSIGED MULTIPLIER USING CLAA AND CSLA 2013 NVD-38 ENCHANCED AREA EFFICIENT ARCHITECTURE FOR 128 BIT MODIFIED CSLA 2013 NVD-39 HIGH PERFORMANCE HARDWARE IMPLIMENTATION OF AES USING MINIMAL RESOURCES 2013 NVD-40 IMPLIMENTATION OF 12C MASTER BUS CONTROLLER ON FPGA 2013 NVD-41 NOVEL HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSOR 2013 NVD-42 VLSI IMPLIMENTAION OF A HIGH SPEED SINGLE PRECISSION FLOATING POINT UNIT USING VERILOG 2013 NVD-43 VLSI IMPLIMENTATION OF FAST ADDITION USIN

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    MTech VLSI IEEE Projects list, We arev Specialized on Btech/MTech/PHD Vlsi Designing (frontend & Backend)ss NVD-01 A DYNAMICALLY RECONFIGUBLE MULTI-ASIP ARCHITECTURE FOR MULTI STANDARD AND MULTIMODE TURBO DECODING 2015 NVD-02 LOW-COST HIGH-PERFORMANCE VLSI ARICTURE FOR MONTGOMERY MODULAR MULTIPLICATION 2015 NVD-03 FUNCTIONAL CONSTRAINT EXTRACTION FROM REGISTER FTRANSFER LEVEL FOR ATPG 2015 NVD-04 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES 2015 NVD-05 DSCANPUF:A DEALY-BASED PHYSICIAL UNCLONABLE FUNCTION BUILT INTO SCAN CHAIN 2015 NVD-06 PRE-ENCODED MULTIPLIERS BASED ON NON-REDUNDANT RADIX-4 SIGNED-DIGIT ENCODING 2015 NVD-07 QUANTUM COST REALIZATION OF NEW REVERSIBLE GATES WITH TRANSFORMATION BASED SYNTHESIS TECHINIQUE 2015 NVD-08 ON THE ANALYSIS OF REVERSIBLE BOOTH’S MULTIPLIER 2015 NVD-09 OPTIMIZED LOGARITHMIC BARREL SHIFTER IN REVERSIBLE LOGIC SYNTHESIS 2015 NVD-10 A NOVEL DELAY & QUANTUM COST EFFICIENT REVERSIBLE REALIZATION OF 2I*J RANDOM ACCESS MEMORY 2015 NVD-11 EXPLOITING SAME TAG BITS TO IMPROVE THE RELIABLITY OF THE CACHE MEMORIES 2015 NVD-12 HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS 2015 NVD-13 32 BIT*32 BIT MULTI PRECISION RAZOR-BASED DYNAMIC VOLTAGE SCALING MULTIPLY OPERATOR 2014(P) NVD-14 AN OPTIMIZED MODIFIED BOOTH RECODER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY OPERATOR 2014(P) NVD-15 HIGH-THROUGHPUT MULTI STANDARD TRANSFORM CORE SUPPORTING MPEG/H.264/VC-1 USING COMMON SHARING DISTRIBUTED ARITHMETIC 2014(P) NVD-16 IMPROVED 8-POINT APPORIXIMATE DCT FOR IMAGE AND VIDEO COMPRESSION REQUIRING ONLY 14 ADDITIONS 2014(P) NVD-17 AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER 2014(P) NVD-18 MULTIFUNCTION RESIDUE ARCHITECTURES FOR CRYPTOGRAPHY 2014(P) NVD-19 LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATD ENCODED WITH HARD SYSTEMATIC ERROR-CORRECTING CODES 2014(P) NVD-20 ENERGY-EFFICIENT HIGH-THROUGHPUT MONTGOMERY MODULAR MULTIPLIERS FOR RSA CRYPTOSYSTEMS 2014(P) NVD-21 A CLASS OF SEC-DED-DAEC CODES DERIVED FROM ORTHOGONAL LATIN SQUARE CODES 2014 NVD-22 EFFICIENT FFPGA AND ASIC REALIZATIONS OF A DA-BASED RECONFIGARABLE FIR DIGITAL FILTER 2014 NVD-23 LOW-POWER DIGITAL SIGNAL PROCESSOR ARCHITECTURE FOR WIRELESS SENSOR NODES 2014 NVD-24 ERROR DETECTION IN MAJIRITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK(EG-LDPC)CODES 2013(T) NVD-25 LOW-POWER HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC 2013(T) NVD-26 RADIX-4 AND RADIX-8 BOOTH ENCODED MULTI-MODULUS MULTIPLIERS 2013(T) NVD-27 DESIGN AND IMPLEMENTATION OF AN ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM-ON-CHIP 2013(T) NVD-28 MULTI OPERAND REDUNDANT ADDERS ON FPGAS 2013 NVD-29 GLOBAL BUILT-IN SELF-REPAIR FOR 3D MEMORIES WITH REDUNDANCY SHARING AND PARALLEL TESTING 2013 NVD-30 A PRACTICAL NOC DESIGN FOR PARALLEL DES COMPUTATIOM 2013 NVD-31 PARALLEL AES ENCRYPTION ENGINES FOR MANY-CORE PROCESSOR ARRAYS 2013 NVD-32 VLSI IMPLEMENTATION OF A HIGH SPEED SINGLE PRECISION FLOATING POINT UNIT USING VERILOG 2013 NVD-33 A VLIW ARCHITECTURE FOR EXECUTING MULTI-SCALAR/VECTOS INSTRUCTIONS ON UNIFIED DATAPATH 2013 NVD-34 A NOVEL MODULO ADDER FOR 2^n-2^k-1 RESIDUE NUMBER SYSTEM 2013(T) NVD-35 LOW-COST FIR FILTER DESIGNS BASED ON FAITHFULLY ROUNDED TRUNCATED MULTIPLE CONSTANT MULTIPLICATION/ACCUMUIATION 2013(T) NVD-36 LOW-POWER, HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC NVD-37 DESIGN AND IMPLIMENTATION OF 32 BIT UNSIGED MULTIPLIER USING CLAA AND CSLA 2013 NVD-38 ENCHANCED AREA EFFICIENT ARCHITECTURE FOR 128 BIT MODIFIED CSLA 2013 NVD-39 HIGH PERFORMANCE HARDWARE IMPLIMENTATION OF AES USING MINIMAL RESOURCES 2013 NVD-40 IMPLIMENTATION OF 12C MASTER BUS CONTROLLER ON FPGA 2013 NVD-41 NOVEL HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSOR 2013 NVD-42 VLSI IMPLIMENTAION OF A HIGH SPEED SINGLE PRECISSION FLOATING POINT UNIT USING VERILOG 2013 NVD-43 VLSI IMPLIMENTATION OF FAST ADDITION USIN

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    © All Rights Reserved
    Скачайте в формате DOC, PDF, TXT или читайте онлайн в Scribd
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    56 просмотров4 страницы

    Mtech VLSI Projects List 2016

    Загружено:

    Nsrc Nano Scientifc
    MTech VLSI IEEE Projects list, We arev Specialized on Btech/MTech/PHD Vlsi Designing (frontend & Backend)ss NVD-01 A DYNAMICALLY RECONFIGUBLE MULTI-ASIP ARCHITECTURE FOR MULTI STANDARD AND MULTIMODE TURBO DECODING 2015 NVD-02 LOW-COST HIGH-PERFORMANCE VLSI ARICTURE FOR MONTGOMERY MODULAR MULTIPLICATION 2015 NVD-03 FUNCTIONAL CONSTRAINT EXTRACTION FROM REGISTER FTRANSFER LEVEL FOR ATPG 2015 NVD-04 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES 2015 NVD-05 DSCANPUF:A DEALY-BASED PHYSICIAL UNCLONABLE FUNCTION BUILT INTO SCAN CHAIN 2015 NVD-06 PRE-ENCODED MULTIPLIERS BASED ON NON-REDUNDANT RADIX-4 SIGNED-DIGIT ENCODING 2015 NVD-07 QUANTUM COST REALIZATION OF NEW REVERSIBLE GATES WITH TRANSFORMATION BASED SYNTHESIS TECHINIQUE 2015 NVD-08 ON THE ANALYSIS OF REVERSIBLE BOOTH’S MULTIPLIER 2015 NVD-09 OPTIMIZED LOGARITHMIC BARREL SHIFTER IN REVERSIBLE LOGIC SYNTHESIS 2015 NVD-10 A NOVEL DELAY & QUANTUM COST EFFICIENT REVERSIBLE REALIZATION OF 2I*J RANDOM ACCESS MEMORY 2015 NVD-11 EXPLOITING SAME TAG BITS TO IMPROVE THE RELIABLITY OF THE CACHE MEMORIES 2015 NVD-12 HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS 2015 NVD-13 32 BIT*32 BIT MULTI PRECISION RAZOR-BASED DYNAMIC VOLTAGE SCALING MULTIPLY OPERATOR 2014(P) NVD-14 AN OPTIMIZED MODIFIED BOOTH RECODER FOR EFFICIENT DESIGN OF THE ADD-MULTIPLY OPERATOR 2014(P) NVD-15 HIGH-THROUGHPUT MULTI STANDARD TRANSFORM CORE SUPPORTING MPEG/H.264/VC-1 USING COMMON SHARING DISTRIBUTED ARITHMETIC 2014(P) NVD-16 IMPROVED 8-POINT APPORIXIMATE DCT FOR IMAGE AND VIDEO COMPRESSION REQUIRING ONLY 14 ADDITIONS 2014(P) NVD-17 AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER 2014(P) NVD-18 MULTIFUNCTION RESIDUE ARCHITECTURES FOR CRYPTOGRAPHY 2014(P) NVD-19 LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATD ENCODED WITH HARD SYSTEMATIC ERROR-CORRECTING CODES 2014(P) NVD-20 ENERGY-EFFICIENT HIGH-THROUGHPUT MONTGOMERY MODULAR MULTIPLIERS FOR RSA CRYPTOSYSTEMS 2014(P) NVD-21 A CLASS OF SEC-DED-DAEC CODES DERIVED FROM ORTHOGONAL LATIN SQUARE CODES 2014 NVD-22 EFFICIENT FFPGA AND ASIC REALIZATIONS OF A DA-BASED RECONFIGARABLE FIR DIGITAL FILTER 2014 NVD-23 LOW-POWER DIGITAL SIGNAL PROCESSOR ARCHITECTURE FOR WIRELESS SENSOR NODES 2014 NVD-24 ERROR DETECTION IN MAJIRITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK(EG-LDPC)CODES 2013(T) NVD-25 LOW-POWER HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC 2013(T) NVD-26 RADIX-4 AND RADIX-8 BOOTH ENCODED MULTI-MODULUS MULTIPLIERS 2013(T) NVD-27 DESIGN AND IMPLEMENTATION OF AN ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM-ON-CHIP 2013(T) NVD-28 MULTI OPERAND REDUNDANT ADDERS ON FPGAS 2013 NVD-29 GLOBAL BUILT-IN SELF-REPAIR FOR 3D MEMORIES WITH REDUNDANCY SHARING AND PARALLEL TESTING 2013 NVD-30 A PRACTICAL NOC DESIGN FOR PARALLEL DES COMPUTATIOM 2013 NVD-31 PARALLEL AES ENCRYPTION ENGINES FOR MANY-CORE PROCESSOR ARRAYS 2013 NVD-32 VLSI IMPLEMENTATION OF A HIGH SPEED SINGLE PRECISION FLOATING POINT UNIT USING VERILOG 2013 NVD-33 A VLIW ARCHITECTURE FOR EXECUTING MULTI-SCALAR/VECTOS INSTRUCTIONS ON UNIFIED DATAPATH 2013 NVD-34 A NOVEL MODULO ADDER FOR 2^n-2^k-1 RESIDUE NUMBER SYSTEM 2013(T) NVD-35 LOW-COST FIR FILTER DESIGNS BASED ON FAITHFULLY ROUNDED TRUNCATED MULTIPLE CONSTANT MULTIPLICATION/ACCUMUIATION 2013(T) NVD-36 LOW-POWER, HIGH-THROUGHPUT,AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC NVD-37 DESIGN AND IMPLIMENTATION OF 32 BIT UNSIGED MULTIPLIER USING CLAA AND CSLA 2013 NVD-38 ENCHANCED AREA EFFICIENT ARCHITECTURE FOR 128 BIT MODIFIED CSLA 2013 NVD-39 HIGH PERFORMANCE HARDWARE IMPLIMENTATION OF AES USING MINIMAL RESOURCES 2013 NVD-40 IMPLIMENTATION OF 12C MASTER BUS CONTROLLER ON FPGA 2013 NVD-41 NOVEL HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSOR 2013 NVD-42 VLSI IMPLIMENTAION OF A HIGH SPEED SINGLE PRECISSION FLOATING POINT UNIT USING VERILOG 2013 NVD-43 VLSI IMPLIMENTATION OF FAST ADDITION USIN

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    © All Rights Reserved
    Скачайте в формате DOC, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 4

    An ISO 9001:2008 Certified Company

    #404, Siri Estates, Opp. Lane to R.S. Brothers, Ameerpet, Hyderabad-500073.


    E-mail: info@nanocdac.com, www.nsrcnano.com, +91-8297578555, +91-9640648777

    VLSI
    M.Tech/M.E IEEE Project List 2015-16
    Nanocdac, 08297578555, info@nsrcnano.com
    CODE

    PROJECT TITLE

    NVD-01

    2015

    NVD-03

    A Dynamically R econfigurable Multi-ASIP Architecture for Multi standard


    and Multimode Turbo Decoding
    Low-Cost High-Perfor mance VLSI Archit ecture for Montgomer y Modular
    Multiplication
    Functional Constraint Extraction From Register Transfer Level for ATPG

    NVD-04

    Fault Tolerant Parallel Filt ers Based on Error Correction Codes

    2015

    NVD-05

    2015

    NVD-08

    DScanPUF: A Delay-Based Physical Unclonable Function Built Int o Scan


    Chain
    Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit
    Encoding
    Quantum cost realization of new reversible gat es with transfor mation based
    synthesis technique
    On the Analysis of Reversible Booths Multiplier

    NVD-09

    Optimized Logarithmic Barrel Shift er in Reversible Logic Synthesis

    2015

    NVD-10

    2015

    NVD-11

    A novel delay & Quantum Cost efficient r eversible realization of 2i j


    Random Access Memor y
    Exploiting Same Tag Bits to Improve the Reliability of the Cache Memor ies

    NVD-12

    Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

    2015

    NVD-13

    32 Bit32 Bit Multi precision Razor-Based Dynamic Voltage Scaling


    Multiplier With Operands Scheduler
    An Optimized Modified Booth Recoder for Efficient Design of the AddMultiply Operator
    High-Throughput
    Multi
    standard
    Transform
    Core
    Supporting
    MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

    2014(T)

    NVD-16

    Improved 8-Point Approximate DCT for Image and Video Compression


    Requiring Only 14 Additions

    2014(T)

    NVD-17

    AreaDelayPower Efficient Carry-Select Adder

    2014(T)

    NVD-18

    Multifunction Residue Architectures for Cryptography

    2014(T)

    NVD-19

    Low-Complexity Low-Latency Architecture for Matching of Data


    Encoded With Hard Systematic Error-Correcting Codes
    Energy-Efficient High-Throughput Montgomery Modular Multipliers for
    RSA Cryptosystems
    A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square
    Codes

    2014(T)

    NVD-02

    NVD-06
    NVD-07

    NVD-14
    NVD-15

    NVD-20
    NVD-21

    YEAR

    2015
    2015

    2015
    2015
    2015

    2015

    2014(T)
    2014(T)

    2014(T)
    2014

    An ISO 9001:2008 Certified Company


    #404, Siri Estates, Opp. Lane to R.S. Brothers, Ameerpet, Hyderabad-500073.
    E-mail: info@nanocdac.com, www.nsrcnano.com, +91-8297578555, +91-9640648777

    NVD-22

    Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR


    Digital Filter

    2014

    NVD-23

    Low-Power Digital Signal Processor architecture For Wireless Sensor Nodes

    2014

    NVD-24

    Error Detection in Majority Logic Decoding of Euclidean Geometry Low


    Density Parity Check (EG-LDPC) Codes

    2013(T)

    NVD-25

    Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based


    on Distributed Arithmetic

    2013(T)

    NVD-26

    Radix-4 and radix-8 booth encoded multi-modulus multipliers

    2013(T)

    NVD-27

    Design and Implementation of an On-Chip Permutation Network for


    Multiprocessor System-On-Chip
    Multi operand Redundant Adders on FPGAs
    Global built-in self-repair for 3D memories with redundancy sharing and
    parallel testing
    A Practical NoC Design for Parallel DES Computation

    2013(T)

    Parallel AES Encryption Engines for Many-Core Processor Arrays


    VLSI Implementation of a High Speed Single Precision Floating Point Unit
    Using Verilog
    A VLIW Architecture for Executing Multi-Scalar/Vector Instructions on
    Unified Datapath
    n k
    A Novel Modulo Adder for 2 -2 - 1Residue Number System

    2013
    2013

    NVD-28
    NVD-29
    NVD-30
    NVD-31
    NVD-32
    NVD-33
    NVD-34
    NVD-35

    2013
    2013
    2013

    2013
    2013(T)

    Low-cost FIR filter designs based on faithfully rounded truncated


    multiple constant multiplication/accumulation
    Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based
    on Distributed Arithmetic
    Design and Implementation of 32 Bit Unsigned Multiplier Using
    CLAA and CSLA
    Enhanced Area Efficient Architecture for 128 bit Modified CSLA

    2013(T)

    2013

    NVD-40

    High Performance Hardware Implementation of AES Using Minimal


    Resources
    Implementation of I2C Master Bus Controller on FPGA

    NVD-41

    Novel High Speed Vedic Mathematics Multiplier using Compressors

    2013

    NVD-42

    VLSI Implementation of a High Speed Single Precision Floating Point Unit


    Using Verilog
    VLSI implementation of Fast Addition using Quaternary Signed Digit
    Number System

    2013

    NVD-36
    NVD-37
    NVD-38
    NVD-39

    NVD-43

    2013(T)
    2013
    2013

    2013

    2013

    An ISO 9001:2008 Certified Company


    #404, Siri Estates, Opp. Lane to R.S. Brothers, Ameerpet, Hyderabad-500073.
    E-mail: info@nanocdac.com, www.nsrcnano.com, +91-8297578555, +91-9640648777

    NVD-44

    Design of High Performance 64 bit MAC Unit

    2013

    NVD-45

    2013

    NVD-46

    FPGA Architecture for OFDM Software Defined Radio with an


    optimized Direct Digital Frequency Synthesizer
    Implementation of UART with BIST Technique in FPGA

    NVD-47

    A High Speed Binary Floating Point Multiplier Using Dadda Algorithm

    2013

    NVD-48

    Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code

    2012(T)

    NVD-49

    High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

    2012(T)

    NVD-50

    Product Code Schemes for Error Correction in MLC NAND Flash


    Memories
    Low-Power and Area-Efficient Carry Select Adder

    2012(T)

    Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD


    Support
    Design and Implementation of 64-Bit Execute Stage for VLIW
    Processor Architecture on FPGA
    Design and FPGA-based Implementation of a High Performance 32-bit
    DSP Processor

    2012(T)

    NVD-51
    NVD-52
    NVD-53
    NVD-54

    2013

    2012(T)

    2012
    2012

    LOW POWER PROJECTS


    NVL-01

    Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

    2015(T)

    NVL-02

    Design Methodology of Sub threshold Three-Stage CMOS OTAs Suitable for


    Ultra Low-Power Low-Area and High Driving Capability
    Low Power and Area- Efficient Shift Register Using Pulsed Latches

    2015(T)

    NVL-04

    A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power


    Supply Rejection

    2015(T)

    NVL-05

    Analysis and Design of a 14.1-mW 50100-GHz Transformer-Based PLL


    With Embedded Phase Shifter in 65-nm CMOS

    2015(T)

    NVL-06

    40-Gbs 0.7-V 21 MUX and 12 DEMUX with Transformer-Coupled


    Technique for SerDes Interface

    2015(T)

    NVL-07

    Low Power Conditional Pulse Control with Transmission Gate Flip-Flop

    2015

    NVL-08

    An Efficient Design Technique for Low Power Dynamic Feed through Logic
    with Enhanced Performance for wide fan-in gates

    2015

    NVL-03

    2015(T)

    An ISO 9001:2008 Certified Company


    #404, Siri Estates, Opp. Lane to R.S. Brothers, Ameerpet, Hyderabad-500073.
    E-mail: info@nanocdac.com, www.nsrcnano.com, +91-8297578555, +91-9640648777

    NVL-09

    Performance Analysis of CNTFET Based Digital Logic Circuits

    2015

    NVL-10

    A 90nm Low Power OTA Using Adaptive Bias

    2015

    NVL-11

    Implementing Low-Power Dynamic Adders in MTCMOS Technology

    2015

    NVL-12

    Design of high speed ternary full adder and three input XOR circuits using
    CNTFETs

    2015

    NVL-13

    An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock


    Generation

    2015

    NVL-14

    Free class ABAB Miller opamp with high current enhancement

    2015

    NVL-15

    Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits

    NVL-16

    Ultralow-Ener gy Variation-Aware Design: Adder Architecture Study

    NVL-17

    Designing Tunable Sub threshold Logic Circuits Using Adaptive Feedback


    qualization
    Quaternary Logic Lookup Table in Standard CMOS

    NVL-18
    NVL-19
    NVL-20
    NVL-21
    NVL-22
    NVL-23
    NVL-24
    NVL-25
    NVL-26
    NVL-27

    14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm


    CMOS With Built-In Eye Diagram Testability
    Power Efficient Class AB Op-Amps with High and Symmetrical Slew Rate
    Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS
    Circuits
    An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator
    With Assistant PushPull Output Stage
    Novel Class of Energy-Efficient Very High-Speed Conditional PushPull
    Pulsed Latches
    Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal FeedThrough Scheme
    Comparative Performance Analysis of XORXNOR Function Based HighSpeed CMOS Full Adder Circuits
    Analysis and Design of a Low-Voltage Low-Power Double-Tail
    Comparator
    Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient
    Embedded Logic

    Cadence2015
    Cadence2015
    Cadence2015
    Cadence2015
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