Common Emitter BJT Amplifier Design Example

Some Random Observations

Conditions for stabilized voltage source biasing
o Emitter resistance, RE, is needed.
o Base voltage source will have finite resistance, RB
o (1+)RE needs to be much larger than RB
o Small RB - relative to RS - will attenuate input signal.
o Larger RE permits larger RB , but results in lower gain.

Gain = -R =

o Split RE with bypassing increases gain.

Requires large bypass capacitor.
Limiting case - entire RE bypassed: Gain =
Simplified rule-of-thumb biasing is adequate.
Conflicting Bias and Gain Issues
Biasing
o If RB is small relative to (1+)RE, VB and RE determine IE and, approximately,
IC. Stable bias => RE large and high gain => RE small.
Gain
o Want gain magnitude RC/RE to be large. This implies a small RE.
Gain-bias interaction
o Want RB to be large relative to RS, while still small relative to (1+)RE. (i.e.
choose RB 10 RS and (1+)RE 10 RB)
o Want VCG= VCC ICRC to be roughly at mid-point between the VCC and the
emitter bias voltage, or 1/3, 1/3, 1/3 rule. RC determines bias and gain.
Design Example
Design an amplifier to meet the following specifications:
Electrical specifications:
o vsigmax=0.1Vpk
o RS=50
o VCC =12V
o 0 C < T < 40 C Requires simulation to verify.
o

| | = |

| 10 @

Minimize cost:
o Minimize bypass capacitors
o Use standard 5% resistors
More typical gain spec:
o 9 |Av| 11

Design Step 1 (Choose RB and RE)

Choose an RB >> 10RS:
o RB5000
o (1+)RE must be 10RB:
10 5000

= 500
100
o Nearest preferred value is 470
o RE= 470
Design Step 2 (Set RC)
For a gain of about -10:
o RC=10RE =4.7k
o Nearest preferred value is 4.7k
SPEC: vsigmax=0.1Vpk
For a gain of -10, the collector voltage vout swings 1 V maximum, so the
collector resistor bias drop could in principle be as little as 1 V.
Design Step 3 (Set bias point neglecting IB)
Recall vsig-max= 0.1 Vpk
o We have plenty of room - choose the collector drop conservatively to allow
for bias point changes with temperature let's use:

o = 4.7
3

o
o

4.7

Thus: = 4700 = 1
And (ignoring IB):

o
o

= + 0.7 = 0.47 + 0.7 = 1.17

RB=5 K

Design Step 4 (Set R1 and R2)

Recall:
o

And
o
Or
o

1 +2

1 +2

2
1 +2

= =

Substituting:
o

= 1 |2 = 1

1 |2 = 1

= 5

= 1.17

1.17
12

2
1 +2

= 0.098 0.1
= 1 0.1 = 5 1 = 50

o Preferred value R1=47 k

Finally
2
o 47 +
= 0.1 0.92 = (0.1)(47) 2 = 5222
2

Preferred value R1=47 k

Design Step 5 (set CB)

RB in parallel with rbg => RB dominates.
Estimate Rin as 4.2 k.
Coupling capacitor, then, should be about 420
1
10

< 420 >

>

10
420220

2
1.19104
19
2

at 20 Hz.

PSPICE Simulation:
10

0
10Hz
100Hz
V(RC:1)/ V(C4:1)

1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz

10MHz

100MHz

Frequency

Frequency response without bypass Capacitor

200

150

100

50

0
10Hz
100Hz
V(RC:1)/ V(C4:1)

1.0KHz

10KHz

100KHz

1.0MHz

Frequency

Frequency response with bypass Capacitor

Sami Sharif
January 2015