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Joan D.

Brun

AT4AA

(COT 8)

Engr. Valdulla

1. Maskable Interrupt: An Interrupt that can be disabled or ignored by the


instructions of CPU are called as Maskable Interrupt.
Eg: RST6.5,RST7.5,RST5.5 OF 8085 are maskable Interrupts.

Non-Maskable Interrupt: An interrupt that cannot be disabled or ignored by the


instructions of CPU are called as Non-Maskable Interrupt.
Eg:Trap of 8085
2. Handshaking

3. Power Failure Interrupts

4. Software Interrupts

5. Disabling Interrupts
able it - usually an enable bit in a configuration register. At the end of the interrupt
configuration sequence for that peripheral, the interrupt will be enabled. But this will
not cause interrupts to begin to be serviced. The CPU will also have a global interrupt
enable mechanism (again, usually a bit in a configuration register) which allows it to
process interrupts. This global interrupt enable will typically be set after all the
individual interrupt enables have been set, which is to say, after all the individual

interrupt sources have been configured. The initialization sequence will look
something like this:
Configure and enable interrupt source 1
Configure and enable interrupt source 2
...
Configure and enable interrupt source N
Enable Global Interrupts
After being enabled, individual interrupt sources can be disabled and re-enabled as
needed at any point in the program, and global interrupts can also be disabled and reenabled at any point in the program. Briefly disabling global interrupts is one way to
assure atomic access to ISR-accessed data
6. Multiple Interrupts
An interrupt event can occur while the processor is handling a previous interrupt
processor is handling a previous interrupt.
If the return address is always stored at a fixed location, the occurrence of an
interrupt while handling a previous interrupt will overwrite the previous return
address.
Most interrupt service routines start with interrupts disabled. This prevents an
interrupt service routine from being interrupted.
C. Data Addressing
1. Definition and Description
Byte addressing refers to hardware architectures which support accessing individual
bytes of data rather than only larger units called words, which would be wordaddressable. The basic unit of digital storage is called a bit. In most common
computer architectures, 8 bits are grouped together to form a byte.
2. Register Addressed Instruction
a. Register Addressing
The most common form of data addressing.
once register names learned, easiest to apply.
The microprocessor contains these 8-bit register names used with register
addressing: AH, AL, BH, BL, CH, CL, DH, and DL.
16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI.

b. Immediate Addressing
Term immediate implies that data immediately follow the hexadecimal opcode in
the memory.
immediate data are constant data
data transferred from a register or memory location are variable data
Immediate addressing operates upon a byte or word of data.
Figure 34 shows the operation of a MOV EAX,13456H instruction.
c. Direct Addressing
Direct addressing with a MOV instruction transfers data between a memory
location, located within the data segment, and the AL (8-bit), AX (16-bit), or EAX
(32-bit) register.
usually a 3-byte long instruction
MOV AL,DATA loads AL from the data segment memory location DATA (1234H).
DATA is a symbolic memory location, while
1234H is the actual hexadecimal location
d. Register Indirect Addressing

Allows data to be addressed at any memory location through an offset address


held in any of the following registers: BP, BX, DI, and SI.
In addition, 80386 and above allow register indirect addressing with any
extended register except ESP.
In the 64-bit mode, the segment registers serve no purpose in addressing a
location
in the flat model.

e. Base-Plus-Index Addressing
Similar to indirect addressing because it indirectly addresses memory data.
The base register often holds the beginning location of a memory array.
the index register holds the relative position
of an element in the array
whenever BP addresses memory data, both the stack segment register
and BP generate the effective address
f. Register Relative Addressing
Similar to base-plus-index addressing and displacement addressing.
data in a segment of memory are addressed by adding the displacement
to the contents of a base or an index register (BP, BX, DI, or SI)
Figure 310 shows the operation of the MOV AX,[BX+1000H] instruction.
A real mode segment is 64K bytes long.