DC Biasing for MOSFET and BJT

Date: October 12, 2015

Instructor: Divya Choudhary
Members: Kha Le, Juan Avalos

(I) Objective of Experiment: The goal of this experiment is to design a voltage divider
DC biasing circuit for NMOS to provide a drain current Id of 0.6mA and a current of
50 uA flowing through the voltage divider resistances. The drain voltage Vd = 7V and
source voltage Vs = 3V. The NMOS has Vt = 1V and KnW/L = 1.2 mA/V^2. Use a
power supply, V(DD) of 10V. The second part of the experiment is to design a voltage
divider DC biasing circuit for an NPN BJT to provide an emitter current IE = 1mA.
Use a power supply Vcc of 10V.

(II) Equipment: DC input voltage generator, DC voltmeter, NMOS, BJT, resistors: 2x of

100k, 2x of 4.7k, 3.3k, 2.7k, 33k, and 68k.
(III) Circuit Diagram and Relevant Calculations
Part 1: NMOS DC Bias

Example Calculation: Id = Is = 0.6mA, Vd =7v, Vs = 3v, Vt =1v, KnW/L = 1.2 mA/V^2

Vdd = 10v (10v-7v)/0.6mA = 5K (Standard value of 4.7k)
2 = Vg 3 Vg = 5v
Part 2: BJT DC Bias

Example Calculation: Ie = 1mA, Vcc =10v, VBE = 0.7v

IcRc = 0.33Vcc = 0.33*10 = 3.33v
Ic = Ie Vce = 0.33*10 = 3.33v
Vr2 = 0.1Ie
Ir1 =Ir2

(IV) Experimental Procedure

Part 1: NMOS DC bias
1. Design the circuit and connect the components.
2. Measure the DC voltages:
a. Across Rg2, Vg2
b. Gate-Source Vgs
c. Drain-source Vds
d. Across Rd, Vrd
e. Compute drain current: Id= Vrd/Rd
f. Across Rs, Vrs
g. Compute source current: Is = Vrs/Rs
Part 2: BJT DC bias
1. Design the circuit and connect the components.
2. Measure the DC voltages:
a. Across R2, Vr2
b. Base-Emitter voltage Vbe
c. Collector-Emitter Vce
d. Across Re, Vre
e. Compute emitter current: Ie = Vre/Re
f. Across Rc, Vrc
g. Compute collector current: Ic= Vrc/Rc
(V) Graphs and Results
Part 1: NMOS DC bias
#
Components Results:
:
a.
Vg2
4.9V
b. Vgs
2.06V
c.
Vds
4.2V
d. Vrd
2.88V
e.
Id = Vrd/Rd 0.612 mA
f.
Vrs
2.89V
g. Is = Vrs/Rs
0.614 mA
Computed currents: ID=VRD/RD=0.612mA, IS=VRS/RS=0.614mA
Part 2:BJT DC bias
#
Components
:
a.
Vr2
b. Vbe
c.
Vce
d. Vre
e.
Ie = Vre/Re
f.
Vrc
g. Ic = Vrc/Rc

Results:
3.14V
0.679V
4.46V
2.46V
0.91mA
3.01V
0.91mA

Computed currents: IE=VRE/RE=0.91mA, IC=VRC/RC=0.91mA

(VII) PSPICE Simulations
NMOS DC bias:

BJT DC bias:

(VI)
Discussion
and
Conclusion:
Experiment 4 consists of DC analysis of both MOSFET and BJT circuits. In the
DC analysis of MOSFET circuits, it is assumed it is assumed to be in saturation-mode
operation. The BJT circuits are also greatly simplified by assuming VBE = 0.7 V, in DC
analysis. Using this knowledge and the characteristics of each, both are used to design a
voltage divider DC biasing circuit. A 10V power supply is applied to both circuits.
The givens for the NMOS DC circuit are the following: drain current, source
voltage, drain voltage, and current of the resistances near the gate. This information is
used to find the four resistances in the circuit (RD, RS, RG1, RG2). Given the drain current,
this is also equal to the source current because gate current is known to be zero (current
in=current out); therefore, the resistances RG1 and RG2 are in series. The given drain
current also leads to an important step, which is finding VGS using the equation of ID for
NMOS. The value of VGS is then used to find VG (VS was also given), and finally use VG
to find these two resistances: RG1 and RG1. The other two resistances (RD and RS) are
simpler to find using the givens: drain current, power supply, and source and drain
voltage.
The BJT design was also required to find the resistances R1, R2, RC and RE. Using
the assumptions and rules given, it is determined that IC = IE and that R1 and R2 are in
series. Given rule 1(ICRC=VCC/3), RC is calculated using ohms law. Rule 4 (VR2=VCC/3)
is used to find RE by using KVL in a loop. Ultimately, rule 5 (IR2=0.1IE) is used to find
the 2 resistances in series with the 10V power supply.