TO STUDY DIFFERENT TYPES

OF LOGIC GATES.
Project Prepared By:
Satyam bansal

XII-A

ROLL NO: 21
Boards Roll Number:
Year: 2015-2016

AIM
TO STUDY DIFFERENT TYPES OF
GATES:

CERTIFICATE

It is hereby to certify that, the original and genuine

investigation work has been carried out to investigate
about the subject matter and the related data
collection and investigation has been completed
solely, sincerely and satisfactorily by Satyam bansal of
CLASS XII A, GOVT. SARVODAYA BAL VIDYALAYA
BLOCK, DILSHAD GARDEN, DELHI: 95

regarding his project titled

TO STUDY DIFERENTS TYPES OF LOGIC
GATES
.

Teachers signature

Acknowledgement

C-

It would be my utmost pleasure to express

my sincere, thanks to My physics Teacher Mr.
RAJESHWARE KUMAR TYAGI

in providing a helping hand in this project.

Their valuable guidance, support and
supervision all through this project titled
To study different types of logic gates
are responsible for attaining its present form.

Satyam bansal
XII A

CONTENTS
a.
b.
c.
d.
e.
f.
g.
h.
i.

Introduction.
Formula used.
Apparatus.
Theory.
Procedure.
Observation.
Results.
Precaution.
Source of error.

INTRODUCTION
A logic gate is an elementary building block
of a digital circuit. Most logic gates have
two inputs and one output. At any given
moment, every terminal is in one of the two
binary conditions low (0) or high (1),
represented by different voltage levels. The
logic state of a terminal can, and generally
does, change often, as the circuit processes
data. In most logic gates, the low state is
approximately zero volts (0 V), while the
high state is approximately five volts
positive (+5 V).
There are seven basic logic gates: AND, OR,
XOR, NOT, NAND, NOR, and XNOR

AND GATE
The AND gate is a basic digital logic gate
that implements logical conjunction - it
behaves according to the truth table to the
right. A HIGH output (1) results only if both
the inputs to the AND gate are HIGH (1). If
neither or only one input to the AND gate is
HIGH, a LOW output results. In another
sense, the function of AND effectively finds
the minimum between two binary digits,
just as the OR function finds the maximum.
Therefore, the output is always 0 except
when all the inputs are 1

INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
A AND B
0
0
0
1

Symbols
There are three symbols for AND gates: the
American (ANSI or 'military') symbol and the
IEC ('European' or 'rectangular') symbol, as
well as the deprecated DIN symbol. For
more information see Logic Gate Symbols.

DIN

ICE Symbol
l

MIL/ANSI SymboL

The AND gate with inputs A and B and output

C implements the logical expression

Implementations

An AND gate is usually designed using

N-channel (pictured) or P-channel
MOSFETs. The digital inputs a and b
cause the output F to have the same
result as the AND function

OR GATE
The OR gate is a digital logic gate that
implements logical disjunction - it
behaves according to the truth table to
the right. A HIGH output (1) results if
one or both the inputs to the gate are
HIGH (1). If neither input is high, a LOW
output (0) results. In another sense, the
function of OR effectively finds the

maximum between two binary digits,

just as the complementary AND function
finds the minimum
INPUT
A

OUTPUT
A OR B

Symbols
There are two symbols of OR gates: the
American (ANSI or 'military') symbol and
the IEC ('European' or 'rectangular')
symbol, as well as the deprecated DIN
symbol. For more information see Logic
Gate Symbols

MIL/ANSI Symbol

ICE Symbol

DIN Symbol

Hardware description
and pin out
OR Gates are basic logic gates, and as
such they are available in TTL and
CMOS ICs logic families. The standard
4000 series CMOS IC is the 4071, which
includes four independent two-input OR
gates. The traditional TTL version is the
7432. There are many offshoots of the
original 7432 OR gate. All have the same
pin out but different internal
architecture, allowing them to operate
in different voltage ranges and/or at
higher speeds. In addition to the
standard 2-Input OR Gate, 3- and 4-Input

OR Gates are also available. In the

CMOS series, these are:
4075: Triple 3-Input OR Gate
4072: Dual 4-Input OR Gate
TTL variations include:
74LS32: Quad 2-input OR gate (Low
power Schottky version)
74HC32: Quad 2-input OR gate (High
Speed CMOS version) - has lower
current consumption/wider Voltage
range
74LVC32: Low voltage CMOS version
of the sam
This schematic diagram shows the arrangement of four OR gates within
a standard 4071 CMOS integrated circuit

Implementations

CMOS OR gate

BJT OR gate

OR Gates Using Diodes

NOT GATE
A NOT gate (also often called Inverter) is a logic
gate. It takes one input signal. In logic, there are
usually two states, 0 and 1. The gate therefore
sends 1 as output, if it receives 0 as input.
Alternatively it received 1 as input, and sends 0
as output.
Generally, below 0.5V is 0, and 45V is 1.

The inverter can be made of a discrete transistor

with other components, or several inverters may
be packaged in an integrated circuit
INPUT OUTPU
A

T
NOT A

0
1

1
0

Symbol
for the NOT gate

MIL/ANSI Symbol

There are three symbols

IEC Symbol

DIN Symbol

Electronic
implementation

NMOS inveter

NPN transistor

Depletion-load NMOS NAND

PMOS inveter

Static COMS inveter

Saturated-load NMOS inverter

logic

Saturated-load NMOS
inverter

Digital building block

This schematic diagram

shows the arrangement of NOT gates
within a standard 4049 CMOS hex
inverting buffer.

The inverter is a basic building block in

digital electronics. Multiplexers,
decoders, state machines, and other
sophisticated digital devices may use
inverters.
The hex inverter is an integrated circuit
that contains six (hexa-) inverters. For
example, the 7404 TTL chip which has
14 pins and the 4049 CMOS chip which
has 16 pins, 2 of which are used for
power/referencing, and 12 of which are
used by the inputs and outputs of the
six inverters (the 4049 has 2 pins with
no connection

Voltage

transfer curve for a 20 m inverter constructed at

North Carolina State University

Formula used
THE BOOLEN EXPRESIONS OF
THREE LOGIC GATES ARE GIVEN BY:

AND: A.B=Y
OR: A+B=Y
NOT: A=Y
WHERE

A,B=Input voltages.
Y=Output voltages.
A=Input A is inverted.

WE HAVE TWO UNIVERSAL GATES ALSO THESE

TWO ARE AS FOLLOW: NAND & NOR gates.
NAND: Y=A.B
NOR: Y=A+B

APPARATUS

DIODES

RESISTANCE

BATTERIES

AN LED

CONNECTING WIRE

THEORY
LOGIC GATES IS A DIGIAL GATES
WHICH FOLLOWS A LOGICAL
RELATIONSHIP BTWEEN THE INPUT
AND OUTPUT VOLTAGES. THE THREE
BASIC LOGIC GATES ARE: AND,OR AND
NOT. EACH LOGIC GATE HAS A SYMBOL,
A BOOLEAN EXPRESSION AND A TRUTH
TABLE TO DEFINE ITS FUCTION. THESE
GATES CAN BE REALISED USING
DIODES AND TRANSISTORS WHICH WE
CAN SEEN ABOVE.

PROCEDURE
FOR AND GATE:
A. ASSEMBLE THE

CIRCUIT AS SHOWN IN FIG.

B.CONNECT BOTH A AND B TO P
AND OBSERVRE THE OUTPUT
WHEATHER IT IS HIGH OR LOW. MARK

THE OUTPUT AS 1 IF IT HIGH AND 0 IF

IT LOW.
C.NOW CHANGE THE CONNECTIONS
AND CONNECT A TO P AND B TO
Q AND AGAIN RECORD THE
OBSERVATIONS AS ABOVE.
D.NOW , REVERSE THE CONNECTIONS
OF A AND B i.e. A TO Q B TO
P. RECORD THE OBSERVATION AS 1
OR 0 .
E.NOW CONNECT BOTH A AND B TO
Q AND AGAIN RECORDN THE
OBSERVATION.
F.SEE THAT THE OBSERVATIONS
MATCH WITH THE TRUTH TABLE FOR
AND GATE.

FOR OR GATE:
A.ASSEMBLE THE

CIRCUIT OR REALIASTION OF OR
GATE AS SHOW IN FIG.
B.CONNECT BOTH A AND B TO P
AND OBSERVE WHEATHER THE
OUTPUT IS HIGH OR LOW. IF THE

OUTOUT IS HIGH, RECORD IT AS 1 AND

0 IF LOW.
C.CONNECT A TO P AND B TO Q
AND OBSERVE THE OUTPUT AS ABOVE.
D.REVERSE THE CONNECTIONS i,e.,
A TO Q AND B TO P AND AGAIN
OBSERVE THE OUTPUT.
E.CONNECT BOTH A AND B TO Q
AND RECORD THE OBSERVATIONS.
F.SEE THAT THE OBSERVATIONS
MATCH WITH THE TRUTH TABLE FOR
OR GATE.

FOR NOT GATE:

A.ASSEMBLE THE CIRCUIT OR

REALIASTION OF NOT GATE AS SHOW

IN FIG.
B.CONNECT A TO Q BASE
COLLECTOR JUNCTION IS IN REVERSE
BIAS AND ALSO BASE AMITTER
JUNCTION IS NOT FORWARD BIASED,
THUS THERE IS NO FLOW OF
COLLECTOR CURRENT. HENCE THERE
IS A VOLTAGE DROP ACROSS Y DUE
TO THE BATTERY B2 AS INDICATED BY
GLOWING LED.
C.CURRENT A TO P, THERE IS FLOW
COLLECTOR CURRENT AS THE BASE
COLLECTOR IS FORWARD BIASED.
VOLTAGE DROP BEING EQUAL TO THE
VOLTAGE OF BATTERY B2, OUTPUT

ACROSS Y IS 0. THUS, GIVING Y

VALUE IS 0.
D.THE OBSERVATION MATCH THE
TRUTH TABLE OF NOT GATE.

OBSERVATIONS TABLE
FOR AND GATE
SR
.
NO

INPUT

OUTPUT

A
CONNECTED
AT

STATE
OF A

B
CONNECTED
AT

STATE
OF B

Y=A.B
1

2
3
4

P
Q
Q

1
0
0

Q
P
Q

0
1
00

0
0
0

FOR OR GATE
SR.
NO

INPUT
A

STATE

STATE

CONNECTE

OF A

CONNECTE

OF B

OUTPUT
Y=A+B

1
0

1
1

D AT

1
2

P
P

D AT

1
1

P
Q

3
4

Q
Q

0
0

P
Q

1
0

1
0

FOR NOT GATE

SR.
NO

INPUT
A
CONNECTED

STATE OF A

OUTPUT

Y=A

AT

1
2

P
Q

1
0

0
1

RESULTS
1.TRUTH TABLE FOR AND GATE:

A
0
0
1
1

B
0
1
0
1

Y
0
0
0
1

2.THE TRUTH TABLE OBTAINED FOR

OR GATE IS:
A
O
0

B
0
1

Y
0
1

1
1

0
1

1
1

3:THE TRUTH TABLE OBTAINED FOR

NOT GATE IS:

0
1

1
0

PRECAUIONS AND SOURCE

ERROR
A.THE CONNECTIONS SHOULD BE
NEAT AND TIGHT.

B.BIASING OF DIODES SHOULD BE

CAREFULLY DONE ACCORDING TO THE
CIRCUIT DIAGRAM.

C.THE NEGATIVE TERMINAL OF

BATTERY SHOULD BE GROUNDED FOR
THE ZERO STATE.

D. A TRANSISTOR IS TO BE USED FOR

REALISATION OF NOT GATE.

E.

RESISTORS REQUIRED IN THE NOT

GATE REALISATION SHOULD BE SUCH,

THAT THERE IS A LARGE FLOW OFF
CURRENT.

TEACHERs REMARKS