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VLSI TITLES (IEEE 2015)

VXVLSI001

Quaternary Logic Lookup Table in Standard CMOS

VXVLSI002

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

VXVLSI003

Z-TCAM: An SRAM-based Architecture for TCAM

VXVLSI004

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device


Licensing

VXVLSI005

All Digital Energy Sensing for Minimum Energy Tracking

VXVLSI006

Recursive Approach to the Design of a Parallel Self-Timed Adder

VXVLSI007

Buffered Clock Tree Synthesis for Skew Optimization

VXVLSI008

A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error


Compensation in 180-nm CMOS

VXVLSI009

Level-Converting Retention Flip-Flop for Reducing Standby Power

VXVLSI010

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low


Adaptation-Delay

VXVLSI011

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS


Technique for DSRC Applications

VXVLSI012

Low-Power Programmable PRPG With Test Compression Capabilities

VXVLSI013

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical


Data Path

VXVLSI014

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval
Checks

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veexplore.vlsi@gmail.com

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VXVLSI015

Reliable Low-Power Multiplier Design Using Fixed-Width Replica


Redundancy Block

VXVLSI016

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS


Technique for DSRC Applications

VXVLSI017

Design of Efficient Content Addressable Memories in High-Performance


FinFET Technology
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA
and ASIC Implementations
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power
Application
Low-Cost On-Chip Clock Jitter Measurement Scheme

VXVLSI018
VXVLSI019
VXVLSI020
VXVLSI021
VXVLSI022
VXVLSI023
VXVLSI024
VXVLSI025

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder


Circuit
Range Unlimited Delay-Interleaving and Recycling Clock Skew
Compensation and Duty-Cycle Correction Circuit
Razor Based Programmable Truncated Multiply and Accumulate, EnergyReduction for Efficient Digital Signal Processing
High-Performance Low-Power Carry Speculative Addition With Variable
Latency
Fault Secure Encoder and Decoder for Memory Applications

VXVLSI028

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque


Magnetic Tunnel Junction
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable
Applications
Low-Power and Area-Efficient Carry Select Adder [Feb 2012]

VXVLSI029

AreaDelayPower Efficient Carry-Select Adder [June 2014]

VXVLSI030

Reverse Converter Design via Parallel-Prefix Adders: Novel Components,


Methodology, and Implementations
Towards 32-bit Energy-Efficient Superconductor RQL Processors: The CellLevel Design and Analysis of Key Processing and On-Chip Storage Units
MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

VXVLSI026
VXVLSI027

VXVLSI031
VXVLSI032
VXVLSI033

Hybrid Architecture Design for Calculating Variable-Length Fourier


Transform

Phone : 0422 - 4274041


Mob : 9043034051 / 41 / 42 / 43

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