A Low Power CMOS Design of An All Digital Phase Locked Loop PDF

Northeastern University
Electrical Engineering Dissertations
Department of Electrical and Computer

Engineering
January 01, 2011
A low power CMOS design of an all digital phase

locked loop
Jun Zhao
Recommended Citation
Zhao, Jun, "A low power CMOS design of an all digital phase locked loop" (2011). Electrical Engineering Dissertations. Paper 38.
http://hdl.handle.net/2047/d20001051
This work is available open access, hosted by Northeastern University.
A Low Power CMOS Design of An All Digital Phase

Locked Loop
A Thesis Presented
by
Jun Zhao
to
The Department of Department of Electrical and Computer Engineering
in partial fulfillment of the requirements
for the degree of
Doctor of Philosophy
in
Electrical Engineering
in the field of
Electrical Engineering
Boston, Massachusetts
Apr 4, 2011
c Copyright 2011 by Jun Zhao

All Rights Reserved
NORTHEASTERN UNIVERSITY
Graduate School of Engineering
Thesis Title: A Low Power CMOS Design of An All Digital Phase Locked
Loop .
Author: Jun Zhao.
Department: Department of Electrical and Computer Engineering.
Approved for Thesis Requirements of the Doctor of Philosophy Degree
Thesis Advisor: Prof. Yong-Bin Kim
Date
Thesis Reader: Prof. Fabrizio Lombardi
Date
Thesis Reader: Prof. Nian Xiang Sun
Date
Department Chair: Prof. Ali Abur
Date
Director of the Graduate School:
Dean: Prof. Yaman Yener
Date
NORTHEASTERN UNIVERSITY
Graduate School of Engineering
Thesis Title: A Low Power CMOS Design of An All Digital Phase Locked
Loop .
Author: Jun Zhao.
Department: Department of Electrical and Computer Engineering.
Approved for Thesis Requirements of the Doctor of Philosophy Degree
Thesis Advisor: Prof. Yong-Bin Kim
Date
Thesis Reader: Prof. Fabrizio Lombardi
Date
Thesis Reader: Prof. Nian Xiang Sun
Date
Department Chair: Prof. Ali Abur
Date
Director of the Graduate School:
Dean: Prof. Yaman Yener
Date
Copy Deposited in Library:
Reference Librarian
Date
Abstract
This dissertation presents a proposed all digital phase locked loop and a digitally controlled oscillator with low power consumption for fractional-N frequency
synthesis applications. The basic operation of the conventional PLL-based frequency synthesizers is first briefly reviewed, followed by the literature review
of some reported digital PLL based frequency synthesizer. An all digital PLL
is thus proposed, including the system architecture and implementations of its
sub-blocks. In the proposed all digital PLL, the PFD-TDC pair used in many
reported digital PLLs is replaced by a customized time-to-digital converter. A
novel Schmitt trigger based digital controlled oscillator is proposed to achieve a
wide linear tuning range with low power consumption.
The novel locking process of the proposed ADPLL is separated into frequency
and phase acquisition. Instead of ahead or behind comparison, the time-todigital converter is used to measure the frequency difference accurately, which
greatly reduces the lock-in time. The phase acquisition only takes two reference
clocks. One cycle for resetting the DCO and the other cycle for updating the
control considering the path delay.
To further prove the feasibility of the novel ADPLL, a fractional-N frequency
synthesizer is implemented based on the proposed ADPLL. An extra TDC is
applied to obtain the fractional value avoiding the use of fractional divider, which
is the main source of fractional spur in a fractional-N frequency synthesizer.
The proposed Fractional-N frequency synthesizer is implemented using a 0.9V
32nm Practical Transistor Model. The phase noise performance, the frequency
locking speed as well as the tuning range of the digitally controlled oscillator
was measured and well agrees with the theoretical analysis.
Acknowledgments
It has been an honor to study at Northeastern University. There are many
people to thank.They have provided inspiration, guidance, and friendship. This
dissertation would not have been completed without the help of many people.
My foremost appreciation must go to my advisor, Dr. Yong-Bin Kim. His
extensive vision and creative thinking have provided the source of inspiration
for me all through my graduate study. This academic research experiences have
encouraged me for continuing exploring the integrated circuits in the future. And
his invaluable assistance in conducting research and writing this dissertation is
greatly appreciated.
I am especially grateful to the members of committee, Dr. Lombardi, Dr.
Sun, and the Electrical and Computer Engineering Department Head, Dr. Abur
for their valuable suggestions and numerous help. Through their instruction, I
learned how to pursue research.
It has been a great pleasure to work in the Electrical Engineering Lab. of
the Northeastern University. I would like to acknowledge to all of my colleagues
for their suggestions and help.
My sincere appreciation goes to my parents who have always given me unconditional love, guidance, and support. Without them, none of these could
have accomplished.
ii
Contents
1 Introduction
1.1 Overview of phase-locked loop . . . . . . . . . . . . . . . . . . .
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Review of frequency synthesizer
2.1 Performance parameters of a frequency synthesizer
2.1.1 Phase noise . . . . . . . . . . . . . . . . . .
2.1.2 Spurious power level . . . . . . . . . . . . .
2.1.3 Output period jitter . . . . . . . . . . . . .
2.1.4 Operating frequency range . . . . . . . . . .
2.1.5 Frequency step . . . . . . . . . . . . . . . .
2.1.6 Channel switching time . . . . . . . . . . . .
2.1.7 Power consumption . . . . . . . . . . . . . .
2.2 Frequency synthesizer architectures . . . . . . . . .
2.2.1 PLL based frequency synthesizer . . . . . .
2.2.2 Table-look-up synthesizer . . . . . . . . . .
2.2.3 Direct digital frequency synthesizer . . . . .
2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3 Design Considerations in Analog PLLs

3.1 Adaptive Bandwidth Technology for PVT Tolerant PLL
3.2 Challenges in the VCO Design . . . . . . . . . . . . . . .
3.3 Challenges in the Charge Pump Design . . . . . . . . . .
3.4 On Chip Digital Calibration . . . . . . . . . . . . . . . .
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
2
6
.
.
.
.
.
.
.
.
.
.
.
.
.
12
13
13
17
18
19
19
20
21
21
22
24
25
27
.
.
.
.
.
29
33
35
38
41
43
4 A Proposed All Digital PLL Architecture

4.1 Analog and digital PLL design trade-offs . . . . . . .
4.2 Digital PLL-based frequency synthesizers . . . . . . .
4.2.1 An all-digital phase-locked loop for high-speed
eration . . . . . . . . . . . . . . . . . . . . . .
4.2.2 A fast lock digital phase-locked loop . . . . .
4.2.3 An all-digital PLL clock multiplier . . . . . .
4.2.4 A phase-domain all-digital phase-locked loop .
4.3 Architecture of the proposed ADPLL . . . . . . . . .
4.4 Lock-in process of the proposed ADPLL . . . . . . .
. . .
. . .
clock
. . .
. . .
. . .
. . .
. . .
. . .
5 Circuit Implement of The Proposed ADPLL

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Digitally controlled oscillator . . . . . . . . . . . . . . .
5.2.1 DCO principle and design . . . . . . . . . . . .
5.2.2 Proposed DCO design . . . . . . . . . . . . . .
5.2.3 Improved structure with larger operating range
5.2.4 Comparison between the two DCO structures .
5.2.5 Simulation result Of the proposed DCO . . . .
5.3 Time-to-digital converter . . . . . . . . . . . . . . . . .
5.4 State Machine . . . . . . . . . . . . . . . . . . . . . . .
5.5 Simulation result of the proposed ADPLL . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. . .
gen. . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
6 ADPLL Based Fractional-N Frequency Synthesizer

6.1 Fractional-N division scheme . . . . . . . . . . . . . . . . . . . .
6.2 Fractional spur analysis in conventional fractional-N frequency
synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Spur Suppression Techniques . . . . . . . . . . . . . . . . . . . .
6.3.1 Spur suppression using DAC phase estimation technique
6.3.2 Spur suppression using random jittering technique . . . .
6.3.3 Spur suppression using noise shaping technique . . . . .
6.3.4 Spur suppression using phase interpolation technique . .
6.4 Proposed ADPLL based fractional-N frequency synthesizer . . .
6.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . .
iv
45
46
49
50
53
55
57
58
59
64
64
65
66
68
71
71
73
75
76
78
80
82
84
87
88
89
90
92
93
96
7 Conclusion
98
Bibliography
100
List of Tables
4.1
A mathematical representations of analog/digital DPLLs . . . .
48
5.1
5.2
Impact of each control bit on the DCO period . . . . . . . . . .

Performance of the proposed DCO . . . . . . . . . . . . . . . .
72
74
vi
List of Figures
1.1
1.2
1.3
The basic structure of a phase-locked-loop . . . . . . . . . .

The The linear model of a phase-locked loop . . . . . . . . .
Jitter performance and the operating frequency range of the
ported analog and digital PLLs. . . . . . . . . . . . . . . . .
. .
. .
re. .
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
The spectrum of an ideal signal and practical signal .

The spectrum of a sinusoid FM signal . . . . . . . . .
The spectrum of a FM signal . . . . . . . . . . . . .
The power spectrum of a frequency source with spurs
Illustration of period jitter . . . . . . . . . . . . . . .
A PLL-based frequency synthesizer . . . . . . . . . .
A fractional-N PLL-based frequency synthesizer . . .
A table-look-up frequency synthesizer . . . . . . . . .
A direct digital frequency synthesizer . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
13
15
16
17
18
22
23
24
26
3.1
3.2
3.3
3.4
Block diagram of a charge pump-based PLL. . . . . . . . . . . .

Conceptual timing diagram of the clock waveforms. . . . . . . .
Conceptual timing diagram of the clock waveforms. . . . . . . .
Block diagram of a 3-stage inverter-based ring oscillator with a
regulator adjusting the control voltage. . . . . . . . . . . . . . .
Transfer functions of the 3-stage inverter-based ring oscillator and
the regulator shown in Fig 2.4 with the process variations. . . .
Block diagram and simulated transfer function of a charge pump
example with 65-nm CMOS technology. . . . . . . . . . . . . . .
Replica current compensation scheme. . . . . . . . . . . . . . .
Common mode feedback circuit for the differential charge pump.
Output currents with and without mismatch suppression. . . . .
30
30
32
3.5
3.6
3.7
3.8
3.9
vii
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3
4
9
36
37
38
39
40
41
3.10 Frequency synthesizer using the on chip digital calibration technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
The principle of a PLL-based frequency synthesizer . . . . . . .

The blcok diagram of a digital PLL . . . . . . . . . . . . . . . .
An all-digital phase-locked loop for high-speed clock generation
The DCO of an ADPLL for high-speed clock generation . . . . .
The fine tuning stage of the DCO . . . . . . . . . . . . . . . . .
An all-digital PLL with small DCO hardware and fast phase lock
A digitally controlled delay cell for the DCO . . . . . . . . . . .
An all-digital PLL clock multiplier . . . . . . . . . . . . . . . .
The PFD for an all-digital PLL clock multiplier . . . . . . . . .
Phase-domain ADPLL-based frequency synthesizer . . . . . . .
Architecture of the proposed ADPLL . . . . . . . . . . . . . . .
Principle of frequency acquisition . . . . . . . . . . . . . . . . .
Failure in phase alignment due to logic blocks between DCO clock
and DCO output . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 A new phase acquisition process with two lock-in cycles . . . . .
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Standard Cell of Digitally Controlled Oscillator. (a) Driving

strength controlled. (b) Shunt capacitance controlled . . . . . .
Equivalent circuit for the calculation of constant delay and delay
tuning range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay comparison of Schmitt inverter and conventional inverter
Digitally Controlled Oscillator (a) Conventional DCO structure),
(b) Proposed DCO structure, (c) Fine delay cell . . . . . . . . .
The proposed DCO structure with increased operating range . .
Power consumption of the conventional and the proposed DCO
structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating range of the proposed DCO: (a) Coarse loop (b) Fine
loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay characteristics of the coarse loop for the Process, Voltage
and Temperature variations. (a) Process variation, (b) Temperature Variation, (c) Voltage Variation. . . . . . . . . . . . . . . .
Block diagram of fractional TDC structure . . . . . . . . . . . .
viii
42
47
49
51
52
52
54
54
56
57
57
59
60
61
62
66
67
69
70
71
72
73
74
75
5.10 Decoding process of the TDC . . . . . . . . . . . . . . . . . . .

5.11 Block diagram of the state machine . . . . . . . . . . . . . . . .
5.12 Lock-in process of the proposed ADPLL. (a) Lock process of the
ADPLL with five different statuses from 000 status to 100
status, (b) Frequency acqusiton at TDCO =TRef during 000 status, (c) Frequency acqusition at TDCO = TRef TDelay during
010 status, (d) Phase acqusitoin process during 011 status.
5.13 Output clock jitter (DCO @ 700MHz) . . . . . . . . . . . . . .
76
77
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
82
84
87
88
89
91
92
94
95
96
Typical fractional-N divider scheme. . . . . . . . . . . . . . . . .

Conventional fractional-N synthesizer. . . . . . . . . . . . . . . .
Normalized Fourier series of the current pulse. . . . . . . . . . .
Spur compensation by a DAC. . . . . . . . . . . . . . . . . . . .
Fractional-N synthesize with random jittering. . . . . . . . . . .
Fractional-N synthesis with modulation. . . . . . . . . . . .
Phase interpolated fractional-N synthesis. . . . . . . . . . . . . .
Principle of an integer-N frequency synthesizer lock-in process. .
Proposed ADPLL based fractional-N frequency synthesizer. . . .
Reference and VCO waveforms in locked state. . . . . . . . . . .
Frequency spectrum of DCO output and reference signal. (a) FFT
analysis of reference signal, (b) Frequency spectrum of reference
signal (c) FFT analysis of DCO output (d) Frequency spectrum
of DCO output. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
78
79
97
Chapter 1
Introduction
Phase-locked loops are widely used in many communication systems for clock
and data recovery or frequency synthesis [1, 17, 3, 4, 8]. Cellular phones, computers, televisions, radios, and motor speed controllers are just a few examples
that rely on PLLs for proper operation. With such a broad range of applications,
PLLs have been extensively studied in literature. The conventional PLLs are
often designed using analog approaches, where analog phase and frequency dector, charge pumps, loop filters (LFs) and voltage controlled oscillators (VCOs)
are employed. However, analog PLLs have to overcome the digital switch noise
coupled with power through power supply as well as substrate induced noise. In
addition, the analog PLL is very sensitive to process parameters and must be
redesigned if the process is changed or migrates to next generation process. Although many approaches have been developed to improve the jitter performance,
CHAPTER 1. INTRODUCTION
it often results in long lock-in time and increasing design complexity.

To alleviate all these problems digital equivalent implementations of analog
circuits should be used whenever possible. One advantage of a digital implementation is the inherent noise immunity of digital circuits. Another advantage of a
digital design is its scalability and easy redesign with process changes or shrinks.
Since analog blocks are present in a number of digital and mixed-signal ICs, their
redesign is an important factor in the release of a new product. However, the
performance requirements of analog blocks necessitates a complete redesign in
a new process, thereby increasing the design cycle time. Reducing the amount
of analog circuitry can improve the redesign time of these mixed-signal ICs.
Due to above mentioned reasons, research in the area of digital equivalent
implementations of analog and RF circuits is in great demand now. This thesis,
in particular, is focused on the digital implementation of phase-locked loops.
Phase-looked loops (PLLs) are important and often performance limiting building blocks in modern SoCs. They are used for clock generation and distribution,
frequency synthesis, clock and data recovery, etc.
1.1
Overview of phase-locked loop
A phase-lock loop [6] is essentially a negative feedback loop in which the phase
of the frequency controlled oscillator is obliged to follow that of the input signal.
One measurement of a PLLs performance is the phase error, which is the phase
difference between the input signal and output signal. A basic block diagram of
PLL is shown in Figure 1.1. When the loop is in lock,the VCO frequency equals
Figure 1.1: The basic structure of a phase-locked-loop

the input frequency, and in order to make the two signals in the same phase, a
control voltage is generated with the phase detector and the loop filter based on
the phase error to tune the frequency of VCO.
When the loop is unlocked, suppose the input signal is
yi (t) = Asin[t + i (t)]
(1.1)
yo (t) = Bcos[t + o (t)]
(1.2)
and output signal is
Suppose the phase detector has a sinusoidal characteristic, so the error signal u1
is
u1 (t) = Kd sin[i (t) o (t)]
(1.3)
Kd represents the phase detector sensitivity(V/rad). Name the transfer function

of the loop filter as f(t), and the loop filter gain as Kf , then the command signal
u2 is Kf u(t) f (t), where symbol * represents the convolution product.The

angular frequency unit is radian per second, which is the time derivative of the
phase. A time domain nonlinear differential equation comes out as
d0
= Kd Kf Kvco sin[i (t) o (t)] f (t)
dt
(1.4)
The phase-locked loop is nonlinear system and it is very complicated to

analyze its performance. Fortunately, when a PLL is in the steady state or in
a very slow transient process, its dynamic response to the input-signal phase
and frequency changes can be well approximated by linear model or small signal
model as shown in Figure 1.2. In the figure, Vdo is the offset voltage of phase
detector, i.e. the output voltage of phase detector when the phase difference is 0.
Figure 1.2: The The linear model of a phase-locked loop
In some applications, it is desirable for Vdo to be 0. Similarly, Vco is the control

voltage that brings the output frequency of the voltage controlled oscillator in
phase with the input when in lock, so different from Vdo which depends on the
phase detetctor, Vco is not a property of VCO instead that is also depends on
the input frequency in some applications.

In the linear model, the phase error between the input and the output, i.e.
|(i (t) o (t)| is small enough.Usually when |(i (t) o (t)| < 21 rad,equation
(1.4) can be written as.
d0
= Kd Kf Kvco [i (t) o (t)] f (t)
dt
(1.5)
Normally it is preferred to express in frequency domain rather than time

domain in terms of the PLLs response to some external disturbances, especially
the noise performance. After Fourier transform, with i (jw), o (jw), andF (jw),
as the Fourier transforms of i (t), o (t)andf (t), a linearized transfer function of
the PLL can be express as,
H(jw) =
KF (jw)
o (jw)
=
i (jw)
jw + KF (jw)
(1.6)
Where K is the product of Kd Kf Kv co, the open loop gain, and usually Kf
is 1. With this equation, PLLs dynamic response to some external disturbances
can be achieved. Some typical disturbances are frequency step, phase step and
frequency ramp.
1.2
Motivation
In designing an analog PLL, the performance is achieved through aggressive circuit techniques. The effort to achieve acceptable performance often translates to
the cost of power and circuit complexity. Feedback control is extensively applied
for accurate biasing to reduce the noise from the loop filter [7, 8], Self-biasing
[9, 10] is another technique that takes advantage of the good matching between
devices in monolithic implementation to adaptively maintain the loop dynamics
under different operating conditions. These techniques often entail the design
of high-gain operational amplifiers with wide input range and wide bandwidth.
Moreover, the stability issue associated with the use of feedback requires accurate process control over the components values. Although replacement with
active devices [10, 17] is common, passive components with high quality factors are preferred in the loop filter [9, 18] for low noise purposes and for better
linearity over a wide range of operation. As a result, the performance of an
analog PLL depends heavily on the process parameters, and therefore, leads to
re-design for each new technology.
The performance of critical analog blocks, however, is degrading as the technology advances into nanometer-scale regime [19]. The ever-increasing problem
of leakage current has prevented the threshold voltage of transistors from scaling
with the supply voltage, and the available voltage headroom is quite small for
any sophisticated analog circuit design [19]. With the reduced intrinsic gain due
to short-channel effects of the transistors and the wider PVT variations in advanced technologies, achieving the systems specifications at a specific operating
frequency has become increasingly difficult. Keeping constant loop dynamics
over a wide operating range without the aid of digital calibration is even harder
and almost an impossible task [17, 18, 20]. Two similar designs [10, 21] show
a dramatic reduction in the operating range as the technology advances from
0.5um to 90nm node.
To overcome those difficulties and enable more desired features that are not
achievable in an analog implementation, designers have become aware of the
many advantages in digital-intensive architectures over purely analog implementations [14, 15]. Circuits implemented digitally can be integrated easily in large
digital ICs, can be migrated easily to different technologies, and can be more
programmable and flexible. As the gates only need to resolve two logical levels, digital circuits are more robust to electronic noise which does not improve
with technology scaling due to the reduced supply voltages [16]. A mixture of
digital circuits into the main analog circuit structure becomes attractive as a design methodology to address non-ideal device characteristics and PVT variations
[17, 18, 20]. Digital programmability can be embedded into analog PLL designs
as well, for example to perform a digital search for faster locking rate or to adaptively change the loop characteristics for lower jitter performance [22, 23]. An
aggressive step further is to replace the loop filter with a fully digital signal processor. This type of implementations is often recognized as digital phase-locked
loops (DPLLs).
Many reported DPLLs so far are basically digital version of their analog
counterparts, in that each blocks are digitized separately. The phase/frequency
detector is replaced by a digital phase/frequency detector, whose output is the
digital representation of the phase frequency error. The analog loop filter is
replaced by a digital loop filter with a small frequency response. The VCO is replaced by a digitally-controlled oscillator (DCO), whose frequency is controlled
by its digital frequency control word. Although those DPLL can de designed
and analyzed based on existing design methodology of analog PLLs, they normally require high resolution/linearity/complexity so that the DPLL behaves
similarly as an analog PLL. For example, a popular type-II digital loop filter,
consisting of multipliers, adders, and so on, may require thousands of gates
and is a large digital component comparing with the remaining components of
DPLL. Because the digital loop filter usually works with binary weighted signals, the output of the digital phase and frequency detector usually needs to be
encoded to a binary weighted signal and the output of the digital loop filter is
usually coded/decoded to some kind of linear coded signal before it is connected
to the digital tuning units of the DCO to achieve better linearity. Figure 1.1
shows the jitter performance and the operating frequency range of some of the
Figure 1.3: Jitter performance and the operating frequency range of the reported
analog and digital PLLs.
10
reported PLLs over the past decade with either analog or digital intensive implementations [7, 8, 21, 24, 18, 20, 17, 9, 10, 25, 26, 27, 28, 29, 30, 31, 32, 53,
57, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43]. The quantization nature of digital
circuits provides better immunity against the process, voltage, and temperature
(PVT) variations. The reported digital-intensive designs have shown robustness
in terms of operating range especially with advanced technologies. As shown
in Figure 1.1(a), while the analog PLLs operating range hardly exceeds two
orders of magnitude even with sophisticated feedback controls to adapt the loop
characteristic to different operating conditions, the DPLL design in [28] achieved
more than 3000 x of frequency range with 90nm CMOS technology.
In this research work, a low complex all digital phase-locked loop (ADPLL)
including a customized time-to-digital converter (TDC), a finite state machine
(FSM), and a digitally controlled oscillator (DCO) is proposed, analyzed, simulated and measured. The proposed ADPLL separates the lock-in process into
frequency and phase acquisition. The TDC is used to measure the frequency
difference precisely so that fewer reference cycles are needed in the frequency
lock-in process compared to the previous blind fast or slow comparison. The
phase acquisition only takes two reference clocks. One cycle for resetting the
DCO and the other cycle for updating the control considering the path delay.
The proposed ADPLL can easily be implemented and employed in some
11
integer-N frequency multiplication applications. However, an unavoidable occurrence is that frequency multiplication (by N), raises the signals phase noise
by 20Log(N) dB. By reducing the value of N, we could racially reduce the phase
noise of the system. However, the channel spacing of an integer-N synthesizer
is dependent on the value of N. A fractional-N frequency synthesizer has benefits compared with classical integer-N implementations. It is accomplished by
adding internal circuitry that enables the value of N to change dynamically
during the locked state. In this paper an all digital phase locked loop based
fractional-N frequency synthesizer is presented. Different from the conventional
fractional-N frequency synthesizer, an extra TDC is applied to obtain the fractional value avoiding the use of fractional divider, which is the main source of
fractional spur in a fractional-N frequency synthesizer. The proposed FractionN frequency synthesizer is implemented using Predictive Technology Model at
0.9V supply voltage.
Chapter 2
Review of frequency synthesizer
A frequency synthesizer is a system for generating any frequency of a certain
range.Regarded as one of the most critical modules, frequency synthesizers are
widely found in modern wireless communications systems. On the transmitter
side, frequency synthesizer provides carrier frequency for the up-convert mixer.
This carrier frequency modulates the low frequency baseband signal coming to
the up-convert mixer, which is then sent out by the power amplifier. On the
receiver side, the low noise amplifier picks up the received signal and amplifies it
to a certain level. The frequency synthesizer again provides the carrier frequency,
but this time to demodulate the received signal to the baseband signal in the
down-convert mixer.
12
CHAPTER 2. REVIEW OF FREQUENCY SYNTHESIZER
2.1
13
Performance parameters of a frequency synthesizer
As a key block in wireless systems, frequency synthesizer demands quite a few

of design considerations. One major concern is the functionality of frequency
synthesizer, including channel switching time, frequency step and operating frequency range. Another concern is the quality of the carrier signal, including
phase noise, spurious power level and output jitter. Also, attention has to be
paid to general considerations of a circuit, such as power consumption. We
discuss all those considerations as follows.
2.1.1
Phase noise
The spectral purity of a periodic signal can be easily characterized and visualized
in the frequency domain. The impulse spectrum of an ideal frequency source
is shown in Fig 2.1a. Fig 2.1b shows the spectrum of its practical counterpart
Figure 2.1: The spectrum of an ideal signal and practical signal
14
having the same nominal output frequency. The ratio between the power at a
frequency offset (foffset) within a certain bandwith to the power of the center
frequency (f0 ), is defined as a phase noise. It is a measure of the relative level
of the undesired noise components,
P hasenoise(fof f set =
N oisepowerat(f0 + fof f set )

P oweratf0
(2.1)
Usually, the measurement bandwidth of the noise power is 1 Hz and the

phase noise is expressed in a logarithmic scale, resulting in an unit of dBc/Hz.
It can be seen that the phase noise is essentially a measure of the instantaneous
uncertainty in a carriers period. This uncertainty can be considered as the
result of frequency modulating the carrier by some other signals and therefore
phase noise can be better understood by examining the frequency modulation
process.
In frequency modulation (FM), the instantaneous frequency of a sinusoidal
carrier is a function of the amplitude of the modulating signal. Suppose this
modulating signal is a sinusoid,
vm (t) = Am cos(wm t)
(2.2)
This assumption does not result in a loss of generality, because any physicallyrealizable signal can be decomposed into a set of sinusoidal signals by Fourier
15
transform. The signal resulting from the frequency modulation is thus written
as
v(t) = Ac cos(wc t + kf
Am
sin(wm t))
wm
(2.3)
Where kf is a constant, Ac the amplitude, and wm is the angular frequency of

the modulating sinusoid. When kf
v(t) Ac [cos(wc t) +
Am
wm
2 , equation (2.3) maybe written as,
mf
mf
cos((wc + wm )t)
cos((wc wm )t)]
2
2
(2.4)
m
Where mf = kf A
is the modulation index. Equation(2.4) shows that at
wm
low modulation levels, frequency modulation of the carrier by a single low-level

noise sinusoid results in the appearance of two sidebands at wc + wm as shown
in Fig 2.2. For the output of a practical frequency synthesizer, the modulating
Figure 2.2: The spectrum of a sinusoid FM signal
signal is not a simple sinusoidal signal as above, but a complex noise, which contains many frequency components. Fig 2.3 shows the power spectrum produced
16
when a sinusoidal carrier is modulated by a more general signal (noise). The

relationship of the device output spectrum to the spectrum of the modulating
noise can be observed in this diagram.
Figure 2.3: The spectrum of a FM signal
Equation (2.1) is a definition of phase noise in terms of power levels. A more

Practical definition of phase noise (at frequency offset fm ) in terms of frequency
deviation from a central value (carrier) can also be given as
frms
)
N oise T o Carrier ratio(dB) = 20log(
2fm
(2.5)
Where fm is the frequency offset from carrier and the frms is the RMS value
of the frequency variation with respect to the carrier frequency within a certain
bandwidth (normally 1HZ). Practically, if the bandwidth is 1 Hz, the result of
equation (2.5) is in unit of dBc/Hz.
2.1.2
17
Spurious power level
The undesired frequency components which appear in the operating band of a

device at some discrete frequency points are called spurs. Their power levels are
described in a way similar to the phase noise power levels, namely by comparison
with carrier power. Fig 2.4 shows an example of a frequency source corrupted
by both phase noise.
Figure 2.4: The power spectrum of a frequency source with spurs

In theory, the phase noise can be defined to measure the phase variation over
a wide band centered on the desired output frequency. But such a wide band
measurement would give a misleading impression because spurs only appear at
discrete frequencies. Spurious power level is measured in a way that is analogous
to phase noise measurements,
Spurious power level(dBc) = 10log(
Spuriouspower
)
Carrierpower
(2.6)
Spurious power level is related to carrier power but is independent of measurement bandwidth, so it is reasonable to express it in unit of dBc (Decibels
18
relative to carrier). Among those spurs shown in Fig 2.4, the two spurs closest
to carrier are of most concern because they may affect the following systems significantly. So the spurious power level normally refers to the spur with relative
higher power.
2.1.3
Output period jitter
In data communication systems, the period jitter of the clock signal are of great
interest. The period jitter is the time difference between a measured cycle period
and the ideal cycle period. The jitter can be measured as peak to peak jitter or
Figure 2.5: Illustration of period jitter
by Root of Mean Square (RMS). The period jitter is illustrated in Fig 2.5a, in
which the dashed curve is the ideal signal, having a period of Tidela, while the
solid curve is the actual clock signal, whose period is Tn. The period jitter in
this case is calculated as:
Jperiod = Tn Tideal
(2.7)
2.1.4
19
Operating frequency range
Normally, the frequency synthesizer produces an output signal whose frequency

is the reference frequency multiplied by some factor. This factor may be fixed,
determined by the circuit design itself, or it may be programmable. But in either
case the output frequency changes if the reference frequency does.
The operating frequency range of the PLL denotes the maxim input frequency range over which the desired frequency ratio between input and output
can be maintained with acceptable output phase noise, spurious power level and
so on. It is important that such operating frequency range is usually determined
by the frequency range of VCO OR DCO, and the frequency multiplication ratio.
This range is dictated by the target application, but the designer should
realize that it also depends on unpredictable effects on devices caused by such
things as temperature variation, supply voltage fluctuation and more, and overdesign the synthesizer accordingly.
2.1.5
Frequency step
The frequency increment of a tunable frequency synthesizer is defined to be the

minimum possible frequency shift of its output when the reference frequency
is fixed. The integer-N synthesizer, the most common one, has a constant frequency increment equal to the reference frequency over the full tuning range.
For some applications, tunable frequency multiplying synthesizers, which
20
generate output frequencies which are N times the input, do not have adequate
frequency resolution (the frequency increment is too large) and more sophisticated technologies, such as fractional-N synthesis, are employed.
2.1.6
Channel switching time
Channel switching time refers to the time needed for a tunable frequency synthesizer to settle to the new output frequency after the reference frequency or
the frequency multiplication ratio is changed. Most indirect frequency synthesizers incorporate some kind of filtering in their feed back loops, and the filter
bandwidth normally affects the channel switching time.
A well-known relation between a filters 3Db bandwidth (B3 dB) and the rise
time (tr ) is shown in equation (2.8), where k is a value between 0.3 to 0.45. The
rise time tr is the time needed for a voltage step to move from 10% to
tr
k
B3dB
(2.8)
90% of its full swing. The equation can be used to estimate the channel switching time during initial design stages. It should however be kept in mind that
equation (2.8) does not involve phenomena such as overshoot and ringing, and
a more refined model should be used in late design stages.
2.1.7
21
Power consumption
The concept of power consumption, which refers to how much energy a device
consumes within a unit time, is applicable for all electronic devices. Power
consumption is always an important consideration for the designers. This is
especially true for portable devices such as mobile phones since it determines
the battery life. Consequently, low power consumption design aspect is always
a big issue in the design stages of those devices.
2.2
Frequency synthesizer architectures
Generally, frequency synthesizers can be categorized into three groups: the tablelook-up synthesizer, the direct synthesizer, and the indirect or phase-locked loop
synthesizer. The table-look-up synthesizer or digital synthesizer generates the
sinusoidal signal piece by piece using digital values of the waveform stored in
memory. The direct synthesizer synthesizes the wanted output frequency from
a single reference by multiplying, mixing, and dividing. The indirect frequency
synthesizer creates its output by phase-locking the divided output to a reference
signal.
2.2.1
22
PLL based frequency synthesizer
A typical structure of a PLL-based frequency synthesizer is shown in Fig 2.6.The

basic function of a PLL is to tune the phase of the VCO to make the frequencies
Figure 2.6: A PLL-based frequency synthesizer
of two inputs of the phase comparator identical and the phase difference between
them constant. With a divider (/N), the actual output frequency of the VCO
is,
Fout = N Fin
(2.9)
Normally N is an integer. By changing the value of N, the output frequency can

be changed with the increment of Fin . To obtain a smaller increment, another
divider is employed to divide down the reference signal Fref by M, thus the
increment is also divided by M. The actual relation between the output (Fout )
and the reference signal (Fref ) is thus,
Fout = N
Fref
M
(2.10)
23
However, with this method, the frequency increment can not be reduced
infinitely because the value of M cant be too large due to the noise performance
issue.
Not only can the phase-locked loop be employed to generate an output frequency with the ratio of an integer, but a ratio which is the sum of an integer
and a fraction of an integer can be obtained, this is often referred as fractional-N
frequency synthesis. To achieve the fractional division ratio, a programmable
divider can be employed in the PLL-based frequency synthesizer. Fig 2.7 shows
a simplified diagram of a fractional-N PLL-based frequency synthesizer with a
Figure 2.7: A fractional-N PLL-based frequency synthesizer
divider including a cycle swallower to obtain a fractional division ratio. With

this fractional division ratio, the ratio between the output frequency and the
input frequency can be fractional since the output of the divider is locked at the
same frequency as the input.
2.2.2
24
Table-look-up synthesizer
While PLL based frequency synthesizer relies on low speed feedback loop to
provide accurate carrier frequency, table-look-up synthesizer generates carrier
frequency very fast by removing the feedback loop. Shown in Fig 2.8, it generates
the signal in digital domain through an accumulator and a read-only memory
(ROM), which is converted to analog waveform by digital-to-analog converter
(DAC). Spurious harmonics at DAC outputs are filtered out by low pass filter
(LPF). As no feedback is involved in synthesizing frequency, settling time is
very fast. Indeed, it could be as fast as the order of gate delays. For example,
table-look-up synthesizer in [44] outputs frequency from DC to 75 MHz with
settling time only 6.5 ns. Other merits include low phase noise, fine frequency
steps and free of stability issue.
Figure 2.8: A table-look-up frequency synthesizer

The most critical drawback of table-look-up synthesizer is its low output
frequency. To reconstruct the analog waveform correctly, according to Nyquists
sampling theorem, the clock frequency has to be no less than twice of the output
frequency. In many RF applications, the carrier frequency has already reached
25
the speed limit of the circuit, to have all the digital parts of table-look-up synthesizer work at least twice the carrier frequency is challenging by any means.
Furthermore, the non-idealities of table-look-up synthesizer would degrade the
output spectra purity.
2.2.3
Direct digital frequency synthesizer
The table-look-up synthesizer can achieve a fine frequency resolution and a fast
frequency-locking speed. However, it cant be directly used in wireless communications operating at a frequency of several GHz because of its high power
consumption and the highest-frequency limitation imposed by the Nyquist sampling theorem [45, 46, 47, 48]. Additionally, a high clock frequency is required
to cover a wide bandwidth that leads to high power consumption. Moreover,
high-frequency spurious tones tend to corrupt the spectral purity. Thus, a tablelook-up synthesizer is usually combined with a fixed-frequency Phase-Locked
Loop (PLL) frequency synthesizer to extend the highest-frequency limitation
[50]. This combined synthesizer is called as Direct Digital Frequency Synthesizer (DDFS). An example of this DDFS is shown in Fig2.9. In this figure, a
rather low-frequency signal Flow is generated using a table-look-up synthesizer,
which is then up-converted to the desired RF frequency with a fixed-frequency
oscillator signal FIF . The fixed high-frequency oscillator signal is generated using a lower reference frequency from a PLL-based synthesizer. Thus, the output
26
Figure 2.9: A direct digital frequency synthesizer

frequency is given by
Fout = Flow + FIF
(2.11)
The main advantage of this architecture is the fixed frequency of the PLL synthesizer. Because the reference choice is free, the loop bandwidth can be optimized
for noise reduction. Besides reduced noise, the frequency can be changed rapidly
by changing the frequency of Flow . However, this architecture suffers from the
limited frequency range because of the low Flow, which can only be increased by
making a faster DAC. Depending on the required spectral purity of the synthesized signal, the DAC needs a large number of bits and will therefore already be
power-hungry. Therefore, the DDFS will only be useful in systems that require
very fast frequency hopping. The flexibility of this architecture can be expanded
by replacement of the table-look-up synthesizer with another PLL. This results
in the so-called dual-loop indirect frequency synthesizer that has more degree of
27
freedom than the standard PLL architecture [49].
2.3
Conclusion
This chapter has given an overview of the frequency synthesizer techniques and
their performance criteria. Specifically, low phase noise, low spurious tone, lowpower single chip solution for wireless communication is the main focus of this
chapter.
The table-look-up synthesizer is a straightforward way to implement a frequency synthesizer. has attractive features such as fast locking speed, high
integration level, and wide tuning range. On the other hand, this architecture
has several disadvantages such as high power consumption, limitation of higher
frequency by Nyquist theorem, and discrete narrow band spurs. So, a tablelook-up synthesizer is usually combined with a fixed-frequency Phase-Locked
Loop (PLL) frequency synthesizer to overcome its highest-frequency limitation
[50]. This combined synthesizer is called a Direct Digital Frequency Synthesizer
(DDFS). This architecture also has disadvantages such as the limited frequency
range because of the low Flow, which can only be increased by making a faster
DAC. Therefore, the DDFS will only be useful in systems that require very fast
frequency hopping.
The phase-locked loop based frequency synthesizer has many advantages
such as the potential for combining high frequency and low power, low cost,
28
effective spurious-noise suppression and its easiness of integration in low-cost IC

processes, like CMOS. This is the reason why the PLL is most popular in almost
all wireless communication chip sets on the market. However, this architecture
has many major disadvantages such as the inverse relationship between the step
size and the phase noise. As the step size decreases, division ratios in the system
must increase. The higher the division ratio, the worse the phase noise within
the loop bandwidth close to the center frequency. Another drawback is a slow
switching speed from one frequency to another because of the negative-feedback
loop dynamics.
The problems that are caused by analog circuits such as variation in the
passive elements values or shift of the center frequency of a frequency synthesizer
can be solved using the All-Digital Frequency Synthesizer (ADFS). In contrast to
conventional Digital Phase-Locked Loop (DPLL), it is an entirely digital system.
So, settling time of the ADFS methods can be made extremely short. Such short
settling time can be an advantage in many applications.
Chapter 3
Design Considerations in Analog
PLLs
The block diagram of a commonly used charge-pump (CP) PLL is shown in Fig
3.1. It consists of a phase and frequency detector (PFD), a CP, a loop filter
(LF), a voltage controlled oscillator (VCO) and a divide-by-N divider. Via the
divider, the VCO output is fed back to the PFD with a divided-down signal
(FED). The other input to the PFD is a fixed reference frequency/phase (REF).
The PFD compares the frequency and phase difference between the two inputs.
The CP produces a current that has an average value proportional to the phase
error. The LF smoothes the current into a voltage on the control node (Ctrl),
which in turn drives the VCO. In the steady state, the PFD inputs are equal
in phase and frequency. The phase error is zero and the frequency and phase
29
CHAPTER 3. DESIGN CONSIDERATIONS IN ANALOG PLLS
30
of the output oscillation signals are synchronized with the reference as shown in
Fig 3.2.
Figure 3.1: Block diagram of a charge pump-based PLL.
Figure 3.2: Conceptual timing diagram of the clock waveforms.
Since the PLL is essentially a negative-feedback loop, stability is key design

criterion. Equation 3.1 shows the open-loop transfer function with a continuoustime approximation which is only valid when considering signals that are much
slower than the reference frequency (the sampling frequency in the system)[38].
Hopenloop (s) = ICP (
1 + s RLF CLF
KV CO 1
)
CLF C3
s
M
s CLF (1 + s RLF CLF +C3
(3.1)
In Equation 3.1, RLF and CLF are the loop filter resistance and capacitance, and
31
C3 is the 3rd order smoothing capacitance along with the parasitic capacitance
associated with the control line. As we can see with the Bode plot shown in
Fig 3.3, because of the two poles at the origin, when the frequency is low, the
magnitude of the open loop transfer function has the 40dB/dec slope and the
phase shift is 180 degrees. The crossover of this 40dB/dec slope and the unity
loop gain is the natural frequency of the system. For the loop to be stable,
a zero is required to increase the phase margin before the loop gain drops to
unity. However, the phase margin introduced by the zero is degraded due to the
existence of higher-order poles in the system. As we can see from the equation,
the zero is formed by the resistor and the capacitor in the loop filter, and usually
a 3rd-order pole is formed because of the capacitor used to smooth the ripple
on the control line. Usually the smoothing capacitance C3 is 1/5 1/10 of
CLF [38], and the phase shift introduced by the 3rd-order pole can be ignored.
The resulting closed-loop transfer function has the damping factor which can
be expressed in terms of the ratio of the natural frequency wn and the zero
frequency wz as shown in Equation 3.2.
wn
, where
2 wz
1
wz =
, and wn =
RLF CLF
(3.2)
ICP KV CO
M CLF
However, this continuous-time analytical model does not take into account
32
Figure 3.3: Conceptual timing diagram of the clock waveforms.

the excessive phase shift cause by the loop delay that comes from the sampling
nature of the loop. To avoid instability due to the sampling delay, the loop
bandwidth is constrained to be low enough compared to the reference frequency.
The performance of an analog-intensive design depends substantially on the
process parameters. This chapter discusses the challenges of a charge pumpbased PLL as the technology scales.
3.1
33
Adaptive Bandwidth Technology for PVT

Tolerant PLL
The loop bandwidth is a critical parameter in the design of PLLs. First of all,
the loop bandwidth should be less than the reference frequency by a factor of 10
to guarantee loop stability. In addition, the loop bandwidth balances the tradeoff between the in-band phase noise (e.g., contribution from the reference clock)
and the out-of band phase noise (contributed from the VCO). For a noisy VCO,
a higher loop bandwidth would be desirable since the VCO noise within the
bandwidth will be attenuated. On the other hand, when the reference clock is not
clean compared to the VCO, a lower loop bandwidth would be desirable in order
to filter the input noise from the reference clock. However, a small bandwidth
would result in a slow transient response. The loop bandwidth calculation,
therefore, must trade off the transient response and the total output phase noise.
In order to achieve the best phase noise performance while maintaining loop
stability and satisfying the settling time requirements, the loop bandwidth must
be optimized.
As we can see from Equation 3.1, the loop characteristics are determined by
the design parameters such as Icp , RLF , CLF , andKV CO . Given a designed VCO
with a gain of KV CO , the loop bandwidth can be set to the desired value by adjusting the charge-pump current Icp and the loop filter resistor RLF . However,
34
PVT variations may lead to uncertainties in the PLL parameters, for example, the VCO gain KV CO . As a consequence, the performance can therefore
be optimal for only a specific operating condition. This essentially results in
compromised performance for the entire operating range [54, 21, 10]. Dynamically scaling the loop characteristics with respect to the reference frequency is
therefore needed, and is usually referred to as the bandwidth-tracking ability.
The PLL designs in [21, 10] achieve the bandwidth-tracking ability using a
feed forward zero. The use of a secondary charge pump for the feed-forward
control results in a nice tracking between the natural frequency and the zero
frequency, and therefore a constant damping factor according to Equation 3.2.
Furthermore, the tracking between the loop bandwidth and the operating frequency is guaranteed by adjusting the charge pump current with the biasing
current that controls the VCOs operating frequency. With a VCO design that
has a constant KV CO across the operating range, the resulting damping factor
and the ratio between the loop bandwidth and the reference frequency rely only
on the ratio of capacitances that can be matched reasonably well in layout. A
simpler method to achieve the bandwidth tracking is proposed in [25], where
the charge pump current is self-biased with the VCO control voltage [55] such
that the charge pump current scales with the operating frequency. A MOS in
triode region is used as the resistor in the loop filter, and it is also biased with
the VCO control voltage such that the zero frequency scales with the operating
35
frequency as well. A special technique is applied in [25] to linearize the VCO

characteristic for an extended operating range.
[54] shows a more general analysis on the criterion for bandwidth-tracking
ability and reaches the same strategy of scaling the charge pump current and
loop filter resistance according to the operating condition. However, as the
technology scales, it has become more and more difficult to achieve bandwidthtracking ability over a wide frequency range with a purely analog method. The
reported design with 0.5-um CMOS technology [21] successively achieves more
than 200,000x of frequency range with the largest possible loop bandwidth over
all operating frequencies for minimal jitter accumulation. However, a similar
design achieves only 20x of frequency range with 0.13-um CMOS technology
[10].
The tracking between the pole and zero frequencies with the operating frequency starts to fail as the short-channel effects become profound in highlyscaled technologies. It is also difficult to maintain a constant VCO gain across
the operating range. As a result, digitally-assisted branches (digital calibration)
are added in the loop filter for more adjustability.
3.2
Challenges in the VCO Design
With the technology scaling, designing a VCO with wide frequency range along
with the reduced supply voltage leads to increased Kvco which results in worse
36
immunity to supply fluctuations and the noise coupled onto the control line
through parasitic capacitors. Furthermore, the reduced voltage headroom results
in reduce linear region in the VCO transfer function.
To demonstrate the challenges in the VCO design, Fig 3.4 and Fig 3.5 show
the the schematic and the transfer function of a 3-stage inverter-based ring
oscillator designed in 65-nm CMOS technology, in which a regulator is needed
to adjusts the operating frequency. The impact of the process variations is also
shown with corner simulations. As we can see from the transfer curve, the linear
region only occupies a small portion of the control voltage range.
Figure 3.4: Block diagram of a 3-stage inverter-based ring oscillator with a

regulator adjusting the control voltage.
Some voltage headroom is needed when the operating frequency is low because of the threshold voltage needed to turn on the devices. This region becomes wider as the technology scales due to the lower VDD to Vth ratio. Velocity
37
Figure 3.5: Transfer functions of the 3-stage inverter-based ring oscillator and
the regulator shown in Fig 2.4 with the process variations.
saturation causes the fall off of KV CO when the operating frequency is high. Furthermore, some voltage headroom is also needed when the operating frequency
is high for the regulator to supply the current for the oscillation. This region
with lower VCO gain increases as well because of the reduced intrinsic gain of
MOS devices as the technology shrinks.
The corner simulations show that the wider process variations causes more
than 2x of frequency deviation, and this translates to a huge change of the control
voltage especially for higher operating frequencies. This dramatic change in the
operating condition can easily drive the transistors of the charge pump and loop
filter (if implemented with active devices) into triode region and can greatly
38
compromise the performance and potentially result in functional failures.
3.3
Challenges in the Charge Pump Design
Charge pumps (CPs) are widely used in analog phase locked systems, such as
phase-locked loops (PLLs), delay-locked loops (DLLs), and clock and data recovery (CDR) circuits. The CP converts the phase difference to a proportional
voltage to adjust the voltage-controlled oscillator (VCO) or voltage-controlled
delay line (VCDL). As the technology keeps scaling, the matching between the
up and down currents in the charge pump becomes worse. The up and down
currents basically flow through different transistor types, and it becomes harder
to match the two inherently different characteristics. As shown in Fig 3.6, the
up and down currents are equal only for a single operating point. The current
Figure 3.6: Block diagram and simulated transfer function of a charge pump
example with 65-nm CMOS technology.
39
mismatch dramatically increases as the control voltage reaches VDD or Vss as

either of the two branches is forced into triode region. Even when the up and
down devices are both in saturation, the operating range with acceptable mismatch becomes smaller as the technology scales because of the reduced output
impedance of the devices. Another issue associated with the current mismatch
is the degraded loop bandwidth since it is the smaller current that determines
the loop gain.
Several methods have been presented to improve the CP mismatch. In [11],
a replica CP and a digital controller are used to calibrate the CP mismatch as
shown in Fig 3.7. However, the mismatch between the two CPs still exists. Since
Figure 3.7: Replica current compensation scheme.
two CPs are calibrated on different controlled voltages, it is hard to compensate
40
the current mismatch due to the channel-length modulation.

In [12], the common-mode feedback circuit is used as shown in Fig 3.8. The
output currents versus the output voltage with and without mismatch suppression is shown in Fig 3.9. Without mismatch suppression, the charging current
and discharging current are close to each other only when the output voltage
is near the common-mode voltage (1.65 V). When the output voltage goes farther away from the common-mode level, the difference between the charging and
discharging current becomes larger. After the introduction of a mismatch suppression circuit, the charging current and discharging current match very well
for a large swing from 0.1 to 3 V. However, an additional reference voltage and
the operational amplifier are needed. The non-ideal effects of the operational
amplifier have to be considered, such as the stability and offset voltage.
Figure 3.8: Common mode feedback circuit for the differential charge pump.
41
Figure 3.9: Output currents with and without mismatch suppression.
3.4
On Chip Digital Calibration
For a typical phase-locked loop (PLL), the jitter performance and the transient
behavior mainly depend on the dynamic parameters, i.e., damping factor and
natural frequency. However, the process and temperature variations alter the
dynamic parameters away from the desired values. For the short-channel devices
in advanced CMOS technology, the device mismatch and channel-length modulation becomes worse. In frequency synthesizers, the mismatch in a CP results
in unwanted spurs and deteriorates the spectral performance. In multi phase
DLLs, the unbalanced CP creates the static phase error to generate the fixed
pattern jitter or degrade the timing margin. Similarly, in conventional CDR
circuits, the mismatch in a CP makes the sampling clock away from the optimal
position to increase the bit error rate. In order to ensure stable operation across
42
the operating conditions and PVT variations, on chip calibration is often applied
to the charge pump and the loop filter to provide different configurations and
adjust the loop characteristics for stability.In addition to the analog adaptation
techniques, digitally controlled branches can be added into the charge pump
and the loop filter to provide different configurations and adjust the loop characteristics for stability [13]. As shown in Fig 3.10, the synthesizer is composed
Figure 3.10: Frequency synthesizer using the on chip digital calibration technique.
of a traditional integer-N PLL with a switched-delay PFD, a digital-controlled

CP, and additional digital calibration circuits. The additional digital calibration circuits include an LD, a BBPD, and a 4-bit SAR controller. When the
phase-locked system is out of lock, all control bits of the SAR controller are
reset. When the lock detector (LD) is locked, the CP is calibrated according to
the relative phase relationship between the up and down controlling signals of
43
the PFD. The calibration process repeats N rounds for an N-bit controlled CP
until all of the control bits are determined.Furthermore, optimization algorithms
such as a gradient-descent algorithm can be adopted along with op-chip jitter
measurement to dynamically minimize the output clock jitter when the composition of noise from different sources are not know a priori. However, the range
of digital calibration must be large enough to cover the desired operating range
and the possible variations. Therefore, the amount of digital branches needed
can be huge.
3.5
Summary
This chapter reviews the conventional analog PLL design and highlights some of
the challenges brought by technology scaling. The wider variability, poor analog
characteristics of devices, and the reduced voltage headroom plague designs
in nanometer CMOS process. To achieve the minimum overall phase noise,
the closed-loop bandwidth must be optimized. It is also desirable to make
the optimum bandwidth setting robust to PVT variations and scalable with
the reference frequency. The requirements for an adaptive loop bandwidth are
derived.Although many sophisticated design techniques have been invented to
address the different challenges, it is worthwhile to investigate a fully digital
implementation, which is not impacted by the technology scaling and leakage
issue. The next chapter will present the fundamental analysis and the design

considerations of a digital PLL.
44
Chapter 4
A Proposed All Digital PLL
Architecture
With the increasing performance and decreasing cost of digital VLSI design technology, all-digital phase-locked loops (ADPLL) have become more attractive.
Although ADPLL wont have the same performance as its analog counterpart,
it provides a faster lock-in time and better testability, stability, and portability
over difference process.
There are two major problems needed to be considered carefully when designing the ADPLL. One is how to design a Digitally-Controlled Oscillator with
wide operating range and high resolution. The other is how to speed up the lockin process, and reduce the clock jitter coming from the reference clock. Usually
the ADPLL structure based on the second order negative feedback system has
45
CHAPTER 4. A PROPOSED ALL DIGITAL PLL ARCHITECTURE
46
a faster lock-in time with a limited lock-in range[51, 52]. One the other hand,
by separating the locking process into frequency and phase acquisition, a wide
lock-in range is available[53, 56]. However, it takes more time due to the blind
ahead or behind comparison as well as the extra phase lock process.
In this work, the new ADPLL also has a separated frequency and phase
lock-in process. Instead of ahead or behind comparison, a time-to-digital
converter is used to measure the frequency difference accurately, which could
greatly reduce the lock-in time. The phase acquisition only takes two reference
clocks. In the first cycle, the DCO is reset by the reference clock, while taking consideration into the delay between DCO output and DCO clock. In the
second cycle, the DCO frequency changes back to the reference clock by updating the control bits. The proposed DCO can achieve 1ps resolution with power
consumption of 2.3mW @ 700 MHz.
4.1
Analog and digital PLL design trade-offs
Fig 4.1 shows the principle of a PLL-based frequency synthesizer. The input and
output are represented by their phase information. The actual time-domain reference signal, VCO output, and divider output are cos(ref (t)), cos(vco (t)) and
cos(div (t)) respectively. The phase detector is essentially a subtracter whose
output is ref (t) div (t). This phase error information is filtered to tune the
VCO, which also performs an integration operation to converter the filtered
47
Figure 4.1: The principle of a PLL-based frequency synthesizer

phase error to VCO phase (vco (t)).
Two quantizers in the figure are optional depending on types of PLLs. For
an analog PLL employing a continuous time phase detector, no quantization
operation is involved. However, almost all analog PLLs employs a discrete time
phase detector in that the phase error sample is only produced once per reference or divider cycle. In such PLLs, the quantizer A(QA) has infinite small
quantization steps and its sampling frequency is the same as the reference frequency in the locked condition. For a digital PLL, the phase error has to be
quantized with finite steps by (QA) so the phase error is represented in discrete
time and discrete value, which is processed by some digital circuit ( in most
cases, a digital loop filter) so that the tuning signal for the oscillator can be
obtained. Usually, such digital circuit operates in the same clock rate as the
QA (ClockB=ClockA). Although the output of the digital circuit may have a
very high resolution, the DCO in a digital PLL normally has a limitation on the
tuning resolution, which is represented as the finite steps of quantizer B(QB).
48
Table 4.1 summarizes the mathematical representations of analog/digital PLLs.

Table 4.1: A mathematical representations of analog/digital DPLLs
Parameters
Frequency of ClockA
Quantization step of QA
Frequency of ClockB
Quantization step of QB
Filter
Continuous-time
analog PLLs
Infinite high
Infinite small
Infinite high
Infinite small
Analog filter
Discrete-time
analog PLLs
Reference frequency
Infinite small
Infinite High
Infinite small
Analog filter
Digital PLLs
Reference frequency
finite step sizes
Reference frequency
finite step sizes
Digital loop filter
In an analog PLL, noise in PFD, charge pump, loop filter and so on is transferred to the VCO output, increasing the output phase noise. In additional, the
design flow and circuit design techniques of an analog PLL are analog intensive
and they are difficult to be reconfigured, adaptive, scaled with new technologies.
Digitizing blocks of an analog PLL gains increasing interest with the increase
of the operating speed of digital circuits. From description above, the digitizing
process is essentially inserting two quantizers in the loop so that the analog filter
can be replaced by digital circuit. The quantizer A is usually implemented in the
phase detector, resulting in a digital phase detector. Although the quantization
introduces some additional quantization noise, the digital circuit itself does not
contribute any additional noise as an analog loop filter does. By using digital
circuits to perform the filtering function, various features can be achieved, such
as dynamic bandwidth, fasy acquisition, auto-calibration, and so on. In addition,
the digital circuit is highly portable for different technologies. However, direct
digitization of an analog PLL requires some mathematical operations in high
precision, some complex code conversion operation, and high precision A/D
49
conversion, resulting a complex circuitry.
4.2
Digital PLL-based frequency synthesizers
Fig 4.2 shows a block diagram of a typical digital PLL. The basic operating Principle of digital PLLs is still the same as that of their analog counterparts, in that
they normally consist of a tunable oscillator, frequency divider, phase/frequency
detector, and loop filter. In an all digital PLL, the DCO usually relies on some
analog oscillating circuit although the oscillator tuning is achieved digitally. The
Figure 4.2: The blcok diagram of a digital PLL
frequency divider, in many cases, can be the same as a conventional frequency

divider used in an analog PLL. The digital phase and frequency detector, which
is usually a combination of an analog phse/frequency detector and a time to
digital converter (TDC), compares the reference frequency with the divider output to produce phase error information represented in digital signals. In some
digital PLLs, the frequency divider and the DPFD are implemented together to
realize more features. The digital loop filter, however, has both digital inputs
and outputs. As we can see, digitizing an analog PLL is essentially replacing the
50
analog loop filter with a digital loop filter together with some ADC and DAC
components as its interface to other analog blocks. Some reported digital PLLs
are reviewed in this section as follows.
4.2.1
An all-digital phase-locked loop for high-speed clock

generation
An all-digital phase-locked loop for high-speed clock generation is presented in

[57]. This ADPLL employs a novel fine-tuning delay cell, which can be reduce
both cost and design time for building a high-resolution cell-based DCO, as
shown in Fig 4.3. There are two identical DCOs in the ADPLL, one (Inner
DCO) is used for tracking the reference clock and the other one (Output DCO)
is used for generating the output clock.
The output clock of the inner DCO is divided by M then compared with the
reference signal (REF CLK). The PFD detects the frequency/phase difference
between the reference signal and the divided output clock and generates an up
(P UP) signal or down (P DOWN) signal to indicate whether the inner DCO
should be sped up or slowed down.The ADPLL controller updates the control
word of the inner DCO according to the output of the PFD. The control word
of the inner DCO is also sent to a low-pass filter to generate the control word
for the output DCO.
This ADPLL uses an adaptive search step when it searches for thr target
51
Figure 4.3: An all-digital phase-locked loop for high-speed clock generation

frequency. The frequency acquisition starts from the middle frequency band of
the DCO and the initial frequency step is one quarter of the frequency tuning
range. This frequency step is divided by two whenever the output of the PFD
changes its polarity until it is reduced to the fine-tuning step of the inner DCO
and the frequency acquisition is done. If the DCOs control word is updated
once every m reference cycles, the worst case lock-in time for this frequency
acquisition, in term of reference clock cycles, can be calculated as
n
T (n) = m(1 + 2log2 ( )) = m(2log2 n 1)
2
(4.1)
Where n is the total number of different frequency levels of the inner DCO.
The DCO in this ADPLL has a frequency tuning range from 41MHz to
545 MHz from HSPICE simulation. As shown in Fig 4.4, the frequency tuning
is achieved by two stages: a coarse-tuning stage and a fine-tuning stage. In
the coarse-tuning stage , the coarse-tuning delay chain wth 64-1 select-path
architecture is used to provide different delays for coarse tuning with a 300ps
52
step on the DCO period. To increase the frequency resolution, a fine-tuning
Figure 4.4: The DCO of an ADPLL for high-speed clock generation
delay cell is added after the coarse tuning stage. The fine-tuning Delay cell
consists of an AND-OR-INV (AOI) cell and an OR-AND-INV (OAI) cell as
shown in Fig 4.5. Both the AOI cell and the OAI cell are shunted with two
Figure 4.5: The fine tuning stage of the DCO
tri-state buffers. Shunted tri-state buffers can increase the controllable range
of the fine-tuning delay cell. The controllable range of the fine-tuning delay
cell should cover one coarse-tuning step (i.e., 300ps). In the fine-tuning delay
cell, six bits (EN1, A1, B1, EN2, A2, B2) can be controlled. Thus, in total 64
53
different delays can be used. After HSPICE simulation, the lookup table for
mapping the fine-tuning control code can be created. The DCO resolution can
be improved to about 5ps by adding a fine-tuning delay cell. Because the PFD
of this ADPLL only needs to detect the polarity of the phase error, digital pulse
amplifiers are used to minimize the dead zone of the PFD.
The measured RMS jitter and the peak-to-peak jitter are 7ps and 20ps respectively at 45MHz and are 22ps and 70ps at 450MHz.
4.2.2
A fast lock digital phase-locked loop
One of advantage of the digital PLL is that some advanced locking behaviors can
be achieved by changing the loop parameters and behaviors on the fly. A fast
phase lock DPLL is reported in [58] (similar approaches are found in [53] and
[59]) and its block diagram is shown in Fig 4.6. This DPLL employs both the
frequency comparator and phase detector. The frequency comparison is done
by initially aligning the DCO output to the reference edge and comparing the
Nth DCO transition edge with the next reference comparator produces signals,
slow or fast to indicate if the DCO frequency is lower or higher than the
desired frequency.
Like many other DCOs, the DCO in this ADPLL is based on a ring oscillator
and the tuning is achieved by changing both propagation delay of one signal stage
and total number of inverters. By changing the number of inverters, four modes
54
Figure 4.6: An all-digital PLL with small DCO hardware and fast phase lock
(frequency bands) are obtained. The propagation delay tuning is achieved by
tuning the current of the inverters as shown in Fig 4.7. Each inverter is cascaded
with 14 bit control MOS devices. The size ratios of the control devices are two
times as shown in the figure. The most significant control bit, bit 13, corresponds
to the largest control devices. According to the simulation, the least significant
bit resolution is 177ps when the most significant control bit (bit13) is asserted.
As a result, the DCO has four frequency bands and 214 frequency levels within
each band.
Figure 4.7: A digitally controlled delay cell for the DCO
55
A fast frequency/phase acquisition approach is used in this ADPLL and it

can finish both frequency/phase acquisitions with 47 reference cycles: at most
8 cycles are needed to find the correct mode/band, and at most 28 reference
cycles are need to acquire the frequency with a binary search method, further
more, at most 11 reference cycles are needed to achieve the phase acquisition.
After both the frequency and phase acquisitions are done, the digital PLL
still dynamically adjusts the phase-gain value to reduce the phase error. When
the phase polarity is changed, the phase-gain value is divided by two, and the
phase-gain is multiplied by two whenever the ADPLL detects eight consecutive
incremental changes in the same direction.
The implementation of this ADPLL requires 4026 transistors and with 923um
921um layout area in a TSMC 0.6um SPDM CMOS process. The ADPLL runs
up to 400MHz with a supply voltage of 3.3V.
4.2.3
An all-digital PLL clock multiplier
Another ADPLL clock multiplier, implemented in 0.35um standard CMOS process, operating from 152MHz to 366MHz, is reported in [60]. Fig 4.8 shows the
block structure of the all-digital PLL. The oscillator for this digital PLL is a
7 state ring oscillator with one inverter replaced by a NAND-gate for shutting
down the ring oscillator during idle mode. To change the frequency of the ring
oscillator, a set of 21 inverting tri-state gates are connected in parallel with each
56
Figure 4.8: An all-digital PLL clock multiplier

inverter. When the tri-state gates are enabled, additional current drive is added
to each inverter state. The 126 (21*6) tri-state gates are controlled by 126 bit
vector, which is decoded from a 7 bit control word. This tuning method guarantees the monotonic frequency tuning because adding current drive by enabling
a tri-state speeds up the oscillator. An advantage of this DCO is that it can be
made from all-standard cells. However, this DCO results relatively high power
consumption and nonlinearity.
The phase detector is a modified tri-state PFD and it produces one signal DIRECTION, showing the polarity of the phase error and one signal
EVENT showing the length of the phase error as shown in Fig 4.9. Another
signal UPDATE is a short Pulse at the end of each phase error, and it works
as a clock signal for the updating all registers in the TDC and the loop filter,
which is a digital recursive filter (as shown in Fig 4.8)
57
Figure 4.9: The PFD for an all-digital PLL clock multiplier
4.2.4
A phase-domain all-digital phase-locked loop
Another all-digital phase-locked loop is reported in [61], in which the DCO

phase is first digitalized and compared with a reference phase (R[K]) which is
also represented with digital signal. The bock diagram of this all digital PLL is
shown in Fig 4.10. The digital reference phase is provided by a accumulator. The
Figure 4.10: Phase-domain ADPLL-based frequency synthesizer
DCO phase is digitized at each reference edge. An oscillator phase accumulator

is used to count the DCO cycles to provide the integral part of the DCO phase.
A time to digital converter (TDC) [62] and a DCO period normalization circuit
are used to obtain the fractional part of the DCO phase. The integral part and
the fractional part are summed together and compared with the reference phase
58
with the phase detector, which is essentially a subtracter. The output of the
phase detector, is thus filtered by the digital loop filter and controls the DCO
after the DCO gain normalization.
The output frequency of this frequency synthesizer can be changed by changing the frequency control word, thus the reference phase (R[k]).
4.3
Architecture of the proposed ADPLL
The block structure of the new ADPLL is shown in Fig4.11. The DCO has 12bit binary weighted control word. Arithmetically incrementing or decrementing
the DCO control word modulates DCO frequency and phase. The control word
corresponding to the period of the reference clock Tref is stored in Reg1. In
Reg2, the control word corresponds to a new period of Tref TDelay , which is
the period of reference clock subtracted by the delay between DCO out and
DCO clock. Unlike the previous ADPLL designs, the clock signals to all the
logical blocks are generated from the DCO output. This ADPLL has 5 different
working status, which is controlled by the state machine as shown in the figure.
The detailed lock-in process will be discussed in the next part.
59
Figure 4.11: Architecture of the proposed ADPLL
4.4
Lock-in process of the proposed ADPLL
Phase lock begins with frequency acquisition. In this mode, a time-to-digital

converter measures the time difference between the reference clock and the DCO
clock. As shown in Fig4.12a, it converts time difference into the digital word T1
and T2 , which are respectively the time difference between DCO clocks rising
edge and the reference clocks rising and falling edges. As a result, the frequency
difference can be defined as follows:
T = (T1 T10 ) + (N 2)T /2
(4.2)
T = 2(T2 T1 )
(4.3)
N is the reference clocks low-to-high or high-to-low transition number during

one DCO clock period from a 4-bit counter. T10 is the stored value of T1 in the
previous DCO period.
60
Compared to other frequency acquisition approaches, the DCO dont need

to be reset at the beginning of every reference cycle for the initial phase alignment, which reduces the design complexity. Moreover, the frequency acquisition
process can be reduced to two or three cycles if the DCO has a good linearity
performance. However, as shown in Fig 4.12b, due to the non-zero setup time,
the last transition of reference clock may be ignored if the time difference T10 is
smaller than the registers setup time, which should be taken into consideration
in the counter design.
Figure 4.12: Principle of frequency acquisition
In phase acquisition, the DCO clock edge will be aligned to reference clock
edge. In practice, there are several stages of logic separating DCO output and
DCO clock such as the duty-cycle corrector in this paper. As a result, the DCO
clock edge cant be aligned to the reference clock by a simple reset process as
shown in Fig 4.13. The delay time TDelay results from the logic blocks between
DCO output and DCO clock. A phase acquisition process is required to get
the phase alignment, which is usually done by comparing the phase position
61
Figure 4.13: Failure in phase alignment due to logic blocks between DCO clock
and DCO output
of the two signals. The adjustment on the control word is made based on the
behind or ahead signal until there is a polarity change. However, such kind
of acquisition process needs to take many cycles, which results in a slow lock-in
process.
A unique reset process is present in this paper, which can reduce the phase
lock process into two cycles as shown in Fig 4.14.
In the first cycle, the DCO is still reset by reference clock with control word
corresponding to Tref e TDelay . The control word is found in a similar way as
mentioned in the frequency acquisition:
T = (T1 T10 ) + (N 2)T /2 + TDelay
(4.4)
Without the delay, the second rising edge will lead the reference clock by such as
62
Figure 4.14: A new phase acquisition process with two lock-in cycles
the DCO output. However, as for the DCO clock signal, this can be compensated
by the existing delay and the second rising edge will be aligned to the reference
clock. In the second cycle, the control word in register1 will be reloaded and
DCO frequency will be the same as reference clock again.
After the phase acquisition, a maintenance mode is applied to preserve the
phase alignment of DCO clock relative to reference clock. The phase detector
generates an ahead or behind signal based on the rising edges of the reference
clock and DCO clock. The ADPLL increments or decrements the control word
every cycle. The magnitude of change, which is the value held in the phase-gain
register is shifted to the left by 1 bit every cycle. When the polarity changes,
the control word and the phase gain will be reset to the initial value stored
during the frequency acquisition. The edge detector keeps comparing the phase
63
difference and updating the fine control bits in order to maintain the phase lock.
The fine resolution of the DCO as well as the bit shift strategy provides a fast
phase lock-in time and better jitter performance.
Chapter 5
Circuit Implement of The
Proposed ADPLL
5.1
Introduction
The architecture of the proposed ADPLL was presented in the previous chapter
and the lock-in process has been analyzed in detail. To further confirm loop
behavior and feasibility of the proposed ADPLL, the proposed ADPLL was
implemented in 32nm Practical Transistor Model WITH 0.9V supply voltage.
This chapter describes the CMOS implement of the key blocks in the proposed
ADPLL such as the digitally controlled oscillator, the time-to-digital converter,
and the state machine. The simulation result was presented at the end of this
chapter which proves the advantages of this new ADPLL design discussed in the
64
CHAPTER 5. CIRCUIT IMPLEMENT OF THE PROPOSED ADPLL
65
previous chapter.
5.2
Digitally controlled oscillator
The controlled oscillator is a key component in PLL, which is a replacement

of the conventional voltage or current controlled oscillator in the fully digital
PLLs. They are more flexible and usually more robust than the conventional
VCO. Furthermore, the design compromise for the frequency gain in voltage or
current controlled oscillator is not necessary in DCOs because the immunity of
their control input is very high. There are two main techniques for the DCO
design as shown in Fig 5.1. One technique changes the driving strength dynamically using the fixed capacitance loading [8], [9] while the other uses shunt
capacitor technique to tune the capacitance loading [10]. Although both of the
approaches have a good linear frequency response and a reasonable frequency
operating range, the power dissipation hasnt been taken into consideration.
Moreover, for the DCO design, there is a tradeoff between the operating range
and the maximum frequency that DCO can achieve. As a result, the increase
of the operating range by adding more capacitance loading will result in a lower
maximum frequency and higher power consumption. Since power consumption
is of extreme concern for portable battery charged computing systems, the reduction of the power consumption has become a major concern in modern electronic
systems.
66
Figure 5.1: Standard Cell of Digitally Controlled Oscillator. (a) Driving strength
controlled. (b) Shunt capacitance controlled
This paper proposes a novel DCO circuit with significantly reduced power
consumption using binary controlled pass transistors and Schmitt trigger inverters.
5.2.1
DCO principle and design
DCO should generate an oscillation period of TDCO, which is a function of

digital input word D and given by
TDCO = f (dn1 2n1 + dn2 2n2 + + d1 21 + d0 20 )
(5.1)
Typically, the DCO transfer function is defined such that the period of oscillation
TDCO is linearly proportional to D with an offset. Therefore, the oscillation
period is rewritten as:
TDCO = Tof f set D Tstep
(D : digital control bits)
(5.2)
67
Where Tof f set is a constant offset period and Tstep is the period of the quantization step. For the conventional driving strength controlled DCO shown in Fig
5.2, the constant delay of each cell is calculated as follows:
Figure 5.2: Equivalent circuit for the calculation of constant delay and delay
tuning range
Tconstant = R1 (C1 + C2 ) + R2 C2
(5.3)
R1,2 1/W1,2
(5.4)
Where R1 ,R2 are the equivalent resistances of M1 , and C1 ,C2 are the total
capacitances at the drain of M1 , , respectively, which mainly consist of drain to
body and source to body capacitances. Assuming they have the same driving
68
strength, the delay tuning range of this standard cell is obtained as follows:
R R
R
Ttune
= (C1 + C2 )(R1 //
//
// //
(C1 + C2 )R1
2
d0
d1 2
dn1 2n1
=
R1 (C1 + C2)
(C1 + C2 )R1
1 + (D W )/W1
R1 (C1 + C2 )
D W
D W
, (Only if
1)
W1
W1
(5.5)
(5.6)
(5.7)
In order to have a good linear tuning range, the width of the transistor M1
has to be increased as illustrated in Equation 4.7. Consequently the equivalent
resistance R1 will decrease, resulting in a smaller delay tuning range. One way
to increase the tuning range while keeping the linear response is to increase the
capacitance loading. However, this will minimize the maximum frequency that
the DCO can accomplish and the power consumption will also be increased.
5.2.2
Proposed DCO design
The proposed DCO employs a new approach to increase the delay tuning range
using digitally controlled pass transistor arrays and Schmitt trigger based inverters [15]. The Schmitt trigger based inverter has a higher VM+ (low to high
switching threshold) and lower VM- (high to low switching threshold) compared
to the conventional inverters as shown in Fig 5.3. As a result, the proposed
DCO circuit provides the same tuning range with a smaller capacitance loading,
69
which is beneficial for power consumption reduction. Moreover, in the conventional DCO circuit, the slope of the input signal to each stage decreases gradually
due to the large delay between each stage. This results in not only a non-ideal
rail-to-rail switch but also a poor power performance. The steep slope of the
output signal from the Schmitt trigger based inverter minimizes this problem to
a certain extend.
Figure 5.3: Delay comparison of Schmitt inverter and conventional inverter
The circuit diagrams of the conventional DCO and proposed DCO are shown
in Fig 5.4. The conventional DCO consists two identical binary controlled coarse
cells as well as a similar fine cell with smaller tuning range. The proposed DCO
also consists of two coarse cells and a fine cell. The coarse cells have tuning
codes of 4 bits with PMOS array or NMOS array in form of thermometer code,
which could provide a better duty cycle performance and linearity. The fine cell
has tuning codes of 6 bits by only NMOS array in the form of thermometer code
as shown in Fig 5.4c. The thermometer code minimizes the jitters. Since they
are grouped per 2 bits, the circuit to convert binary code to thermometer code
is also minimized.
70
(a)
(b)
(c)
Figure 5.4: Digitally Controlled Oscillator (a) Conventional DCO structure),

(b) Proposed DCO structure, (c) Fine delay cell
5.2.3
71
Improved structure with larger operating range
The binary controlled DCO structure has a limited linear operating range as
discussed above. In this work, three stage constant delay chains and a 4:1 Mux
are used to increase the operating range, and the three stage constant delay is
tuned by the fixed code such that each stage provides an accurate delay as shown
in Fig 5.5. As a result, the operating range can be four times larger compared
to the original design.
Figure 5.5: The proposed DCO structure with increased operating range
5.2.4
Comparison between the two DCO structures
The proposed DCO and the conventional DCO are simulated and compared
using 32nm CMOS PTM (Predictive Technology Model) with a supply voltage
of 0.9 Volts. The choice of 12 bits is a compromise between the DCO resolution,
operating range and circuit complexity.
Table4-1 shows the impact of each control bit on the period of the two DCO
structures. Both structures have the same linear tuning range. Since the two
72
DCO structure have the same operating ranges, it is more reasonable for us to
compare their power consumption.
Table 5.1: Impact of each control bit on the DCO period
Control Bits
111111
100000
010000
001000
000100
000010
000001
000000
The conventional DCO

Period (ns) Delta (ns)
1.8022
257.7
1.544.5
134.6
1.4099
69.8
1.3401
34.4
1.3057
19.8
1.2859
9.1
1.2768
9.2
1.2676
-
The proposed DCO

Period (ns) Delta (ns)
1.7918
270.6
1.5212
139
1.382
70.8
1.3114
36.8
1.2746
19.1
1.2555
9.4
1.2461
8.5
1.2376
-
Compared to the conventional DCO, the proposed DCO saves approximately

40% power consumption as shown in Fig 5.6. As discussed above, this reduction
Figure 5.6: Power consumption of the conventional and the proposed DCO
structures
is due to the comparatively smaller capacitance loading for the Schmitt trigger
based inverter than the conventional inverter at the same operating frequency.
The proposed DCO is significantly more power efficient than the conventional
DCO. However, this DCO design has a limited operating frequency range, which
is improved in this paper by employing the fixed delay blocks shown in Fig 5.6.
5.2.5
73
Simulation result Of the proposed DCO
The proposed DCO structure with increased operating range is designed and
simulated using 32nm PTM model. Fig 5.7 shows operating frequency ranges of
the coarse and fine tuning frequency of the novel DCO. The curves have good
monotonousness, which is a key factor in PLL performance. The frequency
ranges are about 570M Hz 800 MHz at the condition of 0.9V supply voltage at
25 C and the delay range of the fine delay chain is about 45ps. The characteristics of the proposed DCO are summarized at table4-2.
(a)
(b)
Figure 5.7: Operating range of the proposed DCO: (a) Coarse loop (b) Fine loop
74
Table 5.2: Performance of the proposed DCO

Items
Resolution
Max. DCO Gain
Avg. DCO Gain
Operating range
Power Consumption
Coarse Delay Fine Delay

6 bit
6 bit
10ps
1ps
7ps
0.7ps
570M Hz 800M Hz
2.2mW @650M Hz
The operational frequency response to the process, temperature and voltage

variation is shown in Fig 5.8. The curves show the normalized data with respected to the center frequency. Fig 5.8 shows that the relative delay per code
is almost same regardless of the process, temperature and voltage variations. In
other words, the proposed DCO design is very robust to PVT variations.
Figure 5.8: Delay characteristics of the coarse loop for the Process, Voltage and
Temperature variations. (a) Process variation, (b) Temperature Variation, (c)
Voltage Variation.
5.3
75
Time-to-digital converter
The TDC used in this paper is composed of two parts: an integer counter that
counts the reference clock edges within one DCO clock period and a fractional
counter that quantizes the residual phase difference, which helps to improve the
resolution of the proposed TDC.
The block diagram of the fractional TDC structure is shown in Fig 5.9. It
consists of 16 delay blocks and two types of independent decoders. The resolution of the TDC is the delay of a single buffer, which minimizes the delay
mismatch compared to the delay of a single inverter. The reference clock waveform propagates through a chain of 8 16 delay elements whose outputs are
sampled by 8 16 flip-flops at the rising edge of each DCO clock.
Figure 5.9: Block diagram of fractional TDC structure
The decoding process is shown in Fig 5.10. The 16 bits output of the delay
block are decoded into the higher 4 bits of T1 and T2 . At the same time, the 8
bits output of each delay block is also decoded into a series of lower 3 bits of
76
T1 and T2 . Based on the output of decoder1, the proper set of T1 (0 : 2) and

T2 (0 : 2) is selected. As is shown in Fig 5.9, the transition takes place in the 2nd
and 6th blocks. As a result, the decoded output of those two blocks is selected
as the lower 3 bits of T1 and T2 . The separation of the decoder into two parts
has greatly reduced the design complexity.
Figure 5.10: Decoding process of the TDC
5.4
State Machine
The state machine is the control unit of the proposed ADPLL, and it has five
different working statuses as shown in Table IV. It takes the reference clock and
DCO output as the input signals, and it outputs four-bit state signals such as
bit0, bit1, bit2, and bit3 as well as a DCO reset signal as shown in Fig 5.11.
77
In the initial 000 status, the control word corresponding to Tref is stored in
register1. After that the lock indicator generates a high voltage signal and ADPLL switches to 001 status. The delay between DCO output and DCO clock
TDelay will be measured by resetting the DCO using reference clock. Counter2 is
used to make sure the reset process only takes two cycles and it will be cleared
after that. In 010 status, a new control word corresponding to TRef TDelay
is stored in register2 and the corresponding lock indicate signal will switches
the status to 011. Then, the reset process will restart again with the control
word corresponding to TRef TDelay and TRef in the first two cycles, respectively.
After that, the ADPLL goes into the maintenance mode and the state machine
will be locked. The five consecutive statuses ensure a fast lock-in and low jitter
ADPLL design.
Figure 5.11: Block diagram of the state machine
5.5
78
Simulation result of the proposed ADPLL
The proposed APDLL structure is designed and simulated using 32nm CMOS
Predictive Transistor Model. The resolution of the TDC, which is the delay of
a single buffer used in the delay chain, is 20ps. The 12 bit digitally controlled
oscillator has a coarse resolution close to 10ps and fine resolution close to 1ps
with a tuning range from 570 MHz to 800 MHz.
(a)
(b)
(c)
(d)
Figure 5.12: Lock-in process of the proposed ADPLL. (a) Lock process of the
ADPLL with five different statuses from 000 status to 100 status, (b) Frequency acqusiton at TDCO =TRef during 000 status, (c) Frequency acqusition
at TDCO = TRef TDelay during 010 status, (d) Phase acqusitoin process
during 011 status.
The lock-in process of the proposed ADPLL is illustrated in Fig 5.12 when
locking to 700MHz.The output of the state machine ensures five consecutive
79
statuses during the lock-in process as shown in Fig 5.12(a). Two-frequency lockin processes are completed during 000 status and 010 status respectively and
the corresponding control word are stored in register 1 and 2 as shown in Fig
5.12(b, c). The phase lock-in process takes 2 clock cycles, as in Fig 5.12(d). As
a result, the whole lock-in process takes about 10 reference cycles.
Fig 5.13 shows the DCO jitter performance after acquisition. As can be seen
here, this ADPLL achieves a peak-to-peak jitter of 67 ps at 700 MHz. There
are around 15 reference cycles in this eye diagram due to the limited disk space
and simulation time.
Figure 5.13: Output clock jitter (DCO @ 700MHz)
Chapter 6
ADPLL Based Fractional-N
Frequency Synthesizer
Digital Phase locked looped based frequency synthesizers have been used in applications requiring either agile frequency switching or high-precision frequency
control. An unavoidable occurrence is that frequency multiplication (by N),
raises the signals phase noise by 20Log (N) dB. By reducing the value of N, we
could racially reduce the phase noise of the system. However, the channel spacing of an integer-N synthesizer is dependent on the value of N. A fractional-N
frequency synthesizer has benefits compared with classical integer-N implementations. It is accomplished by adding internal circuitry that enables the value
of N to change dynamically during the locked state.
Although fractional-N frequency synthesizer could achieve better phase noise
80
CHAPTER 6. ADPLL BASED FRACTIONAL-N FREQUENCY SYNTHESIZER81

performance, faster lock and better spur levels, it also generates fractional spurs
from the fractional divider. By introducing control in the feedback divider,
fractional spurs can be eliminated. In this case, fractional spurs are spread
over the spectrum and become quantization noise which is shaped by the
modulator to high frequencies. A low pass filter with 1 order higher than that
of the delta-sigma modulator is used to filter out the high frequency noise. This
approach is efficient but might not lead to complete elimination of spurs, since
a delta-sigma modulator can generate spurs by itself due to idle tones. Pseudo
random sequences can be mixed with the delta modulator input to reduce the idle
noise, but this will incorporates additional hardware. Another way to suppress
fractional spurs is to reduce the bandwidth, but this result in degradation of the
noise and an increase of the lock time.
In this paper an all digital phase locked loop based fractional-N frequency
synthesizer is presented.different from the conventional fractional-N frequency
synthesizer, an extra TDC is applied to obtain the fractional value avoiding
the use of fractional divider, which is the main source of fractional spur in a
fractional-N frequency synthesizer. The proposed Fraction-N frequency synthesizer is implemented using Predictive Technology Model (PTM) at 0.9V supply
voltage.
6.1
Fractional-N division scheme
Since the output frequencies of the simple integer-N PLL are the integer multiples of the reference frequency, this type of frequency multiplication results in
increased noise at the PLL output, i.e., the noise of the reference input signal
appears at the synthesizer output is amplified by a factor of 20log(N) dB. As an
example, the noise floor will be increased 80dB for N=10,000. This is due to the
fact that the reference frequency is equal to the channel space frequency for the
integer-N type synthesizers. Thus the loop bandwidth should be kept small to
improve in-band phase noise performance at the cost of lock time. A fractionalN technique can reduce the phase noise by increasing the reference frequency,
and use fractional portions of the reference frequency and hence reducing the
value of N used in integer-N dividers. Fig 6.1 shows a simplified block diagram
Figure 6.1: Typical fractional-N divider scheme.

of a typical fractional-N divider. For example, similarly from the dual-modulus
scheme, but over F reference cycles, the total division ratio is given by
[K(N + 1) + N (F K)]/F = (N F + K)/F = N + K/F
(6.1)
where F is the fractional resolution. Therefore, the VCO output frequency is

the reference frequency times (N+K/F). For 200 KHz channel spacing with a
fractional resolution of 16 (4 bit accumulator), the reference frequency can now
be 3.2 MHz and N is reduced by the factor of 16. For example, to generate a
signal of 902.6 MHz, the division ratio will be 4513 with the integer-N divider.
With the fractional-N divider, K=1,F=16, and since the reference frequency will
be 3.2 MHz, the division ratio becomes 282 so that 3.2 MHz(282+1/16)=902.6
MHz. Thus, the division ratio is reduced by the factor of 16(=4513/282). However, fractional division schemes suffer from spurious tones, called fractional
spurs, at the frequency components of
Ff ractionalspurs = Fref
K
, K = 1, 2, 3
F
(6.2)
The fractional spurs are due to the periodicity of the divider modulus control.
Therefore, if the divider modulus can be controlled in a random fashion, the
periodicity can be removed and hence these fractional spurs can be suppressed.
The states of the accumulator can be used for spur-tone suppression by a DAC

that performs phase estimation.
6.2
Fractional spur analysis in conventional fractionalN frequency synthesizer
As discussed in section 6.1, the fractional-N frequency synthesizer can both

generate a high frequency signal with a well-defined frequency and modulate
that signal. The block diagram of a conventional fractional- synthesizer is shown
in Fig 6.2. This structure is very similar to integer-N frequency synthesizer with
the additional of an accumulator. The accumulator is a simple state machine
that changes the main divider value (between N and N+1) during a locked
condition.
Figure 6.2: Conventional fractional-N synthesizer.
By varying the divider number between N and N+1 dynamically, a fractional

divide ratio can be obtained. However, even though a VCO is locked into a
desired frequency, there always exists a phase error or noise at most of comparing

instants due to the uneven division. If out of 2k cycles, we divide by N+1 p times
and by N, 2k p, then average output frequency will be:
Fout = (N + p/2k )fref
(6.3)
where p and k are the fractional parts and the number of the bits of the accumulator.
Similar to the analysis in [63], within one reference cycle, the phase difference
DeltaT between the reference signal and divided output should be:
T =
1
fref
fdiv
p
Tout
2k
(6.4)
At the nth reference cycle, the corresponding phase difference Tn should be:
Tn = b
pn
cTout
2k
(6.5)
bcrepresents the fractional part of the quantity inside (less than 1). Assume
the average phase shift of the divided output to be . In fractional-N frequency
synthesizer, the average control voltage Vctrl should be a constant value. As a
result, the average current of the charge pump should equal to 0 and we get:
Q1
Icp
X
n=0
(Tn ) = Icp
Q1
X pn
(b k cTout ) = 0
2
n=0
(6.6)

Therefore,
Q1
1 X pn
b cTout
=
Q n=0 2k
(6.7)
Q Tout is the time period of the charge pump output current. The pulse position
and pulse width of this periodic current signal can be calculated as following:
pp (n) = (n Tref +
Tn
)
2
pw (n) = ( Tn )
(6.8)
(6.9)
The Fourier series coefficient of each current pulse is:
Cn,k =
1
Tn
1
sin[kwQ ( Tn )] exp[ikwQ (nTref +
)]
k
2
2
wQ =
2
QTout
k = 0, 1, , Q 1
(6.10)
(6.11)
(6.12)
By adding the corresponding Fourier series coefficients of each current pulse

together, we get the Fourier series of the charge pumps output current pulse
noise. This phase noise generated by the fractional divider can be modeled as
if it were an autonomous phase noise source with a special spectral property
and the output frequency spectrum can be calculated through the closed loop
transfer function. The normalized power of the charge pump output current

pulse noises Fourier series components k is shown in Fig 6.3.
Figure 6.3: Normalized Fourier series of the current pulse.
6.3
Spur Suppression Techniques
As discussed in section 6.2, the use of the fraction-N technique introduces periodic disturbances in the loop, resulting in larger spurious modulation of the carrier. Since the generated spurs can fall inside the loop bandwidth, the fractionalN frequency synthesis techniques are not practical unless in-band spurs are suppressed to a negligible level. Another minor penalty is this: the use of higher
reference frequency requires higher complex system operating with the reference frequency, which means higher power dissipation. Several spur suppression
techniques in a fractional-N synthesis will be discussed in this section.
6.3.1
Spur suppression using DAC phase estimation technique
The instantaneous information contained in the accumulator of a fractional-N

synthesizer is equivalent to the phase error. This useful fact prompted one of
the earliest methods to solve the problem of the fractional spurs. The idea is to
generate a properly scaled analog compensating voltage from the information of
the spurious beat tone contained in the accumulator, using a digital-to-analog
converter (DAC), and apply it directly to the control input of the VCO in order
to perform an exact compensation for the phase error produced by the fractionalN synthesis process. The technique is shown in Fig 6.4. Since the phase error
Figure 6.4: Spur compensation by a DAC.
is subtracted in the voltage domain, this technology suffers from analog imperfections. The mismatch results primarily from limited DAC resolution and the
limited accuracy of the DAC. So the amount of spurious suppression is limited a
few tens of dB [64]. Furthermore, this method becomes more difficult to implement, as the reference frequency gets higher, because of the relatively stringent

requirements that the correcting DAC would need to satisfy in terms of short
response time. Also, a precision DAC and some supporting circuitry increase
power consumption. Thus, this approach has not been applied to high-frequency
RF synthesizers in recent years.
6.3.2
Spur suppression using random jittering technique
Random jittering was used to compensate the phase error generated in the loop
in digital domain. As discussed earlier, the spurs in the fractional-N synthesizer
originate from the periodic change in the divider ratio of the dual-modulus
prescaler. The periodicity in the control sequence of the dual-modulus divider
can be eliminated by injecting random jitter. While the compensation technique
using a DAC operates in the analog domain, this technique reduces the spurs
in the digital domain. Shown in Fig 6.5 is a block diagram of a fractionalN synthesizer with random jittering [65]. At every output of the divider, the
Figure 6.5: Fractional-N synthesize with random jittering.
random or pseudo-random number generator produces a new random word, Pn ,

which is compared with the frequency work, k. If Pn is less than k, a divider-by
N is performed, and if Pn is greater than k, a divide-by N+1 is performed. The
frequency word controls the divider ratio N or N+1 such that the average value
can track the desired fractional division ratio.
The random jittering process generates a relatively high noise floor because
the injected phase jitter is white. It also suffers from frequency jitter because
white noise injected in the frequency domain results in
1
f2
noise in the phase
domain. Since the PLL acts as a low-pass filter for jitter generated by the
fractional-N divider, the low-frequency components of the jitter will pass through
the loop and degrade the in-band phase noise in the synthesized signal.
6.3.3
Spur suppression using noise shaping technique
The noise shaping technique using modulator[66], as shown in Fig 6.6, has
recently received a lot of attention as an approach to spurious suppression. The
basic idea of the noise shaping technique is to reshape the spectrum of the
interfering noise such that its power within the useful signal band becomes very
much smaller. Usually, though, this comes at the price of having to suffer a much
bigger noise power than normal somewhere outside the signal band. When this
is combined with a narrow-band filtering, the output signal has a significantly
improved in-band signal to noise ratio. Similarly, in the context of a fractional-N
synthesis, the phase error spectrum is transformed so that the close-in spurious

tones are pushed further away from the carrier to make them easy to suppress
by the PLL loop filter.
Figure 6.6: Fractional-N synthesis with modulation.
This noise-shaping technique is commonly used in high resolution ADC.

frequency synthesizers are a directly extension to the technique used in the
modulators. Again the idea here is to get rid of the low frequency phase error
by rapidly switching the divider ratio between different ratios to eliminate the
gradual phase error at the PFD input. By changing the divider ratio rapidly
between different values, the phase error occurs in both polarities, positive as
well as negative, and in an accelerated rate that explains the phenomena of high
frequency noise push-up. This noise, which is converted to a voltage by the PFD
and the loop filter, is then filtered out by the low-pass filter.
The problem associated with the noise-shaping technique is that the noise
power rise rapidly with frequency. For a third -order modulator, the noise increases at a rate of 40dB/dec. To take full advantage of the noise shaping
technique, the PLL loop bandwidth has to be much smaller than the sampling
frequency, which is the reference frequency. This is obviously poses a serious

limitation on the prospect of using wide-band loops for maximum VCO phasenoise suppression. When high order modulators are used for fractional-N
divider controller, the PLL needs more poles in the loop filter to suppress the
quantization noise at high frequencies.
6.3.4
Spur suppression using phase interpolation technique
The fact that an M-stage ring oscillator produces M different phases can be
utilized to implement a fractional divider, which is known as phase interpolation
technique[67]. Combining a fixed divider N with phase interpolation from a ring
oscillator allows for an N.f fractional division. An implementation of this type
of fractional divider is shown in Fig 6.9. Since the number of inverters in a
ring oscillator is limited by the operating frequency, phase interpolator should
be used to generate finer phases from limited phase available from the VCO. By
choosing the correct phase among the interpolated phases, a desired fractional
division ratio is achieved.
Figure 6.7: Phase interpolated fractional-N synthesis.
6.4
Proposed ADPLL based fractional-N frequency synthesizer
The concept of the digital phase locked loop has existed almost as long as the
PLL itself and has been widely used in clock synthesis and data recovery application. However, the conventional DLL based fractional-N frequency synthesizer
suffers from the spur as discussed in section 6.2. In ultra-scaled technologies,
the ADPLL, which has replaced all the analog components with purely digital
equivalents, is becoming more attractive. The output frequency in fractional-N
designs is given by
fDCO = fREF (N + K/F )
(6.13)
The F is the fractional resolution of the device with respect to the reference
frequency. In the time domain, we can rewrite the equation as follows:
TREF = (N + K/F )TDCO
Without taking into consideration the fractional part,
(6.14)
K
T
,
F DCO
the proposed
architecture is an integer-N frequency synthesizer. The fast lock-in process of a

similar structure has been discussed in chapter IV. A time-to-digital converter
measures the time difference between the reference clock and the divided DCO
output. As shown in Fig 6.7, it converts time difference into the digital word T1

and T2 , which are the time difference between the divided DCO outputs rising
edge and the reference clocks rising and falling edges, respectively. As a result,
Figure 6.8: Principle of an integer-N frequency synthesizer lock-in process.

the frequency (period) difference can be defined as follows:
T = TREF T DCO = (T1 T10 ) + (M 2)T /2
(6.15)
T = 2(T2 T1 )
(6.16)
M represents the reference clocks low-to-high or high-to-low transition number

during one DCO clock period from the 4-bit counter. T10 is the stored value of
T1 in the previous DCO period.
In conventional fractional frequency synthesizer design, the integer divider is
usually replaced by a fractional one. Although the PLL has generated the correct
average phase slope to lock to the fractional channel, it has done so via abrupt
changes in the phase slope that must be quantized in integer multiples of 2.
This spur will be of greater magnitude than a typical reference spur and also
reside on the adjacent channels in worst case channel settings. The proposed

ADPLL based fractional-N frequency synthesizer uses an extra TDC to calculate
the fractional part,
K
T
,
F DCO
as shown in Fig 6.9. The fractional division can be
replaced by a multiplication function and equation 6.15 can be rewritten as
T = (T1 T10 ) + (M 2)T /2 +
K
TDCO
F
(6.17)
Since the phases are not aligned in fractional-N PLL, the phase acquisition process is not required here. During the frequency acquisition, TDC 1 compares
the frequency difference between the reference clock Ref and the divided output
DCO clock
.
N
At the same time, TDC 2 calculates the current DCO output fre-
quency TDCO and multiply it by the fractional factor
K
.
F
As a result, when the
DCO is locked into the desired frequency, there is no spur noise resulted from
the uneven divider anymore. The proposed design provides a low spur and fast
lock-in solution to the fractional-N frequency synthesizer design.
Figure 6.9: Proposed ADPLL based fractional-N frequency synthesizer.
6.5
Measurement Results
The proposed APDLL based fractional-N frequency synthesizer is designed and

simulated using 32nm CMOS Predictive Transistor Model (PTM). The target
spec used for the example design is as the following: Integer part of division, N
is 2, and reference frequency is 300MHz. The effective division ratio is 2.125.
The reference and VCO waveforms in locked state are plotted in Fig 6.10. The
Figure 6.10: Reference and VCO waveforms in locked state.
frequency acquisition time is 6 cycles. In this figure, 17 cycles of the DCO output
signal has same duration of the 8 cycles of the reference signal. This indicates
that the theoretical frequency division ratio of 2.125 is achieved.
The frequency spectrums of DCO output and reference signal are shown in
Fig 6.11. dBc is decibels relative to the carrier. Since the reference clock and
DCO output are both square wave signals, they have a series of harmonic signals
to the carrier signals as shown in Fig 6.11a and c. From the frequency spectrum
as shown in Fig 6.11d, the spurious signal is not obvious as the conventional

fractional-N PLL.
Figure 6.11: Frequency spectrum of DCO output and reference signal. (a) FFT
analysis of reference signal, (b) Frequency spectrum of reference signal (c) FFT
analysis of DCO output (d) Frequency spectrum of DCO output.
Chapter 7
Conclusion
This research focuses on the analysis and design of low noise, low power and high
resolution all digital phase locked loop. Using the theory and circuits developed,
a fully digital fractional-N frequency synthesizer prototype is designed in 32nm
PTM technology. Efforts have been put on the new design of phase acquisition
process, digitally controlled oscillator, and time to digital converter. Several key
research contributions are highlighted below:
1. It is demonstrated the proposed ADPLL is able to operate from 500MHz
to 800 MHz. A unique frequency and phase acquisition process is presented.
The proposed ADPLL is able to lock-in the phase within less than 10 reference
cycles.
2. A 12-bit digitally controlled CMOS oscillator design for low power consumption and low jitter is presented with coarse resolution of 10 ps and fine
98
CHAPTER 7. CONCLUSION
99
resolution of 1 ps.
3. A custom time-to-digital converter (TDC) with two separate encoders
is designed with a resolution of 20ps. The frequency difference between the
reference clock and DCO output is encoded into a 7 bit digital word.
4. An all digital fractional-N frequency synthesizer, which has a better jitter performance by replacing the fractional divider with an additional TDC, is
presented based on the proposed the ADPLL.
Bibliography
[1] I. Hwang, S. Lee, S. Lee, and S. Kim, A digitally controlled phase-locked
loop with fast locking scheme for clock synthesis application, ISSCC Dig.
Tech. Papers, pp. 168-169, Feb. 2000.
[2] D. W. Boerstler, A low-jitter PLL clock generator for microprocessors
with lock range of 340-612 MHz, IEEE J. Solid State Circuits, vol. 34, pp.
513-519, Apr. 1999.
[3] V. R. von Kaenel, A high-speed low-power clock generator for a microprocessor application, IEEE J. Solid State Circuits, vol. 33, pp. 1634-1639,
Nov. 1998.
[4] P. Larsson, A 2-166 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction,
in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 356-357.
[5] I. Young, J. K. Greason, and K. L. Wong, A PLL clock generator with 5 to
110 MHz of lock range for microprocessors, IEEE J. Solid-State Circuits,
vol. 27, pp. 1599-1607, Nov. 1992.
[6] R. E. Best, Phase-Locked Loops, Theory, Design and Applications, New
York: McGraw-Hill, 1993, 2nd ed
[7] R. Shaiatdoust, K. Nagaraj, M. Saniski, and J. Plany, A low jitter 5 MHz
100
BIBLIOGRAPHY
101
to 180 MHz clock synthesizer for video graphics,Proceedings of the IEEE

Custom Integrated Circuits Conference, pp. 24.2.1-24.2.5, May 1992.
[8] A. Young, J. K. Greason, and K. L. Wong, A PLL clock generator with 5
to 10 MHz of lock range for microprocessors, IEEE Journal of Solid-State
Circuits, vol. 27, no. 11, pp. 1599-1607, November 1992.
[9] K. L. Wong, E. Fayneh, E. Knoll, R. H. Law, C. H. Lim, R. J. Parker, F.
Wang, and C. Zhao, Cascaded PLL design for a 90nm CMOS high performance microprocessor, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 422-504, February 2003.
[10] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas,
Self-biased high-bandwidth low-jitter l-to-4096 multiplier clock generator
PLL, IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803,
November 2003.
[11] H. Huh, Y. Koo, K. Y. Lee, Y. Ok, S. Lee, D. Kwon, J. Lee, J. Park, K. Lee,
D. K. Jeong, and W. Kim, A CMOS dual-band fractional-N synthesizer
with reference doubler and compensated charge pump, in IEEE Int. SolidState Circuits Conf., pp. 100-101 Feb 2004.
[12] S. Cheng, H. Tong, J. S. Martinez, and A. I. Karsilayan, Design and
analysis of an ultrahigh-speed glitch-free fully differential charge pump with
minimum output current variation and accurate matching, IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, pp. 843-847, Sep. 2006.
[13] Che-Fu Liang, Shin-Hua Chen, and Shen-Iuan Liu, A Digital Calibration
Technique for Charge Pumps in Phase-Locked Systems, IEEE Journal of
Solid- State Circuits, vol. 43, no. 2, pp. 390-398, Feb 2008.
[14] R. Staszewski, K. Muhammad, D. Leipold, C. Hung, Y. Ho, J. Wallberg,C. Fernando, K. Maggio, R. Staszewski, T.Jung, J. Koh, S. John,
BIBLIOGRAPHY
102
I. Deng,V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman,

O. Eliezer,E. de Obaldia, and P. Balsara, All-digital TX frequency synthesizer anddiscrete-time receiver for Bluetooth radio in 130-nm CMOS,
IEEE Journalof Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, December 2004.
[15] J. L. Sonntag and J. Stonick, A digital clock and data recovery architecture
for multi-gigabit/s binary links, IEEE Journal of Solid-State Circuits, vol.
41, no. 8, pp. 1867-1875, August 2006.
[16] B. Murmann, Digitally assisted analog circuits, IEEE Micro, vol. 26, no.
2, pp. 38-47, March-April 2006.
[17] D. W. Boerstler, A low-jitter PLL clock generator for microprocessors with
lock range of 340 612 MHz, IEEE Journal of Solid-State Circuits, vol. 34,
no. 4, pp. 513-519, April 1999.
[18] H. Sutoh, K. Yamakoshi, and M. Ino, A 0.25 fim CMOS/SIMOX PLL
clock generator embedded in a gate array LSI with 5 to 400 MHz lock
range, Proceedings of the IEEE Custom Integrated Circuits Conference,
pp. 41-44, May 1997.
[19] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in
Deep-Submicron CMOS. Wiley-Interscience, 2006.
[20] D. W. Boerstler and K. A. Jenkins, A phase-locked loop clock generator
for a 1 GHz microprocessor, IEEE Symposium on VLSI Circuits, Digest
of Technical Papers, pp. 212-213, June 1998.
[21] J. G. Maneatis, Low-jitter process-independent DLL and PLL based on
selfbiased techniques, IEEE Journal of Solid-State Circuits, vol. 31, no.
11, pp. 1723-1732, November 1996.
BIBLIOGRAPHY
103
[22] S. B. Anand and B. Razavi, A 2.75 gb/s CMOS clock recovery circuit with
broad capture range, IEEE International Solid-State Circuits Conference,
Digest of Technical Papers, pp. 214-215,448, February 2001.
[23] J. Lee and B. Kim, A low-noise fast-lock phase-locked loop with adaptive
bandwidth control, IEEE Journal of Solid-State Circuits, vol. 35, no. 8,
pp. 1137-1145, August 2002.
[24] B. Razavi, A 2-GHz 1.6-mw phase-locked loop, IEEE Journal of SolidState Circuits, vol. 32, no. 5, pp. 730-735, May 1997.
[25] M. Mansuri and C.-K. K. Yang, A low-power adaptive bandwidth PLL and
clock buffer with supply-noise compensation, IEEE Journal of Solid-State
Circuits, vol. 38, no. 11, pp. 1804-1812, November 2003
[26] J. Lee and B. Razavi, A 40-Gb/s clock and data recovery circuit in 0.18/xm CMOS technology, IEEE Journal of Solid-State Circuits, vol. 38, no.
12,pp. 2181-2190, December 2003.
[27] C. Cao, Y. Ding, and K. K. O, A 50-GHz phase-locked loop in 0.13-um
CMOS, IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 16491656,August 2007.
[28] R. C. H. van de Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M.
Klumperink, and B. Nauta, A 2.5-10-GHz clock multiplier unit with 0.22
ps RMS jitter in standard 0.18-um CMOS, IEEE Journal of Solid-State
Circuits, vol. 39, no. 11, pp. 1862-1872, November 2004.
[29] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H. C.
Luong, A lv 24GHz 17.5mw PLL in 0.18-um CMOS, IEEE International
Solid-State Circuits Conference, Digest of Technical Papers, pp. 158-590,
February 2005.
BIBLIOGRAPHY
104
[30] G. Buren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, and H. Jackel,

A combined dynamic and static frequency divider for a 40GHz PLL in
80nm CMOS, IEEE International Solid-State Circuits Conference, Digest
of Technical Papers, pp. 598-599, February 2006.
[31] J. Kim, J.-K. Kim, B. Lee, N. Kim, D. Jeong, and W. Kim, A 20-GHz
phase-locked loop for 40-gb/s serializing transmitter in 0.13-um CMOS,
IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 899-908, April
2006.
[32] J. Lee, M. Liu, and H. Wang, A 75-GHz phase-locked loop in 90-nm
CMOS technology, IEEE Journal of Solid-State Circuits, vol. 43, no. 6,
pp. 14141426, June 2008.
[33] T. Watanabe and S. Yamauchi, An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time, IEEE Journal of Solid-State
Circuits, vol. 38, no. 2, pp. 198-204, February 2003.
[34] J. Lin, B. Haroun, T. Foo, J. Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, and J. Kirkpatric, A PVT tolerant 0.18MHz to 600MHz
selfcalibrated digital PLL in 90nm CMOS process, IEEE International
February 2004.
[35] T. Olsson and P. Nilsson, A digitally controlled PLL for SoC applications,
IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
[36] P.-Y. Wang, H.-W. Kao, Y.-Y. Lin, M.-T. Yang, J.-B. Yang, H.-J. Hsieh, Y.
Cheng, C.-Y. Chen, and J.-S. Pan, DLL-based clock recovery in a PRML
channel, IEEE International Solid-State Circuits Conference, Digest of
Technical Papers, pp. 570-618, February 2005.
BIBLIOGRAPHY
105
[37] V. Kratyuk, P. K. Hanumolu, K. Ok, K. Mayaram, and U.-K. Moon, A

digital PLL with a stochastic time-to-digital converter, IEEE Symposium
on VLSI Circuits, Digest of Technical Papers, pp. 31-32, June 2006.
[38] D.-H. Oh, D.-S. Kim, S. Kim, D.-K. Jeong, and W. Kim, A 2.8gb/s alldigital cdr with a 10b monotonic DCO, IEEE International Solid-State
Circuits Conference, Digest of Technical Papers, pp. 222-598, February
2007.
[39] V. Kratyuk, P. K. Hanumolu, K. Mayaram, and U.-K. Moon, A 0.6GHz
to 2GHz digital PLL with wide tracking range, Proceedings of the IEEE
Custom Integrated Circuits Conference, pp. 305-308, September 2007.
[40] J. A. Tierno, A. V. Rylyakov, and D. Friedman, A wide power supply
range, wide tuning range, all static CMOS all digital PLL in 65nm SOI,
IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 42-51, January
2008.
[41] P. K. Hanumolu, G.-Y. Wei, and U.-K. Moon, A wide-tracking range clock
and data recover circuit, IEEE Journal of Solid-State Circuits, vol. 43, no.
2, pp. 425-439, February 2008.
[42] A. Rylyakov, J. Tierno, D. Z. Turker, J.-O. Plouchart, H. A. Ainspan, and
D. Friedman, A modular all-digital PLL architecture enabling both 1-to2GHz and 24-to-32GHz operation in 65nm CMOS, IEEE International
February 2008.
[43] A. Rylyakov, J. Tierno, H. Ainspan, J.-O. Plouchart, J. Bulzacchelli, Z.
T. Deniz, and D. Friedman, Bang-bang digital PLLs at 11 and 20GHz
BIBLIOGRAPHY
106
with sub-200fs integrated jitter for high-speed serial communication applications, IEEE International Solid-State Circuits Conference, Digest of
Technical Papers, pp. 94-95, February 2009.
[44] H. T. Nicholas and H. Samueli, A 150-MHz direct digital frequency synthesizer in 1.25-m CMOS with -90-dB spurious performance, IEEE Journal
of Solid-State Circuits, vol. 26, no. 12, pp. 1959C1969, December 1991.
[45] P. H. Saul and M. S. J. Mudd, A Direct Digital Synthesizer with 100MHz
Output Capability, IEEE Journal of Solid-State Circuits, Vol. 23, No. 3,
pp. 819-821, Jun. 1998
[46] Charles G. Ekroot and Stephen I. Long, A GaAs 4-bit Adder-Accumulator
Circuit for Direct Digital Synthesis, IEEE Journal of Solid-State Circuits,
Vol. 23, No. 2, pp. 573-580, Apr. 1998
[47] Akihiro Yamagishi, A 2-V, 2-GHz Low-Power Direct Digital Frequency
Synthesizer Chip-Set for Wireless Communication, IEEE Journal of SolidState Circuits, Vol. 33, No. 2, pp. 210-217, Feb. 1998
[48] Avanindra Madisetti, Alan Y. Kwentus, and Alan N. Willson, A 100MHz,
16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free
Dynamic Range, IEEE Journal of Solid-State Circuits, Vol. 34, No. 8, pp.
1034-1043, Aug. 1999
[49] Yan Shing Tak, A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency
Synthesizer for GSM Receiver, Master Thesis, Dept. of Electrical and Electronic Engineering, Hong Kong University, Nov. 1999
[50] Abdellatif Bellaouar, Low-Power Direct Digital Frequency Synthesis for
Wireless Communications, IEEE Journal of Solid-State Circuits, Vol. 35,
No. 3, pp. 385-390, Mar. 2000
BIBLIOGRAPHY
107
[51] Thomas Olsson and Peter Nilsson, A digitally controlled PLL for SoC
application, IEEE J. Solid-State Circuits, vol. 39, pp 751-760, May 2004.
[52] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee,
P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, All-digitalPLL
and GSM/EDGE transmitter in 90 nm CMOS, in Proc. IEEE Solid-State
Circuits Conf., Feb. 2005, pp. 316-317.
[53] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phaselocked loop with 50-cycle lock time suitable for highperformance microprocessors, IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995.
[54] J. Kim, Design of CMOS adaptive-supply serial links, Ph.D. dissertation,
Stanford University, 2002.
[55] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 124-127, June
2000.
[56] In-Chul Hwang, Sang-Hun Song, and Soo-Won Kim, A digitally controlled
phase-locked loop with a digital phase-frequency detector for fast acquisition, IEEE J. Solid-State Circuits, vol. 36, pp. 1574-1581, Oct. 2001.
[57] C.C.Chung, C.Y.Lee,An all-digital phase-locked loop for high-speed clock
generation, IEEE Journal of Solid-State Circuits, vol.38. No.2, Feb.2003,
pp:347-351.
[58] J.S.Chiang,K.Y.Chen, The design of an all-digital phase-locked loop with
small DCO hardware and fast phase lock, IEEE Transactions on Circuits
and Systems II:Analog and Digital Signal Processing, Vol.46, Issue 7, July
1999, pp:945-950.
BIBLIOGRAPHY
108
[59] S.J.Jou, Y.L.Tsao, I.Y.Yang,An all digital phase-locked loop with modified
binary search of frequency acquisition, IEEE International Conference on
Electronics, Circuits and Systems, 1998, Vol.2, pp:195-198.
[60] T.Olsson, P.Nilsson,An all-digital clock multiplier, Proceedings of IEEE
Asia-pacific Conference on ASIC 2002. pp:275-278.
[61] R.B.Staszewski,D.Leipold,K.Muhammad and P.T.Balsara, Digitally Controlled Oscillator(DCO)-Based Architecure for RF Frequency Synthesis in a
Deep-Submicrometer CMOS Process, IEEE Transactions on Circuits and
System-II, Vol.50, No11. November 2003. pp:815-828.
[62] R.B.Staszewski,D.Leipold,C.M.Hung,P.T.Balsara, TDC-based frequency
synthesizer for wireless applications, IEEE Radio Frequency Integrated
Circuits Synposium, 2004, pp 215-218.
[63] Fan Yiping, Modeling and simulation of Frequency Synthesizer, IEEE
International Symposium on Industrial Electronics. Pusan, South Korea:
IEEE, 2001. pp 684-689
[64] U.L.Rohde, Digital PLL Frequency Synthesizers: Theory and Design,
Prentice-Hall, Englewood Cliffs, NJ, 1983
[65] T.A.D.Riley, M.A.Copeland, and T.A. Kwasniewski,Delta-Sigma Modulation in Fractional-N Frequency Synthesis, IEEE J. of Solid-State Circuits,
vol.28, no.5, pp.553-559, May 1993.
[66] M.H.Perrott,et al,A 27mW CMOS Fractional-N Synthesizer/Modulator
IC, ISSCC Digest of Technical Papers, pp.366-367,1997.
[67] P.R.Grey and R.G. Meyer,Future Directions in Silicon ICs for RF Personal
Communications, IEEE Custom ICs Conf., pp. 6.1.1-6.1.8,1995

A Low Power CMOS Design of An All Digital Phase Locked Loop PDF

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

A Low Power CMOS Design of An All Digital Phase Locked Loop PDF

Загружено:

Авторское право:

Доступные форматы

Northeastern University

Electrical Engineering Dissertations

Department of Electrical and Computer

January 01, 2011

A low power CMOS design of an all digital phase

This work is available open access, hosted by Northeastern University.

A Low Power CMOS Design of An All Digital Phase

c Copyright 2011 by Jun Zhao

Approved for Thesis Requirements of the Doctor of Philosophy Degree

Thesis Advisor: Prof. Yong-Bin Kim

Thesis Reader: Prof. Fabrizio Lombardi

Thesis Reader: Prof. Nian Xiang Sun

Department Chair: Prof. Ali Abur

Director of the Graduate School:

Dean: Prof. Yaman Yener

Approved for Thesis Requirements of the Doctor of Philosophy Degree

Thesis Advisor: Prof. Yong-Bin Kim

Thesis Reader: Prof. Fabrizio Lombardi

Thesis Reader: Prof. Nian Xiang Sun

Department Chair: Prof. Ali Abur

Director of the Graduate School:

Dean: Prof. Yaman Yener

Copy Deposited in Library:

3 Design Considerations in Analog PLLs

4 A Proposed All Digital PLL Architecture

5 Circuit Implement of The Proposed ADPLL

6 ADPLL Based Fractional-N Frequency Synthesizer

A mathematical representations of analog/digital DPLLs . . . .

Impact of each control bit on the DCO period . . . . . . . . . .

The basic structure of a phase-locked-loop . . . . . . . . . .

The spectrum of an ideal signal and practical signal .

Block diagram of a charge pump-based PLL. . . . . . . . . . . .

3.10 Frequency synthesizer using the on chip digital calibration technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The principle of a PLL-based frequency synthesizer . . . . . . .

Standard Cell of Digitally Controlled Oscillator. (a) Driving

5.10 Decoding process of the TDC . . . . . . . . . . . . . . . . . . .

Typical fractional-N divider scheme. . . . . . . . . . . . . . . . .

it often results in long lock-in time and increasing design complexity.

Overview of phase-locked loop

Figure 1.1: The basic structure of a phase-locked-loop

yi (t) = Asin[t + i (t)]

yo (t) = Bcos[t + o (t)]

and output signal is

Kd represents the phase detector sensitivity(V/rad). Name the transfer function

u2 is Kf u(t) f (t), where symbol * represents the convolution product.The

The phase-locked loop is nonlinear system and it is very complicated to

Figure 1.2: The The linear model of a phase-locked loop

In some applications, it is desirable for Vdo to be 0. Similarly, Vco is the control

the input frequency in some applications.

Normally it is preferred to express in frequency domain rather than time

CHAPTER 2. REVIEW OF FREQUENCY SYNTHESIZER

Performance parameters of a frequency synthesizer

As a key block in wireless systems, frequency synthesizer demands quite a few

Figure 2.1: The spectrum of an ideal signal and practical signal

CHAPTER 2. REVIEW OF FREQUENCY SYNTHESIZER

N oisepowerat(f0 + fof f set )

Usually, the measurement bandwidth of the noise power is 1 Hz and the

CHAPTER 2. REVIEW OF FREQUENCY SYNTHESIZER

Where kf is a constant, Ac the amplitude, and wm is the angular frequency of

2 , equation (2.3) maybe written as,

low modulation levels, frequency modulation of the carrier by a single low-level

Figure 2.2: The spectrum of a sinusoid FM signal