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HDL code. The code is then verified for the functionality before converting into gate
level netlist. The netlists were verified using formal verification techniques and then
imported to the place and route tool. The parasitic resistances and capacitances were
then extracted from the layouts and used to back-annotate the netlist for delay analysis
and power simulations.
tasks and streamline information extraction. A detailed overview of the tools and the
process
parasitic
and power
Figure 7.1 illustrates the design and tool flow for the
development and verification of the designs used in this research. The first important
step is design specification. Based on the specification, the design is developed using
Verilog HDL code and the verified behavior of the design is then converted into gate
level netlist using RTL Compiler. All the normal flops in the design are replaced with
scan flops for DFT purpose in scan insertion. The functional equivalence of the scan
inserted gate-level Verilog netlist is verified using Encounter Conformal Equivalency
Checking.
The verified designs are then placed and routed using NanoPlace and
Encounters Common Timing Engine, uses this parasitic information to determine path
delays. The parasitic data is also used for the power simulations by Cadences
Virtuoso UltraSim.
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Design Specification
HDL Coding
Netlist Generation
Scan Insertion
Functional Verification
RC Extraction
STA
Power Analysis
Functional Verification
After implementing the scan chain in a design, the DFT Rule Check (DRC) is run
to check whether design rules are violated.
Conformal Ultra tool has capability for verifying complex datapath logic. So it was added
to extend the logic equivalence checking capability for complex datapaths.
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Verilog RTL
Mapping
Analyze Design
Compare
Diagnose
Mis-Compare?
Done
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7.1.3 FLOORPLANNING
Cadences Encounter platform was used for floor-planning the designs in this
research. It provides initial feedback that evaluates architectural decisions, estimates chip
areas, and estimates delay and congestion caused by wiring. To build a floorplan, a
minimal set of constraints and parameters should be specified in a configuration file as
follows,
In this research, Verilog gate-level netlist was used for placement and route.
The timing file used for each standard cell library which represents the typical
performance at nominal voltage, temperature, and process corner. The LEF file is in
ASCII data format, used to describe the physical geometries of the process technology
and the standard cells.
default value is 1.0. There is 0.95 aspect ratio used for the layouts height versus
width was given for each design. This means that each layout would take on an
almost square appearance. The Power and ground strips were configured to abut ground
with ground and power with power.
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Following cell placement, the filler cells are added as needed to extend power and ground
lines.
NanoRoute is an advanced digital routing tool which helps designers quickly
achieve concurrent timing, area, signal integrity, and manufacturability convergence
during digital implementation. It takes the same input information used by NanoPlace to
produce an optimized routed design.
in
designs
implementation,
buffering,
optimization were disabled during routing. The layout of the placed and routed design
for the 32-bit ECU is shown in Figure 7.3.
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1) Default, and
2) Detailed
As per the Encounter User Guide (EncounterUser Guide (2008)), in default mode, the
nets geometry and the local wire density were considered for the calculated total
capacitance of each net. Here the coupling capacitance is not evaluated in the default
mode. In the detailed mode, the coupling capacitance is also calculated by considering
the actual geometries of adjacent nets on the adjacent metal layer and the same metal
layer when a complete capacitance table is provided. For this research, only the default
RC extraction is conducted.
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Figure 7.3 shows the basic configuration of CTE used for this
research. For each design, the 50 slowest path of timing data were reported.
RC Extraced
Data
Timing
Constraints
CTE
Worst Case
Paths (Top 50)
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Timing library
(typical.lib)
Figure 7.5.
The primary input file contains the required files path, such as the netlist, RC
parasitics for back-annotation (SPEF), and parameters of the process technology. The
test vector file includes stimulus values for the design as well as expected output values.
Test Vector
File
RC Parasitics
File (SPEF)
Process Tech
File
Netlist
Standard Cell
Libs
Ultrasim
Waveform file
(*.trn)
Measurement
Data (*.mto)
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Status Report
(*.log)
Build Model
Create Tests
Write Vectors
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Verilog Netlist
Build Model
1)
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2)
the type of scan implemented in the test mode (such as General Scan
Design (GSD), LSSD (Level Sensitive Scan Design), or boundary
scan): GSD was used in this research.
3)
tester Description Rule (TDR) for the test mode (describes tester
capabilities and limitations)
4)
test functions pin assignments for the Primary Inputs and Primary
Outputs
The TDR file defines the capabilities of the manufacturing tester. The TDR can also
identify the tester features such as number of pins, size of scan buffer, tester termination
of outputs, and bidirectional pins. The assign file specifies test function pin assignments
for the build test mode. It identifies scan chains and compression structures. Other DFTrelated logic from the input files generates the required files for ATPG simulation.
TDR File
Modedef File
Assign File
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