DIGITAL ELECTRONICS

LABORATORY
14:332:368

Dr. Jian H. Zhao

SPRING 2016

DIGITAL ELECTRONICS LAB

SECTION 0

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INTRODUCTION

This laboratory has been designed as a companion to Digital Electronics,

14:330:415. The textbook used is given in the syllabus
The lab will closely follow the material covered in class, however due to
scheduling you may be doing a lab before all the requisite material is covered
during lecture. You are still responsible for the lab. If you are having difficulties
see your lab TA or speak to the professor as soon as possible.
PSPICE Simulation:
You are required to have the lab simulated in PSPICE prior to the actual
performance of your lab. The only exception is for the first lab, where this may
not be possible due to scheduling. (The PSPICE simulation for the first lab is still
due to your TA when you hand in the lab report.) The PSPICE simulation need
not be in formal "lab report" form, but should be neat, professional, and contain
the following as a minimum:

A drawing of the circuit(s) with the node numbers clearly labeled.

A printout of the circuit code and node voltages.
Any specific analysis required for the lab being performed.

Having the lab simulated in PSPICE will save time during the
performance of the lab as it will help you to determine whether or not you have
built the circuit correctly. During the course of the lab your TA will inspect and
grade your PSPICE simulation . You may keep the PSPICE simulation to assist
you in writing the formal lab report, but it must be included in the report when
you hand it in.
Formal Lab Report:
The formal lab report is due to your TA at the beginning of the next lab period and
will contain the following:

An introduction containing a brief description of the lab.

A description of each activity and what was accomplished.
Any data tables or graphs developed in the course of the lab.
Any questions posed in the lab answered.
A brief conclusion/summary outlining the theory/concept explored in
the lab.
The PSPICE simulation.

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Digital Electronics Lab Manual:

This laboratory manual is divided into three sections: a review of the
laboratory equipment, a PSPICE example, and the labs themselves. The
laboratory equipment and PSPICE example sections are material you should
already be experienced with from previous classes. Read and understand each
experiment procedure prior to each lab. The purpose of, and fundamental
principles behind, each lab experiment should be understood clearly.

DIGITAL ELECTRONICS LAB

SECTION I

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LAB EQUIPMENT

General Safety and Procedures

You will be working with live electrical equipment. Even though the
voltages and currents are small, there are still hazards involved. BE CAREFUL.
Exercise common sense. The following are some safety guidelines:

No eating or drinking while working on the lab equipment.

No
excuses. No exceptions.
Check your circuit for accuracy prior to energizing it. A good idea is
to have one person wire the circuit up, and another do an independent
check of the wiring.
Always de-energize a circuit prior to removing or installing a
component.
If in doubt, start voltages low, and work your way up. Overloaded
semi-conductors can be damaged, and will need to be replaced.
If overloaded, semi-conductors can get hot! Be careful.

The Oscilloscope
The oscilloscope is one of the more complex instruments in electronics
labs. Much time can be saved and frustration avoided if care is taken to
thoroughly understand how it works.
The cathode ray tube (CRT) display of the oscilloscope has a tight beam of
accelerated electrons that are scanned to produce light on a phosphor screen. The
input signal controls where the electron beam will scan.
The electron beam needs two voltages to specify its location on the plane
of the CRT screen. The x-coordinate is controlled by the 'time base' section of the
oscilloscope. This section is found on the right side of your instrument. The time
base electronics produce a ramp wave form that causes the electron beam to move
from the left side of the screen to the right. This occurs at the precisely controlled
rate specified on a dial, for example 50 microseconds per centimeter.
The y-coordinate is controlled by the wave form input to either the A or B
channel of the 'vertical amplifier'. This section is usually found on the left side of
oscilloscopes. The 'vertical deflection mode' control determines which of the
inputs (A or B) are displayed. This control also allows the sum of the A and B
vertical deflections to be displayed. Some oscilloscopes provide two methods for
displaying both channels simultaneously. 'Chop' mode switches the electron beam
quickly between the traces on the fly. 'Alt' mode traces one channel completely
and then traces the other channel on the next trigger.

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Our oscilloscopes have a provision for continuously adjustable vertical

deflection and sweep rates. The red knob in the center of these dials is turned to
the left to vary the deflection and sweep to non-calibrated values. This feature is
often a nuisance. You should always check that the red knobs are turned fully
clockwise before making voltage and time measurements.
The input signal is fed into the vertical amplifiers with either AC or DC
coupling. DC is best when it can be used since it shows the actual wave form
voltage. The DC component of a wave form can be suppressed by using AC
coupling.

The Function Generator

Some oscilloscopes have a built-in function generator. There is also a
stand-alone function generator. Their operation is very similar. The function
generator is very easy to use, but can be confusing because there are features that
are not used in the electronics lab. Accidental activation of these features can
appear as a malfunction. Here are some things to watch out for:

The DC offset knob should be pushed in. When pulled out, a DC

offset can be applied and varied by turning the knob.
Make sure that it is in the 'free run' mode.
The fine frequency adjustment is not needed in out labs. Ensure that it
is set to a minimum.
The variable symmetry button should be pushed in so that the light is
off.

The Lead Box

The lead box is a very convenient way to connect the function generator
and the oscilloscope to your circuits. Generally, you will connect the function
generator output to your circuit and to one channel of the oscilloscope. This
allows you to 'see' the input signal to the circuit. The side of the lead box with
two BNC cables is for this purpose. These two cables are connected together and
to the two pairs of terminal posts closest to the cables. The red posts are for the
signal and are connected to the center conductor of the cables. The black posts
are for ground and are connected to the shield of the cables. The other side of the
lead box has only one BNC cable. It is for connecting to the other oscilloscope
input channel to allow measuring voltages in the circuit. As above, the adjacent
red post is for the signal and the black for ground.

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It is important to understand how the ground of the function generator and

the oscilloscope are connected. The outside cases of these instruments are
connected to the AC line ground for safety reasons. This also helps to control
signal 'noise' pickup. You cannot use the shield (ground) of the BNC cable to
carry a signal. Signal sources must only be connected to the red terminals on the
lead box. If you connect a circuit node to a black terminal and the corresponding
BNC cable is connected to an instrument, the circuit node will be shorted to
ground.

The Variable Power Supply

This is a simple, easy to use instrument. The 'output on/off' switch is on
upper right of the front. Normally the dual tracking control (top) is pushed in
which gives the supply its full voltage range. When pulled out and turned, the
voltage range of the supply can be reduced. This is helpful to achieve fine control
of small voltages. The 'common' output terminal usually gets connected to your
circuit ground (it is not connected to ground within the instrument). The current
limit knobs (middle) should be at the 9 o'clock position to protect the circuit from
too much current.

The Multimeter
The use of the multimeter is straightforward. Be aware that when
measuring current there can be a considerable voltage drop across the meter,
(about .5V). It is more accurate to measure currents in your circuits by measuring
voltage across a known resistance. If the measured parameter exceeds the range
set on the instrument, the display will flash. To correct this just change the range.
Note also that the AC/DC button should be in the correct position to read what is
desired.

The Tek-Pac Enclosure

The Tektronics instrument package has a function generator, variable
power supply, and timer-counter instruments. The on/off switch is on the front
left (pull to turn on) or in the back.

DIGITAL ELECTRONICS LAB

SECTION II

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PSPICE REVIEW

PSPICE is a software package that is used to analyze electrical and

electronic circuits. You should have already been exposed to its use in previous
classes. It is a non-copy protected program and, in fact, students are encouraged
to copy it for use in school. You can perform the SPICE simulations on a
computer at home, or on the PC's available for your use in the computer lab in the
Electrical Engineering building.
Computer simulations of the laboratory experiments on PSPICE will be an
integral part of the 14:332:368 lab. The following is an example of its use:

PSPICE EXAMPLE
Chapter 6 in Haznedar explores bipolar logic families, the operation of
which form an integral part of the Digital Electronics course. The
Transistor-Transistor Logic (TTL) family is widely used, and the NAND logic
structure is considered to be the most basic. Figure 6.1 in Haznedar illustrates
a two-input NAND gate, reproduced here as Figure II.1. You will see that
PSPICE is a powerful tool as we use it see how this logic gate operates.
Often, when a circuit is constructed it fails to function properly. The
reason could be that it is simply not biased correctly. The DC node voltages
are calculated automatically by PSPICE every time an analysis is performed,
and provided on the PSPICE Output file. This is very useful, as these DC
node voltages can be compared to the measured DC node voltages in the
laboratory to ensure your circuit was built correctly.
When a logic circuit operates, certain discreet input voltage combinations
generate either a logic-high or logic-low output. These combinations are
shown in a truth table. Other important parameters of a logic gate are how
high an input voltage can go yet still be accepted by the circuit as a low input,
and how low an input voltage can go yet still be a high input. This
information is graphically illustrated by a Voltage Transfer Characteristic
(VTC). Examining the output of a logic circuit with varying inputs or finding
the VTC can be accomplished through the use of PROBE, the graphics postprocessor that comes with PSPICE. Once the output file is examined, we will
explore the use of PROBE.
Figure II.1 shows the circuit with the power supply voltage, input voltages,
and node numbers. (Note that the input voltage isolation diodes shown in
Haznedar are not used.)

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5V

4K

1.6K

130

Q4
Q1
D
Q2

VA
VB

Vo

Q3
1K

Figure II.1

PSPICE has many useful commands. Of course, they cannot all be listed
in these few pages, but here are some things to keep in mind:

If you want to use a transistor in the PSPICE library (such as Q2N3904, or

DN4001), you must include the .LIB statement. If your PSPICE library is
in a different directory, you must stipulate the directory path and the name
of the library file (e.g. .LIB C:\PS\NOM.LIB).

The .OPTIONS statement is very useful in tailoring your output to suit

your needs. Some helpful options are; NOPAGE (suppresses printing of a
new page for each section of output), NOMOD (suppresses printing of
the model parameters), and NODE (creates output of a net list, or node
table). ( e.g. .OPTIONS NOMOD, or .OPTIONS NODE NOPAGE).

The .OP statement gives a more detailed operating point output, and is
very useful in troubleshooting circuits.

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*** PSPICE Output File ***

Commentary:

FIG 6.1 SAMPLE TTL NAND

It is a good idea to segment your circuit code

in some similar way. This will facilitate ease
of alterations or corrections later.

The numbers in parenthesis in the PULSE

command line are initial value, pulsed value,
delay time, rise time, fall time, pulse width,
and period, respectively.

In the .MODEL statement, specific

semiconductor parameters are stated. The
"+" sign indicates a continued line. Does the
logic gate behavior change when a different
diode is used? How does varying the
junction voltage (VJ) change the VTC?

In the .TRAN statement, we will look at a

time segment equal to VB's period of 2E-3
seconds (since VB is twice as long as VA) to
get all the information we need. The data
points are taken in 1E-6 size steps.

In the .DC statement, VB is swept from

0 volts to 5 volts in .01 volt steps to
determine the VTC. This statement, and the
statement making VA a constant 5V, is
commented out using an asterisk for later
use.

Voltage source currents are useful. Can you

use them to find the dissipated power? How
different is the PSPICE dissipated power
from the Haznedar value in the Power
Dissipation section on pp. 244 and 245?
Why is it different?

**** CIRCUIT DESCRIPTION

* Voltages
VCC 8 0 DC 5V
VA
1 0 PULSE (0 5 0 0 0 5E-4 1E-3)
*VA 1 0 DC 5V
VB
2 0 PULSE (0 5 0 0 0 1E-3 2E-3)
* Resistors
RB1 8 3 4K
RC2 8 5 1.6K
RB3 6 0 1K
RC4 8 9 130
* Diode
D1 7 10 DN4001
.MODEL DN4001 D (IS=5.86E-6 N=1.7
+BV=6.66E+1 IBV=5E-7 RS=3.62E-2
+CJO=5.21E-11 VJ=.34 M=.38 TT=5.04E-6)
* Transistors
Q11 4 3 1 Q2N3904
Q12 4 3 2 Q2N3904
Q2
5 4 6 Q2N3904
Q3
10 6 0 Q2N3904
Q4
9 5 7 Q2N3904
* Analysis
.TRAN 1E-6 2E-3
.LIB
*.DC VB 0 5 .01
.OPTIONS NOMOD NOPAGE
.END
**** NODE VOLTAGES
( 1) 0.000 ( 2) 0.000 ( 3) .6691
( 4) .0225 ( 5) 5.000
( 6) 11.9E-09 ( 7) 4.8128 ( 8) 5.000
( 9) 5.000 (10) 4.8128
**** VOLTAGE SOURCE CURRENTS
NAME
CURRENT
VCC
-1.083E-03
VA
5.414E-04
VB
5.414E-04
****

TOTAL POWER DISSIPATION

5.41E-03 WATTS

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PROBE GRAPHICS POST-PROCESSOR

When analysis of the above circuit is complete, you can call up PROBE
from the PSPICE shell command menu. (Some newer versions of PSPICE
automatically go into PROBE when the analysis is complete, if any analysis
was performed.) With the above circuit and PSPICE code, two different
analysis can be performed: Transient_analysis, and Dc_sweep.

Transient_analysis
With the circuit code typed in the way it appears above, PSPICE
will automatically transfer you to the Transient_analysis option in PROBE.
This option enables you to see the input and output values as if you were
using an oscilloscope. Once in the Transient_analysis screen, select
Add_trace from the menu.
Select or type in V(1) and hit enter. This is the VA input square
wave. Note the peak voltage values track with your VA command line in
your PSPICE code. Select Add_trace again, and add V(2). This is VB,
and you can see that VB's period is twice that of VA. Now add V(10),
your logic gate output. Does the circuit act as a NAND gate should?
What do the spikes at the output that occur at the input voltage polarity
shifts mean? Could this cause trouble if the NAND sent its output to the
input of another gate? How could this be prevented?
Some newer versions of PROBE allow you to add an additional
Y-axis. If you use this option, the output and input signals can be seen on
the same graph more clearly.

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Dc_sweep
The voltage transfer characteristic (VTC) is useful in determining
the noise margin of the gate. For PSPICE to analyze the VTC, some
changes need to be made to the PSPICE code. Comment out the VA
PULSE command with an asterisk, and delete the asterisk on the VA 1 0
DC 5V command line. This will put the VA input at a constant 5 volts.
The .TRAN statement is no longer needed, so comment it out with an
asterisk, then delete the asterisk on the .DC VB 0 5 .01 statement. Now
run the PSPICE analysis again. Once the analysis is complete, PSPICE
will automatically transfer you to the Dc_sweep option in PROBE. Select
Add_trace from the menu.
Select or type in V(10) and hit enter. This is the VTC for the TTL
NAND gate. Use the cursor command to determine the break points on
the curve. Are they different from those on the VTC illustrated in
Figure 6.10 in Haznedar? Why? What parameters of the semiconductors
need to be changed to match the figure?

Additional PSPICE Information

It is possible to import the circuit output file (e.g. CIRCUIT.OUT)
to most major word processors. Import it as a text file and delete
unwanted information or alter the format. This can drastically reduce the
PSPICE report size and save time by printing out fewer pages. Save the
output file on a disk and it can be printed out on any computer system, so
you won't have to wait for a long 'print queue' at the computer lab.
The PSPICE Library file can also be looked at or printed out in
similar manner, but care should be taken not to alter the library file in
any way. To prevent this, copy the library file (the only file with a .LIB
suffix) to another directory/disk and change its name before importing it to
a word processor.

Some helpful .MODEL statements:

.MODEL DN914 D (IS=4.77E-10 N=1.59 BV=133.3 IBV=1.0E-07
+ RS=6.01E-01 CJO=4.0E-12 VJ=.75 M=.333 TT=5.76E-09)
.MODEL DN4001 D (IS=5.86E-06 N=1.7 BV=6.66E+1 IBV=5.0E-07
+ RS=3.62E-02 CJO=5.21E-11 VJ=.34 M=.38 TT=5.04E-06)

10

DIGITAL ELECTRONICS LAB

SECTION III

LAB EXPERIMENTS

EXPERIMENT 1:
1.1

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DIODES AND BJT INVERTERS

Introduction

This lab will familiarize you with the voltage transfer characteristics and
switching times of a BJT inverter. There are two different activities. In the first
activity you will look at the operation of a diode and the capacitances at the p-n
junction. In the second, the operation of a BJT inverter circuit, and different ways
to eliminate delays in input response will be explored.
1.2

Spice Assignment

Using the student version of PSPICE to simulate the lab activities. The
Spice assignment should include the following for each activity:
NOTE: The TIP 31 is not in the PSPICE library. You will have to to model the
TIP 31 using the .MODEL statement. There is a model on the WEB site.

1.3

Circuit drawings with the nodes labeled

Spice circuit files
DC node voltages from the Spice output file
Input and output square wave plots

Lab Activities

ACTIVITY 1:

Simple Diode Circuit

This activity takes a simple diode circuit (Fig. 1.1) and inputs
several different square waves. As the diode is forward and reverse-biased,
storage and delay times are measured, and from this data diffusion and junction
capacitance are calculated.
1) Connect the circuit as shown in Figure 1.1, and set the voltage levels of the
square wave to:
(a)

ViL = 0V
ViH = 10V

(b) ViL = -10V

ViH = 10V

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Use the amplitude offset on the function generator to produce a square

wave that is unsymmetrical about the origin (meaning that it changes
from a low to a high value at the origin) for this and all subsequent
parts.

Using a 100KHz square wave, measure the storage time (Ts) of the
diode, then calculate the storage time constant, and Cd.

2) While maintaining 100KHz , change the voltage levels in the circuit to:
ViL = -10V
ViH = 10V

Measure the Recovery Time (TR), then calculate the recovery time
constant, and Cj.

3) Repeat parts 1 and 2 with (a) 1N4001 and then (b) 6A05 (switch to
10KHz).
ACTIVITY 2:

Circuit Response Correction

In this activity, the operation of a BJT inverter circuit (Fig. 1.2)

with a square wave input is explored. The use of a diode and a capacitor to
eliminate circuit response delays (Fig. 1.3) is examined.
1) Connect the circuit illustrated in Figure 1.2a. (Use the 5V source on the
function generator to get a VCC of 5 Volts.) Perform the following:

Start with an input voltage (Vi1) of 0V. Slowly raise Vi1 and measure
Vo1 at 0.2V increments. Stop taking measurements when the
transistor turns on.

Once the transistor turns on, measure the base and collector voltages.
Use these values to calculate the gain B(DC) of the transistor.

Plot Vo1 versus Vi1 and determine VOH, VOL, VIH, VIL, NMH,
and NML.

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2) Now connect the circuit illustrated in Figure 1.2a according to the table
below and input a 10KHz square wave at Vi1. Measure the voltages and
times illustrated in Figure 1.3 and sketch the output voltage waveforms.

(a)
(b)
(c)

RC

RB

ViL

ViH

1K
.1K
.1K

10K
1K
1K

0V
0V
-5V

5V
5V
5V

3) Connect the circuit illustrated in Figure 1.2b (Use a Schottky-barrier diode

to clamp Q1 out of saturation.) and input a 10KHz square wave with ViL =
0V and ViH = 5V.

Measure the voltages and times illustrated in Figure 1.3 and sketch the
output voltage waveforms.

Input a 10KHz square wave with ViL = -5V and ViH = 5V and observe
how the storage time is removed.

Measure the current through the Schottky diode by hooking up a meter

in series with the diode when Vi1 = 5V. (A constant DC voltage is
required to do this.) Verify the relationship:
IBE ICB IRB

4) Connect the circuit illustrated in Figure 1.2c using a 1000pF capacitor.

Input a 10KHz square wave with ViL = -5V and ViH = 5V and record the
times td, tf, ts, and tr.

Sketch the output with respect to the input.

Comment on the disappearance of the storage time and the delay time
when the capacitor is added to the circuit.

5) Repeat parts 1-5 replacing the TIP31 with a 2N3904.

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Vo1

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10V

Vo2

Ts
1K

0V

914

10V
Td
0V
Figure 1.1

Circuit for Junction Capacitance Estimation

10V

10V

10V

RC1
470
Vi1

VCC

VCC

VCC

RB1

Vo1

RC1
470

914
RB1

Vo1

Vi1

CB

TIP 31
2K

2K

2K

Figure 1.2a

Figure 1.2b

Figure 1.2

Vo1

RB1

Vi1

TIP 31

TIP 31

RC1
470

Figure 1.2c

BJT Inverter Circuits

Note: Replace 914 with SR102 in Figure 1.2b and VCC=5v

Vi = 5 V below

Vi1

10V
0V

5s
td1

ts1

tf1

tr1

O H 1

Vo1

O L 1

Figure

1.3

Inverter

Timing

Diagram

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DIGITAL ELECTRONICS LAB

EXPERIMENT 2:
3.1

14:330:368

TTL AND ECL LOGIC GATES

Introduction

In this lab you will examine various logic gates using different BJT
topologies, and verify their characteristics. The first two circuits are TTL
(Transistor-Transistor Logic) configurations and are NAND and NOR gates,
respectfully. The final circuit is an ECL (Emitter Coupled Logic) configuration
and both NOR and OR gates are explored.
3.2

Spice Assignment

Using the student version of PSPICE simulate all lab activities. The Spice
assignment should include the following for each activity:

3.3

Circuit drawings with the nodes labeled

Spice circuit files
DC node voltages from the Spice output file
Input and output square wave plots for all activities similar to the
PSPICE example
VTCs for Activities 1, 3, and 4

Lab Activities

ACTIVITY 1:

TTL 2-Input NAND

In this activity, you will experimentally determine the NAND gate

truth table as well as the VTC under various loading conditions.
1) Build the TTL, 2-input NAND gate illustrated in Figure 3.1 using
Q2N3904 BJTs, DN4001 diodes, and resistors.
NOTE: Q1 is assembled by taking two BJTs and connecting the
collectors together and the bases together similar to the PSPICE example
at the beginning of the lab.

Verify that the circuit follows the NAND gate truth table.

2) Connect input A to 5V and plot Vo for B=0V to B=3V using 0.2V steps.

Find VOH, VOL, VIH, VIL, NMH, and NML from the resulting VTC.

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3) Simulate 10 loads for VOL by connecting the gate output to VCC through a
200 resistor and find VOL.
4) Simulate 10 loads for VOH by connecting the gate output to ground
through a 270 resistor and find VOH.
ACTIVITY 2:

TTL 2-Input NOR

In this activity, you will experimentally determine the NOR gate

truth table.
1) Build the TTL, 2-input NOR gate illustrated in Figure 3.2 using Q2N3904
BJTs, DN4001 diodes, and resistors.

Verify that the circuit follows the NOR gate truth table.

ACTIVITY 3:

ECL 2-input NOR

In this activity, you will experimentally determine the ECL NOR

gate truth table as well as the VTC.
1) Build the ECL, 2-input NOR gate illustrated in Figure 3.3 using Q2N3904
BJTs and resistors. VREF = -1.2V
NOTE: VREF can be created by making a voltage divider network
between -5V and ground.

Verify that the circuit follows the NOR gate truth table.

2) Connect input A to a logic low of approximately -1.6V.

Plot Vo and VB4 for B = -1.8V to -0.8V in 0.1V steps.

Determine VOH, VOL, VIH, VIL, NMH, and NML from the resulting
voltage characteristic.

ACTIVITY 4:

ECL 2-input OR

In this activity, you will experimentally determine the ECL OR

gate truth table as well as the VTC.

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1) Build the ECL, 2-input OR gate illustrated in Figure 3.3 using Q2N3904
BJTs and resistors. VREF = -1.2V

Verify that the circuit follows the OR gate truth table.

2) Connect input A to a logic low of approximately -1.6V.

Plot Vo and VB4 for B = -1.8V to -0.8V in 0.1V steps.

Determine VOH, VOL, VIH, VIL, NMH, and NML from the resulting
voltage characteristic.

Vc c

RB1
4K

RC2

RC4

1.5K

120

Q4

Q1

Q2

To

Loads

Q3

RB3
1K

Figure 3.1 TTL 2-Input NAND With Active Pull-Up

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Vc c

1.5K

120

4K

4K
OUTPUT

B
1K

Figure 3.2 TTL 2-Input NOR

300

270

Q4

V1

Q3

Q2

OR
VREF

V2
2K

1.2K

NOR
2K

VE E

Figure 3.3 ECL 2-Input OR/NOR

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DIGITAL ELECTRONICS LAB

EXPERIMENT 3:
2.1

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MOSFET LOGIC GATES

Introduction

This lab will study the voltage transfer characteristics of nMOS and
CMOS inverters. The rise, fall, and propagation delay times for these inverters
will also be explored.
2.2

Spice Assignment

Using the student version of PSPICE simulate only the nMOS portion of
the lab. (The nMOS in the device library of the student version of PSPICE is an
IRF150. There is no CMOS in the device library of the student version .)
The nMOS name must start with an "M", and the general element line is:
MXXX

ND NG NS NB IRF150

Where ND, NG, NS, and NB are the numbers of the drain, ground, source, and
substrate nodes, respectively. The substrate is usually connected to ground
(node "0" (zero) in most PSPICE circuit files).
The PSPICE simulation should contain the following:

2.3

Circuit drawings with the nodes labeled

Spice circuit files
The VTC for Figure 2.1
At least two full periods of the output wave for all parts of Activity 1

Lab Activities

ACTIVITY 1:

The NMOS Inverter

In this activity, the operation of a simple nMOS inverter will be

explored. You will experimentally determine the VTC, and study rise,
fall, and propagation delay times under various loading conditions
(Haznedar, sections 6.5 and 6.8).

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1) Construct the nMOS inverter circuit illustrated in Figure 2.1 using the
4007 integrated circuit provided, adding a 1K resistor in series with the
input.

Plot the voltage transfer characteristics (Vout versus Vin) for an input
that varies between 0V and 5V.

Record VOH, VOL, VIH, and VIL.

2) Use the function generator to create a 10 KHz, 0 to 4V, square wave.
Using the oscilloscope, measure the rise and fall times of the wave. These
are the system rise time (trs) and system fall time (tfs). Input this wave
into the nMOS inverter circuit.
Measure the rise time (trt), and the fall time (tft). The inverter rise and
fall times are related to these two values through the following
relationships:
(trt)2 = (trs)2+ (trc)2
(tft)2 = (tfs)2 + (tfc)2
Use these relationships to calculate the circuit rise and fall times
(trc and tfc).
Measure the inverter propagation delay time by connecting the input
signal to Channel 1 of the oscilloscope, and the output signal to
Channel 2. The propagation delay is the time difference between when
the input goes high and the output goes low.
3) Repeat Part 2) with a 1000pF load.
4) Repeat Part 2) with a 1000pF load, but eliminate one of the inverter
transistors (QSB) by connecting its gate to ground.
5) Repeat Part 2) with no load, and with Rg = 1M.

NMOS Questions:
1. Determine VT from Part 1) of Activity 1.
2. Show the delay due to adding Rg = 1M in the circuit with both of
the transistors and no capacitive load.
3. Show the delay due to adding the load capacitor (CL = 1000pF),
but with no Rg.

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4. Show the delay due to a load capacitor (CL = 1000pF), but with
QSB eliminated.

ACTIVITY 2:

The CMOS Inverter

In this activity, you will experimentally determine the VTC, and

study rise, fall, and propagation delay times of a CMOS inverter under
various loading conditions, similar to Activity 1.
1) Connect the CMOS inverter circuit illustrated in Figure 2.2, and repeat
Part 1) of the procedure in Activity 1. Limit Vin to VDD (shown in the
Figure).
2) Repeat the measurements from Part 2) of Activity 1 on the CMOS inverter
circuit. Compare, and comment on, the rise time, fall time, and
propagation delay time of these two circuits.
3) Repeat Part 2) of Activity 2 using a 1000pF load.

ACTIVITY 3:

CMOS Logic Gates

In this activity, CMOS NAND, NOR, and XOR logic gates will be
examined, and their parameters explored
1) Using the ECG4007 integrated circuits (illustrated in Figure 2.3), build the
two-input CMOS NAND gate shown in Figure 2.4.
Measure the circuit output (Vout) fall times (tfc) for the following
simultaneous circuit changes :
A 01

NOTE:

B 01

Both VDD and VSS must be connected on each package for

ANY device on the package to work
Use individual n MOSFETS to realize the gate, and leave the
p transistor associated with the n transistor disconnected.

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Follow a similar approach for connecting p MOSFETS.

Measure the circuit output Vout rise time (trc) for the following
situations:
(1)
(2)

A 10
A 10

and
and

B 11
B 10

2) Using the ECG4007 integrated circuits (illustrated in Figure 2.3), build the
three-input CMOS NOR gate shown in Figure 2.5
Measure the circuit output (Vout) rise times (trc) for the following
simultaneous circuit changes :
A 10

C 10

Measure the circuit output Vout fall time (tfc) for the following
situations:
(1)
(2)

B 10

A 01
A 01

B 00
B 01

and
and

C 00
C 01

CMOS Questions:
1. Show the delay due to adding Rg = 1M in the circuit with both of
the transistors and no capacitive load for Activity 2, Part 1).
2. Show the delay due to adding the load capacitor (CL = 1000pF),
but with no Rg for Activity 2.

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VD D = 5 V
5,14
ECG4007
3
4
+
8

12
10

Vo u t

QS B

QS A

Vi n

Figure 2.1

ECG4007 Circuit for nMOS Inverter

VD D = 5 V
14

13
6
+

+
8
Vi n

Figure 2.2

Vo u t

ECG4007 Circuit for CMOS Inverter

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DD
14

13

12

11

10

p
n
n

SS

NOTE: All p-channel substrates are connected to VDD

and all n-channel substrated are connected to VSS

Figure 2.3 Package for ECG4007 Circuit

DD

out

SS

Figure 2.4 Circuit for CMOS 2-Input NAND Gate

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V

DD

C
V

out

SS

Figure 2.5 Circuit for CMOS 3-Input NOR Gate

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EXPERIMENT 4:
4.1

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REGENERATIVE LOGIC CIRCUITS

Introduction

This lab will study the operation of , and verify the characteristic tables
for, the following logic circuits:

4.2

SR Latch constructed of NOR gates

SR Latch constructed of NAND gates
JK Flip-Flop
Clocked SR Flip-Flop

Spice Assignment

Using the student version of PSPICE simulate only the SR Latch

constructed of NOR gates, and the JK Flip-Flop, both of which can be found in
the PSPICE library. Use input waves similar to the PSPICE example found at the
beginning of the lab manual. (The NOR gate is a 7402, and the JK Flip-Flop is a
74107.)
The PSPICE simulation should contain the following:

4.3

Circuit drawings with the nodes labeled

Spice circuit files
At least two full periods of the output wave for each logic gate

Lab Activities

ACTIVITY 1:

Regenerative Logic Circuits

In this activity, various logic circuits are explored and their

characteristic tables experimentally verified. A clock circuit will be
constructed for those circuits that need one.
1) Construct the SR Latch with NOR gates using a 5 V power supply as
illustrated in Figure 4.1. Assume that a logical "0" is 0 V and that a
logical "1" is 5 V. Verify Table 4.1.

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2) Construct the SR Latch with NAND gates using a 5 V power supply as

illustrated in Figure 4.2. Assume that a logical "0" is 0 V and that a
logical "1" is 5 V. Verify Table 4.2.
3) Construct the JK Flip-Flop using a 5 V power supply as illustrated in
Figure 4.3. Assume that a logical "0" is 0 V and that a logical "1" is 5 V.
Verify Table 4.3.
4) Construct the clocked SR Flip-Flop using a 5 V power supply as illustrated
in Figure 4.4. Assume that a logical "0" is 0 V and that a logical "1" is 5
V. Use the clock circuit illustrated in Figure 4.6 to verify Table 4.4. (Note
that Table 4.4 is the same as Table 4.1 with a "clock" column added.)

S
Q

R
Figure 4.1 SR NOR Latch

Table 4.1 SR NOR Latch

Truth Table

S
Q

Q
R

Figure 4.2 SR NAND Latch

Table 4.2 SR NAND Latch

Truth Table

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J Feedback
J

CK

NAND
Latch
R

K
K Feedback

Figure 4.3 Clocked JK Flip-Flop

Qn+

Qn

Qn

Table 4.3 JK Flip-Flop

Truth Table

R'
Q

CK

J n Kn

S'

Figure 4.4 Clocked SR NOR Latch

Qn Q

Table 4.4 Clocked SR Latch

Truth Table

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5V
5V

5V

2.2K

CLOCK

CLOCK

2.2K
10K
10K
10K

1uF

100

Figure 4.6 Clock Circuit

1Y

14

VCC

1A

14

VCC

1A

13

4Y

1B

13

1C

1B

12

4B

2A

12

1Y

2Y
2A

4
5

11
10

4A
3Y

2B
2C

4
5

11
10

3C
3B

2B

3B

2Y

3A

GND

3A

GND

3Y

7402

NOR Functional Table (each Gate)

Inputs

7410

NAND Functional Table (each Gate)

Output

Inputs

Output

1A

14

VCC

1A

14

VCC

1B

13

4B

1B

13

4B

1Y

12

4A

1Y

12

4A

2A

11

4Y

2A

11

4Y

2B

10

3B

2B

10

3B

2Y

3A

2Y

3A

GND

3Y

GND

3Y

7400

NAND Functional Table (each Gate)

Inputs

Output

7408

AND Functional Table (each Gate)

Inputs

Output

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EXPERIMENT 5:
5.1

14:330:368

STATIC CMOS RAM MEMORY CELL

Introduction

This lab will study the construction and behavior of a Static CMOS
memory RAM cell.
5.2

Lab Activity

ACTIVITY :

CMOS Static RAM Cell

In this activity, you will construct a static CMOS memory RAM

cell and verify its behavior by examining its input and output voltage
levels during writing and reading.
1) Build the circuit in illustrated in Figure 5.1 using VDD=+5V and VSS=0V.
2) Input a logic "1" to your constructed RAM cell by applying 5V to the BIT
signal and 0V to the BIT signal.

Cause the BIT and the BIT signals to be written to the cell by
applying 5 V to the LOAD signal.

Now apply 0V to the LOAD signal.

Verify that the signal stored at node A is 5V and the signal stored at
node B is 0V. Show your results in a table.

3) Repeat Part 1) but this time set BIT to 0V and BIT to 5V.

Verify that the signals at nodes A and B are opposite of what they were
before. Show your results in a table.

4) In real RAM circuits, the BIT and BIT lines extend across an entire RAM
chip, and have excessive capacitance in them. This is because the BIT
and BIT lines are bi-directional, and are used for both reading from, and
writing to, the cell. One pair of lines services an entire column of 8192
identical cells. There may be as many as 8192 rows of identical cells. A
unique cell is addressed and read by turning on the LOAD signal for its
row and sampling the BIT and BIT signals for its column. The excessive
capacitance is modeled here by attaching the two 1000 pF capacitors to
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each BIT and BIT line. Unfortunately, the capacitance in real circuits is
so severe that when one attempts to read the RAM cell, the voltage levels
of BIT and BIT are drastically degraded.

Attempt to read the RAM cell when it contains a logic "1" (node A is
5V and node B is 0V) by leaving BIT and BIT undriven, and applying
5V to the LOAD signal. (Use the oscilloscope to determine the
voltage levels of BIT and BIT ).

Now read the cell when it contains a logic "0", recording the actual
voltages you get on the BIT and BIT lines.

During read operations on real RAM chips, if the cell contains a logic "1",
the BIT signal will become 2.9V and the BIT signal becomes 2.1V.

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LOAD

5V

A
B
2000 pF

BIT

2000 pF

BIT
Figure 5.1 CMOS Static RAM Circuit Schematic

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V

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DD
14

13

12

11

10

p
n
n

SS

NOTE: All p-channel substrates are connected to VDD

and all n-channel substrated are connected to VSS

Figure 5.3 Package for ECG4007 Circuit

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PARTS LIST
EXPERIMENT
LAB EXP. 1

ANALOG
100
470
1K
2K
10K
1000pF
TIP 31
1N914
SR102
6A05
2N3904
1N4001

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)

LAB EXP. 2
LAB EXP. 3

Q2N3904
DN4001
120
270
300
1K
1.5K
2K
4K

(6)
(3)
(1)
(1)
(1)
(1)
(1)
(2)
(2)

LAB EXP. 4

100
2.2K
390
820
33K
10K
1uF
Q2N3904
DN4001
2000pF
120
1K
1.5K
4K

(1)
(2)
(2)
(1)
(1)
(3)
(1)
(6)
(3)
(2)
(1)
(1)
(1)
(1)

LAB EXP. 5

CHIP

ECG4007

(3)

SN7400
SN7402
SN7410
SN7408

(3)
(2)
(1)
(1)

ECG4007

(3)

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COMPOSITE PARTS LIST

TRANSISTORS
2N3904
TIP 31
SR102
1N914
DN4001
6A05
RESISTORS
100
120
270
390
820
33K
300
470
1K
1.5K
2K
2.2K
4K
10K

7
1
2
1
4
1

(Schottky Barrier Diode)

1
2
2
2
1
1
2
2
5
2
2
5
1
4

CAPACITORS
1uF
1000pF
2000pF

1
5
2

CHIPS
SN7400
SN7402
SN7410
SN7408

6
4
4
4

36