Fabrication and Characterization of a

Polysilicon MOSFET as a SpinFET Base

Daniel T. Watrous
Department of Electrical and Computer Engineering
University of Utah, Salt Lake City, Utah 84112 1

March 2, 2010

1
Special Thanks to Professor Mark Miller, Justin Jackson and Divesh Kapoor
Contents

0.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

0.2 Polysilicon NMOSFET Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

0.2.1 Structure and Basic Device Characteristics . . . . . . . . . . . . . . . . . . 2

0.2.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

0.2.3 Road Map NMOSFET for 2020 . . . . . . . . . . . . . . . . . . . . . . . . . 6

0.3 SpinFET Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

0.3.1 Structure of Existing SPINFET Devices . . . . . . . . . . . . . . . . . . . . 6

0.3.2 Spin Lattice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

0.3.3 Spin Lattice Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

0.4 Fabrication and Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

0.4.1 Polysilicon NMOSFET Fabrication . . . . . . . . . . . . . . . . . . . . . . . 10

0.4.2 MOSFET Measurements and Characterization . . . . . . . . . . . . . . . . 13

0.4.3 SpinFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

0.5 Conclusions and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

0.6 Ethical Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

0.6.1 Ethical Issues Encountered . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

0.6.2 Ethical Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

List of Figures

1 Schematic diagram MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 MOS capacitor schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 MOS band diagrams for bias conditions . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Theoretical I-V characteristics of an NMOSFET . . . . . . . . . . . . . . . . . . . 5

5 Processing steps for polysilicon self aligning process [6] . . . . . . . . . . . . . . . . 5

6 Spin lattice processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Conduction band due to spin lattice confinement [8] . . . . . . . . . . . . . . . . . 9

8 Electron probabilities within a lattice of confining potentials [8] . . . . . . . . . . . 10

9 Optical microscope image of substrate to polysilicon capacitor across gate oxide

with height and width marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Substrate to Polysilicon capacitor across gate oxide Measurement . . . . . . . . . . 12

11 Polysilicon Test Resistor Measurement . . . . . . . . . . . . . . . . . . . . . . . . . 13

12 Illustration of Al spiking into silicon . . . . . . . . . . . . . . . . . . . . . . . . . . 13

13 10µm gate polysilicon MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Substrate to Polysilicon capacitor across gate oxide Measurement . . . . . . . . . . 14

15 Spin Lattice Patterned Using SEM Lithography (Justin Jackson) . . . . . . . . . . 15

 Abstract

Interest in developing nano-scale devices that manipulate both the charge and spin of electrons has

fueled much research in recent years. To be commercially viable these devices will require proven

and reliable means of fabrication. One solution has been proposed in which a traditional MOSFET

device is modified to create a periodic potential in the inversion layer when actively biased. The

period of this potential is on the order of 10nm. The present research works to establish the

basis of the spin device by fabricating a suitable, small-scale NMOSFET and characterizing the

substrate, polysilicon, and oxide layers. An oxide thicknesses of less than 5nm was obtained.

Very high doping was applied to both the initial substrate on the order of 1.5 × 1020 cm−3 , and to

the polysilicon on the order of 1021 cm−3 . Both aluminum spiking after annealing and depletion

of the polysilicon layer were observed during characterization. Fabrication and characterization

details are presented along with some background NMOSFET and SpinFET theory.
0.1 Introduction 1

0.1 Introduction

This paper discusses the fabrication and characterization of a polysilicon MOSFET as a base

for a SpinFET device. The discussion begins with a review of the well established theory of

NMOSFET devices including schematics and processing steps. This analysis reviews the current

vs. voltage and capacitance vs. voltage characteristics. Polysilicon work function, and depletion

are discussed. Operating modes and surface conditions are considered. This section closes with a

discussion of the future of MOSFET fabrication, including projected feature sizes and timelines.

“Spin” MOSFET, or SpinFET theory is then discussed briefly. This discussion begins with

the modifications to traditional MOSFET fabrication required to produce a SpinFET device.

The properties of the resulting spin lattice are then analyzed, including magnetic properties,

electronic confinement and the resulting band structure for the inverted region at the Si -Si 02

interface. Some potential uses of the SpinFET are then discussed.

Fabrication and characterization details are presented for the NMOSFET device. This sec-

tion includes images of the actual devices and the data that resulted from characterization mea-

surements. Complications in the fabrication process are analyzed and adjustments for future

fabrication are suggested.

This paper concludes with recommendations for future work and a summary of characteriza-

tion results.

0.2 Polysilicon NMOSFET Theory

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are the building block of modern

CMOS (Complimentary MOSFET) technology. MOSFET devices are typically fabricated in

Silicon due to the high quality oxide layer (Si O2 ) which is used as the dielectric for the MOS

Capacitor.

MOSFET devices are fabricated on both p-type (majority holes) substrates and n-type (ma-

jority electrons) substrates and become NMOSFETs and PMOSFETs respectively, where the N

and P indicate the type of inversion layer created when actively biased. The structure of these

devices is identical, but each device performs differently. A large difference in the mobility, µ,
0.2 Polysilicon NMOSFET Theory 2

Figure 1: Schematic diagram MOSFET

between holes and electrons has a significant impact on the performance and characteristics of

each type of MOSFET. The remainder of this chapter discusses the NMOSFET. A schematic

diagram of an NMOSFET is shown in figure 1.

0.2.1 Structure and Basic Device Characteristics

MOS Capacitor

An MOS capacitor is at the heart of a MOSFET device. An MOS capacitor consists of three

layers, metal, oxide and semiconductor. In recent years, heavily doped poly-crystalline silicon

(polysilicon) is frequently substituted for the metal top gate to accommodate a self aligning

fabrication process. Since the metal layer has been replaced with polysilicon, care must be taken

to prevent depletion in the gate layer. A schematic for an MOS capacitor is shown in figure 2.

Figure 2: MOS capacitor schematic

0.2 Polysilicon NMOSFET Theory 3

Several conditions are of interest with respect to a voltage, Vapp , applied to the device as

shown in figure 3. These conditions are accumulation, depletion and inversion (and sometimes

flatband). In accumulation a negative bias voltage is applied to the gate which causes the initial

concentration of holes a the surface due to doping to increase, thus accumulating additional holes.

Depletion is achieved by applying a positive voltage to the gate equal to the threshold voltage

Vth . This attracts electrons to the Si O2 interface in concentration equal to the concentration of

holes which gives charge neutrality at the interface. Inversion is achieved by applying a positive

voltage greater than the threshold voltage Vapp > Vth . At positive applied voltages higher than

the threshold voltage the potential at the interface is inverted, that is, an n-type channel is

created in the p-type material right at the Si O2 surface. This inversion layer can be modeled as

a 2D electron system. The band diagrams illustrating these conditions, including the flat band

condition, are shown in figure 3.

Figure 3: MOS band diagrams for bias conditions

The threshold voltage is proportional to the bulk potential, Ψb . The relationship between

threshold voltage and other device parameters is given in equation (1) [3].

p
2s qNa (2Ψb )
Vth = 2Ψb + (1)
Cox

Capacitance versus voltage

Each of the bias conditions above has a different capacitance associated with it, such that as the

applied voltage changes so does the capacitance of the MOS capacitor. This is due to the changing
0.2 Polysilicon NMOSFET Theory 4

depletion width. There are also frequency considerations related to carrier mobility. In other

words, capacitance in a MOS capacitor depends on both the applied voltage and the frequency of

the applied signal. The small-signal capacitances at low frequency are calculated using equation

(2) [4]. The capacitance can be further separated into two parts, the first corresponding to the

oxide capacitance and the second to the capacitance across the silicon as shown in equation (3)

[4].

d(−Qs )
C= (2)
dVg

1 1 1
= + (3)
C Cox Csi

Current versus voltage

An NMOSFET is fabricated by placing two heavily doped n-type regions on either side of an

MOS capacitor (which has a p-type semiconductor base, see 0.2.1). An illustration is shown in

figure 1. A gate voltage greater than or equal to Vth will produce an inversion layer in the MOS

capacitor that connects the source and drain n regions. Current can then be drawn from source

to drain by applying a voltage, VD from source to drain. As the applied drain voltage changes, so

does the shape of the inversion layer at the Si -Si O2 interface. At high VD , the inversion layer has

the shape of a wedge and the edge of the inversion layer begins to separate from the n+ region

of the drain. This is referred to as pinch-off and has the result of keeping the drain current ID

constant past the saturation voltage, Vs . The resulting current is called the saturation current. A

plot of theoretical currents and voltages for an NMOSFET (5µm gate length) is shown in figure

4.

0.2.2 Fabrication

Current fabrication techniques and processes are well established and mostly consistent through-

out the semiconductor industry. A standard process involves masking certain areas of a silicon

wafer and adding dopant impurities or growing oxide layers. Small feature sizes make accurate
0.2 Polysilicon NMOSFET Theory 5

Figure 4: Theoretical I-V characteristics of an NMOSFET

alignment critical to a successful fabrication process. One technique used to improve alignment

involves replacing the metal gate with polysilicon. This method allows for a self aligning process,

and can accurately produce devices with very small dimensions (currently on the order of 35nm).

Processing steps

The process steps and masks used for the present research were developed at the University of

Utah by Justin Jackson and Mike Sorenson [6]. The process includes four masks which accom-

modate oxide growth, well definition, polysilicon patterning, contact vias and a final metal layer

for probe and bond pads. An illustration of the process is shown in figure 5.

Figure 5: Processing steps for polysilicon self aligning process [6]

0.3 SpinFET Theory 6

0.2.3 Road Map NMOSFET for 2020

The International Technology Roadmap for Semiconductors (ITRS) is a non-commercial consor-

tium sponsored by the major semiconductor manufacturing associations around the world. Its

purpose is to promote cost-effective advancements in performance of semiconductor based de-

vices. A road map, which outlines projected device characteristics and scale, is one result of

this undertaking. The road map represents the scale and speed projections to be achieved by

companies in the semiconductor industry. Current projections lead out as far as 15 years.

Lithography

Lithography projections [1] extend out to the year 2020. In this report, the gate length is projected

to shrink to 6nm. The implications of this are significant for the semiconductor industry. In

relation to the research presented here, this indicates that the target geometry and feature sizes

of a SpinFET device (currently obtained using SEM lithography) will be manufacturing ready

by the year 2020 for mainstream semiconductor devices.

0.3 SpinFET Theory

0.3.1 Structure of Existing SPINFET Devices

Several attempts have been made to create spin polarized semiconductor devices using magnetic

materials at the contacts. The magnetic materials provide a spin polarization to the injected

electrons. One ferromagnetic material used with III/V semiconductors is Manganese (Mn) in

compounds such as (Ga,Mn)As. In order to experimentally test these devices, spin sensing is

required. Spin devices dealing both with electronic and optical applications have been fabricated

in research labs around the world. At the time of this paper there are not yet any commercial

spin devices known to the author.

This present research deviates from previous structures in that the SpinFET devices fabricated

will use carefully engineered confining potentials to create an artificially magnetic material rather

than introducing naturally magnetic materials. In such a device, an inversion layer (at the Si O2
0.3 SpinFET Theory 7

interface) can be modulated between ferromagnetic, quantum insulator and antiferromagnetic

modes my modulating the applied gate voltage [9]. Analysis of the energy band structure in the

periodic inversion layer reveals striking similarities to that of high Tc superconducting materials.

0.3.2 Spin Lattice

The basis of the spin lattice is an MOS capacitor (see 0.2.1). As was discussed in a previous

section, an MOS capacitor can produce an inversion layer at the insulator/substrate interface.

In order to achieve the confining potentials that are required to localize electrons in the lattice,

further processing is required. The process developed for this research requires nanolithography

using a Scanning Electron Microscope (SEM). A pattern is written in a PMMA layer, developed

and the lattice etched. The etching process includes Reactive Ion Etch (RIE) and a quick Buffered

Oxide Etch (BOE), which etch the polysilicon and gate oxide layers respectively. RIE is used

to etch the polysilicon pattern with minimal broadening from lateral etching. The process is

illustrated in figure 6. The resulting lattice holes should etch slightly into the Silicon surface to

increase confinement.

Figure 6: Spin lattice processing

NMOSFET Basis

The MOS capacitor used in this research was part of a polysilicon NMOSFET. The choice to

use an NMOSFET as the base was influenced in part by ease of testing. During the process, a

particular wafer containing a number of die with devices is diced into two separate half wafers.
0.3 SpinFET Theory 8

One half wafer is then processed to produce traditional NMOSFETs. These devices are then

characterized and processing parameters verified. The other half is further diced into individual

dies and patterned using SEM lithography. Once patterned, the processing is completed for these

devices. Characterization of these spin devices and careful comparison to the non-spin devices is

done to analyze the effects of the spin lattice.

0.3.3 Spin Lattice Properties

Magnetic Properties

Two measures of interest in current magnetic devices include weight and power efficiency. In an

effort to reduce weight and increase power efficiency, recent research attention has been given to

finding non-metal materials that exhibit magnetic properties. Until recently, a common problem

with non-metal materials found to exhibit magnetic properties was that they needed to be held at

very low temperatures (in the tens of Kelvin). Work published since 2000 by various researchers

has shown that carbon-60 with a rhombohedral structure is ferromagnetic at relatively high

temperatures [9]. The benefits of a device made from a material which is a natural electric

insulator and non-metal include lighter weight devices and increased power efficiency.

The spin lattice device, which is the subject of this report, is both non-metal and can be made

to electrically insulate. The calculated conduction band for a structure such as an antidot lattice

or the spin lattice discussed in this report is shown in figure 7.

Building Block of SpinFET Device

One theory predicts that spheres of radius 10nm, made of nonmagnetic semiconducting material

and connected by the same material to its nearest neighbor, will exhibit ferromagnetism when

there is exactly one electron trapped in each sphere. Ferromagnetism is believed to result from

Coulomb repulsion between adjacent electrons causing them to assume alternating spins. The

Coulomb repulsion is given in equation (4) (this discussion and equations follow directly from

[9]).
0.4 Fabrication and Characterization 9

Figure 7: Conduction band due to spin lattice confinement [8]

e2 f
κb
u ≡ ~2 5.7985
2m∗ a2
    
a a m f
= (4)
a0 b m∗ 2.9κ

Electronic Structure - Confinement

In the present research, a confining potential is produced at the Si02 surface by an applied gate

voltage. This is accomplished by etching lattice holes and thus producing localized potentials.

These potentials can be analyzed using Poisson’s equation in two or three dimensions. The

probability of an electron being found at a given lattice site is shown in figure 8. A more in depth

discussion is presented in references [7, 8, 9].

0.4 Fabrication and Characterization

A Keithley 4200-SCS is available in the University of Utah Microfab for conducting probe tests

and was used throughout this research. Measurements presented in this section used this platform

almost exclusively.
0.4 Fabrication and Characterization 10

Figure 8: Electron probabilities within a lattice of confining potentials [8]

0.4.1 Polysilicon NMOSFET Fabrication

The polysilicon self-aligning gate fabrication process is explained in detail in a Standard Op-

erating Procedure (SOP) hosted on the Microfab website [6]. The details of the SOP will not

be reproduced here, but deviations and process adjustments will be noted. The purpose of this

section is to present calculations, measurements and other characterization of device features.

Doping Profile

Measurements across multiple die were used to obtain an average resistivity. This was then used
Ω
to obtain the resistance in ohms per square (  ). The resistivity of the substrate was initially
Ω
R = 205  , which corresponds to an initial doping concentration of 2 × 1015 cm− 3. After doping
Ω
the resistivity dropped to R = 26.8  , which corresponds to a concentration of 1.5 × 1020 cm− 3.

The high concentration is due in part to the shallow depth of the doped boron layer.
0.4 Fabrication and Characterization 11

Gate Oxide

The target gate oxide thickness was 5nm. To accomplish this growth the wafer was placed in a

furnace at 1000◦ C under dry oxygen flow at 3.5 SLM for five minutes.

The actual device measured is shown in figure 9. The results of measurement are shown in

figure 10. Based on the area of the capacitor as shown, the resulting oxide thickness is calculated

in equation (5), where A is the area of the capacitor.

 
ox
tox = A
Cox
= 0.295 × 67.5 × 10−12

= 1.344nm (5)

Figure 9: Optical microscope image of substrate to polysilicon capacitor across gate oxide with
height and width marks.

The calculated oxide thickness, x, of a silicon dioxide layer after t seconds of growth is given

by equation (6) [3], where C0 is the surface concentration of oxygen, C1 is the number of molecules

in the sample, κ is the surface reaction rate, and τ is used to account for any initial oxide present.

For small values of t equation (6) can be re-written as (7).

0.4 Fabrication and Characterization 12

Figure 10: Substrate to Polysilicon capacitor across gate oxide Measurement

s 
D 2C0 κ2 (t + τ )
x= 1+ − 1 (6)
k DC1

C0 κ
x= (t + τ ) (7)
C1

Using the above equations the calculated thickness is expected to be 7.34nm, nearly six times

larger than what was measured. closer examination of the C-V curves measured on the part and

shown in figure 10 indicate that the polysilicon layer may be depleting (see [3]). It is expected

that the oxide layer is closer to that which was calculated and the incorrect measurement is due

to depletion in the polysilicon.

Polysilicon resistor

A polysilicon test resistor was included among the devices on each die. The test resistor can be

used to determine the quality and doping profile of the polysilicon layer. Shown in figure 11 is

a resistance measurement across a polysilicon resistor. This measurement indicates a resistance

Ω
of R = 1.2  . Assuming a layer thickness of 50nm, this suggests a doping concentration greater

than 1021 cm−3 .

0.4 Fabrication and Characterization 13

Figure 11: Polysilicon Test Resistor Measurement

Aluminum Diffusivity

The diffusivity of aluminum (Al) in silicon (Si) is very high. One characteristic of an Al-Si system

that causes high diffusivity is that it becomes eutectic [3]. This means that the melting point

of the system is lower than either material independently. Due to the shallowness of the n-type

wells, the Al can easily spike through the n-type well and into the high p-type substrate. The

result is that a resistance is measured across the MOSFET from source to drain. This scenario

is illustrated in figure 12. A discussion of the volume of Al consumed and the depth to which

it is consumed can be found in [3], page 392. This type of spiking was observed in the devices

fabricated during this research.

Figure 12: Illustration of Al spiking into silicon

0.4.2 MOSFET Measurements and Characterization

Current vs. voltage characteristics (I-V) are a common measurement for MOSFET devices.

Shown in figure 13 is an actual device fabricated in the lab. The corresponding I-V characteristics
0.4 Fabrication and Characterization 14

are shown in figure 14. Note that these measurements were taken before annealing.

Figure 13: 10µm gate polysilicon MOSFET

Figure 14: Substrate to Polysilicon capacitor across gate oxide Measurement

0.4.3 SpinFET

Initial results from Scanning Electron Microscope (SEM) lithography are promising and have

yielded a feature size of 100nm. An SEM image of a spin lattice patterned on top of a polysilicon

NMOSFET is shown in figure 15. Etch rates and methods for each layer, both polysilicon and

oxide, are being explored.

0.5 Conclusions and Recommendations 15

Figure 15: Spin Lattice Patterned Using SEM Lithography (Justin Jackson)

0.5 Conclusions and Recommendations

Interest in producing devices that harness both the charge and spin of electrons is growing. Such

devices present several potential benefits in theory, including reduced power consumption, faster

operating speeds and smaller design features which increases the density of components that can

be placed on a die. Commercially viable means for producing spin devices are not yet available.

Some of the fabrication techniques presented in this research make possible prototype devices.

Two benefits gained by choosing the NMOSFET as a basis for future spin devices. First is

the maturity of both research and commercial fabrication techniques and methods. Second, the

NMOSFET provides an integrated testing device with ample data for correlation of results.

Future work should include adjustments to the thickness of the polysilicon layer to limit

the effects of depletion. Lower substrate doping concentration will reduce the threshold voltage,

allowing the devices to turn on at a standard voltage (1-3V). Aluminum spiking can be eliminated

with the use of a barrier metal layer, such as TiN. In addition to the recommendations made

above, further exploration of optical lithography techniques for the spin lattice is needed. This

will ensure that once realized in the lab, these devices will be ready for commercial fabrication.
0.6 Ethical Appendix 16

0.6 Ethical Appendix

0.6.1 Ethical Issues Encountered

Unfortunately, all too often the ethical consequences of modern research are outside the scope

of the microscope. The scale and precision required to fabricate nano-scale devices can be so

demanding that one hardly has time to consider the ultimate destination of the chemical byprod-

ucts produced during fabrication, or even their more immediate effect on the researcher. The

cleanroom environment with its endless hum of air purification equipment, conditioned light, and

restrictive clothing can be numbing. Ultimately, fabrication labor, distribution and real world

use are so far, in both space and time, from the labs of research that they might initially escape

the view of the scientist or engineer.

The chemicals used in a modern nano-scale semiconductor fabrication laboratory can be dan-

gerous and even deadly. Chemicals in both liquid and gas form are used throughout a typical

fabrication process to make modifications to a silicon (or other semiconductor) wafer. The chem-

icals used to clean, dope, etch or otherwise process silicon are rarely consumed completely in

the process and must be disposed of. Some are released into the air, other contaminants may

be released into waterways. As the demand for semiconductor devices increases, so can the

contamination, if not managed properly.

Large scale production, like initial research, will take place in a clean room environment. The

precision and sensitivity of the machinery used to fabricate semiconductor devices often requires

that it operate continually in order to limit the frequency of costly calibration. This imposes an

indirect requirement on future laborers to work long shifts and a clean room environment. For

example, a 12 hour shift in a cleanroom is common in today’s semiconductor industry.

As labor demands increase and market forces push prices lower many companies look to

foreign labor to help cut costs. Foreign labor often represents less expense not only in wage,

but also in retirement, health and other benefits. This may mean that instead of creating new

jobs, the advancement in technology has actually reduced the number of jobs available to native

candidates.

Many of these considerations don’t apply uniquely to the semiconductor industry. They
0.6 Ethical Appendix 17

are, nevertheless, ethical considerations that accompany the development of new technologies.

Chemical byproducts, labor conditions and labor sources all represent ethical issues that arise

with the development of new technology, such as the SpinFET that is presented in this research.

0.6.2 Ethical Impact

A discussion of the impact of a new nano-scale semiconductor device is potentially premature and

challenging. What could James Clerk Maxwell have said would be the impact of his efforts to

unify electricity and magnetism. That single, marvelous feat has completely changed the world

including communications, medicine, manufacturing, agriculture, etc. He could scarcely have

imagined the impact of his research and publications.

While the subject of this research is not being compared to the novelty of Maxwell’s equations,

it still stands that as new semiconductor devices are created there will be an impact on society.

There will be labor issues, environmental issues and even implementation issues. Some people

will want to use technology for war, and others for peace.

The impact of the SpinFET devices, which are the subject of this research, could be used to

implement low power electronics, new ultra-fast communications and even quantum computing.

It is the hope of the author, that any discovery pertaining to his research would be used to make

the world a better place and improve quality of life.

Bibliography

[1] International Technology Roadmap for Semiconductors, International Technology

Roadmap for Semiconductors 2005, Lithography http://www.itrs.net/Links/2005ITRS/

Litho2005.pdf; accessed September 26, 2006.

[2] Simon M. Sze, Physics of Semiconductor Devices, Wiley-Interscience; 2nd edition September

1981

[3] Simon M. Sze, Semiconductor Devices, Physics and Technology, John Wiley & Sons, Inc.;

2nd edition 1985

[4] Yuan Taur, Tak H. Ning Fundamentals of Modern VLSI DEVICES, Cambridge University

Press 1998

[5] Charles M. Wolfe, Nick Holonyak, Gregory E. Stillman Physical Properties of Semiconduc-

tors, Prentice Hall February 1989

[6] Mike Sorenson, Justin Jackson, Self-Aligning Polysilicon Gate MOSFETTechnol-

ogy Description & Documentation http://microfab.utah.edu/TechnologyLibrary/

PolySiliconGateCMOS2004/selfalignpolygate.htm; accessed September 26, 2006.

[7] D. C. Mattis, On the Origin of d-Wave Pair Functions in High-Tc Superconductivity, Inter-

national Journal of Modern Physics September 20, 2006

[8] D. C. Mattis, T. Sjostrom, Bloch’s Theorem in Nanoarchitectures, Modern Physics Letters

April 10, 2006

[9] Daniel C. Mattis, Design of a Nanomagnet, Journal of Statistical Physics June 14, 2003