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Department of ECE (ME-APP)



1. Compare Antifuse and static RAM programming Technologies.
Antifuse programming Technologies
static RAM programming Technologies
configuration cell is used to program
normally it is an open circuit
until forcing a programming current through it
for programming FPGA
Programming current controls the antifuse
resistance (typically for 5mA it is 500
In-system programming (ISP) possibility to
program the chip after it has been assembled on
the PCB
Antifuse-based devices are programmed offline using a special device programmer.

reuse chip during

prototyping reconfigurable
In-system programming (ISP) possibility to
program the chip after it has been assembled on
the PCB
SRAM-based devices are programmed
while resident in the system,

2. Compare FPGA and CPLD?

CPLD's have a much higher capacity than simple PLDs, permitting more complex logic circuits
to be programmed into them. A typical CPLD is equivalent of from 2 to 64 simple PLDs. The
development of these devices followed simple PLD as advances in technology permitted higher
density chips to be implemented. There are several forms of CPLD, which vary in complexity and
programming capability. CPLDs typically come in 44 to 160 pin packages depending on the
FPGA are different from simple PLDs and CPLDs in their internal organization and have the
greatest logic capacity. FPGAs are consists of an array of anywhere from 64 to 1000s of logic
gate groups that are sometimes called logic blocks. Two basic classes of FPGAs are fine grained
and course grained .The course grained FPGA has large logic blocks and fine grained FPGAs has
much smaller logic blocks. FPGAs are come in packages up to 1000 pins are more.
3. Differentiate CBIC & Gate array logic?

Gate array logic

In a gate array (GA) or gate-array
based ASIC the transistors are
predefined on the silicon wafer.
it is often called a masked gate
array (MGA).

Cell-based IC uses predesigned logic cells (AND

gates, OR gates, multiplexers, and flip-flops, for
CBIC means a standard-cellbased ASIC

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Department of ECE (ME-APP)

The standard-cell areas in a CBIC are built of rows

of standard cells. The standard-cell areas may be
used in combination with larger predesigned cells,
known as megacells.

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The logic cells in a gate-array library

are often called macros.


4. Differentiate the PLA from the PAL and PROM?

It has programmable logic
And array is fixed and
with a fixed OR matrix and
OR array is
programmable AND matrix.

Cheaper and simple to



5. Draw the Block Diagram of EX-OR registered output PAL?

6. Draw the Block Diagram of GAL macro cell?

Both AND and OR arrays are
is programmable.
Costliest and complex
than PROMs.

7. List out the types of PAL structure?

Combinational output
Registered output
XOR-Registered output
8. List out three main parts of FPGA & what is PMS?
CLB-Configurable Logic Block
IOB-Input Output Block
PMS-Programmable Switch Matrix
9. List the types of ASIC?
Full-Custom ASICs
Semicustom ASICs :
Standard-CellBased ASICs
Gate-ArrayBased ASICs
Channeled Gate Array
Channelless Gate Array
Structured Gate Array

Programmable ASICs , for which all of the logic cells are predesigned and none of the
mask layers are customized.
Programmable Logic Devices
Field-Programmable Gate Arrays
10. What is Anti fuse?
Anti fuse is an open circuit until forcing a programming current through it
Actel calls its antifuse a programmable low-impedance circuit element (PLICE)
It is an One Time Programming (OTP) technology
Programming current controls the antifuse resistance (typically for 5mA it is 500 Ohms)
11. What is Burning of PROM?
The process of entering data into the PROM by burning internal fuses is called programming or
burning a PROM.
12. What is Full custom ASIC? or What are the features of full custom ASIC? (April15)
To modify according to a customer's individual requirements
All mask layers are customized in a full-custom ASIC
a. Generally, the designer lays out all cells by hand
b. Some automatic placement and routing may be done
c. Critical (timing) paths are usually laid out completely by hand
Full-custom design offers the highest performance and lowest part cost (smallest die size) for a
given design
The manufacturing lead time (the time it takes just to make an ICnot including design time) is
typically eight weeks for a full-custom IC.
13. What is GAL? Give example?
GAL is the Generic Array Logic device
The GAL devices gave them significant advantages over their bipolar PAL counterparts; not only
could GAL devices be programmed quickly and efficiently, but they could also be erased and
reprogrammed. Example: GAL16V8
14. What is Hot electron effect in FAMOS?
Altera MAX 5000 EPLDs and Xilinx EPLDs both use UV-erasable electrically programmable
read-only memory ( EPROM ) cells as their programming technology. The EPROM cell is almost
as small as an antifuse. An EPROM transistor looks like a normal MOS transistor except it has a
second, floating, gate. Applying a programming voltage V PP (usually greater than 12 V) to the

drain of the n- channel EPROM transistor programs the EPROM cell. A high electric field causes
electrons flowing toward the drain to move so fast they jump across the insulating gate
oxide where they are trapped on the bottom, floating, gate. We say these energetic electrons are

the effect is known as hot-electron injection or avalanche injection. EPROM

technology is sometimes called floating-gate avalanche MOS ( FAMOS ).
15. What is OTP & ISP?
In-system programming (ISP) possibility to program the chip after it has been assembled on
the PCB
OTP: One Time Programming
16. What is personality matrix in PLA & give example?
Personality matrix is the Matrix giving the details of PLA structure personalized by making or
breaking the connections among the gates.
Example Functions for PLA Structure:

Personality matrix:

17. List the CAD tools used in different stages of ASIC Design.



Circuit Designer

Initial floor
Behavioural Simulation
Logical Simulation
Synthesis Datapath
Cell libraries
Circuit Schematics

Text Editor C Compiler

RTL Simulator
Synthesis Tools
Timing Analyzer Power Estimator

Circuit Simulation
Megacell blocks

Physical Design

Schematic Editor
Circuit Simulator Router

Layout and floorplan

Place and route
Parasitic Extraction
Place/Route Tools
Physical Design and Evaluation

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18. What is SOG?

A channelless gate-array is called sea-of-gates (SOG) array. The core area of the die
is completely filled with an array of base cells (the base array).
19. What is the number of Fuses in PLA general structure & Draw the sequential
PLA structure?
(2n x k) + (k x m) + m
Where n is number of input variables k is number of products and m is number of
output functions
20. Write the objectives and Goals of System Partitioning?
The goal of partitioning is to divide this part of the system so that each partition is a single
ASIC. To do this we may need to take into account any or all of the following objectives:
A maximum size for each ASIC
A maximum number of ASICs
A maximum number of connections for each ASIC
A maximum number of total connections between all ASICs
21. Differentiate PAL and PLA.
It has programmable logic
Both AND and OR arrays are
with a fixed OR matrix and
is programmable.
programmable AND matrix.


Costliest and more



Explain the architecture of CPLD with neat diagram

With design flow, explain the sequence of steps involved in the ASIC design process.
Describe the different types of ASIC design
Design 4-bit gray code counter using sequential PAL.
Implement BCD to XS-3 code converter using PLA
(a) Explain CAD tools used in ASIC design

(b) Implement 2-bit binary multiplier using ROM

7. (a) Explain the operation of SRAM, EPROM and EEPROM Programming cell.
(b) Write note on Antifuse programming technology.
1. Define Ratio cut in partitioning sizes
The ratio-cut algorithm removes the restriction of constant partition sizes.
The cut weight W for a cut that divides a network into two partitions, A and B , is given by
c ab
a A,b B
The KL algorithm minimizes W while keeping partitions A and B the same size. The ratio
of a
cut is defined as
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R =
In this equation | A | and | B | are the sizes of partitions A and B. The size of a partition is
equal to the number of nodes it contains.
2. Distinguish between Global and Detailed routing
Global routing allocates routing resources that are used for connections. Detailed
routing assigns routes to specific metal layers and routing tracks within the global
routing resources.
The goal of global routing is to provide complete instructions to the detailed router on
where to route every net.
The global routing step determines the channels to be used for each interconnect.
Using this information the detailed router decides the exact location and layers for
each interconnect.
The goal of detailed routing is to complete all the connections between logic cells.
3. Distinguish between system partitioning and floor planning.
system partitioning
floor planning Gate array logic
Divide a large system into ASIC-sized pieces
Arrange the blocks of the netlist on the
4. Expand the terms DRC, SPF, RSPF and DSPF
SPF: Standard Parasitic
Format RSPF: Reduced SPF
DSPF: Detailed
5. List out the different types of partitioning methods.
A Simple Partitioning
Constructive Partitioning
Iterative Partitioning
Improvement The
Algorithm The Ratio-Cut
The Look-ahead
Algorithm Simulated
6. List the factors that are to be considered during floor planning.
The parasitics associated with interconnect: the interconnect capacitance (wiring
capacitance or routing capacitance) as well as the interconnect resistance.
7. What are the objectives and goals of detailed routing?
The goal of detailed routing is to complete all the connections between logic cells. The
most common objective is to minimize one or more of the following:
The total interconnect length and area
The number of layer changes that the connections have to make
The delay of critical paths
8. What are the objectives and goals of placement? (April 15)
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The goal of a placement tool is to arrange all the logic cells within the flexible blocks on a
chip. Ideally, the objectives of the placement step are to
Guarantee the router can complete the routing step
Minimize all the critical net delays
Make the chip as dense as possible
Minimize power dissipation
Minimize cross talk between signals
What are the steps involved in min-cut placement algorithm?
1. Cut the placement area into two pieces.
2. Swap the logic cells to minimize the cut cost.
3. Repeat the process from step 1, cutting smaller pieces until all the logic cells are placed
What are the steps involved in the physical design of ASICs?
Design Netlist (after synthesis)
Clock-tree Synthesis (CTS)
Physical Verification
What is channel definition?
During the floorplanning step we assign the areas between blocks that are to be used
for interconnect. This process is known as channel definition or channel allocation .
What is power routing?
Power routing is the process of distributing two stacked layer of metals one for Vdd and
one for Gnd on a chip in various ways.
Power routing is performed after cell placement, allowing more knowledgeable
placement of power structures in the physical layout. Each of the power buses has to be
sized according to the current it will carry. Too much current in a power bus can lead to a
failure through a mechanism known as electro-migration. The required power-bus widths
can be estimated automatically from library information, from a separate power simulation
tool, or by entering the power-bus widths to the routing software by hand. Many routers
use a default power-bus width so that it is quite easy to complete routing of an ASIC.
What is the need for DRC in ASIC design?
ASIC designers perform a design-rule check (DRC) before fabrication to ensure that nothing
has gone wrong in the process of assembling the logic cells and routing. The DRC may be
performed at two levels. The first level of DRC is a phantom-level DRC, which checks for
shorts, spacing violations, or other design-rule problems between logic cells. This is
principally a check of the detailed router. A second-level DRC is performed at the
transistor level. This is principally a check of the correctness of the library cells.
Write the objectives and goals of floor planning.
The goals of floorplanning are to:
arrange the blocks on a chip,
decide the location of the I/O pads,
decide the location and number of the power pads,
decide the type of power distribution, and

decide the location and type of clock distribution.

The objectives of floorplanning are to minimize the chip area and minimize delay.
15. List the advantages of Global routing
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Global routing allocates routing resources that are used for connections.

The global routing is used to provide complete instructions to the detailed router on where
to route every net.
The global routing step determines the channels to be used for each interconnect. Using this
information the detailed router decides the exact location and layers for each interconnect.
It Minimize the total interconnect length and the critical path delay.
16. State the governing equation for RC interconnect delay model.

17. Define the terms Circuit extraction and Back annotation.

Back annotation: The global router can give us not just an estimate of the total net length, but
the resistance and capacitance of each path in each net.This RC information is used to calculate
the net delays. We can back annotate this net delay information to the synthesis tool for in
place optimization or to a timing verifier to make sure there are no timing surprises. Differences
in timing prediction at this point arise due to different ways in which the different algorithms
estimates the path and the way the global router actually builds the path.
Circuit extraction: After detailed routing is complete, the exact length and position of each
interconnect for every net is known. The parasitic capacitance and resistance associated with
each interconnect, via, and contact can be calculated .This data is generated by circuit
extraction tool.
18. Define sliceable floor plan
If the floor plan is sliced into pieces without cutting the block it is called sliceable floor plan.
19. Write the constraints used in system partitioning?
Timing constraints

Power constraints

Technology constraints

Cost constraints

Test constraints
20. What is Simulated annealing?
A different approach to solving large graph problems that arise in VLSI layout, including
system partitioning uses the simulated annealing algorithm.
It takes an existing solution and then makes successive changes in a series of random moves.
Each move is accepted or rejected based on an energy function, calculated for each new trail
The minimums of the energy function correspond to the possible.
The best solution is the global minimum.
21. What is meant by half perimeter measure?

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The half perimeter measure is one-half the perimeter of the bounding box. For nets with two or
three terminals, the half perimeter measure is same as the minimum steiner tree. The bounding
box is the smallest rectangle that encloses all the terminals.
1. (a) Explain in detail Iterative Partitioning improvement algorithm.
(b) Explain the various steps involved in Floor Planning.
2. (a) Describe the Kernighan-Lin Algorithm.
(b) Differentiate between Global and special routing
3. Discuss in detail circuit extraction and DRC. (April15)
4. Explain the following in the context of floor planning and placement
(a) Cyclic constraints
(b) Channel routing
(c) Clock planning
5. Briefly explain left edge and area routing algorithms.
6. (a) Explain the ASIC physical design flow.
(b) Describe the algorithms used for placement and routing.
7. Write short notes on:
(a) Floor planning tools
(b) Global routing between blocks
(c) Clock routing
8. Explain any one type of partitioning method with example.(April15)


1. Define EDIF. Draw the hierarchial nature of an EDIF file.
One communication standard for exchanging information between EDA tools is the
electronic design interchange format ( EDIF ).

The hierarchial nature of an EDIF file

2. Define Fault Collapsing

Equivalence collapsing: It is possible that two or more faults, produce same faulty
behavior for all input patterns. These faults are called equivalent faults. Any
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single fault from the set of equivalent faults can represent the whole set. In this
case, much less than kn fault tests are required for a circuit with n signal line.
Removing equivalent faults from entire set of faults is called fault collapsing. Fault
collapsing significantly decreases the number of faults to check.Dominance
collapsing: Fault F is called dominant to F' if all tests of F' detects F. In this case, F
can be removed from the fault list. If F dominates F' and F' dominates F, then these
two faults are equivalent.
Functional collapsing: Two faults are functionally equivalent if they produce
identical faulty functions or we can say, two faults are functionally equivalent if we
cannot distinguish them at primary outputs (PO) with any input test vector.
Define the term behavioral simulation.
There are several ways to create an imaginary simulation model of a system. One
method models large pieces of a system as black boxes with inputs and outputs.
This type of simulation (often using VHDL or Verilog) is called behavioral
Define the terms fault equivalence and fault dominance.
Fault Equivalence: Two faults of a Boolean circuit are called equivalent iff they
transform the circuit such that the two faulty circuits have identical output functions.
Equivalent faults are also called indistinguishable and have exactly the same set of
Example: An input line s-a-0 and output line s-a-0 in an AND gate.
Fault Dominance: If all tests of fault F1 detect another fault F2, then F2 is said to
dominate F1. The two faults are also called conditionally equivalent with respect
to the test set of F1. When two faults F1 and F2 dominate each other, then they are
State the objectives of prelayout and postlayout simulation.
Prelayout simulation: Check to see if the design functions correctly.
Postlayout simulation: To check the design still works with the added loads of the
interconnect after physical layout is made and then sent to fabrication.
What are the data formats supported in verilog?
Net: Physical connection between structural elements declared with keyword wire.
Register: Registers represent data storage elements. Registers retain value until another
value is placed onto them. It is declared with keyword reg.
What are the types of simulation?

Behavioral simulation
Functional simulation
Static timing analysis
Gate-level simulation
Switch-level simulation
Transistor-level or circuit-level simulation

8. Distinguish between structures and procedures in VHDL.

Structures in VHDL

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Procedures in VHDL



Structure in VHDL allows the

designer to represent a system in
terms of components and their
interconnections. This module
discusses the constructs available
in VHDL to facilitate structural
descriptions of designs.

Functions and procedures are collectively referred to as

subprograms in VHDL
Functions and procedures in VHDL provide a mechanism
for representing commonly used logic functions, and
especially overloaded functions and procedures for
supporting types such as std logic.
Procedures are widely used to ease the writing of
testbenches and to structure testbenches into understandable
sections of code.
A procedure does not return a value, but does formal
parameters that are replaced by the values of the actual
Procedures Syntax:
procedure <procedure_name> ( <formal_parameter_list> ) is
<list of subprogram
declarations> begin
<list of sequential statements>
end procedure <procedure_name>;

9. What are the features of EDIF?

The most important features added in EDIF 3 0 0 were to handle buses, bus rippers,
and buses across schematic pages. EDIF 4 0 0 includes new extensions for PCB and
multichip module(MCM) data. The Library of Parameterized Modules ( LPM )
standard is also based on EDIF. The newer versions of EDIF have a richer feature
set, but the ASIC industry seems to have standardized on EDIF 2 0 0. Most EDA
companies now support EDIF. The FPGA companies Altera and Actel use EDIF as
their netlist format, and Xilinx has announced its intention to switch from its own XNF
format to EDIF.
10. What is logic synthesis?
Logic synthesis provides a link between an HDL (Verilog or VHDL) and a netlist similarly to
the way that a C compiler provides a link between C code and machine language. Logic
synthesis forces designers to use a subset of both Verilog and VHDL.
11. What is the purpose of ATPG?
Automatic Test Pattern Generation(ATPG) is used to generate the test vectors for testing
the digital circuit using 5-valued D-Algorithm.
12. What is the use of Portmap in VHDL?
The keyword portmap is used in component instantiation statement in
VHDL The component instantiation statement references a component that
can be
Previously defined at the current level of the hierarchy or
Defined in a technology library (vendors library).
The syntax for the components instantiation is as follows,
instance_name : component name
port map (port1=>signal1, port2=> signal2, port3=>signaln);
The instance name or label can be any legal identifier and is the name of this particular
instance. The component name is the name of the component declared earlier using the
component declaration statement. The port name is the name of the port and signal is the
name of the signal to which the specific port is connected. The above port map associates
the ports to the signals through named association
13. Why is parallel fault simulation necessary in ASIC design?
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Parallel fault simulation takes advantage of multiple bits of the words in computer memory.
In the simplest case we need only one bit to represent either a '1' or '0' for each node in the
circuit. In a computer that uses a 32-bit word memory we can simulate a set of 32 copies of
the circuit at the same time. One copy is the good circuit, and we insert different faults into
the other copies. When we need to perform a logic operation, to model an AND gate for
example, we can perform the operation across all bits in the word simultaneously. In this
case, using one bit per node on a 32- bit machine, we would expect parallel fault
simulation to be about 32 times faster than serial simulation. The number of bits per node
that we need in order to simulate each circuit depends on the number of states in the logic
system we are using. Thus, if we use a four-state system with '1', '0' , 'X' (unknown), and 'Z'
(high-impedance) states, we need two bits per node.
14. Write the syntax of loop statement used in VHDL.
Basic Loop statement: This loop has no iteration scheme. It will be executed continuously
until it encounters an exit or next statement.
[ loop_label :] loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
end loop [ loop_label];
While-Loop statement: The while loop evaluates a Boolean iteration condition. When
the condition is TRUE, the loop repeats, otherwise the loop is skipped and the execution
will halt. The syntax for the whileloop is as follows,
[ loop_label :] while condition loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
end loop[ loop_label ];
The condition of the loop is tested before each iteration, including the first iteration. If it is
false, the loop is terminated.
For-Loop statement: The for-loop uses an integer iteration scheme that determines the
number of iterations. The syntax is as follows,
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
end loop[ loop_label ];
The identifier (index) is automatically declared by the loop itself, so one does not
need to declare it separately. The value of the identifier can only be read inside
the loop and is not available outside its loop. One cannot assign or change the
value of the index. This is in contrast to the while-loop whose condition can
involve variables that are modified inside the loop.
The range must be a computable integer range in one of the following
forms, in which integer_expression must evaluate to an integer:
integer_expression to integer_expression
integer_expression downto integer_expression
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15. Give the syntax for data types in VHDL.

Access data types
Scalar data types: Integer, Real, Enumerated & Physical
Composite data types: Array & Record
Data Types defined in the Package Standard of the std Library
Range of values
0, 1
signal A: bit :=1;
an array with each element of
signal INBUS: bit_vector(7
type bit
downto 0);
variable TEST: Boolean
constant CONST1: integer :=129;
range is implementation
dependent but includes at least
(2 31 1) to
+(2 1)
16. What are the features of ATPG?

A basic algorithm to generate test vectors automatically

Detect a fault by first activating (or exciting the fault) in the selected node
using D- calculus

By using Path sensitized method the activated faulty node is controlled and
observed through Primary inputs and outputs.

This basic algorithm of justifying and then propagating a fault works for the
nodes without interference from other nodes.
17. Define PODEM algorithm and its advantages
The path-orianted decision making algorithm solves problem of reconvergent fanout and
allows multipath sensitization. The mathed is similar to the basic algorithm.
18. What are the signals used in BST
TDI-test data input
TDO-test data output
TCK-test clock
TMS-test mode select
19. Define transistor-level simulation
The most accurate but also the most complex & time consuming form of simulation is
transistor level simulation.
20. Write the program for half adder in VHDL
library IEEE;
entity hadd is
port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
sum <= a xor b;
carry <= a and
end dataflow;

1. (a) Write a VHDL program for the Full adder and 4-bit serial in serial out register.
(b) Write briefly about the different types of simulation carried out for Logic synthesis.
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2. Discuss in detail about the various combinational and sequential statements used in VHDL
using suitable example.
3. (a) Explain the four basic parts of boundary scan controller.
(b) Describe the deterministic and non deterministic fault simulation algorithms.
4. (a) Discuss the different delay statements available in Verilog HDL and describe how a
sequential circuit can be modeled using Verilog HDL.
(b) Explain any three simulation modes of a simulator.
5. (a) How priority encoder and 8:1 MUX is modeled using behavioral and data flow modeling?
(b) Discuss inertia and transport delay used in signal assignments in VHDL.
6. (a) Compare and contrast ATPG and BIST schemes.
(b) Write notes on CFI Design Representation
7. Describe the following:
(a) Boundary Scan Test
(b) Automatic Test pattern generator.
1. Expand FLEX and MAX.
Flexible Logic Element MatriX (FLEX)
Multiple Array Matrix (MAX)
2. Differentiate fine-grain and coarse-grain architecture of FPGA
Fine-grained Architecture
Manipulate data at the bit level
Designers can implement bit manipulation
tasks without wasting reconfigurable
For large and complex calculations numerous
fine- grained PEs are required to implement a
basic computation
Much slower clock rates
Extremely costly relative to coarsegrained architectures
Supports partial array configuration and is
dynamically reconfigurable during
application execution.

Coarse-grained Architecture
Manipulate groups of bits via complex functional
units such as ALUs (arithmetic logic units) and
resources are wasted during
data manipulation
Fewer coarse-grained PEs are required to
implement a basic computation
Less Expensive
Both partially and dynamically reconfigurable

3. Differentiate the features of ALTERAs FLEX 8000/10000

Low-cost, high-density, register-rich CMOS
programmable logic device (PLD) family
2,500 to 16,000 usable gates
282 to 1,500 registers


The industrys first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
to 250,000 typical gates
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic

4. Draw the logic block of Actel ACT2 module

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5. How clock is generated and distributed in cyclone FPGA?

Cyclone PLLs provide general-purpose clocking with clock multiplication and phase
shifting as well as external outputs for high-speed differential I/O support. Each
Cyclone device is served by a global clock network composed of up to eight distinct
clock lines. These clock lines are accessible from anywhere in the device and can
be fed either by input pins, PLL outputs, DDR/PCI inputs, or internal logic.
6. List out the advantages of Spartan-II FPGA.
The Spartan-II Field-Programmable Gate Array family gives users high
performance, abundant logic resources, and a rich feature set, all at an exceptionally low
The six-member family offers densities ranging from 15,000 to 200,000 system gates.
System performance is supported up to 200 MHz.
The Spartan-II family is a superior alternative to mask-programmed ASICs. The
FPGA avoids the initial cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits design upgrades in the
field with no hardware replacement necessary (impossible with ASICs).
7. List out the components of cyclone FPGA
The logic array consists of Logic Array Blocks (LABs), with 10 LEs in each LAB.
- An LE is a small unit of logic providing efficient implementation of user
logic functions.
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus
parity (4,608 bits).
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB
rows and columns around the periphery of the device.
Cyclone devices provide a global clock network and up to two PLLs.
8. State the Xilinx FPGA design flow.
VHDL description
Functional simulation
Post-synthesis simulation
Timing simulation
On chip testing
9. What are the different types of interconnections present in Xilinx FPGA?
Direct interconnect: Adjacent CLBs are wired together in the horizontal or vertical
direction. The most efficient interconnect.
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General-purpose interconnect: used mainly for longer connections or for signals

with a moderate fan-out.
Long line interconnect: for time critical signals (e.g. clock signal need be distributed to
many CLBs)
10. What is meant by speed grading?
Most of the FPGA header short chip according to speed is called speed binning or speed
grading. According to Xilinx FPGA product, The speed grade specify the transistor switching
speed that determines how quickly internal clocked circuits can be activated.
11. What is meant by BIDA?
The Bidirectional Interconnect Buffers(BIDA) restore the logic level and logic strength on
long interconnect paths.
12. Define OEM?
For any ASIC, a designer needs design-entry software, a cell library and physical design
software. Often designers buy that software from FPGA vendor. This is called an Orginal
Equipment Manufacturer (OEM) arrangement.
13. What is the function of DLL in Spartan-II FPGA?
Eliminate skew between clock input pad & internal clock input pins throughout the devices
DLL drives 2 global network; Clock mirror; Eliminate clock distribution delay
14. What is fully PCI in Spartan-II FPGA?
Fully Peripheral Component Interface (PCI) used to interface components
15. What is JTAG?
Joint Test Action Group (JTAG)
16. Differentiate between Altera MAX 9000 and Altera FLEX interconnects architecture?
The MAX 9000 is a coarse-grained architecture. Complex PLDs with arrays that are
themselves arrays of macrocells have a dual-grain architecture. The FLEX architecture is of
finer grain than the MAX arrays because of the difference in programming technology. The
FLEX horizontal interconnect is much denser than the vertical interconnect creating an aspect
ratio of 10:1
What are the advantages and disadvantages of FPGA
compared to ASIC?
Faster time-to-market since none of the mask
layers are customized
Simpler design cycle due to software that handles
much of the routing, placement, and timing
Field reprogramability- A new bit stream can be
uploaded remotely
Design turnaround is a few hours

Full custom capability for design since
device is manufactured to design specs
Design cycle is not simple.
Field reprogramability is not possible
Two days to two weeks

18. What is the function of DLL in Spartan-II FPGA?

Eliminate skew between clock input pad & internal clock input pins throughout the
DLL drives 2 global network
Clock mirror
Eliminate clock distribution delay
19. What is the difference between C and S module in ACT-3 logic module
ACT-3 C module
ACT-3 S module
The C module is designed to implement high
combinatorial macros, such as 5-input AND, 5input OR, and so on.
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The S-module is designed to implement

high-speed sequential functions within a single

20. Define segmented Channel routing?

FPGA is a channeled architecture. The logic modules which implement various types of logic
functions are placed in predefined rows. Channels are defined in between rows of logic
modules for routing of nets. The rows of logic modules are called tracks. The tracks are
divided into different segments which can be connected together by programming a horizontal
antifuse. Each input and output of a logic module is connected to a dedicated vertical segment.
Cross antifuses are located at the crossing of each horizontal and vertical segment.
Programming these antifuses produces a bi-directional connection between the horizontal and
vertical segments for routing of nets via channels. This structure of FPGA is called segmented
channel routing.
1. (a) Explain the Configurable Logic Block and IO block of Xilinx XC4000 FPGA.
(b) List the features of Xilinx XC4000 FPGA.
2. Explain ACTELs ACT 1 logic cell and describe the MUX realization of 2-variable
3. Explain in detail the following:
(a) Actel ACT Interconnect Architectures.
(b) Xilinx LCA Interconnect Architectures.
4. Describe the feature and the internal architecture of Altera MAX 9000.
5. Compare the features of APEX and Cyclone FPGA and explain Logic Cell diagram.
6. Explain the architecture and feature of Spartan-II FPGA.
7. Explain Xilinx Vertex II FPGA architecture.
1. List the buses used in SoC interconnection.
AMBA (Advanced Microcontroller Bus Architecture) is a collection of buses from
ARM for satisfying a range of different criteria.
APB (Advanced Peripheral Bus): simple strobed-access bus with minimal
interface complexity. Suitable for hosting peripherals.
ASB (Advanced System Bus): a multimaster synchronous system bus.
AHB (Advanced High Performance Bus): a high- throughput synchronous system
backbone. Burst transfers and split transactions.
2. What is IP core?
The predesigned modules are commonly called Intellectual Property (IP) cores or Virtual
Components (VC).
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Utilizing the predesigned modules enables:

to avoid reinventing the wheel for every new product,
to accelerate the development of new products,
to assemble various blocks of a large ASIC/SoC quite rapidly,
to reduce the possibility of failure based on design and verification of a block for the
first time.
What is codesign?
Hardware-Software Codesign is the concurrent and co-operative design of hardware
and software components of a system.
The SoC design process is a hardware-software codesign in which design
productivity is achived by design reuse.
The design process is the set of design tasks that transform an abstract specification
model into an architectural model.
What are the benefits of SoC?
An System on Chip (SoC) is an integrated circuit that implements most or all of the
function of a complete electronic system.
There are several benefits in integrating a large digital system into a single integrated
circuit These include
Lower cost per gate .
Lower power consumption .
Faster circuit operation .
More reliable implementation .
Smaller physical size .
Greater design security .
What is platform-based SoC?
Platform-based SoC design means to design SoC with relatively fixed architecture.
Thi is important to reduce dsign cycle and cost.
Platform-based SoC design can be defined as the creation of a stable SoC-based
architecture that can be rapidly extended, customized for a range of applications, and
delivered to customers for quick deployment."
Platform based SOCs are systems that contain
IP blocks like embedded CPU, embedded memory,
Real world interfaces (e.g., PCI, USB),
Mixed signal blocks and
Software components
device drivers, real-time operating systems and application code
What is reconfigurable SoC?
Reconfigurable SoCs (RSoCs), consisting of processor, memory, probably ASIC-cores,
and on-chip reconfigurable hardware parts for customization to applications.
RSoCs combine the advantages of both: ASIC-based SoCs and multichip-board
development using standard components
To combine large amounts of reconfigurable logic with embedded RISC processors in
order to allow very flexible combinations of HW and SW processing to be applied to
a particular design problem.
Although the resulting combination does not offer the highest performance, lowest
energy consumption, or lowest cost, in comparison with custom IC or ASIC/ASSP

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implementations of the same functionality, it does offer tremendous flexibility in

modifying the design in the field
Thus, new applications, interfaces, and improved algorithms can be downloaded to
products working in the field using this approach.
7. Write the characteristics of Embedded software.
One of characteristics of embedded software is that it is heavily dependent on the
underlying hardware. The reason of the dependency is that embedded software needs
to be designed in an application-specific way. To reduce the system design cost, e.g.
code size, energy consumption, etc., embedded software needs to be optimized
exploiting the characteristics of underlying hardware.
Embedded software design is not a novel topic.
8. List the functions of RTOS
An RTOS is an OS for response time-controlled and event-controlled processes. It is
very essential for large scale embedded systems.
Functions :
1. Basic OS function
2. RTOS main functions
3. Time Management
4. Predictability
5. Priorities Management
6. IPC Synchronisation
7. Time slicing
8. Hard and soft real-time operability
9. What is TAM?
TAM: Test Access Mechanism is used for SoC Testing.
Deliver test stimuli from the test source to the Circuit
Under Test (CUT).
Transport test responses from the CUT to the test sink.
List the types of Macros used in SoC
Soft Macro
Reusable synthesizable RTL or netlist of generic library elements.
User of the core is responsible for the implementation and layout.
Firm Macro
Structurally and topologically optimized for performance and area through floor
planning and placement.
Exist as synthesized code or as a netlist of generic library elements.
Hard Macro
Reusable blocks optimized for performance, power, size and mapped to a specific
process technology.
Exist as fully placed and routed netlist and as a fixed layout such as in GDSII
11. Name the division of SoC design flow by the Structural RTL level
SoC Design flow is divided by the Structural RTL level into:
Front End: specify, explore, design, capture, synthesise Structural RTL
Back End: Structural RTL place, route, mask making, fabrication.
12. List the Classification of IP Blocks
a. Soft IP (RTL):
i. High flexibility/low predictability
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ii. Synthesize from hardware description language (HDL)

b. Firm IP (gate level):
i. Medium flexibility/medium predictability
ii. Gate level netlist that is ready for P&R
c. Hard IP (layout level):
i. Low flexibility/high predictability
ii. Layout and technology dependent information
13. What are the three layers of System-on-a-chip manufacturing test?
a. The Core layer
b. The System layer
c. The Application layer.
14. Draw the SoC Test Architecture and list the functions of each components.

Test pattern source and sink

The source generates the test stimuli for the embedded core.
The sink compares the responses to the expected responses.
Test access mechanism (TAM)
Test data transport from the test source to the CUT and from the cut to the test sink
Core Test Wrapper
Connects the terminals of the core to the rest of the IC and the TAM
15. Draw the flowchart for typical codesign process.

16. What is Bluetooth?

Bluetooth is a wireless technology standard for exchanging data over short distances
(using short-wavelength UHF radio waves in the ISM(Industrial , Scientific and Medical)
band from 2.4 to 2.485 GHz) from fixed and mobile devices, and building personal area
Bluetooth is managed by the Bluetooth Special Interest Group (SIG), which has more than
19,000 member companies in the areas of telecommunication, computing, networking,
and consumer electronics.
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Bluetooth was standardized as IEEE 802.15.1, but the standard is no longer maintained.
17. List the components in Digital color camera SoC.
Pixel array, ADC, ASP, Timing & Control block and smart function digital block
18. What are the important factors contributed to the emergence of CMOS image sensor
over the CCD camera?
Recent demand for portable, low-power, miniaturized digital imaging systems.
Present-day CMOS offers submicron feature sizes and low defect and contamination
levels, permitting cost-effective pixel sizes and low junction leakage (or dark) current.
Threshold voltage control and uniformity is stable and reproducible.
New circuit techniques that have been invented or adopted from CCD signal processing,
permits both low noise and high dynamic-range imaging that is competitive with the best
9.What is USB, USB 3.0 Features and List the applications of USB?
Universal Serial Bus
USB 3.0 Features Two primary enhancements defined in the USB 3.0 protocol address
the PC and mobile market demands for higher performance and energy efficiency:
adding a second physical datapath and replacing continuous polling with an interruptdriven protocol.
PC Human Interface Devices (HID)
Peripheral Gaming Devices
Game Controllers
Console Keyboards
Presenter Tools
Remote Controls
Consumer Electronics
Barcode Scanners
POS Peripherals
10. List the features of SDRAM controller subsystem.
The SDRAM controller subsystem offers the following features:
Support for double data rate 2 (DDR2), DDR3, and low-power DDR2 (LPDDR2) SDRAM
User-configurable timing parameters
Up to 4 Gb density parts
Two chip selects
Integrated error correction code (ECC), 24- and 40-bit widths
User-configurable memory width of 8, 16, 16+ECC, 32, 32+ECC
Command reordering (look-ahead bank management)
Data reordering (out of order transactions)
User-controllable bank policy on a per port basis for either closed page or conditional open
page accesses
User-configurable priority support with both absolute and relative priority scheduling
Flexible FPGA fabric interface configuration with up to 6 ports and data widths up to 256
bits wide using Avalon-MM and AXI interfaces.
Power management supporting self refresh, partial array self-refresh (PASR), power down,
and LPDDR2 deep power down
1. Explain Embedded software development for SoC.

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Explain SoC architecture of Digital camera and SDRAM.

Explain Configurable SoC with neat block diagram.
Explain Hardware and Software codesign.
Explain Design Methodologies and Processes and Flows of SoC Design.
(a) Explain Bluetooth radio modem as SoC
(b) Write notes on USB.
7. Discuss the Techniques for SoC Testing.

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