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International Journal of Applied Engineering Research

ISSN 0973-4562 Volume 9, Number 20 (2014) pp. 7499-7508


Research India Publications
http://www.ripublication.com

Performance of a 3-Phase Asymmetrical Cascaded Subcell


Multilevel Inverter
Dhanamjayulu C1, Dr. Y Suresh 2,
Ponnambalam Pathipooranam3, Rashmi Ranjan Das4
1, 2, 3, 4

School of Electrical Engineering, VIT University, Vellore, India

Abstract
Asymmetrical cascaded sub cell multilevel inverter is proposed here in order
to overcome the disadvantages faced in the symmetrical cascaded multilevel
inverter. Asymmetrically cascaded sub cell model is generated by grouping up
basic unit cells in series connections in each phase of the model. DC supply
voltages of basic unit sub cells in each phase will have an arithmetic sequence
with common difference of E. Low frequency and high frequency pulse width
modulation techniques (PWM) can be used efficiently and easily for different
operating conditions. This proposed structure reduces the number of switching
devices, no. of driver circuits, reduces installing space for the proposed model,
cost and voltage across the switches.

I. INTRODUCTION
Generally there are many multilevel inverter structures such as Diode-Clamped
multilevel inverter (Neutral Point Clamped), flying-capacitor multilevel inverter and
cascaded multilevel inverter (symmetrical cascaded or cascaded H bridge multilevel
inverter).
Among the above three multilevel inverters cascaded H-bridge is mostly used due
to the major drawbacks in the diode clamped and flying capacitor multilevel inverter.
Disadvantages in diode clamped multilevel inverter are excessive clamping diodes are
required when the number of levels is high, it is difficult to control the real power
flow of the individual converter in the multi converter systems. And the disadvantages
in the flying-capacitor inverter are an excessive number of storage capacitors is
required when the number of levels is high and high level inverters are more difficult
to package with the bulky power capacitors and are more expensive too, and the
inverter control can be very complicated, and the switching frequency and switching
losses are high for real power transmission.

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A cascaded multilevel inverter consists of a series of H-bridge (single-phase full


bridge) inverter units. The general function of this multilevel inverter is to synthesize
a desired voltage from several separate DC sources (SDCSs), which may be obtained
from batteries, fuel cells, or solar cells. In the basic structure of a single phase
cascaded inverter with SDCSs, each SDCS is connected an H-bridge inverter. The ac
terminal voltages of different level inverters are connected in series. Unlike the diodeclamp or flying-capacitor inverter, the cascaded inverter does not require any voltageclamping diodes or voltage-balancing capacitors. In cascaded H-bridge multilevel
inverter, all the N basic H-bridge cells per phase will have equal voltage sources, so
that there will be 2N+1 level in the output phase voltages.
Therefore all the N H-bridge cells will be connected in order to develop single
phase output voltage. But to extract the three phase output voltage from this
configuration, H-bridge structures are needed in each of the three phases. This is not
preferable because numbers of switching devices required are more, separate equal
DC source voltage for each bridge. So to overcome all these disadvantages while
developing a three phase output voltage, a new topology is proposed i. e.
asymmetrical cascaded multilevel inverter with reduced number of switches and for
required number of voltage levels.
Here this model will be explaining in five sections. In first section, had about
discussed the introduction and scope of developing the asymmetrical cascaded
multilevel inverter model. In the second section, will be discussed about the proposed
topology. In the third section, will be discussed about the modulation techniques used
in the proposed model. In the fourth section, will be discussed about the proposed
model simulation and results obtained.
.
II. Proposed TOPOLOGY
Basic unit used to develop the proposed model with two switches is shown in fig. 1,
and the basic unit can be operated in two possible states shown in table. 1. In the basic
unit the two possible output levels are E and 0, with a single DC supply. The switches
should always be operated in inverted condition in order to reduce short circuit of DC
supply.

, 2
, 2

=0

The power circuit of proposed model is shown in the fig. 2. Which is a three phase
asymmetrical cascaded n-level inverter comprised of the basic units in each leg of the
circuit connected in series fashion. No. of basic units used will be according to the no.
of output levels required.
The power circuit shown in fig. 2 require different DC sources, where the DC
voltages connected in each leg should be in arithmetic sequence of common
difference E in magnitude. Here if more the no. of voltages levels required the more
will be the DC voltage sources required. The main advantage in this model is that the

Performance of a 3-Phase Asymmetrical Cascaded Subcell Multilevel Inverter

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DC voltage sources can be replaced with the renewable energy sources like
photovoltaic or fuel cells etc.
As defined above the DC voltage sources used in each leg of the inverter are as
below
1=
2=2
3=3
=
Where, n=no. of basic units.
Maximum output voltage of all basic units of one leg is,
= (1 + 2 + 3 + 4 . . + )
=

( + 1)
2

n =no. of basic units per inverter leg


No. of steps N (voltage levels) w. r. to no. of the used basic units can be given by,
= ( + 1) + 1

Fig. 1 Basic unit

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Fig. 2proposed 3-phase asymmetrical cascade n-level inverter


Table. 1 Switching states of the basic unit
MODE STATE 1 STATE 2 Vo
S1
S2
ON
OFF
E
1
OFF
ON
0
2

Performance of a 3-Phase Asymmetrical Cascaded Subcell Multilevel Inverter

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Fig. 3 Proposed 3-phase asymmetrical cascade 4-level inverter

III. Modulation technique for the proposed inverter


In a multilevel inverter modulation various methods can be used. In general the two
popular methods are 1) Modulation with the fundamental Switching frequency or 2)
Modulation with a high Switching frequency. The fundamental switching frequency is
considered to be most simply and beneficiary compared to other modulation
techniques. In SPWM, introduced by Schonung in 1964 to produce the output voltage
waveform, a sinusoidal control signal (modulating control signals) is compared with a
triangular signal (carrier signal). On the other hand, modification of the modulating
signal introduced many improvements to SPWM technique, resulting in non
sinusoidal carrier based PWM (CPWM) techniques. But the high frequency advanced
PWM techniques such as CPWM and SVPWM require the equal dc voltages
(symmetric topologies).
In order to examine the proposed topology a four level inerter is considered and
the sinusoidal PWM is applied. The different modes of operation are as shown in the
table. The voltage level for each sub cell in a leg is considered as E and 2E. The
gating signals to the switches to produce the required output are also presented.

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sinusoidal pulse width modulation


As shown in fig. 4 PWM signals can be generated by comparing the sine reference
wave with the carrier triangle wave, where sine wave is compared with three carriers
(C1, C2, C3). The gate pulses for each gate can be generated by using Boolean
algebra with some logical operations as shown below,
1 = ( 2 3) + 1
2 = ( 1 2) +

3 = ( 1 2) +

4 = ( 2 3) +

+ is for OR logic and is for AND logic


Switching signals G1, G2, G3, and G4 are given to the switches S1, S2, S3, and
S4 respectively in order to obtain a desired output. In order to avoid the short circuit
problem of DC source voltage the gating signals can be used as below
1=

3=

Table. 2 Modes of operation of proposed inverter for one duty cycle


MODES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

SWITCHING STATES
LINE VOLTAGES
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Vab Vbc Vca
ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON 3E
0
-3E
ON OFF ON OFF ON OFF OFF ON OFF ON OFF ON 2E
E
-3E
ON OFF ON OFF OFF ON ON OFF OFF ON OFF ON E
2E -3E
ON OFF ON OFF ON OFF ON OFF OFF ON OFF ON 0
3E -3E
OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON -E
3E -2E
ON OFF OFF ON ON OFF ON OFF OFF ON OFF ON -2E
3E
-E
OFF ON OFF ON ON OFF ON OFF OFF ON OFF ON -3E
3E
0
OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON -3E
2E
E
OFF ON OFF ON ON OFF ON OFF OFF ON ON OFF -3E
E
2E
OFF ON OFF ON ON OFF ON OFF ON OFF ON OFF -3E
0
3E
OFF ON OFF ON OFF ON ON OFF ON OFF ON OFF -2E
-E
3E
OFF ON OFF ON ON OFF OFF ON ON OFF ON OFF -E
-2E 3E
OFF ON OFF ON OFF ON OFF ON ON OFF ON OFF 0
-3E 3E
ON OFF OFF ON OFF ON OFF ON ON OFF ON OFF E
-3E 2E
OFF ON ON OFF OFF ON OFF ON ON OFF ON OFF 2E
-3E
E
ON OFF ON OFF OFF ON OFF ON ON OFF ON OFF 3E
-3E
0
ON OFF ON OFF OFF ON OFF ON OFF ON ON OFF 3E
-2E
-E
ON OFF ON OFF OFF ON OFF ON ON OFF OFF ON 3E
-E
-2E

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Performance of a 3-Phase Asymmetrical Cascaded Subcell Multilevel Inverter

Fig. 4 sinusoidal pulse width modulation


GATE PULSE (G1)
1.5

AMPLITUDE

0.5

-0.5

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.03

0.035

0.04

0.045

0.03

0.035

0.04

0.045

TIME (msec)
GATE PULSE (G2)
1.5

AMPLITUDE

0.5

-0.5

0.005

0.01

0.015

0.02

0.025
TIME (msec)

GATE PULSE (G3)


1.5

AMPLITUDE

0.5

-0.5

0.005

0.01

0.015

0.02

0.025
TIME (msec)

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GATE PULSE (G4)
1.5

AMPLITUDE

0.5

-0.5

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

TIME (msec)

Fig. 5 switching pulses for the proposed model


PHASE VOLTAGE (Van)
450
400

VOLTAGE (volts)

350
300
250
200
150
100
50
0

0.01

0.02

0.03

0.04

0.05
TIME (msec)

0.06

0.07

0.08

0.09

0.1

0.06

0.07

0.08

0.09

0.1

0.06

0.07

0.08

0.09

0.1

PHASE VOLTAGE (Vbn)


450
400

VOLTAGE (volts)

350
300
250
200
150
100
50
0

0.01

0.02

0.03

0.04

0.05
TIME (msec)

PHASE VOLTAGE (Vcn)


450
400

VOLTAGE (volts)

350
300
250
200
150
100
50
0

0.01

0.02

0.03

0.04

0.05
TIME (msec)

Fig. 6 phase voltages developed by the proposed model

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Performance of a 3-Phase Asymmetrical Cascaded Subcell Multilevel Inverter


LINE VOLTAGE (Vab)
500
400
300

VOLTAGE (volts)

200
100
0
-100
-200
-300
-400
-500

0.01

0.02

0.03

0.04

0.05
TIME (msec)

0.06

0.07

0.08

0.09

0.1

0.06

0.07

0.08

0.09

0.1

0.06

0.07

0.08

0.09

0.1

LINE VOLTAGE (Vbc)


500
400
300

VOLTAGE (volts)

200
100
0
-100
-200
-300
-400
-500

0.01

0.02

0.03

0.04

0.05
TIME (msec)
LINE VOLTAGE (Vca)

500
400
300

VOLTAGE (volts)

200
100
0
-100
-200
-300
-400
-500

0.01

0.02

0.03

0.04

0.05
TIME (msec)

Fig. 7 Line to Line voltages developed by the proposed model


Table. 3. comparison of proposed with other inverter topologies
NEUTRAL POINT FLYING PROPOSED
CLAMPED
CAPACITOR INVERTER
18
18
12
MAIN SWITCHING DEVICES
30
18
12
DIODES
3
3
3
DC BUS
0
9
0
BALANCING CAPACITORS

IV. CONCLUSION
The proposed three phase asymmetrical cascaded multilevel inverter was
implemented with minimum number of switches, gate driver circuits, and reduction of
voltage standing on the switches has been achieved. Due to the above reasons the cost

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and installation area has reduced for the proposed model. Low frequency PWM
techniques have been employed effectively. And the model for four level
compositions have been designed in simulink and simulated successfully.

REFERENCES
[1] HamzaBelkamel, SaadMekhilef, AmmarMasaoud, Mohsen Abdel Naeim,

Novel three-phase asymmetrical cascaded multilevel voltage source inverter,


IET Power Electron., 2013, Vol. 6, Iss. 8, pp. 16961706.
[2] Y Suresh, AK Panda, Investigation on hybrid cascaded multilevel inverter
with reduced dc sources, Renewable and Sustainable Energy Reviews, 2013
Elsevier.
[3] AK Panda, Y Suresh, Research on cascade multilevel inverter with single DC
source by using three-phase transformers,-International Journal of Electrical
Power & Energy , 2012 Elsevier.
[4] Malinowski, M Gopakumar, K Rodriguez, J Pe, Xrez, M. A. : A survey on
cascaded multilevel inverters, IEEE Trans. Ind. Electron., 2010, 57, pp. 2197
2206.
[5] Babaei, E Hosseini, S. H. : New cascaded multilevel inverter topology with
minimum number of switches, Energy Convers. Manage., 2009, 50, pp. 2761
2767.
[6] J Ebrahimi, E Babaei, A new topology of cascaded multilevel converters with
reduced number of components for high-voltage applications-Power
Electronics, IEEE, 2011.
[7] E Babaei A cascade multilevel converter topology with reduced number of
switches-Power Electronics, IEEE Transactions on, 2008.
[8] J Ebrahimi, E Babaei, A new multilevel converter topology with reduced
number of power electronic components-IEEE Transactions on, 2012.
[9] E Babaei, MF Kangarlu, FN Mazgar Symmetric and asymmetric multilevel
inverter topologies with reduced switching devices-Electric Power Systems
Research, 2012 Elsevier.