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Proceedings of the 2006 American Control Conference

Minneapolis, Minnesota, USA, June 14-16, 2006

WeBT17.1

Graphical Programming for Field Programmable Gate Arrays:


Applications in Control and Mechatronics
Jeanne S. Falcon, IEEE, Mike Trimborn


Abstract Field programmable gate arrays (FPGAs) are


being used for an increasing number of embedded control and
monitoring systems. They are less expensive than ASICs in
terms of development and can also be reprogrammed in the
field. FPGAs also have advantages over microprocessors in
that all of the control logic is implemented in hardware. This
leads to a significant advantage in terms of speed. Also,
multiple tasks can run in parallel because each task will utilize
a different set of gates on the FPGA. FPGAs can be used for
control, signal processing, digital communication, health
monitoring, and custom timing and triggering. This paper
presents LabVIEW graphical programming as a high-level
language for FPGAs for use in control and mechatronics
applications.

control and mechatronic systems. Fig. 1 shows a LabVIEW


FPGA example for pulse width modulation (PWM) output
generation. Fig. 2 shows VHDL for the same task [2].
National Instruments (NI) has recently developed several
new design tools and a hardware architecture which can be
used to speed the design and implementation of embedded
control systems utilizing FPGAs. The design tools are based
on LabVIEW FPGA a graphical programming language
for FPGAs. The hardware architecture combines an FPGA
with a microprocessor and is available for desktop

I. INTRODUCTION

mbbeded control systems require a high degree of


reliability and determinism. However, the costs of
designing and testing these control systems can be very high
due to application complexity and stringent performance
requirements. In addition, reducing time-to-market for
product development is essential for many companies. For
researchers, the use of high-level software tools in a unified
environment can abstract away many implementation
details. This facilitates the rapid investigation of advanced
algorithms and control approaches on real-world systems.
Field programmable gate arrays (FPGAs) are being used
for an increasing number of embedded control and
monitoring systems. They are less expensive than ASICs in
terms of development and can also be reprogrammed in the
field. FPGAs also have advantages over microprocessors in
that all of the control logic is implemented in hardware.
This leads to a significant advantage in terms of speed.
Also, multiple tasks can run in parallel because each task
will utilize a different set of gates on the FPGA. FPGAs can
be used for control, signal processing, digital
communication, health monitoring, and custom timing and
triggering.
Programming for FPGAs has previously required
knowledge of VHDL or Verilog [1]. VHDL and Verilog
are taught in electrical engineering programs but not in
mechanical, aerospace, biomedical, or chemical engineering
programs. This has limited the proliferation of FPGAs in
Manuscript received March 27, 2006.
J. S. Falcon is a Senior Engineer with National Instruments, Austin, TX
78726 USA (phone: 512-683-0100; fax: 512-683-5500; e-mail:
jeannie.falcon@ ni.com).
M. Trimborn is LabVIEW Embedded Product Manager with National
Instruments, Austin, TX, 78726 USA.

1-4244-0210-7/06/$20.00 2006 IEEE

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Fig. 1. LabVIEW FPGA program for PWM output.

Fig. 2. VHDL example for PWM output.

computers, PXI/CompactPCI industrial computers as well as


an NI embedded control system called CompactRIO.
Built-in LabVIEW FPGA functions are available for
control and signal processing. Control systems with digital
inputs (such as encoders) and digital outputs (such as PWM
signals) can be built on the FPGA with rates up to 20MHz.
Control systems with analog inputs and outputs can be built
with rates up to 500 kHz. Parallelism is inherent because
separate FPGA gates are used for each loop on a LabVIEW
FPGA diagram. Thus, the addition of control or monitoring
tasks will not slow the overall FPGA application. The total
number of tasks is limited however by the number of gates
of the FPGA.
This paper will present background on FPGAs, discuss
programming methods and system architectures, and
describe the LabVIEW FPGA module for graphical
programming of FPGAs. Several applications in control and
mechatronics will also be discussed.
II. FPGA BACKGROUND
A. FPGA Definition and Market
An FPGA is a chip that consists of many unconfigured
logic gates. Unlike the fixed, vendor-defined functionality of
an application-specific integrated circuit (ASIC) chip, an
FPGA can be configured and reconfigured for different
applications. FPGAs are used in applications where the cost
of developing and fabricating an ASIC is prohibitive, or the
hardware must be reconfigured after being placed into
service. Because FPGAs can be used for implementation of
custom algorithms in hardware, they offer benefits such as
precise timing and synchronization, rapid decision making,
and simultaneous execution of parallel tasks. Today, FPGAs
appear in such devices as electronic instruments, consumer
electronics, automobiles, aircraft, copy machines, and
application-specific computer hardware.
The major manufacturers of FPGAs are Xilinx [3] and
Altera [4] and, together, they comprise more than eighty
percent of the FPGA market [5].
B. FPGA Programming Methods
Historically, programming FPGAs has been limited to
engineers who have in-depth knowledge of VHDL or other
low-level design tools, which require overcoming a very
steep learning curve.
Other FPGA design options are available. Celoxica [6]
offers comprehensive C/C++ design tools for FPGAs.
Mentor Graphics [7] creates FPGA code using C++.
AccelChip [8] offers MATLAB programming capability
for FPGAs including tools for floating-point to fixed-point
conversion.
Xilinx [3] provides a graphical programming option using
Simulink as part of their Xilinx System Generator for DSP.

III. LABVIEW FPGA GRAPHICAL PROGRAMMING


A. LabVIEW FPGA Introduction
The NI LabVIEW FPGA Module extends the LabVIEW
graphical development environment to reconfigurable
FPGAs on various hardware platforms [9]. With the
LabVIEW FPGA Module, the operation of the FPGA device
can be configured as well as the connected analog and
digital I/O by programming in LabVIEW. The graphical
dataflow and parallelism inherent in LabVIEW are useful
for intuitively programming control tasks, algorithms, signal
processing, and logic.
Once the FPGA is targeted in the LabVIEW development
environment, LabVIEW displays only the functions that can
be implemented in the FPGA (Fig. 3). The LabVIEW FPGA
Module Functions palette includes typical LabVIEW
structures and functions, such as While Loops, For Loops,
Case Structures, and Sequence Structures as well as a
dedicated set of LabVIEW FPGA-specific functions for
math, signal generation and analysis, simple control
(including PID), comparison logic, array and cluster
manipulation, occurrences, analog and digital I/O, and
timing. A combination of these functions can be used to
embed logic and intelligence onto the FPGA-based device.
Math and control in FPGA are limited to integer-math
operations. However, simple control blocks such as PID
have been developed with pseudo-floating point capability.

Fig. 3.
LabVIEW FPGA Functions Palette showing programming
structures, timing, math, logic, control, synchronization and I/O functions.

The LabVIEW block diagram is implemented in


hardware, which provides direct control over the
reconfigurable hardware I/O. The I/O signals can be
analyzed and manipulated in ways that are not possible with
fixed I/O hardware. Fig. 4 shows the block diagram for a
simple rising-edge counter. Following the data flow makes it
very easy to understand the behavior of this counter. A
while loop structure is used to continuously read from a
digital line and compare the line status from one iteration to
the next. When the digital line changes state, the counter is

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incremented by one. The counter size is defined by the I32


data type of the counter indicator, making this a 32-bit
counter.
The uniqueness of LabVIEW FPGA is that multiple,
parallel counters can be created through additional While
loops placed on the LabVIEW block diagram. These will
consume completely different sections of the FPGA
resulting in true parallel process. In addition, the hardware
can be reconfigured as needed. For example, the digital I/O
lines connected to the FPGA can be apportioned as needed
into any combination of encoder inputs, counter inputs,
PWM outputs, or serial communication protocols. If
different digital I/O is needed for a new application, the
FPGA is simply re-programmed with LabVIEW FPGA to
provide different I/O configuration.
The hardware configuration on the FPGA can be
augmented with in-line signal processing, health monitoring,
fault detection, logic, and feedback control. Each additional
task consumes additional FPGA gates until the total number
of gates on the FPGA device is consumed.

Fig. 4. LabVIEW FPGA program for 32-bit counter.

B. FPGA Development Flow


After creating the LabVIEW FPGA VI, the code must be
compiled. Similar to other FPGA development tools,
compile time for an FPGA VI can range from minutes to
several hours depending on the complexity of the code and
the specifications of the development system. To maximize
development productivity, a bit-accurate emulation mode
can be used so the logic of the design can be verified before
initiating the compile process. When targeting the FPGA
Device Emulator, LabVIEW accesses I/O from the device
and executes the VI logic on the Windows development
computer. In this mode, it is possible to use the same
debugging tools available in LabVIEW for Windows, such
as execution highlighting, probes, and breakpoints.
Once the LabVIEW FPGA code is compiled, a LabVIEW
host VI can be created to integrate the hardware into the rest
of the test and control system. Fig. 5 illustrates the
development process for creating an FPGA application. The
host VI uses controls and indicators on the FPGA VI front
panel to transfer data between the FPGA on the RIO device
and the host processing engine. These front panel objects are
represented as data registers within the FPGA. The host
computer can be either a PC or PXI controller running

Windows or a PC, PXI controller, Compact Vision System,


or CompactRIO controller running a real-time operating
system (RTOS).

Fig. 5. Application development flow showing FPGA compilation step.

C. Combined FPGA / Processor Architectures


National Instruments provides multiple hardware
platforms with FPGA technology. Fig. 6 shows the
PXI/cPCI Industrial Computer platform, with plug-in FPGA
boards as an option, as well as the CompactRIO
programmable automation controller with an FPGA on the
backplane of the chassis. NI also provides programmable
plug-in FPGA boards for desktop computers. An additional
hardware platform with a programmable FPGA is the NI
Compact Vision System with distributed machine vision and
control capability.
The shared hardware architecture among the platforms is
illustrated in Fig. 7. The desktop PC and the PXI/cPCI
Industrial PC can run Windows or LabVIEW Real-Time on
the main floating point-processor. LabVIEW Real-Time
allows LabVIEW diagrams to run on top of a commercial
real-time operating system for multiple types of targets. In
both the desktop and the PXI system, the plug-in FPGA
board is connected to the processor via the PCI bus. Plug-in
FPGA boards are available with both balanced analog I/O
and multiple digital lines.
The CompactRIO architecture shown in Fig. 7 is similar
to that of the desktop and the PXI system with FPGA
technology.
The floating-point processor in the
CompactRIO controller is tied to the FPGA on the
backplane via an internal PCI bus. The FPGA is, in turn,
connected to the analog and digital I/O modules in a star
topology. Analog modules contain both conversion circuitry
and signal conditioning while digital modules have signal
conditioning alone.

Fig. 6. PXI/cPCI Industrial Computer and NI CompactRIO automation


controller.

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can execute independently so that extremely high loop rates


can be achieved. The limiting factor for FPGAs is the space
available or the number of gates.
D. Use of LabVIEW FPGA with LabVIEW Simulation
Module
A simple analog input and analog output operation written
with LabVIEW FPGA is shown in Fig. 9. The analog I/O
will run at the maximum rate allowed by the FPGA since a
timing VI has not been added to the program. The timing is
then limited only by the conversion rate for I/O on the
FPGA-based device.

Fig. 7. Hardware architecture diagram for FPGA/processor platforms.

Because of the similar hardware architecture, a common


software application architecture can be used for all three
platforms. This software architecture is shown in Fig. 8 and
includes a Host VI (program) running on a Windows PC, a
real-time VI running on the processor, and an FPGA VI
running completely in hardware on the FPGA.
Fig. 9. Simple analog input and output VI written in LabVIEW FPGA for
single-point I/O.

Real-Time Processor

Fig. 10 shows the front panel for this VI when the analog
output is wrapped back to the analog input. The user can
adjust the slider for the analog output on the front panel and
see the result in the graph of the analog input.

Fig. 8. Software application architecture diagram for FPGA/processor


platforms.

With this software and hardware architecture, it is


possible to quickly develop various hierarchical control
strategies. Some lower level control loops can take place
completely in the FPGA. Higher level control loops can be
written for the floating-point processor in the system. In
addition, various tasks such as custom startup and shutdown
behavior, in-line signal processing, and custom timing,
synchronization, and digital communication can be
implemented in the FPGA. Time-critical parallel tasks such
as health monitoring and fault detection can be developed on
the FPGA as well.
While processors run computations in sequence, FPGAs
can run computations in parallel.
New processor
architectures are being released involving multiple cores, but
the FPGA is still the best choice for parallel computation. If
multiple control loops or tasks are implemented in a
processor, then the overall loop rate will decrease. Multiple
control loops and tasks that are implemented in an FPGA

Fig. 10. Front panel of analog input and output VI written in LabVIEW
FPGA.

A simple control program can be developed for the realtime processor using the LabVIEW Simulation Module.
Fig. 11 shows the simulation loop with a signal generator VI
writing a sine wave to the analog output. The analog input
is read back through the FPGA and communicated to the
processor.
Many other dynamic system modeling and control blocks
are available in LabVIEW Simulation Module including

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linear continuous and discrete-time models, as well as both


graphical and textual blocks for nonlinear systems.

Fig. 11. Simple LabVIEW Simulation Module VI which communicates


with LabVIEW FPGA VI through an interface node.

IV. APPLICATIONS
A. High Speed Control on an FPGA for MEMS Device
Using LabVIEW FPGA and the NI PXI-7831R module,
Kurfess and Degertekin implemented parallel, extremely
high-speed control (120 kHz) of an array of Micro ElectroMechanical Systems (MEMS) devices [10]. MEMS devices
are produced in large quantities on a single silicon wafer,
and, even when packaged or built into another device, they
are often spatially arranged in arrays. Kurfess and
Degertekin developed a novel measurement system that can
test multiple MEMS devices in an array simultaneously
rather than stepping and scanning a single measurement
device over the MEMS array. The new measurement system
is itself an array of MEMS microinterferometers. Each
microinterferometer in the array is a position-sensing grating
interferometer (PSGI) capable of measuring out-of-plane
distances with subnanometer accuracy at frequencies more
than 20 MHz. The microinterferometer is 1,000 times
smaller than typical, bench-sized laser interferometers.
Initial results demonstrate mapping of microscale
membranes vibrating in the 2 MHz range.

Fig. 12. SEM image of MEMS microinterferometer.

Kurfess
and
Degertekin
implemented
the
microinterferometer in both single and array units using the
LabVIEW FPGA Module and NI reconfigurable I/O
hardware, which makes the transition from monitoring and
controlling a single interferometer to an array of
interferometers a simple task. They used the NI PXI-7831R

reconfigurable I/O module to provide analog I/O along with


high-speed PID control. They applied the control to a
deformable grating within the interferometer sensor to
minimize the effects of sample misalignment and external
disturbances and improve the sensitivity of the
microinterferometer during operation. They used the
pseudo-floating-point PID example in the LabVIEW FPGA
Module as a basis for the control implementation. With the
high-speed hardware timing capabilities of the LabVIEW
FPGA Module, Kurfess and Degertekin easily achieved the
required 120 kHz bandwidth for the control loop.
In this application, the maximum bandwidth was
determined by the conversion speed of the A/D and D/A
circuitry on the PXI-7831R module. Higher bandwidth
control can be achieved if the digital lines on the plug-in
FPGA board are used for both sensors and actuators. An
example would be encoders or tachometers for sensors and
PWM commands to amplifiers or drives for actuators. Also,
the CompactRIO system includes options for high
bandwidth analog-to-digital and digital-to-analog conversion
circuitry.
B. Single-point I/O on FPGA for Haptics
Kopp and OMalley [11] used LabVIEW Real-Time and
LabVIEW FPGA for control and high-speed single-point
I/O in a haptics experiment focused on creating stiff virtual
walls. A limiting factor for stiffness in virtual walls is the
sampling rate of the control system for the haptic device. If
the desired stiffness is too high in relation to the sampling
rate, then the virtual wall ceases to be passive and exhibits
active behavior in the form of vibrations and, at too high of
a stiffness, instability. The device used in the experiment
was the Phantom Premium 1.0 haptic device from SensAble
Technologies [12]. Using LabVIEW FPGA and a PXI7831R FPGA board, the researchers were able to achieve a
sampling rate of 20 kHz. The Windows/GHOST software
and hardware platform that shipped with the Phantom device
had a maximum sampling rate of 1 kHz. The increased
sampling rate for the FPGA based system resulted in a
maximum wall stiffness of 500 N/m compared to a
maximum wall stiffness of 25 N/m for the
Windows/GHOST system.
C. Phase-Locked Loop for Scanning Probe Microscope
Rychen and Vancura [13] developed a compact, high
speed control system for a scanning probe microscope
(SPM) using LabVIEW FPGA, LabVIEW Real-Time, and a
PXI system. The 1.26 GHz real-time processor ran several
algorithms such as raster scan generators, the tip-sample
distance controller, and auxiliary feedback controllers. A
digital phase-locked loop (PLL) was implemented with
LabVIEW FPGA resulting in a demodulation bandwidth of
more than 10 kHz using the analog I/O lines to interface to
the external components. With a redesign involving the use
of digital I/O lines, 24 MS/s is possible with a frequency
resolution of 0.1 PHz. The fully digital case will yield high-

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phase accuracy compared to the analog circuitry. Also, the


demodulation bandwidth may be adjusted into the millihertz
range for the highest frequency resolution.
TABLE I
SERVO UPDATE RATES FOR NI SOFTMOTION ON VARIOUS
PLATFORMS

D. Model Free Adaptive Control for FPGA


CyboSoft [14] has developed a Model Free Adaptive
(MFA) Control Toolset for LabVIEW. Used in conjunction
with NI SoftMotion on CompactRIO, one option in the
toolset provides high speed positioning control using
LabVIEW FPGA with a minimum sampling period of 25
micro-seconds.
The toolset has been successfully
demonstrated with high precision piezoelectric stages with
significant load changes.
E. Motorcycle Engine Control Prototyping
Dase [15] from Drivven Inc. [16] used LabVIEW FPGA,
CompactRIO, and custom I/O modules to build an engine
control prototyping system. Engine control is a challenging
application involving loop times on the order of
milliseconds and precision fuel and spark timing on the
order of microseconds. Dase was able to completely replace
the ECU on a 2004 Yamaha YZF-R6 motorcycle using the
CompactRIO system such that experienced riders could not
identify significant differences between the factory ECU
control and the prototype control.

Hardware Platform
CompactRIO
PCI/PXI FPGA
PCI/PXI Motion Control
PCI/PXI M Series DAQ
Compact FieldPoint

Servo Update Rate


5 PS
5 PS
62.5 PS
1ms
5 ms

B. Digital Filter Design Toolkit


The NI Digital Filter Design Toolkit provides functions
and interactive tools for design, analysis and implementation
of digital filters within LabVIEW FPGA. The toolkit
includes interactive design methods for both classical filter
design and filter design based on pole-zero placement (Fig.
14). A control law that can be represented as a discrete-time
transfer function can be implemented on the FPGA using
LabVIEW FPGA code generated from the Digital Filter
Design Toolkit.

V. ADDITIONAL TOOLS FOR FPGA DEVELOPMENT


A. SoftMotion Position Control Loop on FPGA
The NI SoftMotion Development Module, shown in Fig.
13, includes enhanced real-time and FPGA algorithms for
motion control and built-in inputs for a variety of feedback
devices including quadrature encoders, and sine cosine
encoders. Table I shows the servo update rates that can be
obtained using NI SoftMotion on a variety of hardware
targets including FPGA targets.
Fig. 14. Interactive filter design using LabVIEW Digital Filter Design
Toolkit.

Fig. 13. Architecture of NI SoftMotion Development Module.

C. State Diagram Editor on FPGA


The LabVIEW State Diagram Toolkit can be used to help
build state machines on an FPGA. The toolkit includes a
state diagram editor for drawing the logic that defines an
application. An example of this is shown in Fig. 15. As
states and transitions are added to the state machine
diagram, LabVIEW generates code to match each change.
The logic for the state machines is represented in the
LabVIEW code by a series of while loops and case
statements. The toolkit can also insert comments in the
LabVIEW block diagram to indicate where additional code
can be added. The entire LabVIEW block diagram can then
be implemented on an FPGA using the LabVIEW FPGA
module.

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Fig. 15. Architecture of NI SoftMotion Development Module.

VI. CONCLUSION
Graphical programming for FPGAs can be used by
control and mechatronic system designers and researchers to
quickly develop robust and high-performance applications.
The combination of FPGAs with floating-point processors
allows engineers to intelligently distribute computation,
control, and signal processing functions. LabVIEW FPGA
is a comprehensive tool for graphical programming FPGAs
and includes functions for timing, logic, synchronization,
high-speed control, analog and digital I/O.
The NI
SoftMotion Module provides motion-specific functionality
for combined real-time processor / FPGA systems. The NI
Digital Filter Design Toolkit can be used in conjunction
with LabVIEW FPGA to quickly prototype and implement
digital filters on an FPGA.
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