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Spring 2015

Week 6 Module 33

Digital Circuits and


Systems
Timing Sequential Circuits
Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay

Sequential Circuit Timing


Once the functionality of a sequential network is designed,
its timing parameters must be determined. Timing problems
can be very subtle because timing parameters can vary with
device age and other operating conditions.

Analysis and Design of Sequential Logic Circuits

Timing Parameters
Global setup time (Tsu)

Global hold time (Th)


Maximum clock frequency
Clock skew.
These parameters are derived using the circuit (known) delays
described below.
tio delay from input of IFL to output of OFL
tif delay from circuit inputs of flip-flop inputs
tfo delay from flip-flop outputs to circuit outputs
tff delay from flip-flop outputs to flip-flop inputs
tc-q clock to Q propagation delay of flip-flops
tsu setup time of flip-flops
th hold time of flip-flops
tc clock delay; time required for clock to reach all flip-flops
Analysis and Design of Sequential Logic Circuits

Global Setup and Hold Times

Changes that occur at inputs can be delayed by as much as


maximum tif by the time they reach the flip-flop inputs. Hence,
we want to setup circuit inputs relative to clock edge appearing
at the flip-flops.
Th
Tsu
CLK (at clock source)

tc
th
tif

CK (at FF clock input)


X (at sequential circuit input)

tsu
tif

D (at FF input)

Tsu tsumax tifmax tcmin

Similarly, hold time of the circuit inputs relative to the system


clock at the source is given by

Th thmax tifmin tcmax


Analysis and Design of Sequential Logic Circuits

Maximum Clock Frequency


Qj

Dj

Comb.
logic

CKj

CLK

Di
CKi

CKi
Qi

Qi

tC-Q

tff

tsu

Dj

Tck (=Tclk)

tff

Edge Triggering

For an edge-triggered circuit: minimum clock period is,

Tclk t C Qmax t ffmax t sumax

Maximum Clock Frequency:

f clk

Tclk

Analysis and Design of Sequential Logic Circuits

Timing Violations
Tclk tC Qmax t ffmax tsumax

The clock period (Tclk) has a lower bound of tff.max .

If the clock period is equal to (tff.max + tC-Q.max) then the


flip-flop state changes can violate setup times.

Remedy :

Use faster flip-flops (decrease tC-Q )


Use faster gates (decrease tff )
Use a slower clock (increase clock period, Tclk)
Analysis and Design of Sequential Logic Circuits

Clock Skew

The previous discussion assumes that clock signals


arrive at all flip-flops simultaneously - this is not a good
assumption since it is not true in practice.

Because of different wire lengths over which the clock


signals travel and the load at the destination, there is a
slight difference in clock arrival times at different flip-flop
inputs.

Clock skew, tskew, is the difference in time between


triggering edges seen at different flip-flops. Clock skew
affects minimum Tclk.
Analysis and Design of Sequential Logic Circuits

Max. Clock Frequency with Skew


Dj

Comb.
logic

CKj

CLK

tff

Di
CKi

CKi

Qj

CKj
Qi

tskew

tskew
tC-Q

Qj

tff

tsu

Di

Tck (=Tclk)

Therefore, for an edge-triggered circuit with clock skew,

Tclk tskewmax tC Qmax t ffmax tsumax

Clock skew is a significant factor in determining the speed of highperformance synchronous circuits. The larger the skew, the slower
the circuit will operate.
Analysis and Design of Sequential Logic Circuits

Timing Analysis Example


For the circuit given below determine all the sequential
circuit timing parameters.

For a D flip-flop use: tsu = 2ns, th = 15ns and tC-Q = 20ns


For a NAND gate use: tp,max = 10ns and tp,min = 3ns
Analysis and Design of Sequential Logic Circuits

10

tif ,max 3t p ,max, nand 30ns


tif ,min 2t p ,min, nand 6ns
.

t ff ,max 2t p ,max, nand 20ns


t ff ,min 2t p ,min, nand 6ns
tc ,max 2t p ,max, nand 20ns

For a D flip-flop use: tsu = 2ns, th = 15ns, tC-Q = 20ns


For a NAND gate use: tp,max = 10ns, tp,min = 3ns

tc ,min 2t p ,min, nand 6ns

Tsu tsu ,max tif ,max tc ,min 2 30 6 26ns


Th th ,max tif ,min tc ,max 20 15 6 29ns
Tclk tC Q ,max t ff ,max tsu ,max 20 20 2 42ns
f clk ,max 1/ 42ns 23.8MHz

Analysis and Design of Sequential Logic Circuits

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Sequential Systems Using Latches

Latches can be used to create sequential systems. However, since these


are level-triggered clocking must be done carefully must ensure that state
changes only once per clock cycle.
tw < tff.min+ tD-Q.min
Dj

Comb.
logic

CLK

CKj

Di
CKi

CLK

Qj

Qi

> (tD-Q.max + tff.max+ tsu.max)

tff

Use narrow-width clock whose pulse width is less than the fastest possible path
through the combinational logic.
To guarantee correct next state, make sure that the clock period is longer than the
worst-case propagation delay through the combinational logic.
Analysis and Design of Sequential Logic Circuits

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Clocking Frequency with Latches


Tclk
CKi
Dj

Comb.
logic

CLK

CK
j

CKj

Di
CKi

tff

Qj

tskew
tw
tsu

Qi

Dj
tskew

tD-Q

tff

tsu

Di

Tclk tskewmax t w t sumin t D Qmax t ffmax t sumax


Analysis and Design of Sequential Logic Circuits

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End of Week 6: Module 33

Thank You

Intro to State Machines

15