Академический Документы
Профессиональный Документы
Культура Документы
Week 6 Module 33
Timing Parameters
Global setup time (Tsu)
tc
th
tif
tsu
tif
D (at FF input)
Dj
Comb.
logic
CKj
CLK
Di
CKi
CKi
Qi
Qi
tC-Q
tff
tsu
Dj
Tck (=Tclk)
tff
Edge Triggering
f clk
Tclk
Timing Violations
Tclk tC Qmax t ffmax tsumax
Remedy :
Clock Skew
Comb.
logic
CKj
CLK
tff
Di
CKi
CKi
Qj
CKj
Qi
tskew
tskew
tC-Q
Qj
tff
tsu
Di
Tck (=Tclk)
Clock skew is a significant factor in determining the speed of highperformance synchronous circuits. The larger the skew, the slower
the circuit will operate.
Analysis and Design of Sequential Logic Circuits
10
11
Comb.
logic
CLK
CKj
Di
CKi
CLK
Qj
Qi
tff
Use narrow-width clock whose pulse width is less than the fastest possible path
through the combinational logic.
To guarantee correct next state, make sure that the clock period is longer than the
worst-case propagation delay through the combinational logic.
Analysis and Design of Sequential Logic Circuits
12
Comb.
logic
CLK
CK
j
CKj
Di
CKi
tff
Qj
tskew
tw
tsu
Qi
Dj
tskew
tD-Q
tff
tsu
Di
14
Thank You
15