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Data Sheet
FEATURES
APPLICATIONS
VIN = 1.8V
VOUT = 1.5V
4.7F
4.7F
16
VIN
13
14
15
VIN VOUT VOUT
1 VIN
100k
VOUT 12
ADP1754
2 VIN
VOUT 11
3 VIN
TOP VIEW
(Not to Scale) VOUT 10
4 EN
SENSE 9
PG
PG
5
GND
6
NC
8
SS
7
07722-001
10nF
4.7F
4.7F
16
VIN
13
14
15
VIN VOUT VOUT
1 VIN
100k
VOUT 12
2 VIN
ADP1755
VOUT 11
3 VIN
TOP VIEW
(Not to Scale) VOUT 10
4 EN
ADJ 9
R1
PG
PG
5
GND
6
SS
7
NC
8
R2
10nF
07722-002
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
GENERAL DESCRIPTION
The ADP1754/ADP1755 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to
1.2 A of output current. These low VIN/VOUT LDOs are ideal for
regulation of nanometer FPGA geometries operating from 2.5 V
down to 1.8 V I/O rails, and for powering core voltages down to
0.75 V. Using an advanced proprietary architecture, the ADP1754/
ADP1755 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 F ceramic output capacitor.
The ADP1754 is available in seven fixed output voltage options.
The ADP1755 is the adjustable version, which allows output
Rev. G
Document Feedback
ADP1754/ADP1755
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 3
Thermal Considerations............................................................ 15
REVISION HISTORY
4/14Rev. F to Rev. G
4/09Rev. 0 to Rev. A
8/13Rev. E to Rev. F
Changes to Ordering Guide .......................................................... 19
6/13Rev. D to Rev. E
Changed Adjustable Output Voltage Option with Soft Start
(ADP1755) from 0.75 V to 3.0 V to 0.75 V to 3.3 V
(Throughout) .................................................................................... 1
Updated Outline Dimensions ....................................................... 19
12/12Rev. C to Rev. D
Added Junction Temperature of 150C, Table 3 ........................... 5
9/12Rev. B to Rev. C
Changes to Absolute Maximum Ratings, Table 3......................... 5
Changes to Ordering Guide .......................................................... 19
2/10Rev. A to Rev. B
Changes to Table 4 ............................................................................ 5
Changes to Ordering Guide .......................................................... 19
Rev. G | Page 2 of 20
Data Sheet
ADP1754/ADP1755
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 F, TA = 25C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT 1
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
VOUT
VADJ
VOUT/VIN
VOUT/IOUT
VDROPOUT
START-UP TIME 5
tSTART-UP
CURRENT-LIMIT THRESHOLD 6
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
ILIMIT
Test Conditions/Comments
TJ = 40C to +125C
IOUT = 500 A
IOUT = 100 mA
IOUT = 100 mA, TJ = 40C to +125C
IOUT = 1.2 A
IOUT = 1.2 A, TJ = 40C to +125C
EN = GND, VIN = 1.6 V
EN = GND, VIN = 1.6 V, TJ = 40C to +85C
EN = GND, VIN = 3.6 V, TJ = 40C to +85C
Min
1.6
IOUT = 10 mA
IOUT = 10 mA to 1.2 A
10 mA < IOUT < 1.2 A, TJ = 40C to +125C
IOUT = 10 mA
IOUT = 10 mA to 1.2 A
10 mA < IOUT < 1.2 A, TJ = 40C to +125C
VIN = (VOUT + 0.4 V) to 3.6 V, TJ = 40C to +125C
IOUT = 10 mA to 1.2 A, TJ = 40C to +125C
IOUT = 100 mA, VOUT 1.8 V
IOUT = 100 mA, VOUT 1.8 V, TJ = 40C to +125C
IOUT = 1.2 A, VOUT 1.8 V
IOUT = 1.2 A, VOUT 1.8 V, TJ = 40C to +125C
CSS = 0 nF, IOUT = 10 mA
CSS = 10 nF, IOUT = 10 mA
1
1.5
2
0.495
0.495
0.490
0.3
TJ rising
PGHIGH
PGLOW
PGFALL
PGRISE
VIH
VIL
VI-LEAKAGE
UVLO
UVLORISE
UVLOFALL
UVLOHYS
ISS
ADJI-BIAS
SNSI-BIAS
Max
3.6
90
400
800
1.1
2
0.5
1.4
6
30
100
+1
+1.5
+2
0.505
0.505
0.510
+0.3
0.6
10
16
105
200
1.5
TSSD
TSSD-HYS
Typ
200
5.2
2
150
15
%
%
%
V
V
V
%/V
%/A
mV
mV
mV
mV
s
ms
A
C
C
1.0
5.5
V
V
ms
10
6.5
%
%
0.4
1.2
0.1
0.4
1
1.58
1.25
0.6
Unit
V
A
A
A
mA
mA
A
A
A
100
0.9
10
10
1.2
150
V
V
A
V
V
mV
A
nA
A
ADP1754/ADP1755
Data Sheet
Parameter
OUTPUT NOISE
Symbol
OUTNOISE
PSRR
Test Conditions/Comments
10 Hz to 100 kHz, VOUT = 0.75 V
10 Hz to 100 kHz, VOUT = 2.5 V
VIN = VOUT + 1 V, IOUT = 10 mA
1 kHz, VOUT = 0.75 V
1 kHz, VOUT = 2.5 V
10 kHz, VOUT = 0.75 V
10 kHz, VOUT = 2.5 V
100 kHz, VOUT = 0.75 V
100 kHz, VOUT = 2.5 V
Min
Typ
23
65
Max
65
56
65
56
54
51
Unit
V rms
V rms
dB
dB
dB
dB
dB
dB
Symbol
CMIN
RESR
Test Conditions/Comments
TA = 40C to +125C
TA = 40C to +125C
Min
3.3
0.001
Typ
Max
0.1
Unit
F
The minimum input and output capacitance should be greater than 3.3 F over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.
Rev. G | Page 4 of 20
Data Sheet
ADP1754/ADP1755
Rating
0.3 V to +4.0 V
0.3 V to VIN
0.3 V to VIN
0.3 V to VIN
0.3 V to +4.0 V
0.3 V to VIN
65C to +150C
40C to +125C
150C
JEDEC J-STD-020
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1754/ADP1755 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (JA). TJ is calculated using the following formula:
TJ = TA + (PD JA)
THERMAL RESISTANCE
JA and JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP with Exposed Pad (CP-16-23)
ESD CAUTION
Rev. G | Page 5 of 20
JA
42
JB
25.5
Unit
C/W
ADP1754/ADP1755
Data Sheet
13 VOUT
14 VOUT
16 VIN
15 VIN
VIN 1
12 VOUT
VIN 1
12 VOUT
VIN 2
ADP1754
11 VOUT
VIN 2
VIN 3
TOP VIEW
(Not to Scale)
ADP1755
11 VOUT
10 VOUT
VIN 3
TOP VIEW
(Not to Scale)
10 VOUT
9 SENSE
EN 4
SS 7
NC 8
GND 6
9 ADJ
PG 5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-003
SS 7
NC 8
PG 5
GND 6
EN 4
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-004
13 VOUT
14 VOUT
16 VIN
15 VIN
ADP1755
Pin No.
1, 2, 3, 15,
16
4
PG
6
7
8
9
6
7
8
N/A
GND
SS
NC
SENSE
N/A
10, 11, 12,
13, 14
17 (EPAD)
9
10, 11, 12,
13, 14
17 (EPAD)
ADJ
VOUT
Mnemonic
VIN
EN
Exposed
paddle
(EPAD)
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 F or greater capacitor. Note that all five
VIN pins must be connected to the source.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal
output voltage, PG immediately transitions low.
Ground.
Soft Start. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 F or greater capacitor. Note that all
five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad be
connected to the ground plane on the board.
Rev. G | Page 6 of 20
Data Sheet
ADP1754/ADP1755
1200
1.510
1000
LOAD = 800mA
1.515
LOAD = 1.2A
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
1.505
1.500
1.495
1.490
800
LOAD = 400mA
600
LOAD = 100mA
400
LOAD = 10mA
200
1.485
25
85
125
40
25
85
07722-008
40
07722-005
1.480
125
1.520
1200
1.515
1000
1.510
1.505
1.500
1.495
1.490
800
600
400
200
100
1k
10k
0
10
07722-006
1.480
10
1k
10k
1.520
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
1.510
LOAD = 1.2A
1000
1.515
1.505
1.500
1.495
1.490
LOAD = 800mA
800
LOAD = 400mA
600
400
LOAD = 100mA
200
LOAD = 10mA
1.480
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Rev. G | Page 7 of 20
3.4
3.6
07722-010
1.485
07722-007
100
07722-009
1.485
ADP1754/ADP1755
Data Sheet
80
70
3500
60
50
40
30
3000
2500
2000
1500
20
1000
10
500
15
10
35
60
85
TEMPERATURE (C)
0
2.3
07722-011
0
40
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
4000
90
2.4
2.7
2.8
ILOAD
0.12
0.10
1
0.08
0.06
VOUT
0.04
50mV/DIV
1.6V
2.5V
10
100
LOAD CURRENT (mA)
VIN = 3.6V
VOUT = 1.5V
1k
10k
Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V
B
W M10s
A CH1
T 10.40%
380mA
07722-015
0.02
07722-012
2.6
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V
0.14
2.60
ILOAD
2.55
2.50
1
2.45
2.40
2.35
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
2.30
2.25
2.20
2.3
2.4
2.5
2.6
2.7
VOUT
20mV/DIV
VIN = 3.6V
VOUT = 1.5V
2.8
07722-013
2.5
B M10s
W
A CH1
T 10.20%
340mA
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V
Rev. G | Page 8 of 20
07722-016
4500
1.9V
2.0V
2.4V
2.6V
3.0V
3.6V
07722-014
100
Data Sheet
ADP1754/ADP1755
0
VIN
1.2A
800mA
400mA
100mA
10mA
10
20
PSRR (dB)
30
VOUT
2
5mV/DIV
40
50
60
70
80
VOUT = 1.5V
CIN = COUT = 4.7F
B
W
M10s
A CH4
T 9.60%
100
10
07722-017
800mV
1k
10k
100k
1M
10M
FREQUENCY (Hz)
70
1.2A
800mA
400mA
100mA
10mA
10
2.5V
60
20
50
30
40
PSRR (dB)
NOISE (V rms)
100
07722-020
90
1.5V
30
50
60
70
0.75V
20
40
80
10
0.001
0.01
0.1
10
100
10
07722-018
0
0.0001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
1.2A
800mA
400mA
100mA
10mA
10
20
30
PSRR (dB)
1.5V
2.5V
0.1
40
50
60
70
80
0.75V
0.01
10
100
1k
10k
100k
FREQUENCY (Hz)
100
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Rev. G | Page 9 of 20
10M
07722-122
90
07081-019
100
07722-121
90
ADP1754/ADP1755
Data Sheet
0
10
1.5V/1200mA
2.5V/1200mA
0.75V/1200mA
1.5V/10mA
2.5V/10mA
0.75V/10mA
20
PSRR (dB)
30
40
50
60
70
90
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
07722-123
80
Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage
Rev. G | Page 10 of 20
Data Sheet
ADP1754/ADP1755
THEORY OF OPERATION
The ADP1754/ADP1755 are low dropout linear regulators that
use an advanced, proprietary architecture to provide high power
supply rejection ratio (PSRR) and excellent line and load transient
response with only a small 4.7 F ceramic output capacitor. Both
devices operate from a 1.6 V to 3.6 V input rail and provide up
to 1.2 A of output current. Supply current in shutdown mode is
typically 2 A.
REVERSE POLARITY
PROTECTION
VIN
VOUT
UVLO
GND
SHORT-CIRCUIT
AND THERMAL
PROTECTION
SENSE
R1
0.5V
REF
PG
R2
PG
DETECT
EN
SS
SHUTDOWN
07722-021
0.9A
REVERSE POLARITY
PROTECTION
VIN
where:
tSS is the soft start period.
VREF is the 0.5 V reference voltage.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (0.9 A).
When the ADP1754/ADP1755 is disabled (using the EN pin), the
soft start capacitor is discharged to GND through an internal 100
resistor.
VOUT
UVLO
GND
(1)
2.50
2.25
EN
SHORT-CIRCUIT
AND THERMAL
PROTECTION
2.00
ADJ
PG
DETECT
0.9A
SHUTDOWN
1.25
4.7nF
1.00
10nF
SS
0.75
07722-022
EN
1nF
1.50
0.50
0.25
0
0
TIME (ms)
10
07722-023
0.5V
REF
PG
VOLTAGE (V)
1.75
ADP1754/ADP1755
T
Data Sheet
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
EN
VOUT
1.0
A CH1
920mV
0.9
EN ACTIVE
0.8
EN INACTIVE
0.7
0.6
0.5
1.6
(2)
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
07722-026
CH1 2.0V BW
VOUT = 1.5V
CIN = COUT = 4.7F
EN THRESHOLD (V)
500mV/DIV
07722-024
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
POWER-GOOD FEATURE
ENABLE FEATURE
The ADP1754/ADP1755 use the EN pin to enable and disable
the VOUT pins under normal operating conditions. As shown
in Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
T
EN
VOUT
VOUT = 1.5V
CIN = COUT = 4.7F
A CH1
1.05V
07722-025
500mV/DIV
Rev. G | Page 12 of 20
Data Sheet
ADP1754/ADP1755
REVERSE CURRENT PROTECTION FEATURE
VIN
1V/DIV
VOUT
500mV/DIV
PG
1V/DIV
CH1 1.0V BW
CH3 1.0V BW
900mV
07722-027
VOUT = 1.5V
CIN = COUT = 4.7F
Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V)
VIN
1V/DIV
VOUT
500mV/DIV
2500
2000
1500
1000
VOUT = 1.5V
CIN = COUT = 4.7F
CH1 1.0V BW
CH3 1.0V BW
0
0
900mV
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V)
Rev. G | Page 13 of 20
3.3
3.6
07722-132
500
PG
1V/DIV
07722-028
3000
ADP1754/ADP1755
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
ILOAD
VOUT
50mV/DIV
B
W M1s
A CH1
380mA
T 11.2%
07722-133
4
CAPACITANCE (F)
ILOAD
1
2
0
0
A CH1
340mA
T 11.0%
10
07722-031
VOUT
20mV/DIV
Rev. G | Page 14 of 20
(3)
Data Sheet
ADP1754/ADP1755
UNDERVOLTAGE LOCKOUT
The ADP1754/ADP1755 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.58 V. This ensures that the
ADP1754/ADP1755 inputs and the output behave in a predictable manner during power-up.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP1754/ADP1755 must not exceed 125C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistance between the junction and ambient air (JA). The JA
value is dependent on the package assembly compounds used
and the amount of copper to which the GND pin and the exposed
pad (EPAD) of the package are soldered on the PCB. Table 6 shows
typical JA values for the 16-lead LFCSP for various PCB copper
sizes. Table 7 shows typical JB values for the 16-lead LFCSP.
Table 6. Typical JA Values
Copper Size (mm2)
01
100
500
1000
6400
1
JA (C/W), LFCSP
130
80
69
54
42
JB (C/W) at 1 W
32.7
31.5
25.5
(4)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN VOUT) ILOAD] + (VIN IGND)
(5)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN VOUT) ILOAD] JA}
(6)
As shown in Equation 6, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125C.
Figure 36 through Figure 41 show junction temperature
calculations for different ambient temperatures, load currents,
VIN to VOUT differentials, and areas of PCB copper.
Rev. G | Page 15 of 20
ADP1754/ADP1755
140
120
LOAD = 800mA
100
LOAD = 400mA
60
LOAD = 200mA
40
LOAD = 100mA
20
LOAD = 10mA
0
0.25
0.75
1.25
1.75
VIN VOUT (V)
2.25
2.75
100
LOAD = 400mA
80
LOAD = 200mA
60
LOAD = 10mA
20
0
0.25
LOAD = 800mA
80
LOAD = 200mA
60
LOAD = 100mA
40
LOAD = 10mA
20
1.25
1.75
VIN VOUT (V)
2.25
2.75
LOAD = 800mA
80
LOAD = 200mA
LOAD = 10mA
40
20
LOAD = 400mA
LOAD = 200mA
60
LOAD = 100mA
LOAD = 10mA
0.75
1.25
1.75
VIN VOUT (V)
2.25
2.75
2.25
2.75
MAX JUNCTION
TEMPERATURE
120
LOAD =
800mA
LOAD = 400mA
100
LOAD = 200mA
80
LOAD = 100mA
60
LOAD = 10mA
40
20
0
0.25
07722-034
100
0
0.25
1.25
1.75
VIN VOUT (V)
LOAD = 1.2A
LOAD = 1.2A
20
0.75
140
MAX JUNCTION
TEMPERATURE
40
LOAD = 100mA
60
120
80
LOAD = 400mA
100
LOAD =
800mA
2.75
120
0
0.25
07722-033
LOAD = 400mA
100
2.25
MAX JUNCTION
TEMPERATURE
LOAD = 1.2A
LOAD = 1.2A
140
1.25
1.75
VIN VOUT (V)
140
120
0.75
0.75
MAX JUNCTION
TEMPERATURE
0
0.25
LOAD = 100mA
40
LOAD = 800mA
LOAD = 1.2A
07722-036
80
120
0.75
1.25
1.75
VIN VOUT (V)
2.25
2.75
07722-037
LOAD = 1.2A
MAX JUNCTION
TEMPERATURE
07722-035
MAX JUNCTION
TEMPERATURE
07722-032
140
Data Sheet
Rev. G | Page 16 of 20
(7)
Data Sheet
ADP1754/ADP1755
MAX JUNCTION
TEMPERATURE
120
LOAD = 1.2A
100
LOAD = 800mA
80
LOAD = 400mA
120
100
LOAD = 1.2A
60
LOAD = 400mA
LOAD = 200mA
40
LOAD = 10mA
20
LOAD = 100mA
LOAD = 200mA
40
0
0.25
0.75
LOAD = 10mA
20
2.25
2.75
MAX JUNCTION
TEMPERATURE
120
LOAD = 1.2A
140
1.25
1.75
VIN VOUT (V)
07722-038
0.75
1.25
1.75
VIN VOUT (V)
2.25
2.75
LOAD = 100mA
0
0.25
LOAD = 800mA
100
LOAD = 400mA
80
LOAD = 200mA
60
MAX JUNCTION
TEMPERATURE
120
LOAD = 1.2A
LOAD = 800mA
100
LOAD = 400mA
80
LOAD = 200mA
60
LOAD = 10mA
40
LOAD = 100mA
20
LOAD = 10mA
40
0
0.25
LOAD = 100mA
20
0.75
1.25
1.75
VIN VOUT (V)
2.25
0.75
1.25
1.75
VIN VOUT (V)
2.25
2.75
07722-039
LOAD = 800mA
80
07722-040
60
MAX JUNCTION
TEMPERATURE
Rev. G | Page 17 of 20
2.75
07722-041
140
140
Figure 42 through Figure 45 show junction temperature calculations for different board temperatures, load currents, VIN to
VOUT differentials, and areas of PCB copper.
ADP1754/ADP1755
Data Sheet
07722-045
07722-044
07722-046
Rev. G | Page 18 of 20
Data Sheet
ADP1754/ADP1755
OUTLINE DIMENSIONS
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
12
EXPOSED
PAD
2.25
2.10 SQ
1.95
0.80
0.75
0.70
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
111908-A
TOP VIEW
0.70
0.60
0.50
ORDERING GUIDE
Model 1
ADP1754ACPZ-0.75R7
ADP1754ACPZ-1.0-R7
ADP1754ACPZ-1.1-R7
ADP1754ACPZ-1.2-R7
ADP1754ACPZ-1.3-R7
ADP1754ACPZ-1.5-R7
ADP1754ACPZ-1.8-R7
ADP1754ACPZ-2.5-R7
ADP1755ACPZ-R7
ADP1754-1.5-EVALZ
ADP1755-EVALZ
1
Temperature Range
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
Rev. G | Page 19 of 20
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
Evaluation Board
Package Option
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
ADP1754/ADP1755
Data Sheet
NOTES
Rev. G | Page 20 of 20