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Dept.of ECE

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UNIT-I: MINIMIZATION TECHNIQUES AND LOGIC GATES

1. How many bits are required to represent the decimal numbers in the range 0 to 999 using

straight binary code? Using BCD codes?

(999) 10 = ( 1111100111 ) 2 10 bits are required using straight binary code

(999) 10 = ( 1001 1001 1001 ) BCD 12 bits are required using BCD code

2. Show that the excess-3 code is self-complementing.

Self-complementing property: 1s complement of XS-3 code of a decimal digit is equal to XS3 code of 9s complement of the corresponding decimal digit.

Example:

XS-3 code of the decimal digit 2

=

0101

1s complement of 0101

=

1010 --------------------(1)

9s complement of 2

= 9-2 = 7

XS-3 code of 7

=

1010 --------------------(2)

The self- complementing property of XS-3 code is proved from equations (1)&(2)

3. How is the letter A coded as in the ASCII code?

7-bit ASCII code for the Letter A is 1000001

4. What is meant by weighted and non-weighted code?

Weighted codes are those, which obey the positional weighting principles. In weighed code,

each position of the number represents a specific weight.

Example: 8421, 2421 & 84-2-1.

Non-Weighted Codes are codes that are not positionally weighted. Each position of the

number is not assigned a fixed value.

Example: Excess-3 & Gray code

5. Add the decimals 67 and 78 using excess-3 code.

67 = ( 0110 0111 ) BCD = ( 1001 1010 ) XS-3

78 = ( 0111 1000 ) BCD = ( 1010 1011 ) XS-3

-----------------------------1 0100 0101 ( + )

0011 0011 0011

------------------------------( 0100 0111 1000 ) XS-3

------------------------------6. Add the decimals 57 and 68 using 8421 BCD code.

57 = ( 0101 0111 ) BCD

68 = ( 0110 1000 ) BCD

-------------------------1011 1111 ( + )

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St. Josephs college of Engineering/

ISO9001:2008

St. Josephs Institute of Technology

1

Dept.of ECE

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0110 0110

------------------------------(0001 0010 0101 ) BCD

------------------------------7. Write the two properties of Gray code & mention the application of Gray code

Properties:

The gray code is non-weighted code, which means that there are no specific weights assigned

to the bit positions.

In gray code, only one bit changes from one number to the next.

Application: Shaft position encoder in which analog data are represented by continuous change

of a shaft position. The shaft is partitioned into segments, and each segment is assigned a

number.

8. a) Convert (11001010)2 into gray code.

b) Convert a Gray code 11101101 into binary code.

Binary to Gray code conversion:

Binary:

Gray:

Gray:

Binary:

De-Morgans theorem 1: The complement of product of any number of variables is equivalent

to sum of the individual complements.

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St. Josephs college of Engineering/

ISO9001:2008

St. Josephs Institute of Technology

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Dept.of ECE

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De-Morgans theorem 2: The complement of sum of any number of variables is equivalent to

product of the individual complements.

Proof:

a) (AB) = A + B

b) (A+B) = AB

A

0

0

1

1

B AB (AB)

0 0

1

1 0

1

0 0

1

1 1

0

A B

1

1

1

0

0

1

0

0

A+B

1

1

1

0

A

0

0

1

1

B A+B

0

0

1

1

0

1

1

1

(A+B)

1

0

0

0

A

1

1

0

0

B

1

0

1

0

AB

1

0

0

0

10. Write the maxterm for M45 using minimum number of variables.

(45) 10 = 101101 = A + B + C + D + E + F

11. Use De Morgans theorem to convert the following expressions to one that has only single

variable inversions?

a) Y = (RST+Q)

b) Z = [ (A+BC) (D+EF) ]

c) X = [ (A+C) (B+D) ]

a) Y = (RST+Q) = ( R+S+T ) Q

b) Z = [ (A+BC)(D+EF) ] = (A+BC)+(D+EF)

Z = A(BC) + D(EF) = A(B+C) + D(E+F) = AB+AC+DE+DF

c) X = [ (A+C) (B+D) ] = (A+C) + (B+D) = AC+BD

12. Define distributive law.

a) X (Y + Z) = XY + XZ

b) X + YZ = (X + Y) (X + Z)

13. Simplify the expression: X = (A+B)(A+B+D)D

X = (A+B)(A+B+D)D = (AA + AB + AD + AB + BB + BD)D

X = ( 0 + AB + AD + AB + B + BD)D

X = (AD + B(A + A + 1 + D))D = (AD + B)D

X = ADD + BD = 0 + BD

X = BD

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St. Josephs Institute of Technology

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Dept.of ECE

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Y = [A(B+C)D] = A + BC +D

15. Describe the canonical forms of the Boolean function.

a) Sum of minterms: Combination of minterms using OR operation

Minterm (standard product) is a combination of n variables using AND operation for the

function of n variables.

Example for function of two variables A & B

F = AB + AB = m1 + m3

F = m(1,3)

b) Product of maxterms: Combination of maxterms using AND operation.

Maxterm (standard sum) is a combination of n variables using OR operation for the

function of n variables.

Example for function of two variables A & B

F = (A+B) (A+B) = M0 M2

F = M(0,2)

16. Describe the importance of dont care conditions.

Functions that have unspecified outputs for some input combinations are called incompletely

specified functions. We simply dont care what value is assumed by the function for the

unspecified minterms.

The unspecified minterms are called dont care conditions. These dont care conditions can

be used on a map to provide further simplification of the Boolean expression.

17. Give the canonical product form of F=x1x2x3+x1x2x3+x1x2x3+x1x2x3

F=x1x2x3+x1x2x3+x1x2x3+x1x2x3

F=001+010+100+011 = m1+m2+m4+m3

F=m (1, 2, 3, 4) ----------This is Sum form of F. Collecting the missing terms in

the Sum form of F derives the product form of F.

Product form:

F=M (0, 5, 6, 7) = M0 M5 M6 M7

F=(000) (101) (110) (111)

F=(x1+x2+x3)(x1+x2+x3)(x1+x2+x3)(x1+x2+x3)

18. Simplify Y = (A+B)(A+C)

Y = (A+B)(A+C) = AA + AC + AB + BC = 0 + AC + AB + BC

Y = AC + AB + BC

Y = AC + AB ---------using consensus theorem XY+XZ+YZ=XY+XZ

19. What is a prime implicant?

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St. Josephs college of Engineering/

ISO9001:2008

St. Josephs Institute of Technology

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Dept.of ECE

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A prime implicant is a product term obtained by combining the maximum possible number of

adjacent squares in the map.

Example: The possible prime implicants in the following K-Map are AB & AB

BC

A

10

00

01

11

10

1

1 0

1

0

3

20. Give the

0 canonical SUM form of F

2

F=(x1+x

0 2+x3)(x1+x2+x3)(x1+x2+x3)(x1+x2+x3)

4

F=(000)

(101) (110) (111) = M0 M5 M6 M7

1

F=M

(0,

5, 6, 7) ----------This is product form of F. Collecting the missing terms

5

1

in the Product form of F derives the SUM form of F.

7

SUM form:

6

F=m

(1, 2, 3, 4) = m1+m2+m4+m3

F=001+010+100+011

F=x1x2x3+x1x2x3+x1x2x3+x1x2x3

0

FD = (A+B)(A+C)(B+C)

22. Define the following: minterm and maxterm?

Minterm (standard product) is a combination of n variables using AND operation for the

function of n variables.

Possible minterms for a function of two variables A & B:

AB, AB, AB, AB

Maxterm (standard sum) is a combination of n variables using OR operation for the function

of n variables.

Possible maxterms for a function of two variables A & B:

A+B, A+B, A+B, A+B

23. Write the minterm of m32 using minimum number of variables.

(32)10 = 100000 =ABCDEF

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St. Josephs college of Engineering/

ISO9001:2008

St. Josephs Institute of Technology

5

Dept.of ECE

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24. Minimize the function using K-map: F=m(1,2,3,5,6,7)

BC

A

00

00

01

11

10

Quad (2,3,6,7) = B

Quad (1,3,5,7) = C

1

0

1 1

1

1

3

0

2

1

4

25. Find the1complement of x+yz.

F = x +5 yz

F = (x7+1 yz ) = x (y + z)

F=B+C

26. For a 6switching function of n variables, how many distinct minterms and maxterms are

possible?

2n distinct minterms and maxterms are possible

27. If A and B are Boolean variables and if A=1 and (A+B) = 0, find B.

If B = 0 ; (A + 0) = (1+0) = 1 =0

If B = 1 ; (A + 1) = (1+1) = 1 =0

So, B takes the value of both 0 & 1

28. Express the switching function f(BA) = A in terms of minterms.

f(BA) = A(1) = A ( B+B ) = AB + AB

29. Apply DeMorgans theorems to simplify (A+BC).

(A+BC) = A (BC) = A (B + C)

30. Plot the expression on K-map: F(w,x,y) =m (0, 1, 3, 5, 6) + d (2, 4)

xy

w

10

00

01

11

10

1

0

1 1

1

X

3

X

2

31. Simplify A+AB+A+B

1

4

A+AB+A+B

0 = A+A + AB + B

5

1

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Dept.of ECE

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= 1+ AB + B

=1

------------------(X+X=1)

------------------(X+1 = 1)

32. Give an example of a switching function for which the MSP form is not unique.

F = m (0, 1, 3, 4, 6) is an example of a switching function for which the MSP

form is not unique

Proof:

Pair (1,3) = wy -------EPI

Pair (4,6) = wy -------EPI

Pair (0,1) =wx -------PI

(or)

Pair (0,4) = xy -------PI

xy

w

10

00

01

11

10

1

0

1 1

1

F = wy + wy + wx

0

(or)

3

F = wy + wy + xy

1

2

0

4

So, for the given example the MSP form is not unique.

0

5

1 Express x + yz as the sum of minterms.

33.

7

x + yz = x(1) + (1)yz = x(y + y) + (x + x)yz = xy + xy + xyz + xyz

6

= xy(1) + xy(1) + xyz + xyz = xy(z + z) + xy(z + z) + xyz + xyz

= xyz + xyz + xyz + xyz + xyz + xyz

= xyz + xyz + xyz + xyz + xyz

------------------(x + x = x)

=111 + 110 + 101 + 100 + 011

=m7 + m6 + m5 + m4 + m3

x + yz =m(3, 4, 5, 6, 7)

34. Express f(a,b,c) = a+bc as sum of minterms

.

A B C B

BC

A+BC

0 0 0

1

0

0

0 0 1

1

1

1

f(a,b,c) = m(1, 4, 5, 6, 7)

0 1 0

0

0

0

0 1 1

0

0

0

1 0 0

1

0

1

1 0 1

1

1

1

1 1 0

0

0

1

1 1 1

0

0

1

35. Prove that a+bc = (a+b)(a+c)

a+bc = (a+b)(a+c)

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St. Josephs Institute of Technology

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Dept.of ECE

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A

0

0

0

0

1

1

1

1

B

0

0

1

1

0

0

1

1

C

0

1

0

1

0

1

0

1

BC

0

0

0

1

0

0

0

1

A+BC

0

0

0

1

1

1

1

1

A+B

0

0

1

1

1

1

1

1

A+C

0

1

0

1

1

1

1

1

(A+B)(A+C)

0

0

0

1

1

1

1

1

b) Z = (A+B)(A+B)

b) Z = (A+B)(A+B) = AA+AB+AB+BB

Z = 0+B(A+A)+B = B+B =B

37. What are Universal Gates? Why are they called so?

A Universal gates are NAND and NOR ,they are called so because using these codes any logical gate

or logical expression can be derived .

38. Define Karnaugh map.

To simplify the Boolean expression that in canonical form, Karnaugh map is used.

39. Implement OR using NAND only.

Input

Output

Rule

((XX)'(YY)')' = (X'Y')'

Idempotent

= X''+Y''

DeMorgan

= X+Y

Involution

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St. Josephs college of Engineering/

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St. Josephs Institute of Technology

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Dept.of ECE

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Input

Output

Rule

((XX)'(YY)')'

=(X'Y')'

Idempotent

=X''+Y''

DeMorgan

=X+Y

Involution

=(X+Y)'

Idempotent

Two forms of a function, one is a sum of products form (either standard or normal), the other a

product of sums form (either standard or normal)

42. Name the three sections of a TTL NAND gate circuit.

i.

Totem pole

ii.

Open collector

iii.

Tristate

43. What is meant by wired operation?

The outputs of two NAND gates or two NOR gates can be connected together to provide a

specific logic function. This type of logic is called wired logic or wired operation.

Example: Open-collector TTL NAND gates, when tied together, perform the wired-AND

logic.

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Dept.of ECE

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Positive logic:In positive logic system the high level H represents logic 1

Eg: positive logic AND gate

1

0

H

X

0

0

1

1

Y

0

1

0

1

Z

0

0

0

1

Negative logic : In negative logic system the low level L represents logic1

0

X

1

1

0

0

Y

1

0

1

0

Z

1

1

1

0

The input capacitance: Each CMOS input presents a 5 pF load to ground. This input

capacitance limits the number of CMOS inputs that one CMOS output can drive.

Propagation delay: The CMOS output has to charge and discharge the parallel combination

of all the input capacitances. This charging and discharging time increases as we increase

number of loads. Thus, fan-out for CMOS depends on the permissible maximum propagation

delay.

46. State the advantages and disadvantages of a totem-pole output.

Advantage: Operating speed is high.

Disadvantage: Output of two gates cannot be tied together to form wired-logic connection for

the purpose of forming a common-bus system.

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47. What is the state of a tristate output when it is disabled?

High-impedance state.

48. Define Propagation delay and Fan out.

Propagation delay of a gate is the average transition delay time for the signal to propagate

from input to output when input changes

The fan out of a gate specifies the number of standard loads that can be connected to the

output of the gate without degrading its normal operation.

49. Show how a two input NOR gate can be constructed from two input NAND gates.

__

A

A.B

B

A

__

A.B

Overlapping in K-map means when the cells which are already grouped in the K-map are used

once again for grouping

Ex:1

1

1

1

1

1

51. Give characteristics and specification of CMOS.

Ans. 1 Power supply (VDD) = 3 15 Volts

2. Power dissipation (Pd) = 10 nW

3. Propagation delay (td) = 25 ns

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4. Noise margine (NM) = 45% of VDD

5, Fan out (FO) = >50

52. Which TTL series is most suitable for battery powered circuits?

Ans. The most suitable TTL series for battery powered circuits is the low power TTL 74L series. Its

power dissipitation is about 1mW, which is very less as compared to other TTL series, It consumes

less power by increasing the value of all internal resistances.

53. What are the advantages of CMOS memory chips over bipolar memory chips?

Ans. Advantages of CMOS memory chip over bipolar memory chips.

1. Power dissipation per gate is very low i.e. about 0.05

dissipation is in milliwatts.

2. CMOS memory chips has high noise immunity than bipolar memory chips.

54. Why TTL logic family is faster then DTL?

Ans. TTL logic family is faster than DTL because in Transistor logic family the propagation delay per

gate is less than or equal to 10 ns except for low power low speed L, TTL. Where, as in Diode transistor

logic the propagation delay per gate in 30 ns. Hence, the speed of TTL logic family is fast as compared

to DTL logic family.

55. Why totem pole outputs cannot be connected together?

Ans. It is because when one output is high the other goes low and wired ANDed connection are used,

then a large current from supply +V will flows to ground through high state gate transistor and low state

gate transistor. Thus, large current will flow which damages the output transistors of totem pole TTL

arrangement.

56. Define noise margin. What is its importance?

Ans. Noise margin is also known as noise immunity. It is defined as the ability of a logic circuit to

tolerate noise without causing any unwanted changes in the output. Also, the quantative measure of

noise immunity is known as noise margin. It is important because it cause the voltage to drop into the

invalid range so as to avoid the effects of noise voltage.

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Dept.of ECE

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57. Compare performance of ECL with TTL.

Ans. Comparison in performance of ECL and TTL is as under.

58. How do open collector outputs differ from totem pole 0/Ps?

Ans. Following is the table of comparison between open collector outputs

Ans. 1. Bit : Bit is an abbreviation of the binary digit and it is the smallest unit of

information. It is either 0 or 1.

2. Byte : A byte is a combination of 8-binary bits A byte contains two nibbles. It is used in case of

representation of memory.

3. Nibble : Binary representation of four bits is called a nibble. In case of BCD i.e. binary coded

decimal and hexadecimal numbers nibble is used as both are four bit numbers

60. In a function of six variables the total maximum number of terms which the

expression can have will be

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Dept.of ECE

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Ans. A function having 6 variables, then the total maximum number of terms will be given by:

61. Explain the difference between Boolean operations OR and XOR. Use truth

tables to described how these operations differ.

Ans.

PART-B

1. Draw and explain the operation of TTL inverter.

Ans.

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Dept.of ECE

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Tristate TTL inverter utilizer the high-speed operation of totem-pole arrangement while permitting

outputs to be wired ANDed (connected together). It is called tristate TTL because it allows three

possible output stages. HIGH, LOW and High-Impedance. We know that transistor T3 is ON when

output is HIGH and T4 is ON when output is LOW. In the high impedance state both transistors,

transistor T3 and T4 in the totem pole arrangement are med OFF. As a result the output is open or

floating, it is neither LOW nor HIGH. The above fig. shows the simplified tristate inverter. It has two

inputs A and E. A is the normal logic input whereas E is an ENABLE input. When ENABLE input is

HIGH, the circuit works as a normal inverter. Because when E is HIGH, the state-of the transistor

T1 (either ON or OFF) depends on the logic input A and the additional component diode is open

circuited as cathode is at logic HIGH. When ENABLE input is LOW, regardless of the state of logic

input the base-emitter junction of T is forward biased and as a result it turns ON. This shunts the current

through R1 away from T2 making it OFF. As T2 is OFF, there is no sufficient drive for T4 conduct and

hence T4 turns OFF. The LOW at ENABLE input also forward biases diode D2, which shunt the current

away from the base of T3, making it OFF. In this way, when ENABLE output is LOW, both transistors

are OFF and output is at high impedance state.

2. Draw the circuit of an open collector TTL NAND gate and explain its operation

Ans. The circuit diagram of 2-input NAND gate open-collector TTL gate is as shown:

Working:

Case.1 : When A = 0,B = 0

When both inputs A and B are low, both functions of Q1 are forward biased and Q2 remains off. So no

current flows through R4 and Q3 is also off and its collector voltage is equal to Vcc i.e. Y = 1

Case2 : When A = 0, B = 1 and

Case 3: When A = 1, B = 0

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St. Josephs college of Engineering/

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Dept.of ECE

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When one input is high and. other is low, then one junction is forward biased so Q2 is off and Q3 is also

off. So collector voltage is equal to Vcc i.e. Y = 1

Case 4: When A = 1, B = 1

When both inputs are high, Q1 is turned off and Q2 turned ON Q3 goes into saturation and hence Y =

0. The open-collector output has main advantage that wired ANDing is possible in it.

3. Draw the circuit of TTL NAND gate and explain its operation. Compare the TTL and ECL

logic families.

Ans. Two input TTL NAND gate-is given in fig. (1). In this transistor T3 and T4 form a totem pole.

Such type of configuration is called-as totem-pole output or active pull up output.

So, when A = 0 and B = 1 or (+5V). T1 conducts and T2 switch off. Since T2 is like an open switch, no

current flows through it. But the current flows through the resistor R2 and into the base of transistor

T3 to turn it ON. T4 remains OFF because there is no path through which it can receive base current.

The output current flows through resistor R4 and diode D1. Thus, we get high output.

When both inputs are high i.e. A = B = 1 or (+ 5V), T2 is ON and it drives T4 turning it ON. It is noted

that the voltage at the base of T3 equals the sum of the base to emitter drop of T4 and

of T2..

The diode D1 does not allow base-emitter junction of T3 to be forward-biased and hence, T3 remains

OFF when T4 is ON. Thus, we get low output.

It works as TTL NAND gate.

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Dept.of ECE

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4. Draw the circuit of Toetem pole NAND gate and explain its operation. Explain why these

cannot be wire ANDed ?

Ans. In TTL Totem pole NAND gate, multiple emitter transistor as input is used. The no. of inputs may

be from 2 to 8 emitters. The circuit diagram is as shown

Case 1:

When A = 0, B = 0

Now D1 and D2 both conduct, hence D3 will be off and make Q2 off. So its collector voltage rises and

make Q3 ON and Q4 off; Hence output at Y = 1 (High)

Case 2 and Case 3:

If A = 0, B = 1 and A = 1, B=0

In both cases, the diode corresponding to low input will conduct and hence diode P3 will be OFF

making Q2 OFF. In a similar way its collector voltage rises Q3 ON and Q4 OFF. Hence output

voltage Y = 1 (High).

Case 4: A = 1, B = 1

Both diodes D1 and D2 will be off. D3 will be ON and Q2 will ON making Q4 also ON. But

Q3 will be OFF. So output voltage Y = 0.

All the four cases shows that circuit operates as a NAND gate.

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St. Josephs college of Engineering/

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_____________________________________________________________

Totem pole cant be Wired ANDed due to current spike problem. The transistors used in circuits may get

damaged over a period of time though not immediately. Sometimes voltage level rises high than the

allowable.

5. Discuss

(i) CMOS inverter

(ii) Tristate logic

Ans. (i) CMOS Inverter: It is complementary MOSFET obtained by using P-channel MOSPET and nchannel MOSFET simultaneously. The P and N channel are connected in series, their drains are

connected together, output is taken from common drain point. Input is applied at common gate terminal.

CMOS is very fast and consumes less power.

(Gate source) voltage of Q1 will be 0 volt, it will be off. But

Q2 will be ON; Hence output will be equal to +VDD or logic 1.

Case 2. When input Vi = 1, The

(Gate source) voltage of Q2 will be 0 volt, it will be OFF, But

Q1 will be ON. Hence output will be connected to ground or logic 0.In this way, CMOS function as an

inverter.

(ii) Tri-state logic: When there are three states i.e. state 0, state 1 and high impendence i.e. called Tristate logic. High impedence is considered as state when no current pass through circuit. Although in

state 0 and state 1 circuit functions and current flows through it.

6. Find the complement of

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Ans.

Its complement is given by:

7. What is K-map? Why we need K-maps? Give the various types of K-map.

Ans. K-map i.e. Karnaugh map is simply a graphical method for representing a Boolean fraction. The

Karnaugh map is a systematic method for simplify and manipulating Boolean expression. It is used to

simplify a logic expression or to convert a truth table to its corresponding logic circuit. It is used for the

minimization of switching functions but upto six variables. For more than six variable it becomes

complex or cubersome.

The K-map for n-Boolean variable switching function consists of

the normal or standard term i.e. one minterm or maxterm.

Need of K-maps: We need K-map for representing Boolean function through graphical method.

Because K-map simplify and manipulates a Boolean expression. So to solve or simplify a Boolean

expression, we use K-map. K-map can be used for problems involving any number of input variables

(upto six variables) which is not easily solve by Boolean Algebra. Types of K-map :

Types of K-maps commonly used are

1. Two variable K-map

2. Three variable K-map

3. Four variable K-map

4. Five variable K-map

5. Six variable K-map

1 Two variable K-map

= M formula is used where, n = Number of variables and M = Number of squares.

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Formula used is = M

Where, n = number of variables, M = Number Of squares

n=4

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variables are A, B, C, D and E. It is shown in figure.

8. Solve following using K-map and Boolean algebra:

Solution.

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Using boolean,

So

Using boolean,

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Grouping of 3 variable K-map

9. Solve following using K-map and boolean algebra:

Solution.

Using boolean,

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Using boolean,

Using boolean,

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10. Solve the following using K-map and verify by using boolean algebra:

(i) F (A, B, C, D) =

Solution

(ii) F (A, B, C, D) =

Solution.

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(iii) F (A, B, C, D) =

Solution

f (A, B, C, D) =

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Ans.

Ans Truth table for F =

This is the output of an XOR gate.

Truth Table :

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Ans.Y=AC +AB+ BC

The canonical SOP form is given by:

Ans. Single bit.

(i) Evaluate the expressions

(i)A+1;

(ii) A + A;

Ans. (i) A + 1 = 1

It comes under OR laws.

Oring an input with 1, always results in a high output.

A+ 1 = 1

Case I, Let A = 0

0+ 1 = 1

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Case II, Let A = 1

1+1=2

Hence, A + 1 = 1

(ii) A + A = A

Case I, Let A = 0

0+0=0

1+1=1

Hence, A + A = A

16. Realize and OR and NOT using NOR gates.

Ans. (i) AND gate using NOR gates:

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Ans. Realization of X-OR using NOR gate only

Ans. f (A B, C D) =

19. Simplify the expression 2. =AB + AC + ABC (AB + C). Implement using

minimum number of NAND gates.

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Ans Z = AB + AC + ABC (AB + C)

= AB + AC + ABC. AB + ABCC

= AB + AC + ABC + ABC

= AB + AC + ABC

=AB(1 + C) + AC

= AB + AC

Implementation using minimum number & NAND gates:

Use a K-map to minimize the function.

Ans.

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21. (i) Make a K-map for the function:

(iii) Minimize it and realize the minimized expression using NAND gates only.

Ans. (i)

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Circuit diagram:

22. Realize OR, AND, NOT, NOR gates using NAND gates only.

Ans. (i) OR gate using NAND only:

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(iv) NOR gate using NAND only:

f (A, B, C, D) =

(0, 1, 2, 3, 5, 7, 8, 9, 11,14)

Ans.

24. Given below a four variable Karnaugh map with four entities. Write the corresponding

Boolean expression.

abcd + a b c d + abc d + abc d

Also, the minimised output is cd.

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25.Obtain the minimal SOP expression for

(0, 1, 2, 4, 6, 9. 11, 12, 13) and implement it in NAND logic.

Ans. f (A, B, C, D) = (0, 1, 2, 4, 6, 9. 11, 12, 13)

Firstly K-map

implement it in NOR logic.

Ans. Firstly, fill given os in K-map, to get the expression in POS form.

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27. Simplify the function using Karnaugh map and implement using minimum Lumber of logic

gates.

F = (2, 9, 10, 12, 13) + D(1, 5, 14)

What are the limitations of Karnaugh map?

Ans.

K-map:

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Implementation using minimum number of logic gates can be obtained from the minimized output of the

given function.

Implementation is as shown:

Limitations of K-map:

For large number of variables i e more than six variables the K-map becomes cumbersome It is difficult

to solve the output of K-map having 7 8 and more variables as it covers more space and need large time

for calculations Also, the K-map for 6 variables is possible and for more variables Q-M method or

tabular minimization method is used

28. Minimize the following four variable functions using sum-of-products

Karnaugh Maps

f(a, b, c, d) = f1(a, b, c, d)

f2(a, b, c, d)

where f1 = a d + bc + b c d +

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and f2 =

Ans.

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list all prime implicants of essential prime implicants. Is the minimum SOP unique, if not all the

minimal solutions for the functions?

F (a,b,c,d,e,f) = (0,2,4,7,8,16,24,32,36,40,48) + d (5,18,22,23,54,56)

Ans. Arrange the minterms according to no. of ls

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Thus, output

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30. Design a combinational circuit which has four inputs and one output. The output is equal to 1

when

(i) All the inputs equal to 1 or

(ii) None of the inputs equal to 1.

(iii) An odd number of inputs are equal to 1.

Draw the logic circuit using minimum number of NAND gates.

Ans.

Truth Table

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designations of mm-terms using Q M method.

Ans. Using Q-M method

(0,1,3,4,6,7,8,9, 14,15)

Step 1

Step 2

Step 3

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Step 4

Step 5

designations of minterms using Q-M method.

Ans.

Step 1:

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Step 2:

Step 3:

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Step 4:

Step 5:

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UNIT-II: COMBINATIONAL CIRCUITS

1. Distinguish between combinational logic and sequential logic.

S.No

Combinational logic circuit

1

Block diagram:

Inputs

Outputs

Inputs

Combinatio

nal circuit

output signals

entirely dependent upon the inputs present

at that time.

Decoder

Outputs

Combin

ational

circuit

Memor

y

element

It consists of a combinational circuit to

which memory elements are connected

to form a feedback path.

The outputs dependent not only on the

present input variable but they also

depend upon the past value of the input

variable.

Sequential circuits are slower than the

combinational circuits.

Sequential circuits are comparatively

harder to design

Example: Serial Adder, Counter, shift

register

Truth table

A

0

0

1

1

B

0

1

0

1

Implementation table

y

1

1

1

0

I0

I1

Logic diagram

1

A

2X1

MUX

3

B

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3. Mention the difference between a DEMUX and a MUX

S.No

DEMUX

1

Block diagram:

Single

Input

MUX

2n Intputs

2 Outputs

2 X1

1 X 2n

MUX

DEMU

X

n selection

inputs

n selection

inputs

Single

output

information on a single line and transmits

this information on one of many output

lines

Data Distributor

circuit that selects binary information

from one of many input lines and

directs it to a single output line.

Data selector

a. Data selection

b. Data routing

c. Operation sequencing

d. Parallel to serial conversion

e. Waveform generation

f. Logic-function generation

5. How does an encoder differ from a decoder?

S.No

Decoder

1

Block diagram:

Encoder

2n Intputs

n Intputs

2n Outputs

n X 2n

2

3

4

Decode

r

A decoder is a combinational

circuit that

converts binary information from n input

lines to a maximum of 2n unique output

lines.

A decoder accepts a set of binary inputs

and activates only the output that

corresponds to that input number.

Example: Binary to Octal decoder

n Outputs

2n X 1

Encode

r

An encoder is a digital circuit that

performs the reverse operation of a

decoder. An encoder has 2n input lines

and n output lines.

An encoder generates the binary code

corresponding to the input activated.

Example: Octal to Binary encoder.

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6. Draw the logic diagram of a one to four line demultiplexer.

Implementation of AND function

Truth table

A

0

0

1

1

B

0

1

0

1

Implementation table

y

0

0

0

1

Logic diagram

I0

I1

0

A

2X1

MUX

B

0

A

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Implementation of OR function

Truth table

A

0

0

1

1

B

0

1

0

1

Implementation table

y

0

1

1

1

I0

I1

Logic diagram

A

1

2X1

MUX

A

1

B B.

8. State the condition to check the equality of two n-bit binary numbers A and

A = An-1 . A3 A2 A1 A0

B = Bn-1 . B3 B2 B1 B0

The two numbers are equal if all pairs of significant bits are equal.

The equality relation of each pair of bits can be expressed logically with an equalence function

(X-NOR):

Xi = AiBi + AiBi

i = 0, 1, 2, 3, .(n-1)

The condition to check the equality of two n-bit binary numbers is

R(A=B) = Xn-1 Xn-2 .. X3X2X1X0

If R(A=B) =1, the two numbers A and B are equal, otherwise they are unequal.

9. Draw a 1 to 2 demultiplexer circuit.

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A3 AIC

A1 draw

A0 theB3logicB2diagram

B1 B

11. Using a single

of0 a 4-bit comparator.

2 7485,

IA > B

4-bit

Comparator

IA < B

IC 7485

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OA > B

OA < B

OA = B

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S.No

DEMUX

1

Block diagram:

Single

Input

DECODER

2n Outputs

1X2

DEMU

X

n Intputs

2n Outputs

nX2

Decode

r

n selection

inputs

information on a single line and transmits

this information on one of many output

lines

Data Distributor

and activates only the output that

corresponds to that input number.

Decoder with enable input is used as

demultiplexer.

A priority encoder is an encoder circuit that includes the priority function. The operation

of the priority encoder is such that if two or more inputs are activated at the same time, the

output binary code will be generated to the highest-numbered input.

14. Design a combinational logic circuit that will allow input signal A to pass through to the output

when the control inputs B and C are different, otherwise the output is high.

ABC

Output

BC

000

1

A

00

01

11

10

001

0

10

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0

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1 1

1

101

1

0

110

1

3

55

111

1

1

2

1

4

5

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Y=A + (BOC)

15. Realize XOR function using only NAND gates.( OR ) Implement Y = A'B + AB' using only

NAND gate

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A

B

A

B

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A

B

19. Draw the logic diagram and truth table for a half subtractor.

Truth Table

X

20. How many binary outputs would a 3 digit BCD-to-Binary converter have?

12 outputs

21. Define Combinational circuit?

A combinational circuit consists of logical gates whose outputs at any time are

determined from the present combination of inputs. A combinational circuit performs an

operation that can be specified logically by a set of Boolean functions. It consists of input

variables, gates and output variables.

22. What is an ALU?

An ALU is an arithmetic logical Unit. It performs all arithmetical like(Addition,

Multiplication, subtraction, division) operations.

23. Give the truth table for half adder and write the expression for sum and carry?

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A half adder is a logical circuit that performs an addition operation on two binary digits.

The half adder produces a sum and a carry value which are both binary digits.

The drawback of this circuit is that in case of a multibit addition, it cannot include a carry.

A

B

C

24. Obtain the expression for sum and carry output of a full adder and implement the same.

S=z

(X

Y)

= Z'(XY'+X'Y) + Z(XY'+X'Y)'.

= Z'(XYM-X'Y) + Z(XY+X'Y').

= XY'Z'+X'YZ'+XYZ+X'Y'Z.

C = XY'Z+X'YZ+XY.

25. Obtain an expression for difference and borrow outputs of a full subtractor.

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26. Define SSI and MSI.

SSI: Small scale integration- less than 10 logic Gates are fabricated in a single chip.

MSI: Medium scale Integration-Logic components fabricated in single packages has an volumes

less than 100. These Ics are used for digital operation for decoders, demux, adders etc.

27. List the applications of decoders.

Ans. 1 Decoders are used in counter systems

2. Decoders are used for A/D conversion.

3 Decoders are used for D/A conversion

4. Decoders are used in seven segment digital displays.

Ans.

29. Explain half subtractor with the help of its internal circuit

Ans. To subtract two numbers i e two Input variables A and B we get two output variable i e difference

D and borrow Bo It is known as half subtractor Functional diagram is shown:

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Its truth table is as shown:

Ans. The selection lines of the DEMUX can be used as input lines of decoder and if the

data input of the demultiplexer is used as the enable input of the decoder then we can use the

demultiplexer as a decoder.

PART-B

1.Implement half adder circuit using 4 : 1 MUX or multiplexers only.

Ans. Truth table of half adder is as shown:

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Implementation:

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Ans. The truth table for 3 bit Gray Code to binary conversion is as shown:

K-Maps:

For 82:

For B1:

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For Bo:

Ans. BCD to Excess-3 Code Converter:

The input variables are BCDs (A, B, C and D) and output variables are excess-3 code (E3, E2, E1 and

E0)

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Truth Table

Minimization Using K-map:

For E3

E3 = A + BD + BS

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For E2

For E1

For E0

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Ans.

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Ans. 3 line to 8 line decoder circuit is as shown:

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It has three input lines i.e. A, B and C and has eight output lines

i.e. D0, D1, D2, D3, D4, D5, D6 and D7

Ans

Logic Circuit:

Ans. For 30: 1 MUX, 5 select lines are required. 4 select lines are for 16 : 1 MUXs and

1 select line for 2: 1 MUX.

number of inputs for a MUX.

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Ans. Full subtractor is used to subtract three bits and generate difference and borrow.

Truth-table of full-subtractor is:

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Ans. 4 bit comparator IC in 7485.

It is used for 16 bit comparator.

Thus, 4 ICS are used, which is as shown:

11. Obtain the truth table for a combinational circuit that accepts a three bit number and

generates an output binary number equal to the square of the input number.

Ans. Truth table is as shown for inputs and the corresponding square outputs.

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Ans.

Ans. Operations Performed by Encoder:

1 Encoder is a combinational circuit which encodes one digital input code to them digital output code

like octal to binary encoder Decimal to BCD encoder etc

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2 It provides the security for the data by encoding it

3 It saves the bandwidth over the channels

Operations Performed by Decoder

1 A decoder is a combinational circuit, that converts n input binary information to 2 output lines e g 2 to

4 line decoder 3 to 8 line decoder etc

2 It is used at the receiver part to decode the information

14. Implement the following function using 3 to 8 decoder

Ans.

15. Define a demultiplexer Show how to convert a decoder into a demultiplexer indicate how to

add a strobe to this system

OR

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16.What is demultiplexer Explain the difference between DMIJX and MUX

Ans. Demultiplexer: Demultiplexer is a device which has single input line and many i e

output

lines The relation of specific output line is controlled by the value of n selection lines It performs the

inverse operation of multiplexer

In case of decoder, it has n input lines and

unique output lines Let us take an example of 2 to 4 line

decoder to convert the decoder into a demultiplexer.

2 to 4 line Decoder:

It can be converted into demultiplexer if D1 i e data Input line is converted to all the AND gates

simultaneously.

Stroke signal is also added to all the AND gates simultaneously as shown in fig.

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Strobe signal is similar to enable signal for chip selection. It is an active low signal. If high signal is

applied to stroke the chip will be disable because i = 0 goes to all the AND gates And we receive no

output at D0, D1, D2 and D3

Difference between DMUX and MUX:

Ans. Gray to Excess3 code converter:

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Circuit Diagram:

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Ans. 3-bit look ahead adder : The bit look ahead carry adder speeds up The process by eliminating

ripple carry delay. It examines all the input bits simultaneously and generates carry-in-bits for all stages

simultaneously. It is done with two additional functions carry generate and carry propagate function.

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The carry generate function indicates as to when a carry-out would be generated by full-adder. A carryout is generated only when both the inputs bits are 1. This condition is expressed as the AND function of

the two bits A and B.

Carry generate (CG) = A . B

Carry propagate (GP) = A

19.Give the logic diagram of 4-to-2 encoder and explain its importance in design of digital system.

Ans. Encoder is a device which encodes the input of any code to output of any code.

Encoder may have

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Circuit diagram

Encoder has very much importance in digital system. With the help of it, we can convert decimal to any

other system like binary or BCD etc.

20. Draw the circuit of a 3 bit binary subtractor and explain its operation with the help of an

example

Ans. Let the three inputs are A, B and C. Output will difference (D) = (A B C) and borrow (Bo).

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Circuit diagram:

Ans. Truth Table:

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The circuit diagram for single bit or one bit comparator is as shown in figure:

Ans. Full adder circuit using NAND gates only is as shown:

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Ans. A BCD adder adds two BCD digits and produces a BCD digit If the sum of BCD digits is less than

equal to 9 then it is valid BCD form If sum is greater than 9 then 6 (six) i.e. (0110)2 is added in sum to

make it valid

Let us 4 bit binary adder A0 A1 A2 A3 and B0 B1 B2 B3 produces sum S0 S1 S2 S3. A combinational

circuit is there to check sum is 9 or more than 9 so that six can be added to it. For combination circuit,

truth-table is as:

K-map

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We will get correct BCD sum from output of Adder-2. Which will be in BCD form.

25. Write note on 3 bit binary magnitude comparator.

Ans. 3 bit binary magnitude comparator:

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Where, A = A2 A1 A0 having three bits and B = B2 B1 B0 also having three bits.

A2 A1 A0 are compared with another three bits i.e. B2 B1 B0

Total combinations are possible. As

A = B and A < B.

= 64. Thus, six variable k-maps are required to solve for A > B,

26. Realize the circuit of a full adder in terms of two half adders from its truth table.

Ans. The full adder can be designed from two half adders like this:

Let the three inputs are A, B and Cin. Two outputs are S (sum) and carry (Co).

27. What are Magnitude comparators Explain the design of magnitude comparators with the

help of a suitable example

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Ans. A comparator is a logic circuit used to compare magnitude to two binary numbers or more The

result will be, either bits will be equal greater or lesser

K-map

Similarly, 7485 is TTL 4 bit magnitude comparator. Thee inputs can be extended to compare more than 4

bits.

28. Use a 8 x 1 MUX to implement the logic function

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Ans.

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UNIT III: SEQUENTIAL CIRCUITS

Q

0

0

0

0

1

1

1

1

J

0

0

1

1

0

0

1

1

K

0

1

0

1

0

1

0

1

Q(t+1)

0

0

1

1

1

0

1

0

D Flip-Flop is best suited for synchronous transfer.

3. What is meant by the term edge triggered?

Output transitions occur at a leading edge or a trailing edge of the clock pulse.

4. Show D flip-flop implementation from a J-K flip-flop

Q

Q(t+1)

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0

0

1

1

0

1

0

1

0

1

X

X

X

X

1

0

Q

0

0

1

1

D

0

1

0

1

Q(t+1)

0

1

0

1

Because of the feedback connection in the JK flip-flop, when both J & K are equal to 1 at the

same time, the output will be complemented while activating the clock pulse.

The output is complemented again and again if the pulse duration of the clock signal is

greater than the signal propagation delay of the JK flip-flop for this particular input

combination (J=K=1)

There is a race between 0 and 1 within a single clock pulse. This condition of the JK FF is

called race-around condition or racing.

9. How do you define Excitation table?

Excitation table consists of two columns, Q(t) and Q(t+1), and a column for each input to

show how the required transition is achieved.

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10. Define the hold time requirement of a clocked FF?

The input must not change after application of the positive going transition of the pulse. The

hold time is equal to the propagation delay of gate.

11. What is meant by triggering of Flip flop?

The state of a flip-flop is switched by a momentary change in the input signal. This

momentary change is called a trigger and the transition it causes is said to trigger the flip-flop

12. Differentiate between Flip flop & Latch.

Flip-flop has clocked memory element. Latch has unclocked memory element.

13. Give the truth table of T flip flop.

Q

0

0

1

1

T

0

1

0

1

Q(t+1)

0

1

1

0

The binary information present at the data i/p of the D FF is transferred to the Q o/p when the

cp input is enabled. The o/p follows the data i/p as long as the pulse remains in its 1 state. When

the pulse goes to 0, the binary information that was present at the data i/p at the time the pulse

transition occurred is retained at the Q o/p until the pulse i/p is enabled again. So D FF is known

as Delay FF.

15. Distinguish between synchronous and asynchronous counters.

S.No

Synchronous counter

1

All the flip-flops are clocked

simultaneously

2

There is no connection between the

output of the first flip-flop and the

clock input of the next flip-flop

3

All the flip-flops are not clocked

simultaneously.

The clock input of each flop-flop is

driven by the output of previous flipflop. External clock is given to the

flip-flop that holds LSB of the binary

count.

Main draw back of these counters is

their low speed as the clock is

propagated through number of flipflops before it reaches last flip-flop.

flip-flops there is no problem of

propagation delay. Hence they are

preferred when number of flip-flops

increases in the given design

4

Parallel counter

Serial counter

5

Design involves complex circuit as Logic circuit is very simple even for

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number of states increases

16. Name the two problems that may arise in ripple counters or asynchronous counters.

1. Cumulative flip-flop Delay

2. There is a possibility of glitches occurring at the output of decoding gates used with a

ripple counter.

17. Why is parallel counter referred to as synchronous?

In parallel counter all flip-flops are triggered by the same clock at the same time. All flipflops are synchronized by the common clock signal.

18. Draw a Mod 6 counter using feedback technique.

In a counter if the next state of some unused state is again an unused state and if by

chance the counter happens to find itself in the unused states and never arrived at a used state

then the counter is said to be in the lockout conditions.

20. What is a self-correcting counter?

A self-correcting counter is one that if it happens to be in one of the unused states, it

eventually reaches the normal count (valid state) sequence after one or more clock pulses.

21. Mention why the decoding gates for an asynchronous counter may have glitches on their

outputs?

Since each flip-flop in the asynchronous counter is triggered by the output of the previous

flip-flop, the output of each flip-flop is delayed by one flip-flop delay time.

The accumulated propagation delays serve to essentially limit the frequency response of

ripple counter.

The decoding gates can be connected to the ripple counter to reset the count. The glitches at

the output of decoding gates are caused by the delay between the flip-flop outputs.

22. State how an asynchronous down counter differs from an up counter circuit

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In asynchronous up counter each flip-flop is triggered by the normal output of the previous

flip-flop.

Whereas in asynchronous down counter each flip-flop is triggered by the complemented

output of the previous flip-flop.

An asynchronous counter in which each flip-flop is triggered by the output of the

previous flip-flop.

24. What is the minimum number of flip-flops needed to build a counter of modulus 60?

Modulus N < 2k , where k is the number of flip-flops

Modulus 60 < 26 = 64, k = 6

The minimum number of flip-flops needed to build a counter of modulus 60 is 6.

25. What is Shift Register?

A register capable of shifting its binary information either to the right or to the left is called a

shift register.

26. What is the major advantage of serial transfer over parallel transfer?

Serial operations require less equipment.

27. What is a universal shift register?

A register may operate in any of the following five modes

1. SISO

2. SIPO

3. PIPO

4. PISO

5. Bidirectional

If a register can be operated in all the five possible ways, it is known as Universal Shift

Register.

28. A shift register comprises of JK flip-flops. How will you complement the contents of the

register?

By setting J and K inputs of all flip-flops to 1 at the same time, we can complement the

contents of the shift register (PIPO) that comprises of JK flip-flops.

29. Mention the uses of shift registers.

Storage Device: The primary use of shift register is temporary data storage.

Time delay generation: A SISO shift register can be used to introduce time delay TD

between the input and the output digital signals. The time delay can be given as T D = N x

(1/fc) Where N is the number of stages and fc is the clock frequency.

Serial-to-Parallel Converter (SIPO)

Parallel-to-serial Converter (PISO)

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Shift register counter: A shift register with the serial output connected back to the serial

input is called shift register counter. Because of such a connection, special specified

sequences are produced as the output. The most common shift register counters are the ring

counter and the Johnson counter.

30. If a serial-in-serial-out shift register has N stages and if the clock frequency is f, what will

be the time delay between input and output?

Time delay between input and output = N / f

Mealy and Moor machines are two models of clocked or synchronous sequential circuit.

Mealy machine: The output depends on both the present state of the flip-flops and on the

inputs.

Moore machine: The output depends only on the present state of the flip-flops.

33. Draw the timing diagram for a 3-stage ring counter.

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State diagram is the graphical representation of state table of sequential logic circuits.

In the state diagram, a state is represented by a circle and the transition between states is

indicated by directed lines connecting the circles.

The directed lines are labeled with two binary numbers separated by a slash. The input value

during the present state is labeled first and the number after the slash gives the output during

the present state.

Example:

0/ 0

0

0

0/ 0

1/ 1

1

1

1/ 0

0

1

0/1

1/ 0

0/ 1

1

0

1/ 1

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35. What is finite state machine?

A finite state machine (or finite automation) is an abstract model describing the synchronous

sequential machine and its spatial counter, part, the iterative network

36. What do you meant by the term state reduction problem?

The reduction of the number of flip-flops in a sequential circuit is referred to as the state

reduction problem. State reduction algorithms are concerned with procedures for reducing the

number of states in a state table while keeping the external input output requirements

unchanged.

37. Define Bit time & Word time.

The time interval between clock pulses is called the bit time, and the time required to shift the

entire contents of a shift register

38. Give applications of J-K flip-flops.

Ans.1. J-K flip-flops are used in shift registers.

2. J-K flip-flops are used in counters.

Ans.

Ans. Race around condition can be eliminated in JK latch by two ways

1. Using the edge triggered J-K flip-flop.

2. Using the master slave J-K flip-flop.

41. What is a Glitch?

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Ans. Glitch is a short duration pulse or spike that appears in the outputs of a counter with MOD

number

42. How many flip-flops are required to count 16 clock pulses? Why?

Ans. To count n clock pulses m flip-flops are required, where,

43. Give application of D and T flip-flops.

Ans. D flip-flops are delay flip flops and are extensively used for temporary storage of data in registers.

Hence, registers make use of D flip-flops.

T flip-flops are toggle flip-flops and are used in counters. Hence, counter designing make use of

T flip-flops.

44. A presettable counter has eight flip-flops. If the preset number is 125, what is the modulus?

Ans.

Thus, MOD 131.

45. Differentiate between sequential and combination circuits.

Ans.

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46. The clock frequency is 2MHz. How long will it take to serial load the eight shift register?

Ans.

n=8

Time taken to load serially the eight bit will be given by

Ans. Flip-flop : Flip-flop is a sequential circuit which is used to store single bit of

information at a time i.e. either 1 or 0 at a time. It has two stable output states. It can stay in one of

the two stable states unless state is changed by applying external inputs. Thus, it as a basic memory

element for storage of data in binary form.

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There are various types of flip-flops

1. S-R flip flop

2. J-K flip-flop

3. D-type flip flop

4. T-type flip-flop

48. What is shift register?

Ans. Shift register : A register capable of shifting its binary information either from right to left or left

to right is known as shift register. It consists of flip-flops connected is cascade. All flip-flops receive a

common clock pulse which causes the shift from one stage to the next stage.

It is of four basis types:

1. Serial in serial out register

2. Serial in parallel out register

3. Parallel in serial out register

4. Parallel in parallel out register.

Bi-directional shift register and Universal shift registers are also used for different applications.

49. What is universal shift register?

Ans. Universal shift register performs similar operation and function as that of bidirectional shift

register i.e. it can shift data from left to right or right to left, in addition to it data can be shifted in and

out and in serial as well as in parallel form.

50. Draw a logic symbol for a D-flip-flop and compare with RS flip-flop.

Ans.

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In case of RS two inputs are there hence four possible combined are used. But in case of D flip-flop it

has only one input so and two combination are used. Also, in D flip-flop what ever we want to store will

be put as input. If we want to store 1. 1 is the input and if 0 is input, 0 will be stored in D flip-flop.

51. Differentiate between synchronous and asynchronous counters.

Ans.

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52. What is buffer register?

Ans. Buffer registers are also called as storage registers. They are primarily used for temporary storage,

of binary information or data. They provide place to hold data until it is processed. That is why they are

known as buffer registers.

53. Suggest four applications of shift registers.

Ans. Applications of shift registers

1. It is used in ring counters.

2. It is used in sequence generators.

3. It is used for data conversion in computers i.e. serial to parallel, parallel to serial etc.

4. It is used for time delays i.e. serial in serial out shift register are used for this purpose.

5. It is used in Johnson counter / twisted ring counter.

54. Differentiate between static and dynamic shift registers.

Ans.

Ans. The mod of 6 bit ring counter is given by 2 where n = number of bits.

2 = 64.

Thus MOD-64.

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56. Give expression for maximum frequency of operation of n-bit Asynchronous and synchronous

counters.

Ans.

It is same for synchronous counter unless no. of flip-flop, where the maximum frequency of

synchronous counter is

Ans.

58. Specially where Master-slave J-K flip flop is preferred for use.

Ans. Master slave J-K flip-flop is preferred where we want to avoid multiple toggling and race around

conduction. In this flip-flop, master F/F is positive edge triggered and slave flip-flop is negative edge

triggered. The slave ftp-flop followed the master flip-flop.

59. Applications of D Flip Flop. ________________________________________________________________________

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Ans.1. D Flip-flop can be used as a delay element

2. As a memory element.

3. In counters! timers.

4. in various types of registers, like in SIPO, SIPO etc.

PART-B

1. Explain T-flip-flop with suitable internal structure.

Ans. The functional block diagram of T flip-flop is as shown in fig.

A T flip-flop is designed by combining both the inputs of Gate 1 and 2 together. Thus, when J = K = 0,

Q have same previous state i.e. hold state or no change state. When J = K = l, Q have toggle state i.e.

invert the previous state.

2. Convert SR flip-flop to T flip-flop.

Ans. Firstly write the truth table for SR to T flip-flop as shown:

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For S:

For R:

Implementation:

3. For the given state diagram, draw the state reduction diagram.

Stats Diagram:

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Ans. The edge triggered D flip-flop uses an edge-detector circuits so that the output will respond to D

input only when the active transition of clock takes place. It is as shown in fig.

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From fig. when enable is 1, the D input will given a 0 at either the

or

inputs of NAND

latch. Thus, 0 becomes same as D. Thus, when enable is 1 the output Q will look exactly like D.

Hence, the D latch is said to be transparent latch.

5. Give the truth-table for each flip-flop type: (a) J-K ; (b) D ; and (c) T

Ans. Truth table of J-K Flip-flop:

2. D Flip-flop:

3. T Flip-flop:

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Toggle means 0 changes to 1 and 1 changes to 0 with the passage of each clock

6. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input

and done output. The counter should produce done output after completion of counter in either

direction.

Ans. 3-bit synchronous up-down counter:

7. Draw the logic circuits and the excitation tables for the T, JK flip-flops.

Ans.

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8. Classify the sequential circuits.

Ans.

S-R flip flop.

Ans. Gated S-R Flip-Flop : A gate S-A Flop/flop requires an enable (E) input. When enable is high,

the output changes according to the inputs S and R. However when enable is ineffective, no change of

state take place. Clock signal may also act as a enable.

Edge Triggered S-R Flip-flop: In edge-triggered S-R flip-flop, the change of state in flip-flop takes

place only when edge (either +ve or -ve) of clock pulse takes place.

10. What is the difference between level and edge triggering? Explain the working of master slave

J-K flip flop.

Ans.

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Master slave JK flip-flop : The master slave flip-flop may be designed using R-S, D and JK flip-flops.

Following figure shows the functional block diagram of master slave JK flip- flop:

In figure m is used for Master and S is used for Slave

Working:

Case 1: When positive clock pulse goes on leading edge is applied, the CLKm is 1 and CLKs is 0, then

data transferred to Qm is held upto CLK = 1

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Case 2: When the clock pulse goes negative, trailing edge is applied, the CLKm = 0 and CLKs = 1, then

Qm and

will be transferred to Q =

and at that duration the inputs at J and K should not change

This is overcome by the use of data lockout.

Internal structures of master slave J-K flip-flop, Truth table is as shown in fig

11. Draw a master-slave J-K flip-flop system. Explain its operation and show that the race-around

condition is eliminated.

Ans.

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A master-slave J-K flip-flop is constructed from two flip-flops. One flip-flop acts as a master and the

other as a slave and the overall circuit is thus, called as master-slave flip-flop. It make use of J-K master

flip-flop and S-A slave flip-flop. The master is positive edge triggered and slave is negative edge

triggered. Therefore, master responds to J-K inputs before the slave. V

If J = 1 and K = 0, the master sets on the positive clock edge. The high output of the master drives the J

input of the slave, so when the negative clock edge arrives, the slave sets, copying the action of the

master.

If J = 0 and K = 1, the master resets on the positive clock edge. The high output of master i.e.

to R input of the slave. Therefore, slave resets on arrival of negative clock edge.

goes

If J = K = 1 for master, it toggles on positive clock edge and the slave them toggles on the negative clock

edge.

When J = K = 1

Let clock = 1 then master is active and slave is in active Therefore, output of master toggle. So S and R

also will be inverted

When clock 0 Master becomes in active and slave is active Therefore, output of the slave will toggle

These changed outputs are again returned back to the master inputs as feedback is connected in fig. But

here clock is 0, the master is still in active So it does not respond to these changed outputs. This voids

multiple toggling which is responsible for Race Around Condition Hence by using Master-Slave J K

Flip-flop RACE AROUND CONDITION will be avoided or eliminated.

12. Explain what is universal shift register? Explain its working.

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Ans. A universal shift register is one which can function in any of the SISO SIPO PISO or PIPO modes

of operation To operate the register universally it contains serial input serial output, parallel inputs,

parallel outputs and must be able to serially shift data to the right or to the left, hold the data or to reset

Thus, it has bidirectional property also It is a 74194 IC Its internal structure is as shown in figure.

13. Draw the logic symbols for T and RS flip-flops. Explain the function of each type of flip-flop.

Ans. RS Flip-flop: Its logic symbol is as shown in fig.

Its internal structure is as shown:

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Its functioning can be explained with the help of truth table as shown:

Case I. When both the inputs i.e. S = R = 0

The data inside the flip-flop do not change i.e. if 0 was the previous data we get 0 as output data and

if 1 was previously stored in flip-flop we get 1 as output data. Hence, no change state.

The flip-flop output is always 0 i.e. if the previously stored data was 0 or 1 we always get 0 output.

Hence, Reset condition or state.

Case III When the inputs are S = 1 and R = 0

The flip flop output is always 1 i e if the previously stored data was 0 to 1 we always get 1 output

Hence set state

Case IV When the inputs are S = 1 and R = 1

The flip-flop outputs Q and

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T-flip-flop:

T flip-flop is also known as Toggle flip-flop It is a modification of the JK flip-flop The T flip flop is

obtained from a JK flip flop by connecting both inputs, J and K together

When T = 0, both AND gates are disabled and hence these is no change in the output When T = 1 (i.e. J

= 1 and K = 1) output toggles i.e. with the passage of each clock the output changes from 0 to 1 and 1

to 0 i.e. it toggles

Its truth table is as shown in fig

14. Draw the circuit of an S-R flip-flop using NAND gates. Modify it to include clock Derive J-K

circuit from S-R flip-flop circuit and explain its truth table

Ans. S-R Flip-flop using NAND gates:

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When any one input of NAND gate is zero, its output is forced to be 1. Now path Q and Q will be

forced to become 1, which is not possible. Hence, Race condition or invalid state.

Case2: When S = 0,R = 1

When S = 0, it will force Q to be 1 and hence both inputs R and Q become 1 and cause Q to be 0. It is

called Reset condition. V

Case3: When S = 1, R = 0

When R = 0, it will force Q to be 1. Hence both inputs S and Q will be 1 and cause Q to be 0. It is

called set condition. V

Case4: When S = 1, R =1

In this case, there will be no change in outputs.

S-R Flip-flop including clock:

The truth table for S-R to J-K conversion is as shown:

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K-maps

Logic diagram:

15. Design a J-K counter that goes through states 2, 4, 5, 7, 2, 4 is the counter-self starting.

Ans.

K-maps

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Circuit

T flip-flop to D flip-flop.

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Ans. T flip-flop to D flip-flop:

Truth table for conversion:

K-map for T:

17. Twisted ring counter is also known as Johnson counter. It is an application of shift register.

Following figure shows the circuit diagram for its operation.

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Ans. Operation : Initially a short negative pulse is provided to clear all the which resets the data to 000

1, 0, 2, 3, 4, 8, 7, 6, 5

Ans. The excitation truth table for synchronous decade counter to count the sequence

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1, 0, 2, 3, 4, 8, 7, 6, 5 is as shown:

Put all others as dont care conditions i.e. 10, 11, 12, 13, 14 and 15 to be dont care.

K-map for TA:

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19.Write short note on the following: Counter design with state equation and state diagrams.

Ans. Counter designing make use of static diagrams and state equations.

State Diagram : The graphical representation of different states of a counter is known as state diagram.

Let us consider an example of 3 bit Ripple counter (up and down)

The numbers written inside the circles are the state numbers and the arrows shows the direction of

counter. In fig. (a) 0 is the initial state i.e. counter starts from 0 and count upto 7 then again 0 and so

on.

So it is up counter.

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Similarly, in fig. (b) initial state is 7so it starts from 7 and goes .to 0 then again 7and so on.

So it is a down counter.

State equation : A state equation is also known as application equation. It is an algebric expression that

specifies the conditions for a flip-flop state transition. The left side of the equation represents the next

state of the flip-flop and the right side gives a boolean function that specifies the present state conditions

that make the next state equal to 1. The state equation can be derived from the state table or logic

diagram.

20. What is race around condition in J-K flip flop? How it is eliminated?

Ans. Race-Around Condition : When J and K both inputs are high i.e. J = K = I, the output will keep

toggling indefinitely. This multiple toggling in J-K F/F is called Race-Around Condition. It can be

eliminated by using master slave J-K flip-flop.

1. Master slave J-K Flip-flop

Ans. 4 bit binary shift Register: This type of Shift Register allows shifting either to left or right side.

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Working

shows the bidirectional shift register When

Fig

signal is Low AND gates 2, 4 6, 8 are

enabled the data shifting is towards left Then the Q states of each flip-flop passes through the A and KA

input of each proceeding flip flop When clock pulse arrives the data shift one place to right or left

depending on

Ans.

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From 0 to 29 the states are valid states and 30 and 31 states are invalid states.

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Circuit diagram

Using T flip flop is as shown in figure

23. Design a BCD counter using JK flip-flops.

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Ans. The BCD decade counter counts from 0000 to 1001 as shown in diagram. The

invalid states 1010 to 1111 should given next states as 0000 which is done by reset logic connected to

clear input of all the flip-flops.

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K-map:

Ans. Up-down counter counts (0, 2, 3, 6, 4, 0,......).

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K-maps

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Circuit diagram

Ans.

K-maps

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Implementation of circuit:

1. How does the architecture of a PAL differ from a PROM?

The programmable array logic (PAL) is a programmable logic device with a fixed OR array

and a programmable AND array.

The Programmable Read Only Memory (PROM) is a programmable logic device with a

fixed AND array and a programmable OR array.

Architecture: PAL

input

Programmable

AND array

Fixed OR

Array

Fixed AND

array

Programmable

output

Architecture: PROM

input

OR Array

output

AND array and a programmable OR array.

PLA can be used to implement complex logic circuits.

It is more economical to use PLA rather than PROM to implement logic circuits that have

more number of dont care conditions in order to reduce number of gates.

PLA is flexible compared to PROM & PAL.

The time interval between clock pulses is called the bit time, and the time required to shift the entire contents

of a shift register is called the word time.

4. What is non- volatile memory?

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Memory units that retain its stored information after removal of power. Eg magnetic disk. This is because the

data stored on magnetic components is manifested by the direction of magnetization, which is retained after

power is turned off.

S.No

EPROM

EEPROM

1

Erasable Programmable Read Electrically Erasable Programmable Read

Only Memory

Only Memory

2

Placing the EPROM chip under Applying electrical signal erases the stored

a special ultraviolet erases the information.

stored information.

3

It can also be called as UV It can also be called as Electrically Alterable

EPROM

ROM (EAROM).

6. What does burning a ROM mean?

The process of entering data into the ROM by burning internal fuses is called programming or

burning a ROM.

7. What are the major drawbacks of the EEPROM?

COST: In EEPROM, the erasing and programming of an EEPROM can be done in circuit.

(Without using separate UV light source and special PROM programmer unit). Because of

this on-chip support circuitry the EEPROM is available with more cost.

DENSITY: The high level integration of the EEPROM occupies more space. For example, 1Mbit EEPROM requires about twice as much silicon as a 1-Mbit EPROM.

8. How many data inputs, data outputs and address inputs are needed for a 1024 4 ROM?

No. of data inputs and outputs = 4

1024 = 210

No of address inputs = 10

9. Describe the basic functions of ROM and RAM

ROM: Read only memory is used to store information permanently. The information can not be

altered.

RAM: Random Access Memory is used to store information. The information can be read form it

and the new information can be written into the memory.

10. How long will it take to erase UV erasable EPROM completely?

15 to 20 min.

11. What is an EAROM?

EAROM: Erasable Alterable Read Only Memory. The stored information is erased by applying

electrical signal.

12. Distinguish between PAL and PLA.

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Programmable Array Logic (PAL) is a programmable logic device with a fixed OR array

and a programmable AND array. Because only the AND gates are programmable, the PAL is

easier to program, is not flexible as the PLA. It uses array logic symbol.

Programmable Logic Array (PLA) is a programmable logic device with a Programmable

AND array and a programmable OR array. PLA can be used to implement complex logic

circuits. It uses conventional symbol. It is more flexible than PAL.

The programmable logic blocks in the Xilinx family of FPGAs are called configurable logic blocks

(CLBs). The CLB of Xilinx 3000 series can be configured to perform any logic function of up to a

maximum of seven variables. .

14. Give the different types of RAM.

RAM can be classified into two types:

1. Static RAM: The storage elements used in this type RAM are latches

( unclocked FFs).

2. Dynamic RAM: A dynamic RAM is one in which data are stored on capacitors which

require periodic recharging (refreshing) to retain the data.

RAMs are manufactured with either bipolar or MOS technologies. Bipolar RAMs are all static

RAM. MOS RAM are available in both static and dynamic types

15. What is dynamic RAM cell? Draw its basic structure.

A dynamic RAM is one in which data are stored on capacitors which require periodic

recharging (refreshing) to retain the data.

16. What is Memory refresh?

Dynamic RAMs are fabricated using MOS technology. They store 1s and 0s as charges on a small

MOS capacitor (typically a few picofarads). Because if the tendency for these charges to leak of after

a period of time, dynamics require periodic recharging of the memory cells This is called refreshing

the dynamic RAM or memory refresh.

17. Distinguish between Bipolar RAM cell and MOSFET RAM cell.

Bipolar RAM cell is a latch which is manufactured with bipolar technology (using BJT). They are all

static RAMs

MOSFET RAM cell a storage element which is manufactured with MOS technology

( MOSFET). Capacitors are provided by metal oxide semiconductor(MOS).

20. What is the difference between PAL and PLA?

Ans.

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Ans. PLDs: Programmable logic devices are the special type of ICs used by the USE and are

programmed before use Different type of logic functions can be implemented using a single

programmed IC chip of PLDs. PLD s can be reprogrammed because these are based on re-.writable

memory technologies Fuse links are used to programmed the PLD b the user according to the type of

PLD to be manufactured

22. Where do we use PLAs?

Ans. 1. Combinational circuits can be implemented using PLAs

2. Sequential circuits can be implemented using PLAs.

3. In sequential circuits implementation flip-flops and buffers are used at output stage with PLA devices

while in combinational circuits only buffers are used.

4. Compact circuits can be built using PLAs, which covers less space.

23. On what basis do we characterize various type of memories.

Ans. Memories can be characterize on various parameters.

1. Characterize based on Principal of operation.

2. Characterize based on Physical characteristics.

3. Characterize based on Mode of Access.

4. Characterize based on Fabrication Technology.

24. What are the characteristics of memories?

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Ans. Characteristics of memory:

1. Memory organization and capacity

2. Physical dimensions

3. Packing of memory

4. Power consumption

5. Cost etc.

PART-B

1. Explain the Bipolar RAM Cell.

Ans. Bipolar transistor is used in bipolar ROM cell. It is as shown in figure.

When base of transistor is not connected with a row no current flows to the base and it represents a

storage of logic 0. On the other hand, when base is connected the flowing to the base of transistor and

it represents a storage of logic 1.

Q 2. Design the OR Matrix or OR array.

Ans. These gives the logical sum terms of output from AND arrays as shown in fig.

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Here X are the fuse links used in diagrams. The interconnections without X are unplugged fuses or

blown off fuse links.

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3. Implement the boolean function using PAL.

Ans. Let the input variables are A, B and C. The K-map minimization is as shown:

Ans. Truth table of Half Adder circuit is:

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Carry = C = AB.

5. What is PAL?

Ans. PAL: PAL is known as programmable array logic. It is a programmed logic device with OR arrays

fixed and AND arrays programmable. Because only AND gates are programmable, the PAL is easier to

program, but it is not as flexible as the PLA (programmable logic array). For example : We have a

boolean function given by

Y (A, B, C,) =

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Ans PLA is Programmable Logic Array It is used where the number of dont care conditions are

excessive In PLAs both AND and OR arrays are programmable The ANI and OR gates are fixed for any

PLA chip It depends on the number of inputs and outputs of PLA. Let us take an example of Half Adder

to illustrate the diagram internal architecture of PLA: Truth Table of Half Adder:

Implementation of Half Adder using PLA is as shown:

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Ans.

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9. A certain memory stores 8 k x 16 bit words. How many data input lines, data output lines and

address lines does it have ? What is its capacity in bytes?

Ans. Memory is M x N form where M are memory locations and N are data input lines.

Here

M = 8K

N = 16

10. What are the various types of ROMs? Discuss their relative advantages and disadvantages.

Ans. ROM : In ROM, read and write operation cannot be periormed with equal ease always read

operation is easier than write operation. It is used to store information which is (I) Permanent group

includes ; masked ROM and PROM (ii) Semi permanent group include; EPROM and EE-PROM. Five

types of ROM-masked ROM, PROM, EPROM, EE-PROM and flash memory are described in the

following paragraphs.

Masked ROM : Programming is done through masking and metallization. process. Manufactures

provides programmed ROM, user cannot write into this memory.

PROM : Programmable Read Only Memory user can program (write) the PROM through special

PROM programmer. It can be written (programmed) once only, user cannot rewrite this memory.

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EPROM : Erasable Programmable ROM. This memory stores a bit by charging the floating gate of an

FET. The chip can be reused may times i.e., user can write this memory many time. Erasing is done

using UV light through a window over the memory chip called quartz window. Erasing process cannot

be done byte by byte or block by block, entire information will be erased at once,- after exposing the

ROM in U.V. light. Therefore, erasing process is slower and time consuming it takes 15 to 20 minutes.

EEPROM : Electrically Erasable PROM. This memory is functionally similar to EPROM, except that

information can be altered by using electrical signals at the register level rather than erasing the

information i.e., it can be erased information byte to byte.

Advantages and Disadvantages:

Advantages:

1. Low cost

2. High speed

3. Flexibility in system design

4. ROM is non-volatile memory

Disadvantages:

1. In EPROM selective erasing is not possible. One time all the locations are erased.

2. IROM has to be removed from socket and put in eraser for erasing.

11. State and explain the difference among ROM, PROM, RAM, SRAM and DRAM.

Ans. ROM : Read only memory (ROM) is the type of memory from which data can be repeatedly read

out. We cant write data in this memory. It is a non-volatile memory i.e. it can hold data even if power is

turned off.

PROM: Programmable ROM is a ROM into which data is permanently stored by special programming

device. A PROM can be programmed once after its fabrication. However another category of PROM is

reprogrammable i.e. it can be programmed again and again and is referred erasable and programmable.

If the erasing of PROM is using ultraviolet then it is EPROM i.e. Erasable programmable ROM.

If the erasing of ROM in using electrical voltage then it is known as electrically alterable ROM i.e.

EAROM.

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RAM : Random Access Memory (RAM) is the memory that can be used for read as well as written

operation. Here access time is same for each location. RAM is a volatile memory so it loses the stored

data when power is turned off. RAM is of two types SRAM and DRAM.

SRAM: Static RAM uses the flip-flop for its basic storage element. It is possible to store data as long as

power is applied to the chip. It make use of cross coupled TTL multiemitter bipolar transistors or cross

coupled MOSFETs for its construction.

DRAM : Dynamic RAM make use of capacitive element for storing the data bit. Binary information is

stored as charge. If charge is present at a capacitive element it represents a logic 1 and in the absence of

the charge a logic 0 is stored. DRAMs consumes less power as compared to SRAMs.

12. Write short note on Classification and characteristics of memories.

Ans. Classification and characteristics of memories Various memory devices can

be classified on the basis of:

1. Principle of operation

2. Physical characteristics

1. Principle of operation : The most commonly used memories are

(a) Sequentially accessed memory.

(b) Random access memory (RAM)

(c) Read only memory (ROM)

(d) Content addressable memory (CAM)

(a) Sequentially accessed memories: In these type of memories the time required to access memory

location is different for different locations. These are of basic two types:

(i) Shift registers

(ii) Charge coupled devices (CCDs).

(b) RAM : Random access memory is the memory which is used for both read and write operation i.e.

data can be read or placed into. Here access time is same for each location. It is of two types:

(i) SRAM i.e. Static RAM

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(ii) DRAM i.e. Dynamic RAM

(c) ROM : Read only memory is the type from which data can be repeatedly read out but cannot be

written into it. It is of two types

(i) Mask programmable ROM

(ii) Programmable ROM.

In case of Mark Programmable ROM it is programmable at the time of manufacturing according to the

information specified by the customer, and cannot be changed after packing.

In case of programmable ROM, data is permanently stored but can be erased either by

ultraviolet light or electrically using electric voltage.

(d) CAM : Content address memory is a special purpose RAM which performs association operation in

addition Read/Write operation.

2. Physical Characteristics : These are of two types :,

(a) Erasable or non-erasable

(b) Volatile or non-volatile

(a) Erasable or non-erasable is a memory in. which the data stored can be erased or non-erased. For

example : ROM is a non-erasable memory

RAM is erasable memory.

(b) Volatile or non-volatile: If the data stored in memory is lost where power is switched off then it is

volatile memory. For example : RAM.

But if the data stored is not lost when power is switched off when it is called non-volatile.

For example : ROM.

13. Draw the circuit of a static MOS RAM cell and explain its operation of Read and Write.

Ans. Random .Access Memory (RAM) is a volatile memory. It can be read as well as written It has two

types static RAM and Dynamic RAM The static RAM can be implemented using bipolar and MOS

technology. The circuit diagram of static MOS RAM is as:

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In this circuit T1 and T3 are loads T2 and T4 are resistances. T9 is used for write operation and T10 for

read operation. X and Y lines are used for addressing the cell. When X = 1 T5 and T6 will be ON when

Y = 1, T7 and T6 will be ON.

(i) Write operation: To make write operation, T9 is turned ON If the data is logic 1, then T3 is turned

ON If data is logic 0 then T1 is ON

(ii) Read operation: For read operation MOSFET (T10) is turned ON This will connect Data-line to

Data-out Hence complement of stored data is read.

14. Explain the architecture and function of programmable logic arrays

Ans. Programmable logic devices (PLD) are special type of ICs which can be programmed by the user

and hence a combinational or sequential circuit can be implemented with these PLO s are of various

types as programmable array logic (PAL) and programmable logic array (PLA) etc The block diagram of

PLA device is as shown:

Input Buffers : These buffers amplify the input signal. These are also used to avoid the loading of

sources connected at the input

AND Matrix: It can be used to implement the product terms in the SOP form Each AND has two matrix

has connections are shown by (X) mark on the line.

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OR Matrix: The OR matrix has OR gates of two inputs The connections are shown by cross (X) mark,

on the line.

lnvert/Non-lnvert: Matrix If the output in active low mode is required then it can be separated with this

matrix otherwise it remain active high with non-invert matrix

Output Buffers: To amplify the output signal and to increase current source capability these buffers are

used.

1. What is asynchronous sequential circuit?

Asynchronous sequential circuit is a system which depends upon the order in which its

input signals change and can be affected at any instant of time. The memory elements

used are time delay devices.

2. What is the difference between synchronous and asynchronous sequential circuits?

S.No

Synchronous sequential circuits

Asynchronous sequential circuits

1

The change of internal state occurs in The change in internal state occurs

response to a clock pulse.

whenever there is a change in input

variable.

2

Memory elements are clocked flip- Memory elements are unclocked flipflops

flops or Time delay units.

3

The present state is totally specified There is no clock pulse. Because of

by FF values and does not change if absence of clock, asynchronous circuits

input changes while clock pulse is are faster than synchronous circuits.

inactive

4

Design is easy.

Design is more difficult because of the

timing problems involved in the

feedback path.

3. Mention the applications of Asynchronous circuits.

Asynchronous circuits are used when speed of operation is important, especially in those

cases where the digital system must respond quickly without having to wait for a clock pulse.

They are more economical to use in small independent systems that require only a few

components

Asynchronous circuits are useful in applications where the i/p signal may change at any time,

independently of an internal clock.

Asynchronous circuits are helpful in verifying that the total digital system is operating in the

proper manner.

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Pulse Mode Circuits

4. Explain the fundamental mode of operation.

Asynchronous sequential circuits must be allowed to attain a stable state before the i/p is

changed to a new value. Because of delays in the wires & the gate circuits, it is impossible to

have two or more i/p variables change at exactly the same instant of time without an uncertainty

as to which one changes first. Therefore, simultaneous changes of two or more variables are

usually prohibited. This restriction means that only one i/p variable can change at any one time &

the time between two i/p changes must be longer than the time it takes the circuit to reach a

stable state. This type of operation is defined as fundamental mode.

5. Distinguish between fundamental mode circuits and pulse-mode circuits.

Fundamental Mode Circuit

The input variables change only when the circuit is stable

Only one input variable can change at a given time

Inputs are levels and not pulses.

The input variables are pulses instead of levels.

The width of the pulses is long enough for the circuit to respond to the input.

The pulse width must not be so long that it is still present after the new state is reached

and cause a faulty change of state.

No two pulses should arrive at the input lines simultaneously.

6. Why is the pulse mode operation of asynchronous sequential circuits not very popular?

Because of the input variable pulse width restrictions, pulse mode circuits are difficult to

design. For this reason the pulse mode operation of asynchronous sequential circuits is not very

popular.

7. What are Latches.

Un clocked memory elements are called latches.

8. Define Flow table.

During the design of asynchronous sequential circuits, it is more convenient to name the

states by letter symbols without making specific reference to their binary values, such a table is

called a Flow table.

9. What do you understand by Race condition?

A race condition is said to exist in an asynchronous sequential circuit when two or more

binary state variables change value in response to a change in an i/p variable. When unequal

delays are encountered, a race condition may cause the state variables to change in an un

predictable manner.

10. Explain non- critical race.

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The order by which the state variables change may not be known in advance. If the final

stable state that the circuit reaches does not depend on the order in which the state variable

change, the race is called a non-critical race.

11. Explain critical race.

If it is possible to end up in two or more different stable states, depending on the order in

which the state variable change, then it is called a critical race.

12. Define the term Maximal compatible.

The maximal compatible is a group of compatibles that contains all the possible

combinations of compatible states. The maximal compatible can be obtained from a merger

diagram.

13. Define closed covering.

The condition that must be satisfied for row merging is that the set of chosen compatibles

must cover all the states that must be closed. The set will cover all the states if it includes all the

states of the original state table. The closure condition is satisfied if there are no implied states or

if the implied states are included within the set. A closed set of compatibles that covers all the

states is called a closed covering.

14. Explain Shared Row method.

The method of making race free assignment by adding extra rows in the flow table is

sometimes referred to as Shared Row method.

15. Define Merger diagram.

The merger diagram is a graph in which each state is represented by a dot placed along

the circumference of a circle. Lines are drawn between any two corresponding dots that form a

compatible pair. All possible compatibles can be obtained from the merger diagram by observing

the geometrical patterns in which states are connected to each other.

16. Explain Multiple row method.

In the multiple row assignment each state in the original flow table is replaced by two or

more combinations of state variables. The state assignment map shows the multiple row

assignment that can be used with any four-row flow table.

y2y1

y3

a0

00

01

11

10

1 b1

c1

d1

c2

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17. What do you meant by the term Hazard.

Hazards are unwanted switching transients that may appear at the output of a circuit

because different paths exhibit different propagation delays. Hazards occur in combinational

circuits, where they may cause a temporary false output value. When this condition occurs in

asynchronous sequential circuits, it may result in a transition to a wrong stable state. Steps must

be taken to eliminate this effect.

18. Differentiae Static & Dynamic Hazard.

Static 1-hazard: The output may momentarily go to 0 when it should remain 1.

Static 0-hazard: The output may momentarily go to 1 when it should remain 0.

Dynamic hazard causes the output to change three or more times when it should change from

1 to 0 or from 0 to 1.

19. Explain Hazards in sequential circuits.

In normal combinational circuit design associated with synchronous sequential circuits,

hazards are not of concern. Since momentary erroneous signals are not of generally troublesome.

If a momentary incorrect signal is fed back in asynchronous sequential circuits, it may cause the

circuit to go to the wrong stable state. The malfunction can be eliminated by adding an extra

gate. To avoid static hazards, the asynchronous sequential circuits can be implemented with S R

latches.

20. Define Essential Hazard.

An essential Hazard is caused by unequal delays along two or more paths that originate from

the same input.

An excessive delay through an inverter circuit in comparison to the delay associated with the

feed back path may cause such a hazard.

Essential hazards cannot be corrected by adding redundant gates as in static hazards.

To avoid essential hazard, each feed back loop must be handled with individual care to

ensure that the delay in the feedback path is long enough compared to delays of other signals

that originate from the input terminals.

21. Explain the use of SR latches in asynchronous sequential circuits.

The use of SR latches in asynchronous circuits produce a more orderly pattern, which may

result in a reduction of the circuit complexity.

An added advantage is that the circuit resembles the synchronous circuit in having distinct

memory elements that store & specify the internal states.

One of the ways to avoid static hazards in asynchronous sequential circuits is to implement

the circuit with SR latches.

22. Define Primitive Flow table.

A primitive flow table is a flow table with only one stable total state in each row.

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23. What do you understand by the term merging?

The primitive flow table has only one stable state in each row. The table can be reduced

to a smaller number of rows if two or more stable states are placed in the same row of the flow

table. The grouping of stable states from separate rows in to one common row is called merging.

24. What is finite state Machine?

A finite state machine (or finite automation) is an abstract model describing the

synchronous sequential machine and its spatial counter, part, the iterative network.

25. Define critical race in asynchronous sequential circuits.

Critical race in asynchronous circuits occur between two signals that are required to

change at the same time when the next stable state is dependent on the delay paths in the circuit.

Data is often entered into a digital system by means of switches. A common characteristic

of all these switches are they have a tendency to bounce when actuated, causing a short

series of repetitive make and break connections lasting for several milli seconds. A latch

circuit can be used as a debounce and the technique adopted is called debouncing.

27. What is State Assignment?

Assigning binary values to each state that is represented by letter symbol in the flow table of

sequential circuit is called state assignment.

The primary objective in choosing a proper binary state assignment in asynchronous circuit is

the prevention of critical races

28. List any two drawbacks of asynchronous circuits.

Race condition

Hazards

29. Draw the state diagram for a four-state machine with one diagonal transition

00/ 0

00/ 0

01/ 0

10/ 0

10/ 0

11/ 1

01/ 0

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a. To reduce the number of flip-flops

b. To reduce the number of gates in the combinational circuit that drives the flip-flop inputs.

31. What is the use of flip-flop excitation table?

If the transition from present state to next state is known in the design of sequential

circuit, the flip-flop excitation table is used to find the flip-flop input conditions that will cause

the required transition.

Dynamic hazard is unwanted switching transition that causes the output to change three

or more times when it should change from 1 to 0 or from 0 to 1.

33. What is state machine?

A state machine is another term for a sequential circuit, which is the basic structure of a

digital system.

34. What is the reason for essential hazard to occur?

Unequal delays along two or more paths that originate from the same input in the asynchronous

sequential circuit is the reason for essential hazard to occur.

35. Define compatible states.

Two states are compatible (equivalent) if in every column of the corresponding rows in

the flow table, there are identical or equivalent next states and if there is no conflict in the output

values.

36. When is a sequential machine said to be strongly connected?

A sequential machine is said to be strongly connected when it goes through all possible

synchronization states. Example: Natural counter.

37. What is One-Hot assignment?

One hot state assignment is made so that only one variable is active or hot for each row

in the original flow table. This technique requires as many state variables, as there are rows in a

flow table. Additional rows are introduced to provide single variable changes between internal

state transitions.

38. What is the difference between an internal state and a total state?

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Internal state: The combination of secondary variables gives the internal state of the

asynchronous circuit.

Total state: The combination of secondary variables (present state) and the external input

variables gives the total state by which the operation of the asynchronous circuit is described.

39. Explain the difference between the stable state and the unstable state.

Stable state: If the next state is equal to the present state for the given input combination, the

state is called stable state.

Unstable state: If the next state is not equal to the present state for the given input combination,

the state is called unstable state.

40. Define cycle.

A cycle occurs when an asynchronous machine makes a transition through a series of

unstable states.

Care must be taken to make sure whether the cycle terminated with a stable state or not.

If a cycle does not terminate with a stable state, the circuit will keep going from one unstable

state to another, making the entire circuit unstable.

41. What is ASM chart?

Algorithmic State Machine (ASM) chart is a special type of flow chart suitable for describing

the sequential operations in a digital system.

A state machine is another term for a sequential circuit, which is the basic structure of a

digital system.

The ASM chart is composed of three basic elements: the state box, the decision box and the

conditional box.

PART-B

Xi

Inputs

Zk

Outputs

Combinational

Logic for

Outputs and

Next State

State Register

Clock

State

Feedback

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(N D + Reset)/0

Reset/0

N D + Reset

Reset

0

Reset/0

0

[0]

Reset

N/0

5

N D/0

5

D/0

ND

[0]

N/0

10

10

D

D/1

[0]

N D/0

N+D/1

ND

N+D

15

15

[1]

Reset/1

Reset

Mealy Machine

Moore Machine

Outputs depend on

state AND inputs

solely of the current

state

an immediate output

change

Outputs change

synchronously with

state changes

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State

Register

Xi

Inputs

Comb.

Logic for

Outputs

Combinational

Logic for

Next State

(Flip-flop

Inputs)

Zk

Outputs

Clock

state

feedback

0

0/0

0

[0]

0

1/0

0/0

1

0

1

1/1

[0]

1

2

[1]

for same output sequence

Six Step Process

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2. Obtain an abstract specification of the FSM

3. Perform a state minimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6.Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;

4, 5 generalized from the counter design procedure

2.Design example of synchronous sequential circuit.

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A Static Hazard is defined when a single variable change at the input causes a momentary

change in another variable [the output].A Dynamic Hazard occurs when a change in the input causes

multiple changes in the output [i.e. from 1 to 0 and back to 1]. In either case of a Static or Dynamic

hazard the product produced is an unanticipated glitch [the hazard]. The resulting glitches in the circuit

may or may not induce additional problems ~ other then increased issues due to switching

noise.However; a problem may occur if the signal with the glitch is a clock line. A glitch on the clock

line to a flip flop will cause device to clock in data when it wasn't meant to.A glitch on a clock line of a

counter will also have a negative effect.In any case,good design practice means designing out these

hazards.There are two types of Static hazards: the high output transitions to a low and back high [a low

going glitch]. Or the low output transitions to a high [1] and back low [0] [a high going glitch]. There

are also two types of Dynamic hazards: the 0 output transitions to a 1 back to 0 and then 1 again. Or the

1 output transitions to a 0 back to 1 and then 0 again.

If Static Hazards are removed from the design, Dynamic Hazards will not occur. A Karnaugh

map [K-map] is the easiest way to eliminate a Static Hazard or glitch. These timing hazards will

develop as random or intermittent circuit failures. The type of circuit failure will depend on the signals

used in the AND / OR gate circuit, and perhaps how often they change state. Another method to

eliminate timing hazards from effecting an IC down the line is to re-clock the final output signals. Reclocking the signal does not eliminate the glitch, but stops it from causing circuit failure. Re-clocking

the signal seems to be common for designers unsure of why the glitch occurs, or how to stop the glitch

from developing. Solving the problem via a K-map results in an additional AND gate, re-clocking

requires an additional flip flop.

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A K-map for each combinatorial logic function which has an output should be used. Redundant

prime implicants should be added to the K-Map (circuit) [shown in RED above], which will guarantee

that all single-bit input changes are covered. Multi-level functions will be reduced to "two-level"

functions, and analyzed by the K-map approach. The procedure for designing a static-hazard-free

network is a straightforward application. The key is to place the function in such a form that the transient

output function guarantees that every set of adjacent 1's in the K-map are covered by a term, and that no

terms contain both a variable and its complement. The former condition eliminates 1-hazards and the

latter eliminates 0-hazards. Dynamic hazards happen because of multiple paths in a multilevel network,

each with its own asymmetric delay.Circuits which contain multiple paths of the same signal should be

re-clocked

before

the

signal

is

used

by

a

circuit.

Static 0 hazards occur in 'Product-Of-Sums' [POS] implementations, but do not occur in 'Sum-OfProducts' [SOP] implementations. Static 1 hazards occur in SOP implementations, do not occur in POS

implementations.

Y= AB + B'C e.g. {ABC} = {111} {101}

Y= AB+B'C

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A

S

B

A

B

BUF

F

YS

DA

B

AND

2

AND 2

A

Y

X1

A

B

OR

2

Y

X2

AB

00

01

11

10

S=0

S=1

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Only two 2-input AND gates are needed for the product terms

AB

00

01

11

10

S=0

S=1

The blue oval shows the redundant term used to cover the

transition between product terms.

(A+B)(B+C) e.g. {ABCD} = {0001} {0101}

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5.Design procedure for Hazard free network.

Designing Hazard Free Circuits

1. static hazards in combinational circuits can be removed by covering any two

minterms that may produce a hazard with a product term to cover both minterms

(hazard cover)

2. for dynamic hazards in multilevel circuits, use a different form of the equation

3. use sum of all prime implicants

4. use a synchronous system >> clock inputs >> clock reading of outputs

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