.t.

Chapter16

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THE G EN ER A LI N S T R U M E N TC P l 6 0 0
The CP1600 and the TMS 9900 were the first two NMOS 16-bit microprocassors
commericiallyavailable.Even
a superficialinspectionof the CP1600showsit to be morepowerfulthan the NationalSemiconductor
Pace(or8900),
yet the CP1600 is not widely used.This is becauseGenerallnstrumentdoesnot supportthe CP1600to the extent
that NationalSemiconductor
supports.Pace,
or most manufacturers
supporttheir 8-bit microprocessors.
GeneralInstrument'smarketing philosophyhas been to seek out very high-volumecustomers;GeneralInstrument supportslow-volumecustomersonly to the extentthat this supportwould not requiresubstantialinvestmenton
the part of GeneralInstrument.
Fromthe viewpointof the low-volumemicroprocessor
user.GeneralInstrument's
marketingphilosophyis unfortunate.
The CP1600is an idealmicroprocessor
for the moresophisticated
videogamesthat areappearing,
and its rich instruction set and capablearchitecture
makeit an idealchoicefor data.processing
terminalsand home computersystems.
However,due to its limitedsupport,potentiallow-volume
CP1600customers
are likelyto chooseanotherequallycapable oroduct.
Three CPl600 parts are avaitable,differentiatedonly by the ctock speedsforwhich they irave been designed.
The CP1600requiresa 3.3 MHz.two-phaseclockand generatesa 600 nanosecond
machinecycle time.
The CP1600requiresa 4 MHz.two-phaseclockand generates
a 500 nanosecond
machinecycle time.
The CP'l6'l0 requiresa 2 MHz.two-phaseclockand generatesa 1 microsecond
cycletirr,e.
ln addition to the CPl600 microprocessorsthemselves, the CPl68O Input/Output Buffer (lOB) is described in
this chapter. Additional support devices for the CPl600 may be found in Volume 3.
The solesourcefor the CP1600is:
INSTRUMENT
GENERAL
M icroelectronics
Division
600 West John Street
Hicksville,
New York 11802
There is no secondsource for the CPl600. GeneralInstrumenthas a policyof discouraging
seconds ourcesfor its
productline.
The CP1600is fabricatedusing NMOSion implantLSI technology:the deviceis packagedas a 40-pin DlP.
Threepowersuppl iesare required'.
+12V, *5V and -3V.

T HE C P1 6 0 0M IC R O C O MP U TESRY S T E MO V E RV I E W
Logic of our general microcomputer system which has been implemented by the cP1600 cPU is illustratsd in
Figure 16-1.
obs.ervethatthecP16oorequiresexternal|ogictocreateitsvarioustimingandc|ocksigna|s.
Some bus interfacetogic is shown as absent becausaa numberof devicesmust surroundthe CPl600; theserntl
'c luoe:
a
1) An addressbuffer.sincedata and addresses
are multiplexedon a single16-bitbus.
2l Bufferamplifiersto providethe powerrequiredby the type of memoryand l/O devicesrnat will normallybe connectedto a CP1600CPU.
3) A one-of-eight
decoderchip to createeight rndividualcontrolsignalsout of threecontrolsoutput by the CP1600.
4J A one-of-sixteen
multiplexchip to funnel sixteenexternalstatus signalsinto the CP1600 if using external
b ranches.

ro- |

were you to compareFigure16-1w'rthan equivalentfigure

for a low-endmicroprocessor
such as the SC/Mp t which is
describedin cnapter3), ttrecP'1600might appearto offerfewer
logicfunctjons;but within the functionsrt
does pr ovide. the CF1600 proviCesconsiderablymore logic
and prcgram execution capabilities Where
low- end
microprocessors
chooseto co^denseontoa singlechipl simpieimplementations
of differentlogicfunctions.hig h- end
productssuch as the cP16c0 chooseto providemore
devices- with greatercapabilities
on each device

Clock Logic

[]

fl

Arithmetic and
lnair
svvre

cP1600cPU
cP1680t / O

I l^i+
v"r r

InterruptPriority
Arbitration

S e r i a l to Pa r a lle l
I n t e r f a ce L o g ic

ROM Addressing
and :
InterfaceLogic

l,/O Ports
Interface Logic

Frgure16- 1 Logicof the Cp1600 CpU and CP1680llo

Buffer
lr
o

to-z

RAM Addressing
and
Interface Logic

REGISTERS
CPl 600 PROGRAMMABLE
The CPl600 has eight 16-bit programmableregisters, which may be illustrated as follows:

JJ

a
=
c
)
=
'i

RO
R ')
RZ )
R 3,
Rl
I
R5 t
RO
R7

Dcta Countcrs
Oau Countc6 whh
suto-incramcnt

Cacral h.rrpora irgistcrs

Stack Pointcr
Program Countcr

UJ

o
o
u,
d
ul

z
o

The way in'which the registersillustratedaboveare used is unusualwhen comparedto other microcomputers
describedin this book. All eight 16-bit registerscan be addressedas though they were generalpurposeregisters;
however,only RegisterR0 has no otherassigned
function.We may thereforelookupon RegisterR0 as the PrimaryAccumulatorfor this CPU.
Registers
R1,R2,and R3 serveas generalpurposeregisters,
but may also be usedas Data Counters.

o
E
o

In additionto servingas generalpurposeregisters,

R4 and Rb may be used as auto-incrementing
Data Counters.
Memoryreferenceinstructionsthat identifyRegisterR4 or R5 as holdingthe impliedmemoryaddresswill causethe
contentsof RegisterR4 or R5 to be incremented
- afterthe memoryreferenceinstructions
havecompletedexecution.

Registers
R6 and R7, in additionto beingaccessible
as generalpurposeregisters,
alsoserveas a StackPointerand a
ProgramCounter,respectively.
Havingthe StackPointeraccessibleas a generalpurposeregistermakesit quite simpleto maintainmore than one
Stackin externalmemory;also,you can easilyaddressthe Stackas data memoryusingthe StackPointeras a Data
Counter.
Havingthe ProgramCounteraccessible
as a generalpurposeregistercan be usefulwhen executingvarioustypesof
conditionalbranchlogic.
While havingthe StackPointerand the ProgramCounteraccessible
as though they were generalpurposeregisters
may appearstrange.this is a featureof the PDP-I1 minicomputer
- and is a very powerfulprogrammingtool.

C P1 6 0 0M EMO R YA D D R E S S IN G
M O DE
The CPl60O addressesmmory and l/O devices within a single addressspace.
Whan referencingexternal memory, you can use direct addressing,implied addressing,or implied addressing
with auto-incremsnt.
Direct addressinginstructions are all two or more words long, where the second or last
word of the instruction object code provides a 16-bit direct address.

CP1600 DIRECT
ADDRESSING

CP1600direct addressinginstructionsare complicatedby the fact that CP1600program

memoryis frequentlyonly '10bits wide.That is to say,eventhoughthe CP1600is a 16-bitmicroprocessor,
its instruction objectcodesare only 10 bits wide.lf programmemoryis only 10 bitswide. then directaddresses
will only be 10
bits wide. A 10-bitdirect addresswill accessthe first'1024wordsof memoryonly.

16-3

Were -u,:u
to impl ementa 16-bitwide programmemory,then you coulddirectlyaddressup to 65,536wordsof memory: hcv'rever,
six bits of the first oblectprogramword for everyinstructionin programmemorywould be wasted.This
mav be illustrated
as follows:
Program
Memory
O

Bit Number

{--

Three memory
reference
instructions
that specify
direct addressi

Six unused
birs in each
of these
memory locations
Two single
word instructions

Instructions that reference memory using implied addressing identify general purpose
RegisterRl, R2. or R3 as containingthe implied address.
A memory referenceinstructionwhich identifiesRegisterR4 or R5 as providingthe external
memoryaddresswill alwayscauseRegisterR4 or R5 contentsto be incremented
followingthe
memoryaccess;thus you have impliedmemoryaddressingwith auto-increment.

c P1 6 0 0
IMPLIED
ADDRESSING

Memory referenceinstructionsthat specify impliedmemory addressingvia Register1,2,3,4, or 5 can access

8-bit memory.An SDBDinstructionexecuteddirectlybeforea valid memoryreference
instructionforcesthe memory
referenceinstructionto accessmemoryone byte at a time. lf impliedmemoryaddressingvia Register1, 2. or 3 is
specified.then the samebyte of memorywill be accessedtwice. For an instructionthat loadsthe contentsof data
memoryinto RegisterRO.this may be illustratedas follows:
Memory

SDBD
Programmemory

MV I R I,R O

PP

oo

16-4

Data memory

lf RegisterR4 or R5 providesthe impliedmemoryaddressfor the instructionwhich followsan SDBDinstruction.then

twice,and two sequentiallow-orderbytesof dataare accessed.
Foran inthe impliedmemoryaddressis incremented
structionwhich loadsdata into RegisterR0,this may be illustratedas follows:
Memory
l,l

SDBD

=
,'-

MVI R5,RO

Program memory

J
2

:
h
f,l

3
,h

PP

oo

Data memory

z
3

The SDBDinstructionmay alsoprecedean immediateinstruction.Now the i mmedi ate data w i l l be fetchedfrom the
low-orderbyte of the next two sequentialprogrammemorylocations.
This mav be i l l ustrated as follows:
Memory

RO

XX

Without the precedingSDBDinstruction.

an immediateinstructionwill accessthe next singleprogrammemoryword
to find the requiredimmediatedata.Ten or morebits of immediatedata will be accessed.
dependingon the width of
programmemoryworos
The GPl6O0 has no Stack raference instructions such as a Push or Pull; rather, a variety of
cP1600
momory reference instructions can identify Register R6 as providing the implied address. STACK
When RegisterRO providesthe impliedaddress.it is treatedas an upward migratingStack A D D R E S S I N G t
Poiriter.When a memorywrite operationspecifiesRegrsterR6 as providingthe impliedmemory
address.RegisterR6 contentswill be incrementedfollowing the memory write. A memory read instructionthat
specifiesRegisterR6 as providingthe impliedmemoryaddresswill causethe contentsof RegisterR6 to be decrementedbeforethe readooerationoccurs.
An unusual feature of the CPl600 is the fact that a variety of secondarymemory referenceinstructions can also
reference memory via the Stack Pointer.When these instructionsare executed.RegisterR6 contentsare decrementedbeforethe memoryaccessoccurs- as though a Pull operationfrom the Stackwere beingexecuted.
Logically,RegisterR6.the StackPointer,is beinghandledas though it were a DataCounterwith post-increment
and
pre-decrement.

I o-5

Ju r : r inS t rl(
r , ' t t On S
U Sed i re C t m e m O ry a d d re S S i ng.Jump i nS truC ttOnS
are all three words long.The direct addressis
o r nDut ec if r om t h e s e c o n d a n d th i rd me mo ry w ords as fol l ow s'

FI

JR or JSR
Word 2

tt

Word 3

AAAAAABEEBBBBBBBJump address(binary)
yy are enable/disable
bits for interrupts
xx ioentify the register where the return address wilr be stored for JSR
xx and yy are describedin detdil in Table 16-4.

You can enableor disableinterruptswheneveryou executea Jump

or Jump-to-subroutine
instruction.
The only difference
betweena Jump instructionand a Jump-to-Subroutine
instructionis that the Jum p-to-Subroutine
instruction
savesthe Programcountercontentsin Register
4,5. or 6. The two high-oiderbits (xx)or the secondJumpto-Subroutine
objectcode word specifieswhich of tne threeregisterswill be used to hold the return
address.
Jump-to-Subroutine
instructions.
like the Jump instruction,
allowdirect memoryaddressing
only.

CP 16 0 0 S T AT U S A N D C ON T R OLFLAGS
The cPl600 cPU has four of the standardstatus ftags; in addition, it
has some unusualcontrol signals.
These are the four standard status flags:
sign fs) Thisstatusis set equal to the high-orderbit of any arithmetic
operationresult.
zero rzl rhis statusis set to 'l when any instruction's
executioncreatesa zeroresult. Thestatusis set to 0 for a nonzero
result
The Carry(C)and Overflow(O)statusesare standardcarryand overflow,
as describedin Volume1.
Fourcontrolsignals(EBcAo - EVcA3l are output duringa Eranch-on-Externat
(BExn instruction.Thesefour signalsare outputto reflect the low-orderfour bits of the BEXTinstruction's
objectcode.Externallogicreceives
thesefour
signalsand (depending
on their state).may or may not returna high input via EBCI.lf EBcl is reiurnedhigh.
then the
BEXTinstruction
will performa branch;if EBCIis returnedlow,thenthe BEXTinstructionwill
causethe nextsequential
instruction
to be executed.
The four controlsignalsEBcAo- EBCA3thereforeprovidethe cp1600 with
a meansof testing 16 externalconditions.

CP 1 6 0 0 C PU P IN S A N D S IGN A L S

.f

CP1600 CPU pins and signalsare iltustratedin Figure16-2.

D0 - D15 is a mul tiplexedAddressand Data Bus.Givena totalof40 pins
in a package,cp1600 designers
havebeen
forcedto share16 pinsbetweenaddresses
and data.Threecontrotsignals,BDIR,BC1, and BC2, identifythe traffic
on the Address/DataBus. External logic (one MSI chipl must decode these
three signals to create eight controt
signals,as summarizedin Table 16-1.
Remainingsignals may be divided into four groups: timing, status/control,
interrupt, and DMA.
Two timing clock signalsare required:@1 and @2.Thesearecomplementary
clocksignalswhich may be illustrated
as follows:
o1

Q2a=.-

r 6-6

r40
239
338
137
536
635
734
833
932
r0
cPt6m
11
CPU
12
13
14
15
16
17
18
ts
?o

EECl
MSYNC
8C1

rcz
80lR
nr(
:J

o14
o l3
D1 2

:-

ur

=
i

D9

o8
oo

5
)

D7
06
o5
D4
D3

a
J
JJ

z
3

e
3

rclT
GNO
ol

o2
vDD
vBB

vcc
BDRDY

ffi
31

BUSRO

30
29
zg
27
26
zs
24
23
22
21

HALT
BUSAK
INTR

]ffi
TCI
EECAO
E8CA1
EBCA2
EBCA3
D2

Pin ?{ame

Oscriotion

Tvpc

DO- Dr5
BO|R,rcr, BC2
ol. (D2
MSYNC
EBCAO
- EBCA3

Data and Addrass Bus

Bus control signsls
Oock signals
M!st6r Synchronrzltbn

TnstEt., Elidirecrionrl

Exrernrl brsnch cdndnbn sddrass lirE3

E.rr6msl bronch co.rditbn input
Program Countr inhitit/softwao
imemrol spnal
WA]T
CRJ stop or stan on high-to-bw rrrnsition
HEh ststs signll
lntorrupt roqucst linas
Tcrminate currcnt intcrrufri
&:s roguest
Enemal bus cofltrol rcknourtdgo
Power rnd Ground

Output
lnput
lnput

E_!g!
rcrT
BDRDY
STPST
HALT

ivfi.ffi
tu

ffio
BUSAK
vB& vCC. VDO, GND

Output
lnput
Inp{Jl

Input
Inpur
OutPut
lnput
Output
Input
Output

Figure16-2. CP1600CPUSignalsand Pin Assignments

MSYNC is a somewhat unusualsignal,as comparedto other microcomputerclock signalsin this book. Following
powerup,Mffi
must be held low for at least10 milliseconds.
risingedgeof WTie. logic interOn the subsequent
nal to the CP1600CPUwill synchronize
the O1 and O2 clocksignalsto starta new machinecycle.Most of the CPU
deviceswe have describedin this book use a resetsignal.or have internalpoweruplogicwhich perfofmsthis clock
synchron
ization.
Now consider the status and control signals.
Firstof all. there are the four control outputs which we havealreadydescribed:EBCAO- EBCA3.There is one conditional Branch instruction (BEXT) which will only branch if a high signal is input via EBCI.When the BEXTinstructionis executed.the low-orderfour BEXTinstructionobjectcode bits are output via EBCA0- EBCA3.External ''
logii is supposedto decodethesefour signalsby whatevermeansaie appropriate
-and thencedeterminewhether
EBCIshouldbe input highor low. A high input,as we havejust stated,will resultin a branch;a low inputwill causethe
next sequentialinstructionto be executed.
In reality,thereis no connectionwithin CP1600CPUlogicbetweenthe EBCIinput and the four EBCA0- EBCA3outputs.So far as externallogicis concerned,
the executionof a BEXTinstructionis identifiedby signallevelsoutputand
maintainedon the EBCAO- EBCA3outputs,while the EBCIinput determines
whethera branchwill or will not occur.
How externallogrcchoosesto determinewhetherEBCIwill be set high or low is entirelyup to externallogic.The only
vital functionservedbv EBCAO- EBCA3is to identifythe instantat which a BEXTinstructionis executed.
Another unusualcontrol signalprovidedby the CPl600 isEiT; this is a bidirectionalsignal.
When input low, this
signalpreventsthe ProgramCounterfrom beingincremented
followingan instructionfetch.This signalis alsooutput
as a low pulsefollowingexecutionof a softwareinterruptinstructionlnstructron
the activeinput and
timingseparates

16-7

aciiveoutputof this signal,providingexterna!loEicadheresto trmingrequrrements.

a conflrctbetweeninput and cutpui logicwill neverarise.
BDREY is equivalentto the WA]T signalwe have describedfor a numberof other microcomputers.
EGF,s
input low by any externallogic v,'nichrequiresmcre time in orderto respcndto an l,'OaccessRecallthat the Cp1600,
usesa singleaddressSoacetc reference
memcryor IZQ6srraes The E'5Ftr sicnalcausesthe CPU to enter a \\/art
statefor as long as ETHff is :erng input Io'r":hcweverdurrngthe Wart stateCPUlogrcis not re'reshedTnusa ',\/art
staie cannotiast for mcre than 40 microseconds.
or the conientso{ internalCPU locationswrll be lcst
STPS-fla Halt/Resetinput, is an edge-triggered
signal When externallogicrnputsa high-to-lcwtransitionuiaffi
the CPUwill completeexecutronof any interruptinstructionthen will ente!'aHalt stateand output HALT hrgh lf a

n n n- r nt ar nr nt 2hlci n a tru C ti Oni S b e i n g e x e C u te d.then the H al t S tatew i l l nOt berng unl rl C Ompl eti onOf next int er r upt able
rn s t r uc t ion' s ex ec u ti o n . T h e H a l t s ta te w i l l l ast untrl external l ogrc i nputs another hi gh-to-l ow ffi
t r anst t ion. at
w h i c h t im e t he H a l t o u tp u t w i l l b e re tu rn e d l ow and normal programmrng executi on w rl l conti nue. E xecut ion of t he
H L T r ns t r uc t ion a i s o c a u s e s th e C P1 6 0 0 to e nter a H al t state. as descri bed above
L e t us now look a t i n te rru p t s i g n a l s .
The CP1600 has two interrupt request inputs - INTR ana lffiT.
lffi
has higher prioriry than lffiRT lTfiR- cann o t be dis abled Ty p i c a l l y ,T N T H " w i l lb e u s e d t o tri gger an i nterrupt upon pow er fai l ure or other catast r ophes.
Th e int er r upt ac k n o w l e d g e s i g n a l i s c re a te d by external togi c w hi ch must decode the B C 1 , B C z, and BDI R sign a l s , as s hown in T a b l e 1 6 -' i . O b s e rv e th a i t here are, i n fact. tw o i nterrupt acknow l edge si gnal s: the f ir st iI NTAK)
a ck nowledgest he i n te rru p t i ts e l f.w h i l e th e s e cond (D A B ) i s used as a strobe for external l ogrc to return an I nt er r upt add re s s v ec t or . T he i n te rru p t s e q u e n c e i s d e s c ri bed l ater i n thrs chapter
Th e CP 1600 has tw o a d d i ti o n a l i n te rru p t-re l atedsi gnal s w hrch are unusual w hen compared to other m icr ocom put er s
d e sc r ibed in t his b o o x
TCI is out put high w h e n a n En d -o f-l n te rru p trnstructi on i s executed. Thi s srgnal makes i t easy for ext er nal logic t o
.rp n or z t o; nr or r , , n rn r;6 1 i 1 i gw
g h i c h e x te n d a c rossthe executi on of an i nterrupt servi ce routi ne. W e have discussed t his
su bjec t in s om e de ta i l w h i l e d e s c ri b i n g th e 8 259 P ri ori ty Interrupt C ontrol U ni t i n C hapter 4.
,vPr

Y'l

Table16-1 CP1600Bus ControlSionals

DLI

BC 2

BDIR

SIGNAL

FUNCTION

NACT

T h e C P U i s i nacti ve and the D ara/A ddress B us i s i n a hrgh im peo a nce state.

BAR

A m emory address must be i nput to the C P U vi a the D ata/ Addr ess

Bus.

'l

IAB

Acknow l edged external i nterrupt requesti ng l ogi c must p lace t he

s ta rti ng addressfor the rnterruptservi ce routi ne on the A ddress Bus.

'i

DWS

D ata w ri te strobe for external memory.

ADAR

T h i s si gnal i denti fi es a ti me i nterval duri ng w hrch the D ata/ Addr ess

B u s i s fl oated. w hi l e data i nput on the D ata B us i s bei ng i nter pr eled
a s the effecti ve memory addressduri ng a di rect memory addr essing
o Perati on.

DW

T h e C P U i s w ri ti ng data i nto external memory D W w i l l pr eceoe

D W S by one machi ne cycl e.

'I

ut 6

T h i s i s a read strobe w hi ch external memory or l /O l ogi c can use in

o rd er to pl ace data on the D atazA ddressB us

,]

,l

INTAK

T h i s i s an i nterrupt acknow l edge si gnal l t i s fol l ow ed by IA D which

i s a strcbe tel l i ng the external l ogi c w hi ch i s bei ng acknow l edged t o
i d enti fy i tsel f by pl aci ng an addressvector on the D ata/A ddress Bus.

16-8

MC
ll

rri r2 i.r 3

T1tT2

tl

T3l T4
I

Undefined
state
preceding
data output

Fioure16-3. CP1600MachineCvclesand Bus Timino

I

BAR
M C1

11i

lll

DTB
MC3

NACT
MC2

12:' 13114

rr l

12i 13lto
r ll

r llttl13
Ir

Instruction
address out

Instruction
obiect code in

Frgure16-4. CP1600lnstructionFetchTimrng

16-9

FETCH
INSTRUCTION

READ
TEMoRY
I

BAR

NACT
M C2

DTB
MC3

lJl

Itll

ttl

I
I

NACT

t- I
,,1,"1,,1.,1
T2 ,,i*1,'i,,
-^

Mc1

'l

tr l

- I.t- ^i ll- 4 .- r, z l

lJl

l tl

l .i

aan
MC 1

I
|

NAcr
MC 2

I
|

DTB
MC3

llit
llirr.lr r i rr rzlrslrellirzlrsi'o
r'irzi
i'ri l
I

Data address out

Data in

F i^, , . a 1 A-E r.p 1 A n n T i m i n g fo r Memory R ead Instructi on w i th l mpl i ed Memory A ddressing

TIMING AND EXECUTION

CP1600 INSTRUCTION
CP1600 instructionsare executed as a sequenceof machinecycles.Eachmachinecycle hasfour clock periods,
as illustratedin Figure16-3. Machinecyclesare identifiedby theircycle numberand by the levelsof the BC1.BCz,
Thisnamebecomesthe
and BDIRsignals.Eachof the eight levelcombinations
is givena name.takenfromTable'16-1.
namecf the machinecycle Thus in Figure16-4.and in subsequent
instructiontiming illustrations.
each machinecycle is identifiedby a signal name from Table 16-1.
Figure16-3showsgeneralcasetimingfor dataoutputor inputon the Data/Address
Bus.In betweendatainput or output occralionsthe bus is floated.

CP1 6 0 0 M E MOR Y A C C E S S T IMING

Figure16-4 illustratesinstructionfetch timing for a CP160Oinstruction'sexecution.Threemachinecyclesare reat t 'roA l-)".in a th c f ir gl m aChine Cy Cle an addr e S S i S O u t p u t . N O t h i n g h a p p e n s d u r i n g t h e S e C O n d m a C h in e C yC l e ; i t i s a

Y v" e v

"rrmr qn: ninn" m :n h i q g c y c l e th a t ro u ti n e l y s eparatestw o C P 1600 B us access machi ne cycl es.The obj ect code f or t he
a cc es s ed r ns t r uctto ni s re tu rn e d d u ri n g th e thi rd machi ne cycl e
Fi g ur e 16- 5 illustra te s ti mi n g fo r th e s i m p l est memory read i nstructi on' s executi on. In thi s case the dat a m em or y
a d dr es s is t ak en f r c m o n e o f th e C P U re g i s te rs There
.
i s no di fferencebetw een ti mrng for the three mach ine cycles of an
i n st r uc t r c n [ et c h c : a d a ta m e m o ry re a d . As i l l ustratedi n Fi gure 16-5. a si mpl e memory read i nstruction'sexecut icn
ccns is ls of t wo t h re e -ma c h i n e c y c l e me mo ry read operati ons.separated by a spaci ng no operati on m achine cycle

to- tu

MEMORYWRITE

FETCH
INSTRUCTION
BAR

M c1
I lt

NACT

DTB

fr v/lczlMca
| llt
lt

BAR

NACT

NACT

DW

DWS

Mc rlMc z lMc 3 lMc 4

l! rlrt t l. rllt rl

t:l
lr l

rs!rc
rz!ralrcT1i:T2 i T31ra rrlrzi,mjr+lrrI rz!rslrclrrlrzlrs!rrlrr!,rz!
rr!rz t.lli rz
i*
l
l
al
trrl
l
l
l
l
l
l
l
i*lrr!
i'.i
ltl

Data out

Data address out

Figure16-6. CP1600Timingfor MemoryWrite Instructionwith lmpliedMemoryAddressing

Figure 16-6 illustrates timing for a simple CPl60O memory write instruction execution. Data is output for two
machinecycles,givingexternallogicampletime to respondto the data output.Externallogicusesthe DWS machine
cycle as a write strobe.
-

Any memoryreferenceinstructionthat specifies

directmemoryaddressing
will requireonethree-clock-period
machine
cycleto fetch eachword of the instructionobjectcode;an NACTclockperiodwill seperaleeachmachinecycle.After
the first instructionfetch machinecycle.an AD,AR-NACT
clockperiodcombinationwill be insertedin the second(and
presend
third. if
instructionfetch machinecycle.Duringan ADARclock period.BC1 is high.while BC2 and BDIRare
low. No other control signals are active.Thus, for a two-word memory read or memory write instruction that
specifies direct addressing,the following clock periods and machine cycles will be required for instruction execution:
Direct Addressing
Memory Read
Machine Cycles

Direct Addressing
Memory Write
Machine Cycle
Fetch first instruction
obiect code word

OTB
NACT<-Spacing

DTB
machinecycle--=-*NACT
z BAR

BAR r

NAcr|

ADAR){-Fetch
NACTI
DTB ,/
NACT*-Spacing

secondinstrucriong<
object code word
machine cycle----*

BAR )
Memoryread
NACT> <-machine
cycte
DTB ,

Memorywrite
machinecrcre--)i

16-11

| r'racr
ADAR
| ruaCr
\ DTB
NACT

(:,11,
;**
DWs

lr

t ll

TllTzltglra
I
t
t'

Figure16-7. CP1600Wait StateTiming

T H E C P l 6 0 0 WA IT S T A T E
The CPl600 has a Wait state equivalentto thosedescribed
for othermicrocomputers
in this book.Externaliogicthat
requiresmoretime to respondto an accessmust input EDRDYlow beforethe end of the BARmachinecycle,durinq
which an addr essis output and the deviceis selected.
Timing is illustratedin Figure16-7.

lf you examineFigures16-4.16-5and 16-6.you will seethat an addressis outputduringa BARmac hinecycleto initiate any externaldeviceaccess.The BARmachinecycleis alwaysfollowedby an NACTmachinec.ycle;in the middleof
T1 duringthisNACTmachinecycle,theCPl600samplesffiRDTl{B-5'FDY
is low.then a sequenceof NACTmachine
cyclescccursInthemiddleof T4foreveryNACTmachinecycle,theCP1600samplesEDffiTagain.Upondetect
EffiDY high.the CP1600resumesinstructionexecutionwith a DTB machinecycle.
A Wait state must last for less than 4O microseconds,since the CPl600 is a dynamicdevice.

T H E C P16 0 0 H A L T S T A T E
The GPl600 has a Halt state which may follow executionof the Halt instruction,or may be initiatedby external
logic.
When the Halt instructionis executed,then.followingthe instructionfetch machinecycle,the H,ALTsignalis output
high and a sequenceof NACT machinecyclesis executed.
Externallogicinitiatesa Haltstateby makingthe STPSTinputundergoa high-to-lowtransitionFollowingexecutionof
the next interruptableinstruction,a Halt state begins The HALT signal is output high and a sequenceof NACT
machinecyclesis executed. ,
A Halt state.whetherit is initiatedby executron
of a Halt instructionor by a high-to-lowtransitionof STPST.must be
terminatedby a high-to-lowtransitionof STPST.This will causethe Halt stateto end at the conclusionof the next
NACTmachrnecycle.Timrngfor a Haltstatewhich is initiatedand terminatedby STPSTmay be illustrated
as follows:
STPST

HALT

HALT STATE

16-12

as an input inhibitsCPl600 ProgramCounterincrementlogic.Thus,external

tneffisignat
PCIT
input
low - in which casethe sameinstructionwill be continuouslyre-executed
can
logic
.
goes
high
aga'n However.PTTI shouldonly changelevelswhile the CPU has been
unlirFCTT
)
' halted.Thus. PCITand STPSTshould be used together as follows:

rcTTREOUEST

SEOUENCE
CPl 600 INITIALIZATION
The CPl600 is initialized by inputting the ili$ilCfirst applied to the GPU.

signal low for a minimum of 1O milliseconds after power is

makea low-to-hightransition.markingthe end of the initialization,

on a risingedgeof the O'l clocksigffimust
as follows:
nal.On the next risingedge of @1.instructionexecutionwill begin.This may be illustrated

MSYNC

When instructionexecutionbegins.interruptsare disabled.The followingsequenceof machinecyclesis executed:

NACT
IAB {Read Data/Address Bus and load into Program Counter
NACT
NACT
NACT
Program Counter contents to fetch first instruction
BAR{-Output
NACT
DTB
etc

Duringthe IAB machinecycle,externallogicmust supplya 16-bitaddressat D0 - D15.Your externallogicmust providethis address.

which in the simplestcasemaybe 0000 by groundingthe bus.or FFFFl6by tying it to +5V following
a startup.
The addresswhich is input at IAB is outputat BAR.initiatingprogramexecution.

C P l60 0 D M A L OGIC
CPl609 DMA logic is quite standard.When extarnal logic wishes to transfer data under DMA control, it inputs
BUSRO low. At the conclusion of the next interruptable instruction's execution, the CPU floats the
'Data/Address Bus and enters a Wait state, during which a saquenco of NACT machine cycles is executed.
EmT
is output low at the beginning of the first NACT machine cycle.
The NACT machinecycles that occur duringa DMA operationrefreshthe CPU.NACTmachinecyclesthat occur
duringa Wait statedo not refreshthe CPU.This meansthat any numberof NACTmachinecyclescan occurduring a
DMA break,while a Wait statemust be shorterthan 40 microseconds.
The DMA breakends'g1engternal logicinputsE'[SF-O-high
sampledduring1t of eveE PMA NACT
again.EIISFO-is
machinecycle.WhenEUSROissampledhigh,two additionalNACT
machinecyclesareexecuted.then BUSAKis output high and normalprogramexecutionresumes.
DMA timing is illustratedin Figure 16-8.

16-13

Last machinecycle
of an inlerruptable
instruction's
executron

NACT

NACT
trl

lll

Tt; 12l T3 tT4

Itl

Tl l T2tT3rT4
l tl

lll

T1 I T2 I T3 lT4
lll

* , n/\

Figure16-8. CP1600DMA Timing

INTAK

NACT

trt
rl l
T l l T 2 r T 3l T 4
tl l

I
I
I tl
I

t.l
-tl

I
_^t
_I
rJl
I

fi i'.1,,i'{
l',i'i[,i'.1,,i
"i"1
-i',i'.1',

BDIR
D0D15
Current Program
Counter contents
wnnen to memory
stack

Extemal
logic inputs
staning
address
for Interrupt
service routine

Figure16-9 CP1600 InterruptServiceRoutinelnitialization

16-'14

Start executing
interrupt
serviceroutine

EXECUTE/FETCH
INSTRUCNON

INSTRUCTON
FETCH

DTB

NACT

BAR
MC1

It

rtrcs

r',rcz I
r
r

lr

BAR

trtl

lrrtlrlr

DTB
MC3
I

rrireira!ralrr rslrarr!rz!rslre

rr ! rz r3l 14lrrlrz!rairolrrlrzlrs!
I

NACT
MC2

-l',,i:ij
Mc1

ttl

3
=
i
tl

t
a
a
{
uJ
2
o

:
c

lnstruction
address out

Next instruction
address out

TCI instruction
object code in

Next instruction
obiect code in

Fioure16-10. CP1600Timinofor TCI lnstruction's

Execution

T HE CP1 6 0 0I N TE R R U PLOGIL
T
The CPl600 uses a vsctored interrupt processingsystom.
Externallogic requestsan interruptby inputtinga low signalateithertheJNffi'oriffi'plns.
Followingthe executionof the next interruptable
the interruptby pushing
instruction.the CP1600acknowledges
RegisterR7 contents(theProgramCounter)onto the Stack:then the CP1600outputs111, followedby 010 at BC1,
Bus.These16 bits of data
BC2.and BDIR.Externallogic must respondby placing16 bits of dataon the Data/Address
will be loadedintoRegisterR7.the ProgramCounter,thus causingprogramexecutionto branchto an interruptservice
routinededicatedto the interrupt.Timing is illustratedin Figure16-9.
TheElTsrgnal is output low followiirgexecutionof a softwareinterruptinstruction(SlN).This is the only microcomputerdescribedin this bookwhich allowsexternallogicto respondto a softwareinterruptin this fashion.Allowingexternallogic to respondto a softwareinterruptonly makessensewhen you anticipateyour productbeing used in a
minicomputer-like
Typically.the softwareinterruptwill interfaceto logic of a front panelor console.
environment.
When an SIN instructionis executed.a one-machine
cycle low PCITpulseis output
in
You may.if you wish.end an interruptserviceroutineby executinga TerminateCurrentInterrupt(TCl)instruction.
which casethe TCI signalwill be output high.
Timing for TCI is given in Figure 16-10.
Followingan interruptacknowledge,
the interruptserviceroutinemust executeinstructionsin orderto disableinterR7.the ProgramCounter,which is autoruptsand savethe contentsof registers
on the Stack.Theexceptionis Register
mati callypushedonto the Stackfollowingan interruptacknowledge.
Externallogic is entirelyresponsible
for any type of interruptpriorityarbitrationwhich may occur,and for the generation of the interruptvectoraddresswhich must be input {ollowingan interruptacknowledge.

16-15

It is ouite easyto generatesignalsequivalentto other microcomputer

systemoussesfrom the CP1600SystemBus.
Thorcfnro\/^,, ^2^ use partsdescribedin Volume3 to handleCP'l600 interruotrequlrements.
v'

Ivv

vvr '

T H E CPl 6 0 0 IN S TR U C TION
SET
The CP1600instructionset is relatively
straightforward.
Addressing
modes.whichwe havealreadydescribed.
aresimple.anCinstructions
aretypicalof thosewe haveseenand described
for othermicrocomputers
Unusualfeaturesretating to addressingmodesavailablewith individualinstructionsare summarizedin Table 16-2, which describesthe
CP1600instructionset
lf you have never programmeda PDP-11minicomputer,then you should pay particularattention to programming techniques that result from the Stack PointEr and Program Counter being accessed as ganeral purpose
registers.
A wide varietyof Register
Operateinstructions
allowyou to computedataand loadthe resultdirectlyinto RegisterR7.
the ProgramCounter.In effect,thesebecomecomputedJump instructions.
The abilityto manipulateRegisterR6.the StackPointer,as though it werea generalpurposeregistermeansthat it is
easyto maintaina numberof differentStacksin externalreadlwritememory.
The Jump-to-Subroutine
instructionhas a minicomputerflavorto it. Ratherthan savingthe returnaddresson the
Stack.RegisterR7 contentsare movedto GeneralPurposeRegisterR4 or R5.A numberof minicomputers
will savea
subroutinereturnaddressin a generalpurposeregisterin this fashion.The'problem
with this logicis thatyou mustexecutean additionalinstructionwithin the subroutineto savethe returnaddresson the Stackif you are going to use
nestingsubroutines.
lf you arepassingsubroutineparameters,
however,this is an excellentarrangement.
for the Jumpto- Subroutine
instructionplacesthe addressof the parameterlist directlvin a DataCounterwithauto-increment.
We
havedescribedthe conceptof parameterpassingin Volume1. Chapter7.
Note that the CPi600 instructionset lacksa logicalOR.
ln Tables16-2 and 16-4.instructionlengthis given in termsof "words" ratherthan "bytes".as we havedone in previouschapters.Sinceonlythe lower10 bits of theCP1600objectcodearepresentlyused,systemconfigurations
need
not havethe full '16-bitword size Hencea "word" may be 10 to 16 bits wide.dependingon the implementation.
The followingnotationis used in Table16-2:
AD DR
cond
DATA
DISP
E
EBCA0-3
EBCI
LABEL
ffi
RB
RD
RM
RR
RS
Statuses

One word of directaddress

Conditionon which a branchmav be taken Tablei6-3 listsall 14 branchconditions.
One word of immediaredara.
One word displacement.
SeeTable l6-4 for locationof sion bit.
Externalbranchcondition
The externalbranchconditionaddresslines:EBCA0,EBCAl.EBCA2.and EBCA3.
The externalbranchconditioninout line.
A 16-bitdirectaddress.targetof a Jump instructionSeeTable16-4 for the bit format.
The softwareInterruptoutput line
GeneralPurposeRegisterR4,R5, or R6.
One of the generalpurposeregisters.
used as a destinationfor operationresults.
One of the generalpurposeregistersusedas a DataCounter.R4 or R5. if soecified.is auto-incremented
afterthe memoryaccessR6 is incrementedaftera write. and decremented
beforea read
GeneralPurposeRegisterR0,Rl. R2,or R3.
One of the generalpurposeregisters,
usedas the sourceof an operand.
s tne srgn status
C the Carrystatus
Z the Zerostatus
O the Overflowsiatus
The followrngsymbolsare used in the STATUSES
column:
X tne statusf lag rs affectedby the opdrat'on
a blankmeansthe statusf lag rs not affected
0 tne operationclearsthe statusflag
1 the operatron
setsthe flag
2 the Overflow f lag is affectedonly on 2-bit shiftsor rorates

'16-16

SW

The StatusWord. whosebits correspond

to the conditionof the statusflags in the followingway:

32r

B'r No.

Ffzfofc-l

StatusWord

When the statusword is copiedinto a register,it goesto the upper half of each byte:

)
J

r RRJ

t swr

)
W hen th e s ta tu s w o rd i s l o a d e d fro m a regi ster.i t comes from the upper hal f of the l ow er b yt e:

7
J7

a
t

tswl
)

x<y.z>

(.21

t1

tt tl
A
tA
_

Bits y through z.of the Registerx. For example,R7<'15.8) representsthe upper byte of the program
Counter
lndicatesthat the operand".2" is ootional
A low pulse
Contentsof locationenclosedwithin brackets.lf a registerdesignationis enclosedwithin the brackets.
then the designatedregister's
contentsare specified.lf a memoryaddressis enclosedwithin the brackets,
then the contentsof the addressed
memorylocationare specified.
lmpliedmemoryaddressing:
the contentsof the memorylocationdesignated
by the contentsof a register.
LogicalAND
LogicalExclusive-OR
Additionor subtractionof a displacement.
dependingon the sign bit in the ob;ectcode.
Data is transferredin the directionof the arrow.

-)

16-17

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Codes
Table 16-3. CP1600BranchConditionsand Corresponding

MiIEMONIC

c
LGT
NC
LLT

ov
NOV

PL

)
i,0
I

E
EO
t{zE
NEO
LT

G
LE

ERANCH CONDITION

OBJECTCODE
DESIGNANOT{

d)r

C =l
Catry
{bgiccl gr!.tr
C =0
fb Cr.ry
lbqi:d 16

rhrr)
l @1
thm)

O=l
Or.rfiow
O =0

@10

r0r0

l,lo ovrfiow
S =0
Phr.

mil

s:1
Mnur

10tI

Z =l
Zro l.Crdl
Z =O
fforucro {rcr cquel}
'- . . , \
S r *O =l

0r@

t6r d[,1
'-=;r
S Y O=O
Graarr drrn or cquel
zV {S Y OI = I

1r@
o101
t rol
ol r0

Lecs trm or aqd

GT

usc
ESC

z v(SvOl = O
Crartr thln
. _
-'
C Y S =t
.-'trqUrip
md clry
C Y S :O
i -- Equd dgn lrid c-ry

1lt0
otil
ltlt

The followingnotationis used in Table16-4:

)
'

Whereten digitsare shown,they are the ten low-orderbits of a 10 to 16-bitword. (Wordsizedependson the system
notationfor an entireword (10 to '16
Where four digitsare shown,they representthe hexadecimal
implementation.)
bits).
Two bits indicatingone of the first threegeneralpurposeregisters
bb
Fourbits giving the branchcondition.as shown in Table 16-3
cccc
Threebits indicatinga destinationregister.RD
ddd
Four bits giving the externalbranchcondition,E
eeee
llll
One word of immediatedata
mmm Threebits indicatinga DataCounterRegisterRM
m
One bit indicatingthe numberof rotatesor shifts:
0 one bit oosition
1 two bit positions
p
One bit of immediateaddress
P
digit (4 bits)of immediateaddress
One hexadecimal
rr
Two bits indicatingone of the first four generalpurposeregisters
sss
Threebits indicatinga sourceregister.RS
z

I
,

Sign of the displacement:

0 add the displacement
to PC contents
from PC contents
1 subtractthe displacement
ln the "MachineCycles"column.when two numbersare givenwith one slashbetweenthem le.g.,7/9\.executiontime
dependson whetheror not a branchis taken.When two numbersare given.separatedby two slashes(suchas 8//11).
executiontime dependson which registercontainsthe impliedaddress.

16-23

t
Table 16-4 CPi 600 Insrrucrron
Set OblecrCodes
MA C H IN E
MA C H IN E

C Y C LE S
ADCR RO
ADO ADDR,RD
A D D @ .R M , R D
ADDI DATA,RO

0 0 m i0 1 d d d
10',il000ddd
PPPP
1 0 1 lm m m d d d
'1011111ddd

ADDR RS,RD
AND ADOR,RO

iltl
0O11sssddd
11100@ddd

ANOA RM,RD
ANDI DATA,RO

PPPP
1 l lOm m m d d d
1 1 ]0 11ld cld

ANDR RS,RD
B OISP
Bcond DISP
BEXT DISP,E
at

MVII DATA,RD

PPPP
lfficccc
PPPP
10@z1eee
PPPP

CMP.'I RM,RS
CMPI DATA,RS
CMPR RS,RO
COMR RD
O E C RR D

ots
EIS
GSWD RR
HLT
INCRRD
J

4O t r L

PPPP
I1 0 lm m m sss
1 1 0 1 1 1 lsss
ml
0 l0 1 sssd d d
om@r 1ddd
000001oddd
rrrl?
ffi2
0OOOI10Or
0000
0000001ddd
0004
I 1ppppppOo

8//11

0@4
l1 p p p p p p 1 0

JR RS
JS R R B , L A E E t

7/9
7 /A

stN (2)

l0

S LL R R (.2)
S LLC R R (,2}

8//11

S LR R R (,2)
S U 8 A D D R ,R O

S U B @ R M,R D
SUBT DATA,RD

o
b

S U B R R S ,B D
SWAP RR(.2}
TCI
TSTR RS

X OR A D OR ,R O

17

X OR t(i ]R M,B D
XORI DATA.FD
X OR R R S .R D

MOVE RS,RO
MVI ADDR,RD

0004
bbppppppO't
PPPP
0OI osssddd
r 0 lm o o d d d

MVI , RM,RD

PPPP
l0 lOm m m d d d

to-14

C Y C LE S

o
b

0@10l Omn

1l
A /e

0OO1110mn
00OO1
1 lsss

6/8

0@l l 0l mn
0OO11l 'l mrr
0001
0007
0@01'l 0l 1m
00O10O
lmn
0OO101l mn
0@t lOomn
11o@oodctd
PPPP
l lOommmddd

o
R/9
6/8

4
6
6/8
6/8
6/8
10

8//11

I r00l I l ddd
lill
0'lOosssddd
00O1O@nn
0005
0olOssssgs
11 t l000ddd
PPPP
'I l l l mmmddd
111111l ddd

1a

0004
bbppppppOO
PPPP

JSRE R8,LA8EL

PPPP
10O1I lOsss
101011oddd

QTT'

PPPP
@ 1 0 sssl1 l

0004
b b p p p p p p1 0
PPPP

PSHR RS

SAR RR(,2)
SARC RR(.2)
SDBD

7/9

0004
' I lp p p p p p o l

JSRD R8,LA8EI

lill
0000100ddd
OO@l 10l Om
l0OOZOt0oO

ruLR RD
RLC RR(,2}
R R C R R I,2)
RSWD RS

PPPP
JE LABEL

N E GR R D
N OP (2)
NOPP

PPPP
JO LABEL

PPPP
l 0Ol mmmsss
'l 0Oll 1'l sss

o
l0

ffi

0 1 1r d d d d d d
1 ' 1 0 1 o @ sss

MV OO R S ,R M
MVOI RS,OATA

8//11

Qa

CIRR RD
CMP ADOR,RS

MV O R S ,A OOR

10101I l ddd
iltl
l@1Ooosss

10

ilil.
0 I l0sssddd
10OOz@O0O

OB JE C T C OD E

iltl
0l l l sssddd

A
6/8

6/ /7

8//11
8

/:

THE BENCHMARKPROGRAM
1
I

For the CPl600 our benchmark program may be illustrated as follows:

MVII
MVII
MVt@
MVII

'
.
!

IOBUF.R4
TABLE,Rl
R1.R5
CNT,R2

ADDRESS
INTOR4
STARTING
LOADTHEI/O BUFFER
TABLE
ADDRESS
THE
INTOR1
STARTING
LOAD
LOADADDRESS
OF F|RSTFBEETABLEWORD|NTOR5
LOADWORDCOUNTINTOR2

MVr@ R4,Ro
LoADNExrDATAwoRDFRoMroBUF
loop
3
INNEXT
TABLE
WORD
;
MVO@ RO,Rs
STORE
woRDcouNT
l
Rz
DEcREMENT
oecn
tFNor END
RETURN
BNzE LooP
3
=MVo@ R 5 ' R 1 R E T UR N A D D R E S S o F N E XTFREETABLEBYTE
ii
S

The input tableIOBUFand the datatableTABLEcan haveany

Tnis benchmarkprogrammakesveryfew assumptions.
length.and can resideanywherein memory.The addressof the first freeword in TABLEis storedin the f rrstword of the

TABLE.

a
a:
a
l,l

2
)
!
h
f

E
3

\)

16-25

cP 1600
SystemBus
Signals

8080A
SystemBus
Signals

AO
A 15

High-order
byte
Loar-order
D7 I
byte

Dot
Dot
D7t

BC't
BC2

I of 8 Decoder

BD IR

INT
INT
BUSEN
HOLD

BDYIN
WAIT

lfrSVNe

rr.r;

STSTP
HALT
Tr'l

EBCAO
EBCA3
EBCI

Figure16-1'1 CPi 600 ro 80BOABus Conversron

16-26

SUPP ORTDEVICESTHAT MAY BE USED WITH THE CPl600

A CP1600 microcomputersystem with any significantcapabilitieswill use support devices of some other
with the CP1680.(described
microprocessor.
Parallell/O capabilityis available
next),.butpriorityinterruptlogic.DMA
just
few
a
logic,and seriall/O logic.to mention
commonoptions.may needadditionalsupportdevices.Fortunately.
it
is quite easy to generatean 8o80A-compatiblesystem bus from the CPl60O system bus. Logic is illustratedin
Figure16-11.
The CP16004is the fastestversionof the CP1600CPU;it runs rvith a 500 nanosecond
machinecycle.The CP1600
machinecycleis equivalentto an 80804 clockperiod.Sincethe standard80804 clockperiodis also500 nanoseconos,
no speedconflictswill arise.
The bus-to-bus
in Figure16-11 is self-evident,
interfacelogicillustrated
with the exceptionof busdemultiplexing
logic.
The CP1600Data/Address
Bus is shownbufferedby a demultiplexing
bufferthat is connectedto two latchedbuffers.
Oneof the latchedbuffersacceptsthe demultiplexer
outputsonlywhen a validaddressis beingoutput,as identifiedby
BAR high. The secondlatchedbuffer may be a bidirectional
latchedbuffer.or it may be two unidirectional
latched
buffers.Threelatchingstrobesare required:DTB.lAB, and DWS.
DTBand IAB aredata input strobes.DTBstrobesdatainput that is to be interpreted
as data,while IAB strovesdata input that is to be interpreted
Sofar asexternallogicis concerned,bothof thesesignalsaresimpledata inas an address.
put strobes.We could thereforegeneratea singledata input strobeas the OR of DTB and lAB. When this data input
strobeis high, informationon the 80804 SystemBus sideof the latcheddata buffermust be input to the buffer;this
data must simultaneously
be transmittedto the multiplexer.
I

)l
?

DWS is the dataoutputstrobe.When high,thissignalmuststrobedatafrom the multiplexer

to the latcheddatabuffer;
this latcheddata must immediatelyappearat the 80804 system Bus side of the latcheddata buffer.
Sincethe CP1600usesa 16-bitDataBus.you will probablyha'veto generatetwo externaldevicedata busses:a highorderbyte bus and a low-orderbyte bus.All externaldevicesthat transmitor receiveparalleldata must be presentin
duplicate.For example.were 8255 parallelinterfacedevicesto be present.the followingconnectionswould be required:

wFRD
DO
D7
D8
D15
AO
A1
A2
A15

6tt3
oDl

wR-

WR

FN

AO
A1

AI

:dE

Ltr

16-27

5tc5
PPI

svstem
busses
aresinsularlv
incompatibre.
Youshourd
norarrempt
touseMC6800
supp(
lff::t;t,,? il: yrtttt:

=iei

IMSKO

2
3

tlt

vq

D6

ffiT
rcLB
PDO
PD l
PD2
PD3
PD4
PD 5
PD6
PD7

P i nN a me
D 0 -D 7
i
P O o- PD 1 5 I
B D IRBC
, 1 ,B C z
cK l
'.- .
LE

PE
AN

INTR_O

Ter

IMSKI
IMSKO

EFFOF
FdH'
vcc, vDD,cND

5
6
7
I
9
10
1l
12

mm

JY

IMSKI

38
37

nl

D3

40

EL

JO

cP 1680
loB

t5
to

35
34
33
32
31
30
29
28
27
26
25

M'RbF
GN D
VDo
PE
ffi
P D15
P D14
P D13
PO12
P D 11
PD1O
PD9
PD8

17
td
IJ

Description
CPU Data/Address Bus
Peripherall/O Port
8us Control signals
Clocksignal
Chip Enable
l/O handshakecontrol
l/O handshakecontrol
lnterrupt request
Terminatecurrent interrupt
Daisy chain priority
Daisychain priority
Error interrupt request
Reset
Power. Ground

BC2
BDIR

Tvpe
Bidirectional,tristate
Bidirectional
Input
Input
lnput
Output
Input
Output
Input
Input
Output
Input
Input

Figure16-12 CPtO80tOBSignatsand pin Assiqnments

Io-lu

F
<

;E
>d

o- sE F - - >

63H8 2 ? 6 " i

3d
UV
U OUU S
:rud

3d
HV
unuHl
!rud
tM

o-

.\
t

fi

i!

FEHg
s?E
16-29

BUFFER(IOB}
THE CPl680 INPUT/OUTPUT
The CPl680 IOB is a parallell/O device designedspecificallyfor the CPl600 CPU.This device providesa singte
15-bit parallell/O port, which may optionatlybe configuredas two 8-bit l/O ports. Primitivehandshakingcontrol
signals are available with the parallel l/O logic. Elementaryinterval timer and prioritized interrupt logic is also
provided.
Figure16-1 also illustratesthat part of our generalmicrocomputersystem logic which has been implementedon
the cPl680 toB.
The CP1600IOBis packagedas a 40-pin DlP.lt requirestwo powersupplies,*5V and +12V. All inputsareTTL compatible.The deviceis implementedusing N-channelMOStechnology.
Figure 16-13 illustratesa CPl600 microcomputersystem with three CPl680 IOB devices in the configuration.

CP 1 E8 O I O B P IN S A N D S IGN A L S
The CPl680 IOB pins and signalsare illustratedin Figure16-12.We willsummarize these signalsand the functions they serve before examining device operationsin detail.
Let us begin by lookingat the interfacebetweenthe CP1680IOBand the CP1600CPU.
D0 - D7 provide an 8-bit parallel Data/AddressBus via which all communicationsbetvrieenthe CPU and IOB occur. This bus must connectto the low-ordereight bits of the 16-bitCPU.Data/Address
Bu$.
The three bus controlsignals,BCl, BC2, and BDIR,connectthe CPl68O tothe CPl60O as itlustratedin Figure
16-13. The CP1680IOBdecodesthesethreebus controlsignalsinternally.
A clock input is requiredby the CP1680.This clock input {CK1}is used by internal logic to determinewhen BCl,
BC2, and BDIR are valid. CK1 must have the followinqwaveform:

rl l

ll

T1l T2l T3tT4

Irl

r r fr z

13 IT4
I

CK1 must be derivedfrom the CP1600clock signalsby externallogic

Let us now lookat the interfacebetweenexternallogic and the CP1680lOB.
PDO- PDl5 provide a 16-bit parallel l/O port which can optionally be configured as
cPl600 r/o
two 8-bit !/O ports.While PDO- PD15 are in theorybidirectional.
thesepinsare moreac- PORT PIN
curatelydescribedas pseudo-bidirectional.
This is becausewhen a zerohas beenwritten CHARACTERISTICS
to one of theseoins.the outout can sink 1.6 mA for an outoutvoltaoeof *0.5V. External
logicwill havea hardtime overcomingthis sink in orderto pull the pin high.ln contrast,when a I is writtento one of
thesepins.the outputsourceslust 100pA at +5V. Externallogicwill havelittleproblemsinking1OOpAin orderto pull
you shouldoutputa 'l to any pin that is subsequently
a pin low.Therefore.
to receiveinputdata Externallogicwill then
leavethe pin high when inputting1, while pullingthe pin low to input 0.
The handshaking
controlsignalswhich link the CP1680IOBwrth externallogic are PE and EfA pg is a controlsignal
which is output by the CP1680.and ffi is a controlsignalwhich is i,rputto the CP1680.
Now considerCP'1680interruptsignals.
An interrupt request is transmitted to the cPl600 cPU viaTtIiFO. The cPU acknowledges the interrupt via the
TNTAKcombinationof BDIR, BCl, and BC2.Tei must be output tow by the CPU at the end of the intemrpt service routine.Thissignalis requiredby CP1680interruptlogic.which usesthe lowTTpulse in its priorityarbitration,
as describedlaterrn this chaoter.

I O-JU

Interrupts may be generated by conditionsinternalto the CP1680.or by a tow input atffiffiF.

reservedfor error conditionsdetectedby externallogic.

TneffiF-O'H'input
is

\
, IMSKI and IMSKO are interrupt priority input and interrupt priority output signals,respectively.Thesesignalsare
used to generatedaisychain interruptprioritiesbetweenCP1680IOBdevices.as illustratedin Figure16-13.We will
describeCP1680interruptprioritiesin moredetaillaterin this chapter.
TiEEF is the master reset control input for the CPl68O.Thissignalmust be input low for at least10 milliseconds
in
orderto resetthe CP1680lOB.

REGISTERS
CP1680ADDRESSABLE
The CP1680 has eight addressablelocations,which may be illustrated as follows:

Theseeightaddressable
locationsareall 8-bit registers;
they areaddressed
usingthe firsteightaddresses
in a 256-addressblock,as follows:
Register
Control
Data buffer.low-orderbyte
Data buffer.high-orderbyte
Timer.low-orderbyte
Timer.high-orderbyte
l/O interruplvector
Timerinterruptvector
Errorinterruptvector

1 6 -3 ' r

Address
\J
1

will be identifiedby the eighthigh-order

Theactual256 addresses
CP1600DataiAddressBus lines.which wi1 be u
to createCP1680deviceselectlogic ThisdeviceseiectlogiccreatesGitne chip enablesignal);it may be illusrratr
as follours:
DO
I
t

o7
D8
O
a

D 15

D0---D7atCPl680

00000Y

Y Y

Valid CPl680 addresses

M a y b e 0 0 0 , 0 0 1 , 0 1 0 , 0 1 1 . 1 0 0 , 1 0 1 . 'l 1 0 . t I I

May have any 8-bit pattern that device select logic

has been designedto createG low in responseto.

T H E C P1 6 80C O N TR OLR E GIS T E R

We will summarizethe individualbits of the CP1680controlregisterbeforedescribingthe operationsthey control
Here are CPl680 Gontrolregisterbit assignments:

43210

No.

#-Bir

CPl680 Control register

This.is.called
the
r/o active 1
I o - parailer
o'l'
1 1 - Parattet
l/o inactivef ::aoJ
l-E:HEAOV

ERRORinput signal level held here

0 - PD0-PD15configuredas two 8-bit ports
'l - PD0-PD15configured as one 16-bh port
0 - Disable parallell/O and Error interrupts
'I - Enableparallell/O and Error intemrpts
0 - Disabletimer interruots
1 - Enabletimer interruots
0 - Disableclock logic
1 - Enableclock logic
Parity of D8-D15 bvre
Pariryof D0-D7 byte

16-32

I\
I

O : even parity
t : odd ParitY

Bit 0 is alwaysthe complementof the PE controloutput.This bit may be interrogated

by the CPU.lf paralleldata
transferinterruptsare disabled.this allowsthe CPUto pollon statuswhen monitoringparalleldata trans fers.
PEsignal
levelsare illustratedin Figures16-14and 16-15
Bit I reflectsthe levelof theffiOF-input. lf paralleldata transferinterruptlogic is disabled.then the Errorinterrugt
logic is alsodisabled.Thus,the CPUmust alsoexaminethe Errorstatusbit when pollingthe CP1680.
Bit2determineswhetherPDO-PD15willactasasingle16-bitl/Oport.orastwo8-biti/Oports
Thisisonlyimpofiant
when outputtingdata.
Controlregisterbits 3 and 4 areusedto enableand disableparalleldata transferand Errorinterruptlogic,and timer intorrr rnt

lnnin

Controlregisterbit 5 is usedto enableand disableCP1680intervaltimer logic.lf this bit is 0, the intervaltimerwill not
decrement.
Bits6 and 7 reporlthe parityof tne high-order
byteand low-orderbytefordatathat is inputoroutputvia PD0- PD15.0
indicateseven paritywhile 'l indicatesodd parity.
't

All Controlregisterbits may be writtenintoor read.You shouldbe verycarefulwhen settingor resettingindividualbits

not to simultaneously
modifyotherControlregisterbits.This meansyou shoulduse a three-instruction
sequencewith
an AND or OB maskto set or resetany Controlregisterbit. For detailssee Volume 1-Qas1c
Colceptg

CP1680 DATA TRANSFER

OPERATIONS

The CPU inputs and outputs data via the CPl680 IOB by executing MVI and MVO instructions,respectively.
The CPUmust accessthe CP1680in byte mode,sincean 8-bit Data/Address
Bus (D0- D7)connectsthe CPUand the
CP1680lOB.Whetherthe l/O port PD0- PD'15is configuredas a single'16-bitport or as two 8-bit portshasno bearing
on the fact that the CPU must accessthe CP'1680in bvte mode.
The most efficient way of accessingthe CPl680 is by using the SOBO instructionwith implied memory addressing.Considerdata input.lf PDO- PD'15is configuredas two 8-bit l/O portsand you wish to access,ustone of
thesel/Oports.thenyoucanuseimpliedmemoryaddressingviaRl.R2.orR3
Wemayillustrateinputf romrhehighorderbvte cf l/O Pc:t PDB- PD15 as follo,,vs

Register0l
4F

I O-JJ

lf PDO- Pll15 3re configuredas tv/oB-bit| 'O oortsor as a single16-bitl/O port.and you want to readboth lrO oorts.
therryor: shoulduse the SDBDinstructionwith rmplredmemoryaddressing
via R4 or R5 This may be iilustraredas
iollows:

Co rr t r ol legi, \ t : e itrt 2 l c o n fi g u re s PD O - PD 1 5 as a si ngl e 16-bi t l /O port or as two 8-bit l/O ports.

Ci vr ; n t hr : ia. , : 11111;3
i l r1 \' a
r n d l Vl VOrn s tru c tro n si i n byte mode) shoul d be usedto accessthe Cp1680.when shouldthese
i r r . i , i :l :::fl S

t)r-a '.t i ' /

Th c dr ] s v v er, : iha t i h e P E a n o ffi -s rg n a l s c o n trol event sequences.

C o n s ider par allel d a ta i n p u t, a s i l l u s tra te d i n Fi gure 16-14.

When the CPU is ready to input data in resets the

Control registerREADY bit low. This forces the PE
output high
Extemallogic uses PE high to trigger data rransfer
to the PD'1680.Externallogic signals the end of
data input by inputting ffi- low

IN iRO

:)i iAf

Frgure16-14 PD16B0Handshaking
wrth Data Inpur

16-34

registerbit 0 to 0, this forcesthe PE controlsignalhigh.

When the CpU is readyto receivedata. it resets-Control
When externallogic sensesPE high, it must transmitdata to the PDO- PDl5 l/O port.At this point it makes no
port.Externallogic will pull to
differencewhetherpins have beenconfiguredas two B-bit portsor as a single16-bit
groundselectedhigh pins.while leavingotherhigh pinsalone.When externallogic hascompleteddata input. it sigials the fact by inputtingffi-tow. lt is the high-to-lowtransitionof the AR controlinputwhich indicatesthe presenceof
new data for the CpU to read.When AH'makesits high-to-lowtransition,PEalsomakesa high-to-lowtransition.and
via lfffRa,.Figure16-14
C"",J r"gir,.r bit O is set to 1 lf interruptshavebeenenabled.then an interruptis requested
high-to-low
transition.
a
making
shown
assumesthat interruptshave beenenabled;thereforeINTR-Ois

The CpU will acknowledgethe interruptrequest.as describedearlierin this chapter,by outputtingINTAKvia BC1.
BC2.and BDIR.Logic internalto the CP1680usesINTAKto resetINTROhigh again
Thereare manywaysin which externallogiccan determinewhen to setl-R high again.ln Figure16-14we show exterthe CPUmust haveacknowledged
nal logicusingPEto setAFhigh. Clearly.when PEmakesa low-to-hightransition,
m lo;; thereioreexternatlogiccan now setffi'nign. Now that El: nign again,externallogiccan input new data.An
alternative
schemewould be for externallogicto constantlyholdAR-low.usingthe levelof the PEoutputto determine
When PE is high,externallogicwill transmitnew data to the CP1680once.As
when new data couldbe transmitted.
soonas it transmitsnew data,externallogicwillstrobethe datawith a short,highARpulse"then wait for PEto go low
and high againbeforeinputtingmoredata.This may be illustratedas follows:

AF

-+

CPUis
ready

Extemal
logic inputs
data

agai n
for input

Data output handshakingis illustratedin Figure16-15.

When CPU outputs data, PE is automatically set
high
Extemallogic uses PEhigh as a "valid data ready"
signal. After readingthis data it resets ffi'tow

DO - D7

PE

AH

iNTFO

INTAK

for DataOutput
Figure16-15.PD1680Handshaking

16-35

Extemal
logic inputs
data

The most important point to note is that there is no control bit which specifiesdata input mode or data output
mode.Thus, the signalseguenceswe describedfor data input and those we are about to describefor data output occur automatically;the input or output mode is purely a function of CPU and external logic interpretation.
WhenevertheCPUoutputsdatatothePDl630,thearrival
of dataforcesPEoutputhighllPD0-PDiShasbeeirconfiguredas two 8-bit ports,then the arrivalof a singledata byte to eitherport will causePEto be output hi-ohlf PDOPD'15is configuredas a single'16-brtl/O port, then PD will not be output high untrl two byresof data have been
receivedfrom the CPU bv the PD1680.
OncePEis outputhigh.nothingmorehappensu'ntilexternallogicresponds.
Externallogiccannottell by the simpleinspectionof any controlsignalswhethera data inputoperationor a data outputoperationis in progress.
lt is up to you.
when designingyour system.to dedicateCP1680devicesto inputor output;or you mustgenerateyourown identificaIn Figure16-15we simplyassumethat externallogic knows
tion logic in the eventthat a CP1680IOBis bi directional.
if the data is 8 bitswide.external
data is to be read,and knowswhetherthe data is 16 bitsor 8 brtswide.Furthermore.
logicmustknowwhich 8 bits to read ln any event.when externallogichascompletedits undefinedoperations.
it must
inputAR low.The high-to-lowtransitionof AF'forces
PElow again.and if interruptsareenabled.an interruptwill be requestedvia IIITFt'. When the CPU acknowledges
the interruptby outputtingINTAKvra BC1. BC2. and BDIR.the
PDl680 usesthe INTAKpulseto resetINTRQnign.
The methodusedby externallogicto resetA-Fhighagainis undefined.In Figure16-15.we show PEgoing high as the
triggerwhich externallogicusesto resetAR high.This is clearlya viablescheme;PEwill not go high againtrntilfresh
datahasbeenoutput,at which point it is safeto assumethat the CPUknowspriordatahasbeenreadby externallogic.
It would be equallyviablefor externallogicto holdffi-continuouslylow, transmittinga short.high pulsewheneverit
readsdata.This mav be illustratedas follows:
rE

- t-

+
I

CPU has
output
oata

Extemal
logic has
read data

CPUhas
outplJt
more data

External
logic has
read data

Becausethere are no control signalswhich identify the PD1680 operatingin input mode or output mode, there
is no straightforwardscheme for handlingbidirectionaldata transferswith a single PD1680 device.

T HE C P 1 6 8 0 IN T E R V A LT IME R
The CP1680 has very elementaryintervaltimer logic.A 16-bitTimerregister.addressed
as two separate8-bit locations,decrementsonceeveryeight CK'l pulses,providingthe timer has beenenabled You enableand disabletimer
logicvia Controlregisterbit 5. As a separateevent,timer interruptsmay be disabledvia Controlregisterbit 4. lf timer
interruptsare enabled.then when the timerdecrements
to 0. an interruptrequestwill occur.ffimer interruptlogic is
describedwith otherCP1680interruptlogiclaterin this chapter)lf timer interruptsare not enabled.then the timer itself is effectivelydisabled.sinceyou cannottest any timer statusflag to see if the timer timed out; nor can you accuratelyreadthe contentsof the Timerregisters
on the fly. sincethereis no protectionagainstreadingtimer contents
while it is in the processof being decremented.
The only timer programmableoption you have is to load an initial value before the timer is enabled.The timer
has no buffer; therefore, once it times out it begins decrementingagain, if still enabled,beginningwith the
value FFFF15.This may be illustratedas follows:
Timeintervals-

[<-

Load
Timer
stanrn9
valu e XXXX
a no s t an
Timer

xxxx.8.cKr -+F-

r ---'{*-FFFF.8..K

Time out.
Restarl

Time out.
Restart

16-36

rr* 1..* r --{

fime out.
Restan

The only accuratelong time intervalsyou can computeare exactmultiplesof FFFF16'8'CK1.

cycle time. Thus. CK1 equals500
The CP16004usesa 4MHz two-phaseclock,which generatesa 500 nanosecond
multiple
262.'144
milliseconds
intervals
must
be
an
exact
o'f
CP'16004
-the time it will
time
and long
nanoseconds,
FFFF16
from
0000.
decrement
to
takefor the counterto
a 600 nanosecond
cycletime; therefore.longtime inter3MHztwo-phaseclock,which generates
milliseconds.
314.572
vals must be exactmultiplesof
J.
I hE Lt , I O U U U S E S A ^

IJ

cycletime.will computelongtime inclockand hasa onemicrosecond

TheCP1610.which runson a 2MHztwo-phase
tervalsthat are exactmultiolesol524.288 milliseconds.
J

=
,J,
.lJ

s
c.J'
o
{
gJ

z
c
,o

c
E
o
Yt

You cannotattemptto generateclockperiodsthat are multiplesof shortertime intervalsby loadingsomeinitialvalue

intothe timerfollowingeachtime out; an unknownamountof timewill elapsebetweenthe intervaltimer interruptocThe lengthof this unknownperiodof time will dependon the numberof non-intercurringand beingacknowlOdged.
ruptableinstructions
which may be executingin sequencewhen the interruptrequestfirst occurs.plus any higher
priorityinterruptswhich mayexist.Therefore,
if you loadan initialvalueinto the timer.it shouldbe to computean isoli nstructionsequence.
ated time intervalonly. Hereis an appropriate
MVI
ANDI
MVO
MVll
MVO
MVll
MVO
MVI
ADDI
MVO

REGISTEB
CONTENTS
IOB,RO
;INPUTCONTROL
4
AND
BITS
5
CFH.RO ;ZERO
TO CONTROL
REGISTER
RO.|OB
;RETURN
TIMER
LOW-ORDER
2AH.R0
;TRANSMIT
RO,|OB+3 ;lNlTlALBYTE
TIMER
HIGH-ORDER
34H.R0
;TRANSMIT
R0,JOB+4 :lNlTlALBYTE
REGISTER
CCNTENTS
|OB.RO
:LOADPRIORCONTROL
30H.R0
;SETBITS4 AND 5
R0.|OB
:STARTTIMER

The instructionsequenceabovebeginswith three instructions

that load the CP1680Controlregistercontentsinto
Register
R0. Bits4 and 5 arezerod,then the resultis returnedto the CcntrolregisterThus,the time. and timei'interan SDBDinstructionSincethe dala sourceis eight bits vrrde.only the lowruptsare disabledWe dc not botherrarith
orderbyt o{ RegisterR0 will be significant.Thrsberngthe case.we can use an 8-bit immediateAND masr to mt City
RegisterR0 contentsbeforereturningthe low-orderbyte to the Controlregister.
halt
RO.Eachbyte is writtenout to the appropriate
Next.we loadthe initialtimervalue.onebyteat a time.intoRegister
Sincean 8-bit data path connectsthe
of the Controlregister.Onceagainwe do not needto usethe SDBDinstruction.
CPUto the 1680 lOB.only the low-orderbyte of RegisterR0 will be significantduring the data output .
Finally.we start the timer by loadingControlregistercontentsinto RegisterR0.settingbits 4 and 5 to'l and writing
backthe result.
you clearany timer interruptrequestswhich may at that time be pending.
When you write into the Timerregisters.

CPl6 8 0 I N T ER R U P TL OGIC
A CPl680 IOB will generate an interrupt request by outputting a low signal atTtiffiE if any one of these three
conditionsoccurs:
1) A low input atmE6fi-'.Externallogiccan requestan rnterruptvia the CP1680using theffi-OF input.
2\ Theffi-handshakingcontrolinput makesa high-to-lowtransitionThis is illustratedin Figures16-14and 16-15
from 1 to 0.
3) The lntervalTimerdecrements
One controlbit appliesto
Recallthat therearetwo separateinterruptenable/disable
controlbits in the Controlregister.
Timer.while the othercontrolbit appliesto both tfreffi'handshakinganOEH-RG-interrupts.
the l.nterval
Interrupt prioritiesamong the three sourceswithin a single CP1680 IOB are as follows:
hiohesr
EF'FOR-'
IT"
na-nOsbat<ing
Timer lowest
When more than one CPl680 IOB is presentin a CPl6O0 microcomputersystem, then daisy chain priority is implemented using the MSKI input signaland the MSKOoutput signal.Signalconnectionsare illustratedrn Figure
16-13.The manner in which intarruptprioritiesare handledby the CPl680 is a little unusual.
Two or more CP1680devicesmay combinetheir interruptrequestsignals.which are wired ORedand inpul to the
CP1600 viaTfriJEdTheCP1600acknowledges
an interruptvia the INTAKcombinationof BC'l. BCz.and BDIR.We de-

16-37

receivethe INTAK combination:

scribedthis processearlierin the chapter.All CP1680 devicessimultaneously
raisesits IMSKOsignalhigh,causingit to becomethe IMSKIinput to the
however.a CP1680which is acknowledged
nextCP1680in the daisychain.Any devicethat receives
a high IMSKIinput ignoresthe interruptacknowledge.
Thus,
CP1680devicein the daisychainwill processthe interruptacknowledge.
only the highestpriority.interruptreQuesting
However,it takesa finiteamountof time for IMSKOhigh signalsto propagate
as IMSKIsignals.and thusripplethrough
a maximumof eightCP1680devicesmay be presentin the darsychain A ninthdevice
the daisycharn.Consequently.
will receiveits IMSKIhigh signaltoo late and will respondto an interruptacknowledge.
CP1680IOBdevicesmaintaintheirinterruptprieritystatusuntil they receivea high TCI pulse.At that time.priorinterrupt prioritiesare resetat all devices.and new priorityarbitration
beginsThus.when usingCPl680 IOB devices,you
are required to end all interrupt service routines by executing a TCI instruction.
Notethat if oneCP'1680IOB
hasmorethan one activeinterruptrequestiforexample,an ERROR
interruptrequestand a
timer interruptrequest).
then this internalinterruptprioritywill takeprecedence
over the daisychaininterruptpriority.
That is to say,the ERROR
interruptrequestwill be acknowledged
and servicedf irst.Afterthe nextTCIinstructionis executed.the timer interruptrequestwill be servicedbeforeany interruptrequestfrom a lowerpriorityCP1680deviceis
acknowledged.
Every CPl680 device has three 8-bit Interrupt Vector registers, one dedicated to each of the three interrupt
sources. These three lnterruptVector registerswere illustratedearlierin the chapter. Following an interrupt
acknowledge, when the IAB c,ombinationappearsat BCI ,B,Cz, and BDIR,the contents of the Interrupt Vector
register for the highest priority active interruptwill be returnedto the CPU. Interruptacknowledgetiming is illustratedin Figure16-9.At the interruptservicelocationa Jump-to-Subroutine
instructionwill probablybe stored.
Sincethe Jump-to-Subroutine
objectcode is threewordslong.a maximumof 85 interruptscan be originedin the first
256 words of memory.This is more than sufficient.sinceonly eight CP1680deviceswith 24 interruptscan be supportedin a singledaisychain.

16-38

DATA SHEETS
\
I f nir sectioncontainsspecificelectricaland timing data for the followingdevices:

:ffitrs,-li:,*",

l
16-D1

c P l 6 0 0 . C P 16 0 0 A .C P 1 6 1 0
BUs TIHING OIAGRAH

ll

6z
s cf,naa00-0t5
<
OI'TPW

rF+
OI'TPUTFC+I TO
FETCHDISPUCEIIXT

.H

Pf,OGRAT
@UNER

EBCI-

lr Pttr
EEXI IXSTRUCNOI

CIRE+

00r'r clR

LEGID:,\\\\\\ m-Dt5 EUs

r\\\\\r g;161X6 DtREgItOr

TYPICAL IXSTRUCTION SEOUENCE

G...,.il.;

+-r Fi:r Frr F-ri1r

*=.! Frs_,Frst FTs!Frr--,

Ir

94v
OEY
I

lz

l;

ll
tl
tl
ll
il

I
I
I
I
I

lFla,

Frrs

g cl, tc? ,
80Il

-J

-1

rsYrci

tro

l-

EUS
c]{lrgtrc Ftfl
Flolr st rc

ourrul r@

lr#
tBF -

r-

i /

t a , -1

8rJ3
8u5'
ouTPurour.Gtic rhol
Y LtD ourryr rcot ro
FLOrrr00t

Flsz

k-+l
trpul
rrSrRuol0r
oR D rr
OPRTXO

BRANCH Oil EXTERNALCONOITIOX TNSTRUCTION

Data sheets on pages 16-D2 through 16-D6 reprinted by permission of General Instrument Corporation.

16-D2

cP1600
(CPl600)
ELECTRTCAL
CHARACTERTSTTCS
llerlmum Ratlngr'
voltags
Voo,Vcc,GNDandall otherinpuVoutput
with resgectto Vrr
-0.3v to +18.0v
. -55oCto +150'C
Temperature
Storage
.0"C to +70oC
OperatingTemperature

'E x c e e d i n g t h e s e r a t i n g s c o u l d c s u 3 o
prmanent dameg6 to thege devicos.
Functional ogoration at thes cgnditions is
not implied-ope16ting conditions aro
specified below.

Stendard Condluonr: (unless otherwise noted)

Voo=+1?V+5%,
7omA(typ) , 11omA(max.) Var= -3Vi10i6, o.2mA(typ), zmA(max.)
OperatingTemperature(Tr)=0oG to +70cC
Vcc=+SVts%,l2mA(typ) , 2smA(max.)
Ch.r.cl.dttlc
OC CHARACTERISTICS
Clock Inputr
Hig h
Low
Loglc lnputr
Low
High (All LinesexceptBDRDY)
High (Bus DataReadyLine
See Note)
Loglc Outputr
Hig h
Lo\ry(DataBus Lines DO-D15)
Low (Bus Control Lines,
BC1 ,BC2,BD I R)
Low (All Others)

;
)
:

Tvp"

trr

Syn

Hln

Vrxc
Vr lc

10.4
0

V oo

0.6

VrrVr r

0
2.4

0.65
Vcc

Vr xr

3.0

Vcc

VoH
Vor

2:

0.5

v
v

lor = 1@pA
lor = 1.6mA

lor = 2.0mA
lor-= 1.6mA

Vcc

0.45
0.45

Vor
Vol

Unltr

Condltlonr

AC CHARACTERISTICS

Clock Pub lnput , Ol or 62

PulseWidth

r 62, r O 2

Skew (d1, 62delayl

ns

120

I t 2, t z t

Olo'ci Period

tcy

0.3

Rise & FallTimes

Merler SYNC:
Delay from 6
DO-OI5 Bur Slgnrlr
Output clelaylrom Ol
(floatto output)
Outputdelaytrom 62
(output to tloat)
Input setuptime before 61
Input hold time after C1
Bur Control Slgnrlr
BC1,BC2.BDIR
Outputdelaylrom 01

tr, tt

15

ns

tms

30

ns

t ao

120

ns

BUSAK Output delay from 01

TCI Output delay from 61
TCI PulseWidth
EBCA output delay from BEXT
ingut
EBCA wait time tor EBCI input

tg r
tg r
te z

;
r0

ns
2.0

t au
tro
tTw

ns
ns
ns

t oc

120

n3

ns
ns

150
200
300

t oe
trr

lrS

n3

150
400

n3
ns

CAPACITAI{CE
61, 62 Clock Input capacitance
Input Crplclt nc.
DO-D1 5
AllOthe r
Output Crp.clt nc.
DO-OI5 in high impedancestate

,)

co1,cc,

20

30

pF

c lN

o
5

't2
10

pF
9F

Co

15

pF

1 TTL Load & 25 pF

II
I

TA = +25'C; Voo= t12V; Vcc= *5V;

Vrr = -3V: t0'l t CA= 120ns

"Typical valu6 are at +25oCand nomrnalvoltages.

NOTE:
The Bus Data ReaDY(BDRDY)line is samplodcturingtime period TSI after a BAR or ADAR bus control signal.BDROYmusl
9o low reguesting a wait 3tate 5() ns before the o;d of TS1 and remaih low lor 50 ns minimum. BDRDY mey 9o. high
asynchronously.In responseto BDRDY,the CPU ryillextendbus cyclesby aclctingsctditionelmicrocyclosup to a msximum
ol 40 psec durstion.

16-D3

cP 16 0 0 A
(C P 1 6 0 0A )
E LE CT RI CA Lc H A R A C T E R IS T IC S
Marlmum Rstlngt'
Yoltages
Voo,Vcc.GNDandall otherinpuvoutput
-0.3Vto +18.0V
rvilhrespectlo Vrr
. -55oCto+150'C
StorageTemperature
. 0oC to +70'C
Temperature
Operating

'E x c e e d i n g l h e s e r a t i n g s c o u l d c a u se
p e r m a n e n l d a m a g e t o t h e s e d e v i ce s.
Functional operation at thes conditions is
n o t i m p l i e d - o p e r a t i n g c o n d i t i o n s ar e
soecifiedbelow.

Strndrrd Condlilonr: (unlessotherwisenoted)

0.2mA(typ), 2mA(max.)
70mA(typ), 140mA(max.) Vss=-3V11oo,i.
Voo=+12V:5%,
OperatingTemperature(Te)=ooCto +70"C
12mA(typ), 25mA(max.)
Vcc=+5V+5%,
Chrrlclcrlttlc
DC CHARACTERISTICS
Clock Inputr
Hig h
Low
Loglc Inputr
Low
High (All Lines exceptBOROY)
High (8us Data ReadyLine
See Note)
Loglc Outputr
Hig h
Low (OataBus Lines DO-D15)
Low (BusControl Lines,
BC1.BCz. BDr R)
Low (All Others)

Tvp"

Mar

Unltr

10.4

V oo

0.6

v
v

Vr l
Vr x

0
2.4

0.65
Vcc

Vr *r

3.0

Vcc

Vo*
Vor.

2:

Sym

Mln

Vr xc
Vr r c

Vcc

0.5
0.45
0.45

Vor
Vou

Condlllonr

l ox = 1@pA
l or = 1.6mA
l or = 2.0mA
l or= 1.6mA

AC CHARACTERISTICS
Clock Pslrc lnputr, 61 or 02
PulseWidth
Skew(61, 62 delay)

62, r62
I r 2, t 2t

ns

oc

0
o.25

ns

Clobk Period

tcy

Rise& Fall Times

llerler SYNC:
Delaytrom d
DO-DI5 Bur Slgnrlr
Output delay lrom 61
(tloal to output)
Output delay lrom 62
{outputto tloat)
Inputsetuptime btored1
Inputhold time after 61
Bur Control Slgnrlr
BCI,BCaBOTR
Outputdelaylrom 61

tr, tf

15

ns

lms

30

ns

t eo

o<

ns

BUSAKOutput delay lrom 61

TCI Output delay trom 01
TCI PulseWiclth
EBCA output delay from BEXT
lnpul
EBCAwait time tor EBCI inout

t ar
t gr
tsa

<.v

tsu
tro
ttw

ns
ns
ns

t:"
10

loc

200

ns
ns
ns
ns

150
200
300

t oe
lr r

pS

150
400

ns
NS

1 TTL Load & 25 pF

lI

TA = +25'C: Voo= *12V; Vcc= +5V;

V a r =- 3 V ; t C 1 t 6 2 =1 2 0 n s

CAPACITAXCE
61, 62 Clock Input capacitance c61,c6/
lnput C.p.ctt nc.
DO-D15
All Other
Oulpul Crprcltrncc
OO-O15in high impedancestate
VD

"l

20

30

pF

6
t

12
10

pF
pF

15

pF

"Typical values are at +25oC and nomrnalvoltages.

NOTE:
The Bus Data ReaDY(BDRDY)line is sampledduring time perioctTSI after a BAR or ADAR bus control signal.BORDYmust
go low requestings wait state 50 ns bfore tfre eid ot TS1 and remain low lor 50 ns minimum. BDROY may 90 high
asynchronously.lh responseto BDRDY,the CPU witlxtend bus cycles by adclingadctitionalmicrocycl$ up to a marimum
of 40 rsec duration.

16-D4

cP 1 .6 1 0
(CP1610)
CHARACTERTSTTCS
ELECTRTCAL
Marlmum Rallngr'
voltages
Voo,Vcc,GNDandall otherinpuvoutput
-0.3Vto +18.0V
with respectto Vrr
. -55"Cto +150"C
StorageTemperature
.0"C to +70oC
Temperature
Operating

'E x c e e d i n g t h e s e r a t i n g s c o u l d c a u s g
p e r m s n o n l d a m a g e t o t h e s o c l e v i c o 3.
Functional opsration at thes conditions i3
not implied-opefating conditions at6
sgecitied below.

Standerd Condltlonr: (unless otherwise noted)

-lJ

1V+5%,70mA(typ). 11OmA(max.) Var=-3V11096,

0.2mA(typ), zmA(max.)
VDD=+I
OperatingTemperature(T^1=g'g to +70'C
12mA(typ), 25mA(max.)
Vcc=+5V15%,

=
)
:

Charactcrlrllc

OC CHARACTERISTICS
Clock Inputr
High
Low
I nput current
Loglc Inputr
Lorv
High (All LinesexceplEDRDY)
High (Bus DataReadyLine
See Note)

.t

3
't,

n
J
)l

Loglc Outputt
High
Low (DataBus Lines DO-O15)
Low (BusControlLines,
BC1 ,BC2,B Dt R)
Low (All Others)

3
!
n
3

sym

Ml n

Vr xc

10.0

"r'

Typ"

Mrr

Unltr

V oo

v
v

0.6
t5

mA

Condlllonr

Vnc = Voo -1

v
v

Vr r
Vr x

0
2.4

0.65

Vr xa

1n

Vcc

Vor
Vo r

,:

0.5

v
v

lox = 100rrA
lor = 1.6mA

0.45
0.45

v
v

lor = 2.0mA
lor = 1.6mA

I"
Vcc

Vol
Vor-

AC CHARACTERISTICS

.)

Clock Pulrc lnputr, dl ot 02

PulseWidth

r62, r62

250

Ske w (61 .d 2 delay )

r12 tzl

0
0.5

ns
ns

Clobk Period

tcy

Rise& FallTimes
Mr3ter SYNC:
Delaylrom 6
DO-O158ur Slgnrlr
Output delay trom dl
(tloatto output)
Outputdelaylrom 62
(outputto lloat)
Input setuptime before61
Input hold time after d1
Bur Control Slgnrlr
8C1.BC2.BDrR
Outputdelayfrom 61

tr, tt

2.0
15

tms

30

ns

t ao

200

ns

1 TTL Load & 25 pF

ns
ns
ns

II

BUSAK Output delsy trom 61

TCI Outputdelayfrom 61
TCI PulseWidth
EBCA output delay from BEXT
in pu t
EBCA wait time for EBCI ingut

lar
t ar
t aa

;
10

10

t oc
t gu
lr o
trw

150
M
300

t oe
t er

/rs
ns

26

ns

ns
ns
ns

150
400

ns
ns

TA = +25"C: Voo= +12V; Vcc= +5V;

Vrr = -3V: t61 t 02 = 120ns

CAPACITANCE
d1, 62 Clock Input capacitance co1,c6:
lnpul Crp.cltrnc!
c lN
DO-D1 5
All Othe r
Outpul C.p.cltrnc.
OO-O15in high ampedsncestale
Co

20

30

pF

12
10

9F
pF

15

pF

"Typical valuesare at +25'C and nomtnatvoltagos.

NOTE:
The Bus OataReaDY(BORDY)lino is sampledduring time period TSI sfter I BAR or ADAR bus control signal.BDRDYmust
go low requesting I wait state 50 ns btoro tne end of TSI and remain low for 5O ns minamum.BORDY may 90 high
asynchronously.tn responsto 8ORDY,the CPU willextend bus cyclas by acldingadclitionalmicrocyclesup to a maximum
of 40 ssec cruralion.

16-D5

roB1680
E LE CT RI CA LC H A R A C T E R T S T IC S
M ax im umRat l n g s '
V99 and Vsg and all other input/outoutvoltages
........
with respe ctto G ND. .
. - 0 . 3 v t o +1 8 V
. . . . . - 5 5 o c t o +1 5 0 " C
Sto rag eTemg er at ur e
.......0oCto-70oC
Ope ratin gTemp er at ur e

'E x c e e d i n g t h e s e r a t i n g s co u l C ca u se
permanentdamage.Functionatoperationof
t h i s d e v r c e a t t h e s e c o n d i ti o n s i s n o t
implied-operating ranges are specitied
Derow.

Sta nd ard Co nd lt ions ( unles s ot her wis e not ed)

All voltagesreferencedto GND
VDo: * 12 V =5 0/b
+$ \rr :!o r'o

V66:

Ope ratin gTe mper at ur e( Te) = 0' C t o t 70' C

Sym b o l

Characterlgllc

Ml n

Tvp"

Mar

Unll

Condlllon

O C C H A R A C T ERIST ICS
Clock Input:

Logic Inputs:

Hig h

Vinc

Low

v itc

Voo
0

Hig h

L o g i c O u t p u t s:

Vcc

z.q

Low

Vi,

Hig h

voh

Low

Vot

0
2.4

lon = 100pA
l o ,= 1 . 6 m A

Vcc

A C C H A R A C TERIST ICS
Clock Inputr

Ctocxperiod

eRi

lPc

4.0

0.4

,:

Clo ck w idt h
Rise & F all t im es

tcr,tct

10

ps
ns
ns

CAPACITAN CE1To= 25' 6,

Voo = + 12V,
.
Vcc = *5V)
Input Capacitance:D0-D7
All others
Ou tpu t Cag ac it anc e:

12
10

V,n = 0V

pF

V'"= ov

1<

cor,

pF

' - T y p i c a l v a l u e s a r e a t *2 5 o C a n d n o m in a l vo lta ges

TIMING

D I AGRAM
1 T Si1

r_l
' T S2 1

lT S3 p

lTS cq

tTS l t

1TS 31
'TS 21

l TS al

tTS l t

1TS 21

|---.1
'rS3p

tlc --------------tl

cK1'

-r
EO|F
a.t

q.r

r/*

--'tJ

Noter CK 1 ' not drawn to scale

toc F-

C I R C U I T D E S C RIPT ION
T h i s c i r c u r l r s d e sid n e d to p r o vr d e a ll th e d a ta b u tte ri ng and
c o n t r o l t u n c t , c n s r e q u ir e cj wh e n In te r ta cin g th e Se ti es l 600
M r c r o p r o c e s s c r S y sle m lo a sr m p le p e r a p h e r adl e vice. Oata i s
t r a n s l e r r e d l o a n d lr o m lh e p e r ip h e r a lo n 1 6 b id ir e clio nall l nes.
e a c h o f w h r c n c a n b e co n sid e r e d to b e a n in p u l o r o u lput. The
t r a n s t e r o t I n l o r m atio n with th e CP1 6 0 0r sa cco m g lish e dvraan 8b i t h i g h w a y , t h e 1 6 - b r tsb e tn g tr a n ste r r e da s two 8 - b it b ytes.the
r e g i s t e r a d d r e s s e s a r e a ssr g n e d CP1 6 0 0 m e m o r y lo cati ons.as
l o l l o w s ( N i s a n a r b r tr a r y sta r tin g a d d r e ss) :

R egl !l er A ddre3r
N
N .1
N '2
N *3
N *4
N .5
N .6
N *7

16-D6

Oercrlpllon
C ontrol R egtster
D ata R egi ster Low Order 8-bi ts
Oata R egi ster H i gh Order 8-bi ts
Ti mer Low Order 8-bi ts
Trmer H rgh Order 8-bi ts
P ertpheralInterrupt A ddress V ector
Ti mer Interrupt A ddress V ector
Error Inlerruol Actdress Vector