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[Abstract] Previously, we proposed n'- p+ double-gate SO1 MOSFETs, and fabricated this device, and
demonstrated high-speed, low-power performance with a gate length
of 0.2 pm [ 11. In this paper, we have derived
a threshold voltage model V& for short channel devices to predict how far this device can be scaled. Using this model,
which agrees with numerical data, we evaluated V~ lowering AV& with decreasing the gate length LG, and showed
that we can design a 0.05 W-LG device with A V of
~ 25 mV and an S-swing of 65 mvldecade.
[Theory] In n+- p+ double-gate So1MOSFETs (Fig.
l), both gate oxide thicknesses are the same and the
same gate voltage VG is applied to the both gates. The
channel doping concentration N~ is as low as 1015 cm-3
independent of Lc,.
- The threshold voltage for long
channel n+- p+ double-gate SO1 MOSFETs, Vtw, is
given by [2]
where
is the gate oxide thickness, tSi is the SO1
thickness, $sth is the surface potential for long channel
devices at VG = VthL, V F B ~is the flatband voltage
associated with n+ gate, V F B is
~ the flatband voltage
associated with pf gate, and AVm = Vmp - Vmn.
Solving a two-dimensional potential distribution in
the channel region with a method similar to that
described in [3], we found that the minimum surface
potential, $sm,is given by
+2 4 m e - g
qsm= V, - V, - &AVm
6t0x + tsi
[Results and Discussion] Analytical v t h and sswing models agree well with numerical data (Fig. 2).
The short channel effect is characterized by the function
of exp(-L&h). Therefore, the device should be designed
1
2qs+V,
-52
Jme
''
95CH35763
69
References
[ l ] T. Tanaka, et al., IEEE Trans. Electron
Device Letter, EDL-15, p. 386, 1994.
[2] K. Suzuki,et al., SSDM, p. 274-276,1994.
[3] K. Suzuki, et al., IEEE Trans. Electron
Devices, ED-40, p. 2326, 1993.
[4] G. Baccarani, et al., IEEE Trans. Electron
Devices, ED-31, p. 452, 1984.
[5] P. J. Wright, et al., IEEE Trans. Electron
Devices, ED-37, p. 1884, 1990.
VG
I I
n'
n
SI
POlyslllCon
n+
- Metal
SI02
0.3
to.
= 4 nm
3 1OOr
2 90-
>
E
m 80E
-V,
Ec -0.1
0
0
I
'
E
0
c
= 1.0 V (Analytical)
V, = 0.05 V (Numerical)
V, = 1.0 V (Numerical)
-0.21 .
0.0
"
1.0
0.5
--V,
-V,
'iE
c
Q)
v, = v,,, - 0.2 v
a#
tsl=40nm
= 4 nm
to.
ts,=20nm
ts I = 20
0
0
= 0.05 V (Analytical)
= 1.0 V (Analytical)
V, = 0.05 V (Numerical)
V, = 1.0 V (Numerical)
706050
0.0
'
'
0.5
Gate length (pm)
1.0
(b)
Fig. 2. Comparison between numerical and analytical data. Numerical data are calculated with a two-dimensional
(b) Dependence of subthreshold swing on LG.
device simulator. (a) Dependence of threshold voltage on h,.
50
40
--
2 5
30
-1
>=
2
"x
0
b
1 >a
20
)
.
10
,hL
...........
0.0
0.1
0.2
0.3
0.4
Gate length (pm)
0
0.5