Pageiii

IntroductiontoCMOSOPAMPsandComparators
RoubikGregorian

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1.OperationalamplifiersDesignandconstruction.2.Comparator
circuitsDesignandconstruction.3.Metaloxidesemiconductors,
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Tomywife,Agnes
Andourchildren,ArisandTalin

Pagevii

Contents
Preface

ix

1
Introduction

1.1ClassificationofSignalProcessingTechniques

1.2ExamplesofApplicationsofOpAmpsandComparatorsinAnalog
MOSCircuits

Problems

16

References

16

2
MOSDevicesasCircuitElements

17

2.1Semiconductors

17

2.2MOSTransistors

21

2.3MOSTransistorTypes:BodyEffect

27

2.4SmallSignalOperationandEquivalentCircuitofMOSFETTransistors

30

2.5WeakInversion

39

2.6ImpactIonization

40

2.7NoiseinMOSFETS

41

2.8CMOSProcess

44

Problems

45

References

47

Pageviii

3
BasicAnalogCMOSSubcircuits
3.1BiasCircuitsinMOSTechnology

48

3.2MOSCurrentMirrorsandCurrentSources

55

3.3MOSGainStages

63

3.4MOSSourceFollowers

74

3.5MOSDifferentialAmplifiers

77

3.6FrequencyResponseofMOSAmplifierStages

84

Problems

92

References

94

4
CMOSOperationalAmplifiers

95

4.1OperationalAmplifiers

95

4.2SingleStageOperationalAmplifiers

100

4.3TwoStageOperationalAmplifiers

106

4.4StabilityandCompensationofCMOSAmplifiers

112

4.5DynamicRangeofCMOSOpAmps

126

4.6FrequencyResponse,TransientResponse,andSlewRateof
CompensatedCMOSOpAmps

132

4.7NoisePerformanceofCMOSOpAmps

137

4.8FullyDifferentialOpAmps

140

4.9CMOSOutputStages

149

4.10OpAmpswithRailtoRailInputCommonModeRange

164

Problems

170

References

173

5
Comparators

175

5.1CircuitModelingofaComparator

175

5.2SingleEndedAutoZeroingComparators

177

5.3DifferentialComparators

182

5.4RegenerativeComparators(SchmittTriggers)

192

5.5FullyDifferentialComparators

198

5.6Latches

205

Problems

212

References

213

6
DigitaltoAnalogConverters

48

214

6.1DigitaltoAnalogConversion:BasicPrinciples

214

6.2VoltageModeD/AConverterStages

218

Pageix

6.3ChargeModeD/AConverterStages

231

6.4HybridD/AConverterStages

234

6.5CurrentModeD/AConverterStages

238

6.6SegmentedCurrentModeD/AConverterStages

244

Problems

252

References

254

7
AnalogtoDigitalConverters
7.1AnalogtoDigitalConversion:BasicPrinciples

255

7.2FlashA/DConverters

263

7.3InterpolatingFlashA/DConverters

270

7.4TwoStepA/DConverters

273

7.5SuccessiveApproximationA/DConverters

282

7.6CountingandTrackingA/DConverters

294

7.7IntegratingA/DConverters

295

Problems

300

References

301

8
PracticalConsiderationsandDesignExamples

303

8.1PracticalConsiderationsinCMOSOpAmpDesign

303

8.2OpAmpDesignTechniquesandExamples

316

8.3ComparatorDesignTechniquesandExamples

349

Problems

355

References

355

Index

255

357

Pagexi

Preface
Operationalamplifiers(opamps)andcomparatorsaretwoofthemostintricate,andinmanywaysthemostimportant,buildingblocksofananalogcircuit.These
componentsareusedinsuchdevicesasswitchedcapacitorfilters,analogtodigital(A/D)anddigitaltoanalog(D/A)converters,amplifiers,modulators,rectifiers,
peakdetectors,andsoon.Theperformanceofopampsandcomparatorsusuallylimitsthehighfrequencyapplicationanddynamicrangeoftheoverallcircuit.
Withoutathoroughunderstandingoftheoperationandbasiclimitationofthesecomponents,thecircuitdesignercannotdetermineorevenpredicttheactualresponse
oftheoverallsystem.Hencethisbookgivesafairlydetailedexplanationoftheoverallconfigurationsandperformancelimitationsofopampsandcomparators
exclusivelyinCMOStechnology.Whilethescalingpropertiesoftheverylargescaleintegration(VLSI)processeshaveresultedindenserandhigherperformance
digitalcircuits,theyhavealsochangedthedesigntechniquesusedforCMOSanalogcircuits.Therefore,themainpurposeofthesediscussionsistoillustratethemost
importantprinciplesunderlyingthespecificcircuitsanddesignprocedures.Nevertheless,thetreatmentisdetailedenoughtoenablethereadertodesignhigh
performanceCMOSopampsandcomparatorssuitableformostanalogcircuitapplications.
Themainemphasisofthisbookisonphysicaloperationanddesignprocess.IthasbeenwrittenasaunifiedtextdealingwiththeanalysisanddesignofCMOSop
ampsandcomparators.Itisintendedforclassroomadoptiontobeusedasaseniororgraduateleveltextintheelectricalengineeringcurriculumofuniversitiesand
alsoastrainingandreferencematerialforindustrialcircuitdesigners.Toincreasetheusefulnessofthebookasatextforclassroomteaching,numerousproblemsare
includedattheendofeachchaptertheseproblemsmaybeuseforhomeworkassignments.Toenhanceitsvalueasadesignreference,tablesandnumericaldesign
examplesareincludedtoclarifythestepbystepprocessesinvolved.Thefirsttwo

Pagexii

chaptersprovideaconcise,basiclevel,and(Ihope)cleardescriptionofanalogMOSintegratedcircuitsandthenecessarybackgroundinsemiconductordevice
physics.TheremainderofthebookisdevotedtothedesignofCMOSopampsandcomparatorsandtothepracticalproblemsencounteredandtheirsolutions.The
bookalsoincludestwointroductorychaptersontheapplicationsofopampsandcomparatorsinA/DandD/Aconverters.Foramoredetaileddiscussiononthe
importantsubjectofdataconverters,readersarereferredtothePrinciplesofDataConversionSystemDesignbyBehzadRezavi,andDeltaSigmaData
Converters:Theory,DesignandSimulationbyStevenR.Norsworthy,RichardSchreier,andGaborC.Temes.
ThisbookisbasedinpartonapreviousbookIcoauthoredwithGaborC.Temes,titledAnalogMOSIntegratedCircuitsforSignalProcessing.Theoriginal
materialhasbeenaugmentedbythelatestdevelopmentsintheareaofanalogMOSintegratedcircuits,inparticularopampsandcomparators.Mostofthematerial
andconceptsoriginatedfromthepublicationscitedattheendofeachchapteraswellasfrommanypracticingengineerswhoworkedwithmeovertheyears.
Sincetheoriginalbookevolvedfromasetoflecturenoteswrittenforshortcourses,theorganizationofthematerialwasthereforeinfluencedbytheneedtomakethe
presentationsuitableforaudiencesofwidelyvaryingbackgrounds.HenceItriedtomakethebookreasonablyselfcontained,andthepresentationisatthesimplest
levelaffordedbythetopicsdiscussed.Onlyalimitedamountofpreparationwasassumedonthepartofthereader:mathematicsonthejuniorlevel,andoneortwo
introductorylevelcoursesinelectronicsandsemiconductorphysicsaretheminimumrequirements.
Thebookcontainseightchapters.Chapter1providesabasicintroductiontodigitalandanalogsignalprocessing,followedbyseveralrepresentativeexamplesof
circuitsandsystemsutilizingCMOSopampsandcomparators.Thismaterialcanbecoveredinonelecture(twohourlecturesareassumedhereandthroughoutthe
preface).
InChapter2thephysicsofMOSdevicesisdescribedbrieflyandlinearizedmodelsofMOSFETs,aswellasMOScapacitorsandswitchesarediscussed.The
technologyusedtofabricateCMOSdevicesisalsodiscussedbriefly.Onceagain,dependingonthebackgroundoftheaudience,twoorthreelecturesshouldsuffice
tocoverthecontentofthischapter.
Chapter3coverssomeofthebasicsubcircuitscommonlyutilizedinanalogMOSintegratedcircuits.Thesesubcircuitsaretypicallycombinedtosynthesizeamore
complexcircuitfunction.Completecoverageofalltopicsofthischapterrequiresaboutthreelectures.
InChapter4circuitdesigntechniquesforrealizingCMOSoperationalamplifiersarediscussed.Themostcommoncircuitconfigurations,aswellastheirdesignand
limitations,areincluded.Fullcoverageofalltopicsinthischapterrequiresaboutfourlectures.
InChapter5theprinciplesofCMOScomparatordesignarediscussed.Firstthesingleendedautozeroingcomparatorisexamined,followedbysimpleandmul

Pagexiii

tistagedifferentialcomparators,regenerativecomparators,andfullydifferentialcomparators.Twolecturesshouldbesufficientforcompletecoverageofthischapter.
Chapters6and7,whichcoverCMOSdigitaltoanalogandanalogtodigitalconverters,serveaspracticalapplicationexamplesofopampsandcomparators.The
fundamentalsandperformancemetricsofthedataconvertersarepresentedfirst,followedbyadiscussionofpopulararchitecturesofNyquistrateconverters.Digital
toanalogconvertersaredividedintovoltage,charge,andcurrentscalingtypes.Analogtodigitalconvertersincludehighspeedflash,mediumspeedsuccessive
approximation,andlowspeedserialconverters.Completecoverageofalltopicsmayrequirethreetofourlectures.
InChapter8thedesignprinciplespresentedinChapter4and5areemployedtoworkoutseveraldesignexamplestoacquaintthereaderwiththeproblemsand
tradeoffsinvolvedinopampandcomparatordesigns.Practicalconsiderationssuchasdcbiasing,systematicoffsetvoltage,andpowersupplynoisearediscussedin
somedetail.AlltopicsinthischaptercanbecoveredinthreelecturesifthedetaileddiscussioninSections8.2and8.3iscondensed,thematerialcanbepresentedin
twolectures.
Thus,dependingonthedepthofthepresentation,fullcoverageofallmaterialinthebookmayrequireasmanyas20twohourlecturesorasfewas16.
Iamgratefultomanypeoplewhohavehelpedmedirectlyorindirectlyintheelaborateandsometimesoverwhelmingtaskofpublishingthisbook.Inparticular,I
wouldliketothankmycolleaguesDrs.S.C.Fan,B.Fotouhi,B.Ghaderi,andG.C.Temes,whoreadandcriticizedversionsofthemanuscript.Theircommentshave
beenmosthelpfulandaregreatlyappreciated.MostofthedifficulttypingtaskwasdonebyMs.W.IrwinandD.Baker.Iamgratefulfortheirexcellentand
painstakinghelp.Last,butnotleast,Iwouldliketoexpressmygratitudetomyfamilyforgraciouslysufferingneglectduringthewritingofthisbook.Withouttheir
understandingandsupportthisworkwouldnothavebeenpossible.
ROUBIKGREGORIAN
SARATOGA,CALIFORNIA
JANUARY1999

Page1

Chapter1
Introduction
Operationalamplifiers(opamps)andcomparatorsaretwoofthemostimportantbuildingblocksforanalogsignalprocessing.Opampsandafewpassive
componentscanbeusedtorealizesuchimportantfunctionsassummingandinvertingamplifiers,integrators,andbuffers.Thecombinationofthesefunctionsand
comparatorscanresultinmanycomplexfunctions,suchashighorderfilters,signalamplifiers,analogtodigital(A/D)anddigitaltoanalog(D/A)converters,input
andoutputsignalbuffers,andmanymore.Makingtheopampandcomparatorfasterhasalwaysbeenoneofthegoalsofanalogdesigners.Inthischapterthebasic
conceptofdigitalandanalogsignalprocessingisintroduced.Thenathirdcategoryofsignalprocessing,thesampleddataanalogtechnique,whichisinbetweenthe
twomainclassifications,isdescribed.Finally,afewrepresentativeexamplesaregivenofcircuitsandsystemsutilizingCMOSopampsandcomparators,toillustrate
thegreatpotentialofthesecomponentsaspartofanMOSLSIchip.
1.1
ClassificationofSignalProcessingTechniques[14]
Electricalsignalprocessorsareusuallydividedintotwocategories:analoganddigitalsystems.Ananalogsystemcarriessignalsintheformofvoltages,currents,
charges,andsoon,whicharecontinuousfunctionsofthecontinuoustimevariable.Sometypicalexamplesofanalogsignalprocessorsareaudioamplifiers,passive
oractiveRCfilters,andsoon.Bycontrast,inadigitalsystemeachsignalisrepresentedbyasequenceofnumbers.Sincethesenumberscancontainonlyafinite
numberofdigits(typically,codedintheformofbinarydigits,orbits)theycanonlytakeondiscretevalues.Also,thesenumbersarethesampledvaluesofthesignal,
takenatdiscretetimeinstances.Thusboththedependentandindependentvariablesofa

Page2

digitalsignalarediscrete.Sincetheprocessingofthedigitalbitsisusuallyperformedsynchronously,atimingorclockcircuitisanimportantpartofthedigitalsystem.
Thetimingprovidesoneormoreclocksignals,eachcontainingaccuratelytimedpulsesthatoperateorsynchronizetheoperationofthecomponentsofthesystem.
Typicalexamplesofdigitalsystemsareageneralpurposedigitalcomputeroraspecialpurposedigitalsignalprocessordedicatedto(say)calculatingtheFourier
transformofasignalviathefastFouriertransform(FFT),oradigitalfilterusedinspeechanalysis,andsoon.
Bycontrast,analogsignalprocessingcircuitsutilizeopamps,comparators,resistors,capacitors,andswitchestoperformsuchfunctionsasfilters,amplifiers,rectifiers,
andmanymore.Tounderstandthebasicconceptsofthemostcommonlyusedconfigurationsofananalogcircuit,considerthesimpleanalogtransferfunction

ItiseasytoverifythattheRLCcircuitshowninFig.1.1acanrealizethisfunction(Problem1.1).Althoughthiscircuitiseasytodesign,build,andtest,thepresenceof
theinductorinthecircuitmakesitsfabricationinintegratedformimpractical.Infact,forlowfrequencyapplications,thiscircuitmaywellrequireaverylargevalued,
andhencebulky,inductorandcapacitor.Toovercomethisproblem,thedesignermaydecidetorealizethedesiredtransferfunctionusinganactiveRCcircuit.Itcan
readilybeshownthatthecircuitinFig.1.1b,whichutilizesthreeoperationalamplifiers,iscapableofprovidingthetransferfunctionspecifiedin

Figure1.1
Secondorderfilterrealization:(a)passivecircuit(b)activeRCcircuit.

Page3

Figure1.2
Switchedcapacitorrealizationofaresistivebranch.

Eq.(1.1).Thiscircuitneedsnoinductorsandmayberealizedwithsmalldiscretecomponentsforawidevarietyofspecifications(Problem1.2).Itturnsout,however,
thatwhileintegrationofthiscircuitonabipolarchipis,inprinciple,feasible(sincetheamplifiers,resistors,andcapacitorsneededcanallbeintegrated),therearesome
majorpracticalobstaclestointegration.TheseincludetheverylargechipareaneededbytheRCcomponents,aswellasthestringentaccuracyandstability
requirementsfortheseelements.Theserequirementscannotreadilybesatisfiedbyintegratedcomponents,sinceneitherthefabricatedvaluesnorthetemperature
inducedvariationsoftheresistiveandcapacitiveelementstrackeachother.Theresultingpolezerovariationsaretoolargeformostapplications.
Priortomid1970s,analogcircuitssuchastheoneshowninFig.1.1wereimplementedusingintegratedbipolaropampsanddiscretepassivecomponents.Inthe
1970stwodevelopmentsmadeitpossibletofullyintegrateanalogcircuitsinmetaloxidesemiconductor(MOS)technology.Thefirstdevelopmentwastheemergence
ofatechniquecalledswitchedcapacitor(SC)circuits[6],whichisaneffectivestrategyforsolvingboththeareaandthematchingproblemsbyreplacingeachresistor
inthecircuitbythecombinationofacapacitorandafewswitches.ConsiderthebranchesshowninFig.1.2.Here,thefourswitchesS1,S2,S3,andS4openandclose
periodically,ataratewhichismuchfasterthanthatofthevariationsoftheterminalvoltagev Aandv B.SwitchesS1andS4operatesynchronouslywitheachotherbutin
oppositephasewithS2andS3.ThuswhenS2andS3areclosed,S1andS4areopen,andviceversa.NowwhenS2andS3close,Cisdischarged.WhenS2andS3open,
S1andS4close,andCisrechargedtothevoltagev C=v Av B.Thiscausesachargeq=C(v Av B)toflowthroughthebranchofFig.1.2.Next,Cisagain
dischargedbyS2andS3,andsoon.IfthiscycleisrepeatedeveryTseconds(whereTistheswitchingperiodorclockperiod),theaveragecurrentthroughthe
branchisthen

Thusiavisproportionaltothebranchvoltagev Av B.Similarly,forabranchcontainingaresistorR,thebranchcurrentisi=(1/R)(v Av B).Thustheaveragecurrent

flowinginthesetwobranchesarethesameiftherelationR=T/Cholds.

Page4

Figure1.3
Secondorderswitchedcapacitorfiltersection.

Physically,theswitchestransformthecapacitorC,anondissipativememoriedelement,intoadissipativememoryless(i.e.,resistive)one.
ItisplausiblethereforethatthebranchofFig.1.2canbeusedtoreplaceallresistorsinthecircuitofFig.1.1b.Theresultingstage[3]isshowninFig.1.3.Inthis
circuit,switchesthatbelongtodifferent''resistors"butperformidenticaltaskshavebeencombined.Furthermore,thesecondoperationalamplifier(opamp)inFig.
1.1b,whichactedmerelyasaphaseinverter,hasbeeneliminated.Thiswaspossiblesincebysimplychangingthephasingoftwooftheswitchesassociatedwith
capacitorC3,therequiredphaseinversioncouldbeaccomplishedwithoutanopamp.
AsFig.1.3illustrates,thetransformedcircuitcontainsonlycapacitors,switches,andopamps.Amajoradvantageofthisnewarrangementisthatnowalltime
constants,previouslydeterminedbythepoorlycontrolledRCproducts,willbegivenbyexpressionsoftheform(T/C1)C2=T(C2/C1).HeretheclockperiodTis
usuallydeterminedbyaquartzcrystalcontrolledclockcircuitandhenceisveryaccurateandstable.TheotherfactorofthetimeconstantisC2/C1,thatis,theratioof
twoonchipMOScapacitances.Usingsomesimplerulesinthelayoutoftheseelements,itispossibletoobtainanaccuracyandstabilityontheorderof0.1%forthis
ratio.Theresultingoverallaccuracyisatleast100timesbetterthanwhatcanbeachievedwithanonchipresistorandcapacitorfortheRCtimeconstant.
Adramaticimprovementisalsoachievableforthearearequiredbythepassiveelements.Toachieveatimeconstantintheaudiofrequencyrange(say10krad/s),
evenwithalarge(10pF)capacitor,aresistanceof10M isrequired.Sucharesistorwilloccupyanareaofabout106m2,whichisprohibitivelylargeitisnearly
10%oftheareaofanaveragechip.Bycontrast,foratypicalclockperiodof10s,thecapacitanceoftheswitchedcapacitorrealizinga10M resistorisC=T/R
=105/107=1012F=1pF.Thearearequiredrealizingthiscapacitanceisabout2500m2,only0.25%ofthatneededbytheresistorthatitreplaces.

Page5

TheseconddevelopmentthatmadetherealizationofthefullyintegratedanalogMOScircuitspossiblewasthedesignoftheMOSopamp.Perhapsthemost
generallyusefulanalogcircuitfunctionisthatoftheoperationalamplifier.Priortoabout1977,thereexistedaclearseparationofthebipolarandMOStechnologies,
accordingtothefunctionrequired[1,5].MOStechnology,withitssuperiordevicedensity,wasusedmostlyfordigitallogicandmemoryapplications,whileall
requiredanalogfunctions(suchasamplification,filtering,anddataconversion)wereperformedusingbipolarintegratedcircuits,suchasbipolaropamps.Sincethat
time,however,rapidprogressmadeinMOSfabricationtechniquesmadeitpossibletomanufacturemuchmorecomplexandflexiblechips.Inaddition,new
developmentsoccurredincommunicationtechnology(suchasdigitaltelephony,datatransmissionviatelephonelines,adaptivecommunicationchannels,etc.)which
requiredanaloganddigitalsignalprocessingcircuitryinthesamefunctionalblocks.Theanalogfunctionsmostoftenneededarefiltering(forantialiasing,smoothing,
bandseparation,etc.),amplification,sampleandholdoperations,voltagecomparison,andthegenerationaswellasprecisescalingofvoltagesandcurrentsfordata
conversion.Theseparationoftheseanalogfunctionsfromthedigitalonesmerelybecauseofthedifferentfabricationtechnologiesusedisundesirable,sinceitincreases
boththepackagingcostsandthespacerequirementsandalso,duetotheadditionalinterconnectionsrequired,degradestheperformance.Hencetherewasstrong
motivationtodevelopnovelMOScircuits,whichcanperformtheseanalogfunctionsandwhichcanalsosharetheareaonthesamechipwiththedigitalcircuitry.
Comparedwithbipolartechnology,MOStechnologyhasbothadvantagesanddisadvantages.MOSdevicehasextremelyhighimpedanceatitsinput(gate)terminal,
whichenablesittosensethevoltageacrossacapacitorwithoutdischargingit.Also,thereisnoinherentoffsetvoltageacrosstheMOSdevicewhenitisusedasa
chargeswitch.Furthermore,highqualitycapacitorscanbefabricatedreliablyonanMOSchip.Thesefeaturesmaketherealizationofsuchcircuitsasprecision
sampleandholdstagesfeasibleonanMOSchip[1].Thisisusuallynotpossibleinbipolartechnology.
Onthenegativeside,thetransconductanceofMOStransistorsisinherentlylowerthanthatofbipolartransistors.Atypicaltransconductancevalueforamoderate
sizedMOSdeviceisaround2.5mA/Vforabipolartransistor,itmaybeabout50timeslarger.ThisleadstoahigheroffsetvoltageforanMOSamplifierthanfora
bipolaramplifier.(Atthesametime,however,theinputcapacitanceoftheMOStransistoristypicallymuchsmallerthanthatofabipolartransistor.)Also,thenoise
generatedinanMOSdeviceismuchhigher,especiallyatlowfrequencies,thaninabipolartransistor.Theconclusionisthatthebehaviorofanamplifierrealizedonan
MOSchiptendstobeinferiortoanequivalentbipolarrealizationintermsofoffsetvoltage,noise,anddynamicrange.However,itcanhavemuchhigherinput
impedancethanthatofitsbipolarcounterpart.
Asaresultoftheseproperties,thelargestuseoftheMOSopampisexpectedtobeaspartofanMOSLSI(largescaleintegration)chip.Herethedesignoftheop
ampcantakeadvantageoftheimportantperformancespecificationsthatareneeded.Theloadingoftheopampisoftenverylightandusuallyonlyasmall

Page6

valuedcapacitorhastobedrivenbytheseopamps.Switchedcapacitorcircuitsfallespeciallyintothiscategory,whereelementvalueaccuracyisimportantbutthe
signalfrequencyisnottoohighandthedynamicrangerequiredisnotexcessive.Voiceandaudiofrequencyfilteringanddataconversionareinthiscategoryand
representthebulkofthepastapplications.
InadditiontofrequencyselectiveswitchedcapacitorfilteringintroducedinFig.1.3,whichhasbeenthemostcommonapplicationofMOSopamps,therearemany
otherfunctionsforwhichopampsandcomparatorscanbeused.Theseincludeanalogtodigital(A/D)anddigitaltoanalog(D/A)dataconversion,programmable
gainamplificationforAGCandotherapplications,peakdetection,rectification,zerocrossingdetection,andsoon.Theyhavealsobeenusedextensivelyinlarge
mixedsignalanalog/digitalsystemssuchasvoicecodecs,highspeeddatacommunicationmoderns,audiocodecs,andspeechprocessors.Thisrangewillexpand
continuouslyasthequality(bandwidth,dynamicrange,powerconsumption,etc.)ofthecomponents,especiallyopampsandcomparators,improves.
1.2
ExamplesofApplicationsofOPAMPsandComparatorsinAnalogMOSCircuits
Inthissection,afewselectedexamplesofpracticalanalogMOScircuitsaregivenwhereCMOSopampsandcomparatorsareusedextensively.Ofcourse,the
readershouldnotexpecttounderstandthedetailsofthesesystemsatthisstage.However,thediagramsmaygiveanideaofthepotentialsofthesecomponentsin
analogsignalprocessing.
Asmentionedearlier,oneofthemostimportantapplicationsofCMOSopampsisinswitchedcapacitorfilters.Figure1.4ashowsthecircuitdiagramofaseventh
orderswitchedcapacitorfilter.ItsmeasuredfrequencyresponseisshowninFig.1.4b.Themeasuredpassbandvariationforthedeviceislessthan0.06dB.This
representsasuperiorperformance,whichcouldnothavebeenachievedwithoutextensivetrimmingusinganyotherfiltertechnology.
AnobviousapplicationofaCMOSopampistherealizationofchargemodedigitaltoanalogconverters(DAC).Itcanbeobtainedbycombiningaprogrammable
capacitorarrayandanoffsetfreeswitchedcapacitorgainstage.AnexampleofanNbitchargemodeDACisshowninFig.1.5,whereVrefisatemperature
stabilizedconstantreferencevoltage.TheoutputoftheDACistheproductofthereferencevoltageandthebinarycodeddigitalsignal(b1,b2,b3,...,bN).InChapter
6thedesignofsuchcircuitsisdiscussedinsomedetail.
Modulators,rectifiers,andpeakdetectors[6]belongtoanimportantclassofnonlinearcircuits,whichcanbeimplementedwithacombinationofopampsand
comparators.Inanamplitudemodulatortheamplitudeofasignalx(t)(usuallycalledthecarrier)isvaried(modulated)bym(t),themodulatingsignal.Hencethe
outputsignaly(t)istheproductofx(t)andm(t),ory(t)=x(t)m(t).Aperiodiccarriersignal,whichisreadilygeneratedfromastableclocksource,isasquarewave
alternatingbetweentwoequalvaluesV.Aneasywaytoperformmodulationwith

Page7

Figure1.4
(a)Circuitdiagram(b)measuredfrequencyresponseofaseventhorderswitchedcapacitorlowpassfilter.

Page8

Figure1.5
Multiplyingdigitaltoanalogconverter.

Page9

Figure1.6
Switchedcapacitormodulatorwithtwoclocksignals.

asquarewavecarrieristoswitchthepolarityoftheinputsignalm(t)periodically.Astrayinsensitiveswitchedcapacitormodulatorcircuitwhichperformsaccording
tothisprincipleisshowninFig.1.6.Theclockphases 1and 2areoperatedatthefastclockrate c,whilethephase achangesattheslowcarrierfrequencyrate
.Normally, cismuchlarger(byafactorof30ormore)than ca.
ca
Anothernonlinearcircuitisafullwaverectifierthatconvertsaninputsignalv in(t)toitsabsolutevalue|v in(t)|.Asimplewayofimplementingaswitchedcapacitorfull
waverectifieristoaddacomparatortoanamplitudemodulator.ThecircuitofaswitchedcapacitorfullwaverectifierbasedonthemodulatorofFig.1.6isshownin
Fig.1.7a.HereAissetto"1"ifv in>0andto"0"ifv in<0,whileBissetto bythecomparatorandthelatchthatfollowsiteachtime 1,goeshigh.ThesignalsA
andBthensetthepolarityofthetransferfunctionsothatitinvertsthenegativeinputsignals,butnotpositiveones.Figure1.7bshowsanautozeroingcomparator,
whichisdiscussedindetailinChapter5.
Apeakdetectorisacircuitwhoseoutputholdsthelargestpositive(or,ifsospecified,negative)voltageearlierattainedbytheinputsignal.AnMOSpeakdetectoris
showninFig.1.8.Theopampactsasacomparator,withv out=Vmaxandv inasitsinputs.Ifv in>Vmax,theopampoutputgoeshighandM1conducts,chargingCuntil
v out v inisreached.Ifv in<Vmax,theopampoutputislow,M1iscutoff,andv out=VmaxisheldbyC.
OneofthemostimportantapplicationsofthecomparatorsisinA/Dconverters.AsuccessiveapproximationA/DconverterisonetypeofmediumspeedNyquist
rateconverterthatcanberealizedusingaprogrammablecapacitorarray(PCA)andavoltagecomparator.A5bitconverterisshowninFig.1.9.Forhighspeed
operation,flashA/Dconverterscanbeused.Inthisconfigurationanarrayof2NcomparatorsareusedforanNbitA/Dconverter.AconceptualdiagramofanNbit
flash

Page10

Figure1.7
Switchedcapacitorfullwaverectifier:
(a)completecircuit(b)offsetcompensatedcomparator.

A/DconverterisshowninFig.1.10.AnalogtodigitalconvertersarediscussedindetailinChapter7.
WiththerecentrapidprogressmadeinMOSfabricationtechniquesandtheemergenceofthesubmicronCMOStechnology,manyintricatesystemscontaininganalog
anddigitalfunctionshavebeencombinedinafullyintegratedform.OnedrawbackofthesubmicronCMOStechnologyisthereductioninthepowersupplyvoltage,
whichresultsinareducedsignalswingandhencealowerdynamicrange.Toimprovetheperformanceofthesystemandreducetheeffectsofnoiseinjectionfromthe
power,ground,andclocklines,mostmodernhighperformancemixed

Page11

Figure1.8
Continuoustimepeakdetector.

Figure1.9
FivebitsuccessiveapproximationA/Dconverter.

Page12

Figure1.10
ConceptualdiagramofanNbitA/Dconverter.

signalintegratedcircuitsmakeuseoffullydifferentialsignalpaths.Withopampsandcomparators,thefullydifferentialsignalpathsrequirefullydifferentialoutputsas
wellasinputs,andtheyareknownasfullydifferentialopampsandcomparators.Sincethistechniqueusessymmetricallayout,manyofthenoisevoltages(power
supplynoise,clockfeedthroughnoise,offsetvoltages)appearascommonmodesignals.Theyaretoaconsiderableextentcanceledinthedifferentialoutputvoltage
v outatallfrequencies.AhighfrequencyhighQswitchedcapacitorbandpassfilterthatusesafullydifferentialsignalpathisshowninFig.1.11.Thisfilteristypically
usedinaradiofrequency(RF)receiversystem,whichrequireshighselectivityathighfrequencies[7].Thetwocomplementaryswitchblocks(X1andX2)areshown
inFig.1.12.ThefilterusesfullydifferentialsinglepoletransconductancefoldedcascodeopampswithsourcefollowercommonmodefeedbackasillustratedinFig.
1.13[8].Thisopampachieves100MHzunitygainbandwidthand60dBofgainwith1mAoftotalcurrentconsumption.Fullydifferentialopampsarediscussedin
detailinChapter4.

Page13

Figure1.11
Schematicdiagramofasixthorderswitchedcapacitorallpolebandpassfilter.

Page14

Figure1.12
Twoswitchblocksforadoublesampling.

Anotherapplicationofthefullydifferentialopampsisinoversampling,ordeltasigmaA/Dconverters.Theoversamplingconvertersoperateatsamplingratesof16to
512timestheNyquistrateandincreasethesignaltonoiseratiobysubsequentfiltering.Theoversamplingtechniqueslendthemselvesmostfavorablytoapplications
thatrequirearelativelylowfrequency(<1MHz)andhighresolution(>12bits).Themostobviousapplicationofdeltasigmaconvertersisindigitaltelephony

Figure1.13
Widebandopampforthefilter.

Page15

Figure1.14
(a)FullydifferentialCMOSimplementationofasecondorder
deltasigmamodulator(b)twophaseclockscheme.

anddigitalaudio.Figure1.14showsafullydifferential,switchedcapacitorCMOSimplementationofasecondorderdeltasigmamodulator[9].Itconsistsoftwo
parasiticinsensitiveintegrators,acomparatorthatservesasa1bitA/Dconverter,andatwolevel(1bit)D/Aconverter.Useofafullydifferentialconfiguration
attenuatespowersupplynoise,clockfeedthrough,andevenorderharmonicdistortion.Themodulatoroperatesontwophasenonoverlappingclocksconsistingofa
samplingphaseandanintegrationphase.Itachieves16bitdynamicrangewithanoversamplingratioof256andasignalbandwidthof20kHz.

Page16

Astheexamplesaboveillustrate,presentdayCMOSopampsandcomparatorsandtheiruseinanalogMOScircuitshavereachedacertainlevelofmaturity.
Already,almostanyanalogsignalprocessingtaskinthevoiceoraudiofrequencyrangehasapossiblesolutionusingsuchcircuits.Asfabricationtechnologyand
circuitsdesigntechniquescontinuetoadvance,thespeedanddynamicrangeofthesecircuitswillincrease,allowingtheiruseinsuchlargevolumeapplicationsas
videoandradiosystems,imageprocessing,highspeedtransmissioncircuits,andsoon.
Problems
1.1.ShowthatthecircuitofFig.1.1acanrealizethetransferfunctionofEq.(1.1).WhatshouldbetheelementvaluesR,L,andC?
1.2.CalculatethetransferfunctionoftheactiveRCcircuitofFig.1.1b.AssumethatthecircuitistorealizethetransferfunctionofEq.(1.1).Writetheavailable
equationsfortheelementvalues.Howmanyelementvaluescanbechosenarbitrarily?
References
1.R.W.Brodersen,P.R.Gray,andD.A.Hodges,Proc.IEEE,67,6175(1979).
2.Y.Tsividis,Proc.IEEE,71,926940(1983).
3.R.Gregorian,K.W.Martin,andG.C.Temes,Proc.IEEE,71,941966(1983).
4.D.J.AllstotandW.C.Black,Jr.,Proc.IEEE,71,967986(1983).
5.P.R.GrayandR.G.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,2nded.Wiley,NewYork,1984.
6.R.GregorianandG.C.Temes,AnalogMOSIntegratedCircuitsforSignalProcessing,Wiley,NewYork,1986.
7.BangSupSongandP.R.Gray,IEEE,J.SolidStateCircuits,SC21(6),924933(1986).
8.T.C.Choi,R.T.Kaneshira,R.W.Broderson,P.R.Gray,W.B.Jett,andM.Wilcox,IEEEJ.SolidStateCircuits,SC18(6),652664(1983).
9.B.P.Brandt,D.E.Wingard,andB.A.Wooley,IEEEJ.SolidStateCircuits,SC26(4),618627(1991).

Page17

Chapter2
MOSDevicesasCircuitElements
InthischapterthephysicsofMOS(metaloxidesemiconductor)devicesisdiscussedbriefly.Themostimportantandsimplestcurrentvoltagerelationsaregiven,and
simplemodelsintroducedforMOStransistorsinlinearoperation.Thediscussionhereisinthesimplestpossibleterms,aimedatprovidingsomephysical
understandingofthehighlycomplexdeviceoperationforthecircuitdesigner.Precisionanddepthhaveregretfullybeensacrificedintheprocess.Theambitiousreader
isreferredtotheexcellentspecializedworkslistedasreferencesattheendofthechapter.
2.1
Semiconductors
Inmetals(e.g.,aluminum,copper,silver)thataregoodelectricalconductors,theatomsarearrangedinaregularcrystalarray.Theelectronsfromtheouter(valence)
shelloftheatomsarefreetomovewithinthematerial.Sincethenumberofatoms,andthusthenumberoffreeelectrons,isverylarge(ontheorderof1023cm3),
evenasmallelectricfieldresultsinalargeelectroncurrenthencethehighconductivityobservedforthesemetals.
Thepictureisquitedifferentforaninsulatorsuchassilicondioxide(SiO2).Herethevalenceelectronsformthebondsbetweenadjacentatomsandhenceare
themselvestiedtotheseatoms.Thusnofreeelectronsareavailableforconductionandtheconductivityisverylow.
Semiconductors(suchassiliconorgermanium)areinbetweenconductorsandinsulatorsintheirelectricalproperties.Atverylowtemperatures,thevalenceelectrons
areboundtotheiratoms,whichagainformaregularlattice.However,asthetemperatureisraised,duetothethermalvibrationsoftheatoms,somebondswillbe
broken,andanelectronescapesfromeachofthesebonds.Suchelectronsare

Page18

capableofconductingelectricity.Furthermore,eachfugitiveelectronleavesachargedeficit(calledahole)behindinthebond.Avalenceelectroninabondclosetoa
holecaneasilymoveover,fillingtheholeandleavinganewholeinitsownbond.Theeffectisthesameasiftheholehadmovedfromonebondtothenext.Sincethe
hole''moves"inadirectionoppositethatofthemovingvalenceelectron,inanelectronicfielditbehaveslikeapositivelychargedparticle.
Electricalconductionisthuspossibleforasemiconductoratroomtemperature.Thedensityofthermallygeneratedelectronsandholesis,however,muchsmallerthan
thatofthefreeelectronsinmetal.Typicalnumbersare1010chargecarrierspercubiccentimeterforsiliconand1013ingermanium.Inwhatfollows,thecurrently
dominantmaterial,silicon,isdiscussedexclusively.
Addingforeignelements(dopants)tothepuresiliconcanraisethenumberoffreechargecarriersinasemiconductor.Silicon(andgermanium)hasfourvalence
electrons.Ifanatomofanelementwithfivevalenceelectrons(suchasarsenic,phosphorus,orantimony)isaddedtothesemiconductor,itmaytaketheplaceofa
siliconatominthecrystallattice.Thusfourofitsvalenceelectronswillparticipateinthefourbondstyingtheatomtoadjacentsemiconductoratomsinthelattice.The
fifthvalenceelectronoftheforeignatom,however,willnothaveaplaceinanybondandwillthusbefreetomoveawayfromitsparentatom.Hencesuchadopant
element(calledadonor,sinceitcontributesfreeelectronstothesemiconductor)enhancestheconductivityofthematerial.
Addingatomsofanelementwiththreevalenceelectronswillalsocontributetotheconductivity.Nowtherewillbeabondlackingavalenceelectronforeachdopant
atom.Thuseachsuchatomcreatesonehole.Thesedopants(e.g.,boron,aluminum,andgallium)arecalledacceptors,sincetheholeswillpropagatebyaccepting
boundvalenceelectronsfromadjacentsemiconductoratoms.
Indopedsemiconductorstherewillbecarriersduetothermaleffectsaswellastothedonor(oracceptor)atoms.Materialscontainingdonorswillthushavebothfree
electronsandholes,buttherewillbemoreelectronsthanholes.Suchsemiconductorswillbecalledntype,wherenstandsfornegative.Materialscontaining
acceptorswillhaveamajorityofholestheyarecalledptypesemiconductors,wherepstandsforpositive.
Asemiconductorstructurecanalsobefabricatedthatcontainstwoadjacentregionsofdifferenttypes(Fig.2.1).Thesurfacejoiningthetworegionsiscalledapn
junction.Whenthejunctionisfabricated,therandomthermalmotionofthe

Figure2.1
Apnjunctiondiode.

Page19

Figure2.2
Ionlayersinapnjunction.

majoritycarriers(electronsinthentyperegion,holesintheptyperegion)willcauseelectronstospilloverfromthentyperegiontotheptyperegion.Viceversa,
holeswillmovefromtheptyperegiontothentypesemiconductor.Thusthisrandommotion(calleddiffusion)resultsintheptypesemiconductorbeingcharged
negativelywhilethentyperegionischargedpositively.Theeffectwillbestrongestnearthejunction:There,intheptyperegion,thenegativelychargedacceptor
atomswillnolongerbeneutralizedbyholes,and(inthentyperegion)freeelectronswillnolongersurroundthepositivelychargeddonorions.Henceinthisareaa
dipolelayeroffixedionswillbeformed(Fig.2.2).Theelectricfield compensateforthelargernumberofavailablemajoritycarriers.
Theequilibriumwillbeupsetifavoltagesourceisconnectedtothewiressolderedtothesemiconductor(Fig.2.3).Assumefirstthatthepolarityofthesourceissuch
thatitmakesthepregionmorepositivewithrespecttothenregionthatis,v>0inFig.2.3.Thenvwillreduce causedby,say,abatteryofv=0.8Vcanresult
inalargemajoritycarriercurrent(say,

Figure2.3
Circuitfortestingapndiode.

Page20

Figure2.4
Currentversusvoltagecharacteristics
ofapnjunctiondiode.

i=1A)inthecircuit.Hencevwiththepolarityindicatedwillbecalledforwardvoltageandiforwardcurrent.
Letusnowreversethepolarityofthevoltagesourcesothatv<0inFig.2.3.Nowvwillaid inobstructingtheflowofmajoritycarriersfromregiontoregion.Ifv
islargeenough,themajoritycurrentisessentiallyeliminated,andonlytheflowofminoritycarriers(electronsmovingfromthepregiontothenregion,andholes
movingintheoppositedirection)remains.Sincethenumberofminoritycarriersis,however,smallandnearlyindependentofv,theresultingnetcurrentwillbesmall
andnearlyconstant.Thisisthecaseofreversevoltageandcurrent.WiththereferencedirectionsusedinFig.2.3,nowi<0.Figure2.4illustratestheoverall
behaviorofiasafunctionofv.Adetailedtheoreticalanalysis[1,Sec.4.32,Sec.6.6]revealsthatthedescribingequationis,toagoodapproximation,

HereISisthesaturationcurrent,determinedbythegeometryandthematerialpropertiesofthedevice,q 1.61019Cistheelectroncharge,andk 1.3810

23
J/KisBoltzmann'sconstant.Tisthetemperatureofthesemiconductor,inKelvin.Atroomtemperature(T=300K),kT/q 26mV.ISisusuallyverysmall,onthe
orderof109Aorless.Thusiincreasesexponentiallywithvforv>0,whilei ISandisverysmallifv<0(Fig.2.4).
Thebehavioroftheregiondirectlyadjacenttotheboundarybetweenthepandnregionsisofprimeimportance.Asmentionedearlier,themajoritycarriersarevery
sparseinthisareasomehaveimmigratedintotheotherregion,andtheothershavebeenpushedbackintotheinsideoftheirnativeregionbythefield .Hencethe
borderareacontainsonlythefixedions,chargednegativelyintheptyperegionandpositivelyinthentypematerial(Fig.2.3).Thisareaishencecalledthedepletion
region.Itswidthincreaseswithincreasing henceitwillbegreater(smaller)forreverse(forward)voltagev.
Duetothefield ,avoltage i(oftencalledthebuiltinvoltage)appearsacrossthedepletionregionforv=0.Thetotalpotentialacrossthejunction,forv 0,is
thus iv.Typically, i=0.5to1V.
Forv<0,thepnjunctioncanberegardedasacapacitor,sinceonlyasmall

Page21

saturationcurrentISflowsforadcvoltagev,andsinceadjacentpositive(+Q)andnegative(Q)chargesarestoredinthedepletionregion(Fig.2.3).Sincethe
chargestoredisanonlinearfunctionofv,thecapacitanceisnonlinear.WeshalldefinethecapacitanceCbytheincrementalrelationC=dQ/dv.Itcanthenbeshown
[1,Sec.3.32,Sec.6.5]thatforthedeviceillustratedinFig.2.3,

holds.Here S 1.04pF/cmisthepermittivityofthesilicon S= 0KS,where 0isthepermittivityoffreespace( 0 8.861014F/cm)andKS 11.7isthe

dielectricconstant(alsocalledtherelativepermittivity)ofsilicon.AistheareaofthejunctioninsquarecentimetersandNa(Nd)isthenumberofacceptor(donor)
atomspercubiccentimeter.NotethatCdecreaseswith|v|.Itcanbeshown[1,Sec.3.3]thatthequantityunderthesquarerootsignis( S/xd)2,wherex d(in
centimeters)isthewidthofthedepletionregionhenceC= SA/xdholds.
2.2
MOSTransistors[1,2,Sec.9.2]
ConsidernextthestructureshowninFig.2.5.Itisasandwichofseverallayers:Fromtoptobottom,itcontainslayersofmetal,silicondioxide(SiO2,anexcellent
insulator),ptypesilicon,andasecondmetallayerconnectedtoground.Itiscalledametaloxidesemiconductor(MOS)structure.Letvbenegativethenan
electricfieldwillbecreatedacrossthedioxidelayer,whichwillattractpositivecharges(holes)totheregionRunderthetopmetalelectrode(Fig.2.5).Thusnegative
chargeswillbestoredinthetopmetalelectrodeandpositivechargesinR.ThedevicewillthusbehaveasacapacitorCofmagnitude

where

isthepermittivityoftheSiO2,and

ox

ox

Kox 0.35pF/cm,whereKoxisthedielectricconstantofSiO2(Kox 3.9).Aistheareaofthetopelectrode,

Figure2.5
Metaloxidesemiconductor
(MOS)structure.

Page22

Figure2.6
Capacitanceversusvoltagecharacteristics
ofanMOSstructure.

andlisthethicknessoftheSiO2layer.*TheptypeSilayerbetweenRandthebottommetallayerbehavesasaresistorhencetheoverallstructuresimulatesalossy
capacitor.
Next,letvbeasmallpositivevoltageinFig.2.5.Theelectricfieldwillnowrepelholes.Asaresult,thefixednegativelychargedionsinRwillbeabandonedbythe
mobileholes,andanetnegativespacechargewillappearinR,whichisnowadepletionlayer.Thuschargeisagainstoredinthetopelectrodeandacapacitoris
created.Forverysmallvaluesof
Eq.(2.3)willremainvalidforthemagnitudeofthecapacitance.Asthevalueofvisincreased,however,thechargeinR
becomesgreatersincethedepletionregionwidens.Sincetheaverageionisnowfartherawayfromthesurface,theeffectivevalueoflinEq.(2.3)increasesandC
decreases.
Ifvisincreasedevenfurther,aneweffectappears.Sincethethermalgenerationofholesandelectronsoccurscontinuouslyinthesemiconductor,ifthefieldcreated
byapositivevisstrongenough,itcanattractthermalelectronstoRthesewillthenmovetothesurface.Whenthisoccurs,thecapacitorstorespositivechargesinthe
topelectrode,whilenegativeones(electrons)arestoredinthesurfacelayer.Thus,inEq.(2.3),lagainbecomestheSiO2thickness,andhenceChasthesamevalue
asithadfornegativevoltagev.TheoverallbehaviorofCasafunctionofvisillustratedschematicallyinFig.2.6,whichalsogivesthenamesofthethreeoperating
regions.Thenamesofthefirsttwoareevidentthethirdoneiscalledtheinversionregion,since(duetothehighvoltagev)mobileelectronsareattractedintoR,
whichthusbehavesasann(ratherthanap)typematerial.Itshouldbenotedthatsincethermalelectronsaregeneratedataslowrate,thevoltagevmustbepresent
forsometimebeforetheinversionlayerisformedhenceitwillnotappearifvisahighfrequency(say,f>1kHz)signalratherthanaconstantvoltage.
ConsidernextthestructureshowninFig.2.7.Anewfeatureisthepresenceoftwon+(i.e.,heavilydopedntype)regionsintheptypematerial.Theoneontheleft
willbecalledthesourceavoltagev Sisconnectedtoit.Then+regiononthe
*

Often,theoxidethicknesslismeasuredinangstroms(1=108cm).Usualvaluesoflarebetween50and200.

Page23

Figure2.7
MOStransistor.

rightwillbecalledthedrainitsvoltageisdenotedbyv D.Thetopmetalelectrodewillbecalledthegateitsvoltageisv G.Thebodyofthesemiconductorisusually

calledthesubstrateorbulk.TheoveralldeviceistheMOStransistor.Itsoperationisdiscussedbrieflynext.
Letthesourcebegrounded,sothatv S=0.Also,letv Dhaveasmallpositivevalue,say0.5V.WewillconsiderthebehaviorofthedraincurrentiDasv Gisraised
fromzerotohigherpositivevalues.Sincethegateisinsulatedfromtherestofthedevicebytheoxidelayer,itwillnotconductanycurrent.Then+drainregionandthe
surroundingptypesubstrateformapnjunction.Sincethesubstrateisgrounded,whilev D>0,thisjunctionisreversebiased.Henceforv G=0,iD 0.
Asv Gisincreased,theregionRunderthegatewillfirstbedepleted,theninverted,asdiscussedearlierinconnectionwithFigs.2.5and2.6.WhenRisdepleted,iD
remainszero,sincetheareaaroundthedrainisstillreversebiased.However,thesituationchangeswhenv Gissolargethatinversionoccurs,sothatRisfilledwith
electrons.Now,alayercontainingmobileelectrons,calledaninversionlayerorchannel,connectsthedraintothesource.Sincethedrainispositivewithrespectto
thesource,electronswillflowfromthesourcetothedrainandapositivecurrentiD>0willbeobserved.Thesmallestvoltagev Gnecessarytoproduceachannelis
calledthethresholdvoltageandisdenotedbyVT.Usually,VTisgivenasthev GvalueneededforiD=1Aitmayrangefromafractionofavolttoseveralvolts.
ItshouldbenotedthatforthestructureofFig.2.7,mostoftheelectronsinthechanneldonotoriginatefromthermaleffectsinthebulkinstead,theyaredrawnbythe
electricfieldduetov Goutofthesource.Someelectronsarealsodrawnfromthedrainhowever,sincev D>0,thedrainsubstratejunctionismorereversebiased,
andhenceitisharderforelectronstoescapefromthedrain.
Sinceapotentialdifferencev Dexistsbetweenthetwoendsofthechannel,theelectronsinthechannelwillbeattractedtothedrain.Therefore,inadditiontothe
randomthermalmotionoftheelectrons,asteadymotion(calleddrift)willoccur,whichcausesthecurrentflow.Forsmallv D,thechannelwillthereforebehaveasa
resistor,andhenceiD v D/R,wherethechannelresistanceRisgivenby

Page24

Figure2.8
PinchoffinanMOStransistor.

HereListhelengthandWthewidthofthechannel,andnisthemobilityoftheelectronsinthechannel,*definedbytherelation(electrondriftvelocity)=(mobility)
(electricfield).Finally,Qnisthechargedensity(inC/cm2)oftheelectronsinthechannel.Sincev Gcanbeconsideredasthesumoftwoterms,VT(necessaryto
maintainthedepletionregionunderthechannel)andv GVT(necessarytomaintainthechannel),wehave

whereCox=

/listhecapacitance(perunitarea)oftheoxidelayerseparatingthegatefromthechannel.Hence,forsmallv D(

ox

),therelation

holds.Thusthetransistoractsasaresistor,withresistanceR=[nCoxW/L(v GVT)]1controlledbyv G.
Ifv Disincreasedsothatitisnolongernegligiblecomparedtov G,Eq.(2.6)willbecomeinaccurate.Sincethepotentialofthechannelatthegroundedsourceiszero
whileatthedrainitisv D,wecanassumethatitsaveragepotentialisv D/2.Hencetheaveragevoltagebetweenthegateandchannelis(v Gv D/2).Replacingv Gby(v G
v D/2)inEq.(2.6)gives

Equation(2.7)remainsagoodapproximationforv D<v GVT.Thisrangeiscalledthelinearregion(ortrioderegion)ofoperationoftheMOStransistor.

Whenv D v GVT,anewphenomenonoccurs.ConsiderthesituationillustratedinFig.2.8,whereonlythestructurenearthesemiconductorsurfaceisshown,magni
*

Themobilityinthebulkofthesemiconductorishigher,sincendecreaseswiththeconcentrationofionizedimpurities.Typicalvaluesaren 1000cm2/VsforND=1016cm3,

whilen 100cm2/VsforND=1019cm3.

Page25

fied.Asthefigureindicates,duetothevariationofthepotentialalongthechannel,thechargedensityQndecreasesnearthedrain.Ifv D=v GVT,atthedrainthegate

tochannelvoltageisnolongersufficienttomaintainthechannel.Thusthedepletionregionsurroundingthesource,thechannel,andthedrainextendsallthewaytothe
surface.Thisphenomenonissometimescalledpinchoff,andtheregionwhereitoccursisthepinchoffpoint(Fig.2.8).Ifv Disincreasedfurther,thepinchoffpoint
willmovetowardthesource,sincetheareawherev Gv D VTwillincrease.Hencethechannelwillnowextendonlyfromthesourcetothepinchoffpoint,thelatter
beingsomewhereunderthegate.Theregionbetweenthepinchoffpointandthedrainisdepleted.Electronsfromthechannelareinjectedintothisdepletionregionat
thepinchoffpointandareswepttothedrainbythefieldcreatedbythepotentialdifferencebetweenthedrainandthepinchoffpoint.Thevoltage
is
thusdividedbetweenthetwoseriesconnectedregions:thechannelbetweenthesourceandthepinchoffpoint,andthedepletionregionbetweenthepinchoffpoint
andthedrain.Clearly,thelatterhasahigherresistance,andhencemostofv DSinfactappearsacrossit.Anyincreaseofv Dwill,toagoodapproximation,resultinan
equalvoltageincreaseacrossthedepletionregionandwillhardlychangeiD.Thus,forv Dv GVT,fromEq.(2.7),

ThisphenomenoniscalledsaturationvDsat=v GVTisthedrainsaturationvoltageandiDsatasgivenbyEq.(2.8),isthedrainsaturationcurrent.
Thedraincurrentdoes,inreality,increasesomewhatwithincreasingv D.Thiscanbeattributedtothemoveofthepinchoffpointtowardthesourceforincreasingv D
andhencetotheshortenedchannelasEq.(2.8)indicates,iDincreasesasLisreduced.Asanapproximation,thiseffect(oftencalledchannellengthmodulation)
canbeincludedintheformulaforiD(v D)intheformofanaddedfactor(1+lv D).HerelisadeviceconstantthatdependsonL,onthedopingconcentrationofthe
substrate,andonthesubstratebias(discussedinthenextsection).ForL 10mm,typicallyl 0.03V21generally,l~1/L.
Itisusualtointroducetheabbreviations

ThenthesaturationcurrentgivenbyEq.(2.8)becomes

whichincorporateschannellengthmodulation.Figure2.9showsthevariationofiDwithv Gforconstantv D.Figure2.10illustratesitsdependenceonv Dforvariousv G

values,wherev G1,v G2,v G3.
AllderivationsofthissectionwereperformedforthestructureshowninFig.2.7,whosesource,drain,andchannelwereallntype.Thisdeviceiscalledannchannel
MOS,orNMOStransistor.Asimilararrangementcanbeconstructedbycreatingp+drainandsourcediffusionsinanntypesubstrate.Nowanegativev Gisneeded
tocreateaptypechannelunderthegate,andanegativev Disusedto

Page26

Figure2.9
Draincurrentversusgatevoltage
characteristicsofanMOStransistor.

attracttheholesinthechanneltothedrain.Also,iDwillbenegativeifthereferencedirectionofFig.2.7isused.TheresultingdeviceiscalledapchannelMOSor
PMOStransistor.Formulas(2.3)to(2.9)remainvalidifsomesmallchangesaremade.Themobilitynofelectronsmustbereplacedbyp,theholemobilityinthe
channel.Aswouldbeexpectedfromthemoreelaboratemechanismofholeconduction,p<n.Typicalmobilityvaluesinthechannelregionforanimpurity
concentrationof1016cm3aren=1000cm2/Vsandp=400cm2/Vs.TheelectronchargedensityQninthechannelistobereplacedbyQp,theholecharge
densityalso,anegativesignmustbeincludedinEqs.(2.6)to(2.9)toaccountforthechangeinthechargeofthecarriers.Finally,v Dmustbereplacedby|v D|inEq.
(2.9),sincenowv D<0.Inconclusion,Eq.(2.7)becomes

Here
andVT<0.Equation(2.10)describesthedraincurrentcharacteristicsinthelinearrange.ThebehaviorofiDinthesaturationregioncanbe
obtainedbymodifying(2.9):

Figure2.10
Draincurrentversusdraintosourcevoltage
characteristicsofanMOStransistor.

Page27

Figure2.11
Transistorsymbols.

ThecircuitsymbolsusedforNMOSandPMOStransistorsareshowninFig.2.11aandb,respectively.Ifthetypeisunimportant,thesimplifiedsymbolofFig.2.11c
maybeusedforbothNMOSandPMOSdevices.
Sincetheoperationofthedevicesdescribedinthissectionisdependentontheelectricfieldinducedbythegatevoltage,theyarecalledfieldeffectdevices(FETs),or
MOSFETs.*
SincePMOStransistorsaremoreeasilyfabricatedthanNMOStransistors,theywereinitiallypredominant.However,later,whenthetechniquesforthereliable
productionofNMOSdevicesweredeveloped,thelatterbecamestandard.Themainreasonforthisisthehighermobilityofelectrons,whichmakestheNMOS
transistorsfasterthanPMOStransistors.
2.3
MOSTransistorTypes:
BodyEffect
TheMOStransistorsdescribedinSection2.2,bothNMOSandPMOStypes,shareseveralfeatures.Inthestructure,thegateisinsulatedelectricallyfromtherestof
*

Sincethechargecarriershereareeitherelectronsorholes(notboth),FETsarealsosometimescalledunipolardevices,tocontrastthemwithbipolartransistors,inwhichboth
electronandholecurrentsexist.

Page28

Figure2.12
Symbolsfordepletionmodetransistors.

thedevicebytheSiO2layerunderit.Henceitisoftencalledaninsulatedgatefieldeffecttransistor(IGFET).Also,thevoltagev Ginducesandenhancesthedrain
current.Thusthedevicesdescribedoperateintheenhancementmode.
ItisalsopossibletofabricateanMOStransistorthatconductsdraincurrentwhenv G=0.Forexample,anntypelayercanbeintroducedbydoping,whichconnects
thesourceanddrainofanNMOSdevice.Withsuchadopedchannel,thefieldofthegateisnotneededtoproduceaninversionlayertheregionR(Fig.2.7)now
hasa''builtin"conductingntypechannel.
However,ifanegativegatevoltageisapplied,thefieldthuscreatedwillrepelelectronsandcreateadepletionlayerinthechanneladjacenttotheSiO2surface,
therebyreducingtheconductivityandthusthedraincurrent.Ifthemagnitudeofthenegativegatevoltageissufficientlylarge,thechannelbecomescompletelydepleted
andiD 0results.Thevaluev GatwhichthisoccursisagaincalledthresholdvoltageandisdenotedbyVT.Now,however,VT<0.Suchadeviceiscalleda
depletionmodeFET.
Itshouldbenotedthatevenwithoutadopedlayer,anNMOStransistorcanconductforv G=0duetooxidecharges[1,Sec.7.4]ifthebulkisverylightlydoped.It
isalsopossibletocreateadepletionmodePMOSdevice,withVT>0,byestablishingaptypedopedchannel.
Therelations(2.6)to(2.11)remainvalidfordepletionmodedevicesifthevalueandsignofVTischosenappropriately,asdescribedabove.Twosymbolsoftenused
todenotedepletionmodeMOSFETsareshowninFig.2.12.
Atotallydifferentstructurecanalsobeusedtoproduceadepletionmodefieldeffecttransistor(Fig.2.13).Here,alightlydopedntypelayer(channel)connectsthe
n+sourceanddrainregionsandthegateisap+regionimplantedinthislayer.Hence,forv S=v G=0andv GD>0,adraincurrentwillflow.Ifv Gismadenegative,the
p+implantactingasthegatewillbesurroundedbyadepletionlayerthegreater|v G|,thedeeperthelayer.Themobileelectronsinthechannelcannot

Figure2.13
Junctionfieldeffecttransistor.

Page29

enterthisdepletionlayer,ortheonealongthepnjunctionbetweenthechannelandthesubstrate.Hencetheeffectivecrosssectionofthechannelisreducedas|v G|is
increased.Atsomevaluev G=VP(VP<0),iDbecomeszero(inpractice,<1A).ThusVPplaysthesameroleasVTforadepletionmodeMOSFETitiscalledthe
pinchoffvoltage.Itcanbevisualizedasthegatevoltage,whichcausesthetwodepletionregionsinthechanneltomerge,leavingnoconductivepathbetweensource
anddrain.
ThedevicedescribedandshowninFig.2.13iscalledannchanneljunctionfieldeffecttransistor(JFET),sinceitsgateisseparatedfromtherestofthedevicebya
reversebiasedpnjunctionratherthanbyanSiO2layerasfortheMOSFET(IGFET).SincetheJFETishardlyeverusedinanalogMOSintegratedcircuits,itisnot
discussedindetailhere.AcleardescriptionofitsphysicsandcurrentvoltagecharacteristicsisgiveninSec.2.5ofRef.1.
Next,akeylimitation(calledthebodyeffect)ofMOSFETsusedasanalogcircuitelementsisdescribed.InthediscussioninSection2.2itwasalwaysassumedthat
boththebulkandsourcearegrounded,sothatv B=v S=0held.Often,circuitconsiderationsmakethisconvenientarrangementimpossibleandv S v Bmustbeused.
Obviously,thevoltagev Sv Bmustbesuchthatthesourcebulkjunctionisreversebiasedotherwise,alargejunctioncurrentwillflowinsidethetransistor.This
currentmaydamagethedevice,andinanycasewillimpedeitsproperoperation.Thus,say,inanNMOStransistor,thebulkmustbebiasedtomakeitnegativewith
respecttobothsourceanddrain.
Ifthesourcepotentialisnotzero,thevoltagesv Gandv Dmustbereplacedinallequationsbyv GS=v Gv Sandv DS=v Dv S,respectively.Inaddition,thedepletion
regionaroundthechannel(Fig.2.8)willbecomewiderifthereversevoltagebetweenthebulkandthesource(andhencethechannel)isincreased.Sincethevoltage
v G=VTisthegatevoltagenecessarytomaintainthedepletionregion(withoutcreatingachannel),VTwillincreaseinmagnitude.ThedependenceofVTonthevoltage
canbeshown[1,Sec.8.2]tobeintheform

Here,VT0isthethresholdvoltageforv SB=0and isadeviceconstantgivenby

InEq.(2.13), Sisthepermittivityofsilicon: S= 0KS,KS 11.7.Also,Nimpisthedensityoftheimpurityionsinthebulk.ForNMOS,Nimp=NA,theacceptorion

densityforPMOS,Nimp=ND,thedonoriondensity.Forexample,forNimp=1015cm23and800oxidethickness(i.e.,Cox 4.41028F/cm2), 0.423V1/2.
Finally, pisamaterialconstant*ofthebulkitsvalueisaround0.3V.
*

whereEiistheintrinsicFermienergyandEftheFermienergyofthesemiconductor[1,p.318].

Page30
TABLE2.1.KeyUnitsandConstantsforMOSTransistors

Thisphenomenon,thebodyeffect,isamajorlimitationofMOSdevicesoperatedwithv S v Bitsevilinfluencewillbelamentedrepeatedlylaterinthebook.AsEqs.
(2.12)and(2.13)show,toreducethebodyeffect,Nimpshouldbemadesmall.However,forverysmallNAvalues(say,NA<1013cm3),anNMOSmaybehaveasa
depletionmodedevice,asexplainedearlier.Thusthebodyeffectcannotbeeliminatedcompletely.SomekeyconstantsandformulasonMOSFETsaresummarized
inTables2.1and2.2.
2.4
SmallSignalOperationandEquivalentCircuitofMOSFETTransistors
EarlierthephysicalprinciplesandbasicoperationofMOStransistorswerediscussedbriefly,andformulasderivedthatgavethedraincurrentasafunctionofthe
voltagesand/orcurrentsatthevariousterminalsofthedevice.Intheseearlierdiscussionsitwasassumedthatallvoltagesandcurrentswereconstantorthatthey
variedsufficientlyslowlysothatallcapacitivecurrents(andhenceallcapacitancesthemselves)couldbeneglectedinthediscussions.Ontheotherhand,theformulas
derivedwerevalidforlargeaswellassmallvoltageandcurrentvariations.
Inmanyimportantlinearapplications(suchasoperationalamplifiers,discussedinChapter4)thevoltagesandcurrentsofthetransistorvarysorapidlythatcapacitive
effectscannotbeignored,andhencethecapacitancesofthedevicemustbeincludedintheanalysis.Atthesametime,insuchcircuitsthesignalsaresufficientlysmall,
sothatlinearapproximationsmaybeusedinallnonlinearrelations.Thissimplifiestheequationsandpermitstheuseoflinearmodels(simplelinearequivalentcircuits)
forthesenonlineardevices.

Page31
TABLE2.2.DrainCurrentRelationsforMOSFETsinLargeSignalLowFrequencyOperation

Page32

Inthefollowingdiscussion,weconcentrateonthelinearizedapproximationandmodelingprocessforMOSFETsoperatingintheirsaturationregions,whichisthe
usualconditionforlinear(analog)operation.Afterward,wegiveabriefoverviewofthelinearizationandmodelingfordevicesthatoperateintheirtriode
(nonsaturated)orcutoffregion.AssuminganNMOStransistor,andcombiningEqs.(2.9)and(2.12),therelation

results.Hereweused

wecanwrite

Here( iD/ v GS)0andsoondenotethepartialderivativesevaluatedatthebiaspoint. iDisthedeviation(increment)ofiDfromitsbiasvalue v GS, v DS,and v SBare

theincrementsofv GS,v DS,andv SB.AlldeviationsmustbesmallforEq.(2.15)tohold.Ifonlytheincremental(smallsignalac)componentsareofinterest,Eq.(2.15)
canbewrittenas

Figure2.14
LowfrequencyequivalentcircuitofaMOSFET.

Page33

where

Heregdisthe(incremental)drainconductancegmandgmbaretransconductancesthatcanberepresentedbyvoltagecontrolledcurrentsources(VCCSs).Hencean
equivalentcircuitmodel,showninFig.2.14,canbeconstructed.Thevaluesofgm,gmb,andgdcanbefoundfromEq.(2.14):

Hence,toagoodapproximation,gmandgmbareproportionalto
TheotherimportantcomponentsofthecompletesmallsignalmodeloftheMOSFETarethecapacitorsrepresentingtheincrementalvariationsofstoredchargeswith
changingelectrodevoltages.Theseplayanimportantroleinthehighfrequencyoperationofthedevice.Theintrinsiccomponentsoftheterminalcapacitancesofthe
MOSFETdevices(associatedwithreversebiasedpnjunctionsandwithchannelanddepletionregions)arestronglydependentontheregionofoperation,whilethe
extrinsiccomponents(duetolayoutparasitics,overlappingregions,etc.)arerelativelyconstant.Assumingagainthatthetransistoroperatesinthesaturationregion,it
canbeassumedthatthechannelbeginsatthesourceandextendsovertwo

Page34

thirdsofthedistancetothedrain.Inthisregionofoperation,themostimportantcapacitancesarethefollowing:
1.Cgd:GatetoDrainCapacitance.Thisisduetotheoverlapofthegateandthedraindiffusion.Itisathinoxidecapacitance,andhencetoagoodapproximation
canberegardedasbeingvoltageindependent.
2.Cgs:GatetoSourceCapacitance.Thiscapacitancehastwocomponents:Cgsov,thegatetosourcethinoxideoverlapcapacitance,and
voltageindependentinthesaturationregion.

isnearly

3.Csb:SourcetoSubstrateCapacitance.Thiscapacitancealsohastwocomponents:Csbpn,thepnjunctioncapacitancebetweenthesourcediffusionandthe
substrate,and
whichcanbeestimatedastwothirdsofthecapacitanceofthedepletionregionunderthechannel.TheoverallcapacitanceCsbhasavoltage
dependencewhichissimilartothatofanabruptpnjunction.
4.Cdb:DraintoSubstrateCapacitance.Thisisapnjunctioncapacitanceandisthusvoltagedependent.
5.Cgb:GatetoSubstrateCapacitance.Thiscapacitanceisusuallysmallinthesaturationregionitsvalueisaround0.1COX.
Figure2.15illustratesthephysicalstructureofanNMOStransistorandthelocationsofthecapacitancesinthecutoff(Fig.2.15a),saturation(Fig.2.15b),and
nonsaturationortriode(Fig.2.15c)regions.Table2.3liststheterminalcapacitorsoftheNMOSdeviceandtheirestimatedvaluesinthethreeregionsofoperation.
ThenotationsusedarethoseshowninFig.2.15atoc.Figure2.16depictsthecompletehighfrequency(ac)smallsignalmodeloftheMOSFET.Inanalyzingthe
smallsignalbehaviorofMOSFETs,themodelofFig.2.14canbeusedifonlylowfrequencysignalsarepresentifthecapacitivecurrentsarealsoofinterest,the
circuitofFig.2.16mustbeapplied.
FromthemodelsofFigs.2.14and2.16andaccompanyingdiscussions,anumberofgeneralstatementscanbemadeaboutthedesirableconstructionofaMOSFET:
1.Forhighacgain,gmshouldbelarge.Thiswillbethecase,byEq.(2.18),if shouldbeaslargeastheallowabledcpowerdissipationpermits.
2.AsthenegativesigninEq.(2.19)indicates,thebodyeffectreducesthegain.Tominimizegmb,byEqs.(2.19)and(2.13),weneedlargeCOX,smallNimp(i.e.,lightly
dopedsubstrate),andalargebiasvoltage

forthesource.

Page35

Figure2.15
ParasiticcapacitancesinMOSFETinthe(a)cutoff
region,(b)saturationregion,and(c)trioderegion.

(Ofcourse,ifv SBisconstant,noincrementalbodyeffectoccursandtheserequirementsareirrelevant.)
3.Ideally,theMOSFETinsaturationshouldbehaveasapurecurrentsource.Hence,asFig.2.14illustrates,gdshouldbesmall.ByEq.(2.20)thisrequiresasmall
biascurrent
andasmall .Since isintroducedbychannellengthmodulation,itcanbereducedbyincreasingLandalso[1,Sec.8.4]byincreasingNimp.A
summaryoftheformulasderivedinthissectionisgiveninTable2.4.

Page36
TABLE2.3.TerminalCapacitancesofaMOSFETintheThreeMainRegionsofOperationa

Page37

Figure2.16
HighfrequencyequivalentcircuitofaMOSFET.

Next,wediscussbrieflythelinearmodelofaMOSFETthatisbiasedinitsnonsaturated(triode)region.Usually,suchadeviceisusedasaswitchthatisopenedor
closed(turnedonoroff)byalargegatevoltageorasafairlylinearlargevaluedvariableresistor.Hence,herewederiveitsmodelonlytoanalyzeitsbehaviorinsuch
applications.Weassumethatv GSisconstantandthat
andhencenegligible.UndertheseconditionsitcanbeseenfromEq.(2.7)thatwhenthedevice
conductsdraincurrent,itbehaveslikearesistorconnectedbetweenthedrainandsourceterminals.Theequivalentsmallsignaldraintosourceresistanceforthecase
ofv DSnearzeroisgivenby

andisthuscontrolledbythegatevoltageoverdrive
Inhighfrequencyapplication,thedevicecapacitancesmustalsobeincludedinthemodel.AsimpleequivalentcircuitisshowninFig.2.17.Sincenowacontinuous
channelextendsfromthesourcetothedrain,thegatetochannelcapacitanceC'gsisconnectedtoboththedrainandthesource.Anaccuratehighfrequency
representationofthechannelshouldincludeadistributedresistivelineextendingfromthesourcetothedrainandcapacitivelycoupledtoboththegateandthe
substrate.However,asafirstapproximation,C'gscanbetreatedasalumpedcapacitancepartitionedequallybetweenCgsandCgd,asindicatedinthelastrowofTable
2.3.
Finally,ifthedeviceiscutoff,nochannelexistsandthemodelcontainsonly

Figure2.17
Highfrequencymodelofa
MOSFETinitstrioderegion.

Page38
TABLE2.4.SmallSignalParametersofMOSFETSinSaturationa

SeeFig.2.16.| vDS| 1isassumedinallformulas.

Page39

Figure2.18
Highfrequencymodelofa
MOSFETinitscutoffregion.

thecapacitances,withthevalueslistedinthefirstrowofTable2.3.AsimplifiedmodelofaMOSFETinthecutoffregionisshowninFig.2.18,wherethedrain
sourceresistanceisinfinityandCgsandCdscapacitorsareduetogateoverlapandfringingcapacitances.ThegatetosubstratecapacitanceCgdinthecutoffregionis,
however,highlynonlinear,andforthegatetosourcevoltagearoundzeroitsvalueisapproximatelyequaltoWL'Cox,whereL =L2LovandLovisthelengthofthe
overlapbetweenthegateandthesourcedraindiffusionregions.
2.5
WeakInversion
ThetriodeandsaturationregionsofoperationdiscussedearlierinthischapterassumethatthedeviceisoperatedinstronginversionandVGSVT 100mV(foran
NMOStransistor).IfVGSVT<100mV,thedeviceisintheweakinversionregion(alsocalledthesubthresholdregion)andoperationofthenchannelMOS
transistorwiththesourceconnectedtosubstrateismoreaccuratelydescribedbythefollowingexponentialrelationshipbetweenthegatetosourcecontrolvoltageand
draincurrent:

andtheparametersmandnaredefinedintermsofthevariouscapacitancesinthedevice[3].Equation(2.22)assumesthatthedeviceisoperatedwith
TheMOStransistorsoperatingintheweakinversionregion,similartobipolardevices,haveanexponentialrelationship.However,sinceID0isverysmall(ontheorder
of10to20nA),theavailablecurrenttochargeanddischargecapacitancesisalsosmall,resultinginpoorfrequencyperformance.Inpractice,MOStransistorsare
operatedinweakinversiononlyinlowfrequencyapplicationswhenlowpowerconsumptionisdesired.

Page40

2.6
ImpactIonization[4]
OneofthesevereproblemsinsubmicronMOStechnologiesoperatingatsupplyvoltagesaround5Visimpactionization.Figure2.19illustratesannchannelMOS
devicecrosssectionshowingtheimpactionizationcurrentflowandtheIVcharacteristicasaresultofimpactionization.Asdepictedinthefigure,whenthedrainto
sourcevoltageisincreased,thestrengthoftheelectricfieldatthedrainendofthechanneleventuallybecomeshighenoughtoinducesignificantimpactionization
currentwhichoriginatesfromthedraindepletionregionandflowsintothesubstrate.Oncethishappensthecurrentthatflowsintothedrainterminalhastwo
components.OnecomponentistheMOStransistorchannelcurrentthatflowsfromthedraintothesource,andtheotheristheimpactionizationcurrentthatflows
fromthedraintothesubstrate.Theimpactionizationcurrentisnotafunctionofthetransistorchannellength,andthemagnitudeofthecurrentisnotreduced
dramaticallysimplybymakingthelengthlonger.Thecurrentislargelydeterminedbythepeakelectricfield,whichinturnisafunctionofthegateoxidethickness,drain
junctiondepth,dopingconcentrationinthesubstrate,thevoltagebetweenthedrainterminalandthedrainendofthechannelregion,andthegatetodrainvoltage.In
technologieswithfeaturesizesintherangeof2m,forannchannelMOSdevice,theimpactionizationcurrentequals1%ofthedraincurrentwhenthevoltage
betweenthedrainandthedrainendofthechannelisintherange4to9V,andthedeviceisbiased

Figure2.19
(a)AnnchannelMOSdevicecrosssectionshowing
impactionizationcurrentflow(b)IVcharacteristic
observedasaresultofimpactionization.

Page41

inthesaturationregion.InpchannelMOSdevicestheeffectoccursatsubstantiallyhigherfieldstrengths.
Theimpactionizationhasseveralpotentiallydamagingsideeffects.OneseriousnegativeconsequenceshowninFig.2.19bisdegradationofthetransistoroutput
impedance,whichresultsinreducedgaininamplifierstagesthatusetransistorsasactiveloads.Onewaytodealwiththisproblemisthroughcircuittechniques,where
ashieldingnchanneldeviceisplacedinserieswiththetransistor,preventingitfromhavingaVdSgreaterthanhalfthesupplyvoltage[4].Theseconddamagingeffectis
thepossibilityoftriggeringlatchupduetotheohmicdropinducedbytheionizationcurrentthatflowsintothesubstrate.Latchupisaphenomenoncausedbythe
parasiticlateralpnpandnpnbipolartransistorscreatedonthechip.Thecollectorsofeachtransistorfeedtheother'sbase,andthiscreatesanunstabledevicesimilar
toapnpnthyristor[5].Thiscausesasustaineddccurrentthatmaycausethechiptostopfunctioningandmayevendestroyit.Latchupmaybepreventedbyproper
substratestrappingandusingguardringstosurroundsomecriticaltransistorsonthechip.Anotherstrategyistoreducethesubstrateresistance.Inthismethodthep
andnchanneltransistorsareformedinalightlydopedepitaxiallayerthatisgrownonalowresistivitysubstrate.Finally,thethirdserioussideeffectofimpact
ionizationisthethresholdshiftoftheMOSdeviceduetothecontinuousoperationintheimpactionizationmode.Thisphenomenonisduetothehighelectricfield
whichcreateshighenergycarriesthatcanbetrappedinthegateoxide,resultinginlongtermthresholdshift.Severalprocessmodificationshavebeenproposedthat
areeffectiveatraisingthevoltageatwhichimpactionizationbecomesaproblem.Onetechniqueistolowertheimpuritygradientinthedrainjunctionusinglightly
dopeddrain(LDD)structures.
2.7
NoiseinMOSFETs
Therearethreedistinctsourcesofnoiseinsolidstatedevices:shotnoise,thermalnoise,andflickernoise.
ShotNoise
Sinceelectriccurrentsarecarriedbyrandomlypropagatingindividualchargecarriers(electronsorholes),superimposedonthenominal(average)currentI,thereis
alwaysarandomvariationinS.Thisisduetofluctuationinthenumberofcarrierscrossingagivensurfaceintheconductorinanytimeinterval.Itcanbeshownthatthe
meansquareofinSisgivenby

whereq=1.61019Cisthemagnitudeoftheelectronchargeand fisthebandwidth.Thisformulaonlyholds,however,ifthedensityofthechargecarriersisso
lowandtheexternalelectricfieldissohighthattheinteractionbetweenthe

Page42

Figure2.20
Thermalnoiseinaresistor:(a)noisyresistor
(b)and(c)equivalentcircuits.

carriersisnegligible.Otherwise,therandomnessoftheirdensityandvelocityisreducedduetothecorrelationintroducedbytherepulsionoftheircharges.Thenoise
currentisthenmuchsmallerthanpredictedbyEq.(2.24).
InaconductingMOSFETchannel,thechargedensityisusuallyhighandtheelectricfieldislow.Therefore,Eq.(2.24)doesnothold.Thenoisecurrentdueto
randomcarriermotionsishencebetterdescribedasthermalnoise,whichisdiscussednext.
ThermalNoise
InarealresistorR,theelectronsareinrandomthermalmotion.Asaresult,afluctuatingvoltagev nTappearsacrosstheresistorevenintheabsenceofacurrentfrom
anexternalcircuit(Fig.2.20a).ThustheThveninmodelofthereal(noisy)resistoristhatshowninFig.2.20b.Clearly,thehighertheabsolutetemperatureTofthe
resistor,thelargerv nTwillbe.Infact,itcanbeshownthatthemeansquareofv nTisgivenby

HerekistheubiquitousBoltzmann'sconstant,and fisthebandwidthinwhichthenoiseismeasured,inhertz.(Thevalueof4kTatroomtemperatureisabout1.66
1020VC.)
IfEq.(2.25)wastrueforanybandwidth,theenergyofthenoisewouldbeinfinite.Infact,however,forveryhighfrequencies( 1013Hz)otherphysicalphenomena
enter,whichcause

todecreasewithincreasingfrequencysothattheoverallnoiseenergyisfinite.

Theaveragevalue(dccomponent)ofthethermalnoiseiszero.Sinceitsspectraldensity
isindependentoffrequency(atleastforlowerfrequencies),itisa
whitenoise.Clearly,Fig.2.20bmayberedrawnintheformofaNortonequivalentthatisasa(noiseless)resistorRinparallelwithanoisecurrentsourceinT(Fig.
2.20c).Thevalueofthelatterisgivenby

whereG=1/R.

Page43

Figure2.21
Equivalentmodelsofthe
thermalnoiseinaMOSFET.

SincethechannelofaMOSFETinconductioncontainsfreecarriers,itissubjecttothermalnoise.Therefore.Eqs.(2.25)and(2.26)willhold,withRgivenbythe
incrementalchannelresistance.Thenoisecanthenbemodeledbyacurrentsource,asshowninFig.2.21a.Ifthedeviceisinsaturation,itschanneltapersoff(Fig.
2.8)andtheapproximationR 3/2gmcanbeusedinEq.(2.26).
InmostcircuitsitisconvenienttomodeltheeffectofinTcausedbyavoltagesourceconnectedtothegateofan(otherwisenoiseless)MOSFET(Fig.2.21b).This
''gatereferred"noisevoltagesourceisthengivenby

BothinTandv nTdependthusonthedimensions,biasconditions,andtemperatureofthedevice.Asanexampleoftheirordersofmagnitude,foratransistorwithW=
200m,L=10m,andCox=4.34108F/cm2(correspondingtoanoxidethicknessof800)whichisoperatedinsaturationatadraincurrentiD=200A,the
gatereferrednoisevoltageatroomtemperatureisabout
Ifthedeviceisswitchedoff,Rbecomesveryhigh,andtheequivalentnoisecircuitwillbeacurrentsourcewithavaluegivenbyEq.(2.26).Clearly,
henceforusual(lowormoderate)externalimpedancelevels,theMOSFETcanberegardedasanoiselessopencircuitifitisturnedoff.

isverysmall

Page44

Flicker(1/f)Noise
InanMOStransistor,extraelectronenergystatesexistattheboundarybetweentheSiandSiO2.Thesecantrapandreleaseelectronsfromthechannel,andhence
introducenoise[6,7].Sincetheprocessisrelativelyslow,mostofthenoiseenergywillbeatlowfrequencies.Asbefore,apossiblemodelofthisnoisephenomenonis
acurrentsourceinparallelwiththechannelresistance.Thedcvalueofnoisecurrentisagainzero.Itsmeansquarevalueincreaseswithtemperatureandthedensityof
thesurfacestatesitdecreaseswiththegateareaWLandthegateoxidecapacitanceperunitareaCox.Fordevicesfabricatedwitha"clean"process,thegate
referrednoisevoltageisnearlyindependentofthebiasconditionsandisgivenbytheapproximatingformula

HereKdependsonthetemperatureandthefabricationprocessatypicalvalue[8,p.31]is31024V2F.Forthetransistordescribedintheprecedingexample,
theformulagivesanoisevoltageof
Thenoiseprocessdescribedisusuallycalledflickernoiseor(inreferencetothe1/ffactorin
frequencies(say,below1kHz)itisusuallythedominantnoisemechanisminaMOSFET.

1/fnoise.Astheexamplegivenillustrates,atlow

Inconclusion,thechannelnoiseinaMOSFETcanbemodeledbyanequivalentnoisecurrentgenerator,asinFig.2.21a.Inthesmallsignalmodelthisgeneratorwill
beinparallelwiththecurrentsourcesgmv GSandgmbv BS(Fig.2.16).Itsvaluecanbechosenastherootmeansquare(RMS)noisecurrent,whichfromEqs.(2.26)
(2.28)is

Notethatthemeansquaresofthenoisecurrentsareadded,sincethedifferentnoisemechanismsarestatisticallyindependent.Alternatively,thenoisecanbe
representedbyitsgatereferredvoltagesource(Fig.2.21b),inserieswiththegateterminal.Thevalueofthesourceisin/gm,withingivenbyEq.(2.29).
2.8
CMOSProcess
TheCMOSprocessprovidesthemostflexibilitytothecircuitdesigner,duetotheavailabilityofcomplementaryMOSdevicesonthesamechip.Theoriginal
motivationfordevelopingtheCMOStechnologywastheneedforlowpowerandhighspeedlogicgatesfordigitalcircuits.Therequiredisolationbetweenthetwo
differentdevicetypesisaccomplishedbytheuseof"wells,"thatis,large,lowdopingleveldeepdiffusions,whichserveasthesubstratesforoneofthetwodevice
types.Asanexample,Fig.2.22showspartofannwellCMOSchip,wherehighresistivityptypesubstrateisusedforthenchanneldevices,anddiffusednwells
forthepchanneldevices.

Page45

Figure2.22
Devicestructurefabricatedinahighperformance
nwellCMOSprocess.

Aswillbeshowninlaterchapters,aCMOScircuitcanbeoperatedwithasinglepowersupply,anditcanbeusedtorealizehighspeed,highgain,lowpoweranalog
amplifierstages.Anadditionaladvantageisthatforthedevicesinthewell(inFig.2.22,thePMOStransistor),thesourcecanbeconnectedtothewell,thereby
eliminatingthebodyeffect,andifthedeviceisusedinanamplifier,increasingthegainofthecircuit.This,however,resultsinalargestraycapacitancebetweenthe
sourceandthesubstrate,duetothelargesizeofthewelltobodyinterface.AnotherimportantadvantageoftheCMOSprocessistheavailabilityoftransmission
gatesmadeofaparallelconnectionofcomplementarytransistorsthatcanbeusedasswitches.Whensuchtransmissiongatesareused,thesignalisnolongerlimited
toalevel,whichisathresholdvoltagebelowthatofthehighclocksignal,asisthecasewhensinglechannelswitchesareused.Inaddition,inCMOSchipsabipolar
transistorcanbefashionedfromasourcediffusion,thewell,andthesubstrate.Thiscanbeusedinanemitterfollowerbufferstage(describedlater),inabandgap
voltagereferencecircuit,andsoon.
Inadditiontotransistors,analogMOScircuitsusuallyrequireonchipcapacitors,andsometimesalsoonchipresistors.Inasilicongate"doublepoly"process,a
secondlayeroflowresistivitypolysiliconisavailableforuseasaninterconnectorfortheformationofafloatinggateformemoryapplications.Thesetwolayersof
polysiliconcanalsobeusedasthetopandbottomelectrodesofamonolithiccapacitor.Figure2.22showstheconstructionofacapacitorwithtwopolysilicon
electrodes.ResistorscanbecreatedonanMOSchipusingadiffusedorimplantedlayeronthesurfaceofthesubstrate.Sincethesheetresistanceoftheseresistive
layersisrelativelylow(typically25to70 forasquarelayer),thesizeoftheresistorsobtainableonareasonablysmallareaislimitedtoabout100k .Thehigher
resistivitywelldiffusionisalsoavailableasaresistor.Thisresistor,however,hasmuchhighervoltageandtemperaturecoefficientscomparedtodiffusedorimplanted
ones.
Problems
2.1.Apnjunctiondiodeisconnectedtoanexternalvoltagevintheforwarddirection(Fig.2.3).Reversingthepolarityofthevoltagereducesthecurrentbyafactor

Page46

Figure2.23
CircuitforProblem2.8.

106.AssumethatthediodesatisfiesEq.(2.1)andisatroomtemperature.Whatisv?
2.2.Forapnjunction(Fig.2.3),NA=ND=1016ions/cm3,|v|=5V,A=0.34mm2,andthemeasuredvalueofCis27pF.Howmuchisx d,thewidthofthe
depletionlayer?Howmuchis i?
2.3.UsingthedefinitionR=1/( iD/ VDS),calculatethechannelresistanceofanNMOStransistorfrom(a)Eq.(2.6),(b)Eq.(2.7),and(c)Eq.(2.9).
2.4.ForanNMOStransistor,n=103cm2/Vs,thethicknessofthegateoxideis103(1=108cm),W=25m,andL=5m.Thethresholdvoltageis4V.
CalculateiDforv S=v B=0Vandv G=6V,and(a)v D=0.1V,(b)v D=2V,and(c)v D=4V.
2.5.RepeatthecalculationsofProblem2.4ifv S=0,v B=3V,and p=0.3V.Whatconclusionscanyoudrawfromyourresultsregardingthebodyeffect?
2.6.ForanNMOStransistor,k =2A/V2,W=30m,L=10m, p=0.3V, =1.5V ,and =0.03V1.Findtheincrementalconductancesgm,gd,andgmb
forv SB=0V,v 0DS=5V,andi0D=10A.RepeatyourcalculationsforvSB=2V!
2.7.AnNMOSswitchtransistorhasagatetosourcevoltagev GS>VT.Itsdrainisopencircuited.Howmuchisv DS?Why?
2.8.InthecircuitofFig.2.23,theswitchSisopenedatt=0.(a)Isthetransistoroperatinginitslinearorsaturationregion?(b)Neglectingbodyeffectandchannel
lengthmodulation,findv(t)bysolvingtheappropriatedifferentialequationforthecircuit.
2.9.InthecircuitofFig.2.24anoisevoltagev nisgeneratedduetothermaland

Figure2.24
CircuitforProblem2.9.

Page47

Figure2.25
CircuitforProblem2.10.

shotnoiseeffects.ForwhatvalueofRwillthetwonoisevoltagesv nTandv nSbeequal?

2.10.Calculatetheincrementalimpedance v/ iseenatnodeAofthecircuitsshowninFig.2.25.
2.11.ShowthatthetransconductancegminthesaturationregionisequaltothedrainconductanceinthetrioderegionforagivendeviceandafixedVG.
References
1.R.S.MullerandT.I.Kamins,DeviceElectronicsforIntegratedCircuits,Wiley,NewYork,1977.
2.A.S.Grove,PhysicsandTechnologyofSemiconductorDevices,Wiley,NewYork,1967.
3.Y.P.TsividisandR.W.Ulmer,ACMOSvoltagereference,IEEEJ.SolidStateCircuits,SC13(6),774778(1978).
4.C.A.Laber,C.F.Rahim,S.F.Dryer,G.T.Uehara,P.T.Kwoh,andP.R.Gray,IEEEJ.SolidStateCircuits,SC22(2),181189(1987).
5.S.M.Sze(Ed.),VLSITechnology,McGrawHill,NewYork,1983.
6.M.B.DasandJ.M.Moore,IEEETrans.Electron.Devices,ED21(2),247257(1974).
7.P.R.GrayandR.G.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,Wiley,NewYork,1977.
8.P.R.GrayandD.A.Hodges,andR.W.Brodersen(Eds.),AnalogMOSIntegratedCircuits,IEEEPress,NewYork,1980.

Page48

Chapter3
BasicAnalogCMOSSubcircuits
InthischaptersomeofthebasicsubcircuitscommonlyutilizedinanalogMOSintegratedcircuitsareexamined.Theseblocksincludeavarietyofbiascircuits,current
mirrors,singlestageamplifiers,sourcefollowers,anddifferentialstages.Thesesubcircuitsaretypicallycombinedtosynthesizeamorecomplexcircuitfunction.The
operationalamplifierandcomparator,coveredinlaterchapters,areexamplesofhowsimplesubcircuitsarecombinedtoformmorecomplexfunctions.
ThefirstpartofthischaptercoversthesubjectofthebiascircuitsinCMOStechnologyandthecurrentmirrors.Next,theCMOSgainstageisintroduced,with
particularemphasisontheuseofactivedevicesasactiveloads.Thecurrentmirrorsubcircuitcoveredasabiasingelementisutilizedasadynamicloadtoobtain
veryhighvoltagegainsfromasinglestageamplifier.Thedifferentialamplifier,whichrepresentsabroadclassofcircuits,isdiscussednext.Thedifferentialamplifieris
oneofthemostwidelyusedgainstages,whosebasicfunctionistoamplifythedifferencebetweentwoinputsignals.Finally,thelastpartofthechapterdealswiththe
smallsignalanalysisandfrequencyresponseofCMOSamplifierstages.Agoodunderstandingofthetopicspresentedinthischapterisessentialfortheanalog
CMOSdesigner,asmostdesignsstartatthesubcircuitlevelandprogressupwardtorealizeamorecomplexfunction.
3.1
BiasCircuitsinMOSTechnology
Opampandamplifierstages,describedindetaillater,needvariousdcbiasvoltagesandcurrentsfortheiroperation.Anidealvoltageorcurrentbiasisindependentof
thedcpowersupplyvoltages(VDD>0andVSS 0)andoftemperature.
ToobtainthedcbiasvoltagesVo1,Vo2,...,Von,whereVSS<Vo1<Vo2<

Page49

Figure3.1
(a)DiodeconnectedNMOStransistor(b)currentvoltage
characteristicofdiodeconnectedtransistor.

Von<VDD,voltagedivisioncanbeused.PureresistivedividersareseldomusedinMOStechnologybecausetheresultingvoltagescannotbeuseddirectlytoestablish
biascurrentsinMOStransistors.Instead,combinationsofMOSFETsandresistorsareoftenused.AMOStransistorwithitsgateconnectedtothedrainformsa
twoterminaldevice,asshowninFig.3.1a.ItscurrentvoltagecharacteristicsareshowninFig.3.1b.SinceVDS=VGS,thedynamicresistancerdsischaracterizedby

Therefore,ausefulapproximationvalidforlowfrequencies,smallsignals,andnegligiblesubstrateeffectsisthatthedevicebehaveslikearesistorofvalue1/gm.Any
numberofnandpchanneldevicesandresistorscanbecombinedtoformavoltagedivider,asshowninFig.3.2,wherebothnandpchanneltransistorsareused

Figure3.2
Voltagedivider
basedbiascircuit.

Page50

andVSS=0ischosen.SinceVGS=VDShereforbothdevices,theconditionforsaturation,

issatisfied.Hencethecommonvalueofthedraincurrentsisgivenapproximatelyby

HereIbiasisusuallyspecifiedthenVo1andVo2canbeselectedandEq.(3.3)usedtofindtheW/LratiosofthedevicesandthevalueRoftheresistor.
AnundesirablefeatureofthisconfigurationisthatthebiasvoltagesandcurrentdependonthesupplyvoltagesVDDandVSS.Infact,thebiascurrentincreasesrapidly
withincreasingpowersupplyvoltage.Sincesuchbiasstringsareusedtoprovidebiasforotherdevicesinthecircuit,thedcpowerconsumptionoftheoverallcircuit
becomesheavilydependentonthesupplyvoltages.
ACMOScircuitwith(theoretically)perfectsupplyindependenceisshowninFig.3.3.IfQ3andQ4arematchedtransistorssothat(W/L)3=(W/L)4,theyideallycarry
equalcurrents.Choosing(W/L)1=(W/L)2willthenresultinVGS1=VGS2,

Figure3.3
VTreferencedsupply
independentCMOS
biassource.

Page51

andthevoltageacrosstheresistor,IbiasR,willbeequaltoVGS0.Thisequilibriumconditionleadstotheequation

Equation(3.4),whichisindependentofVDD,canbesolvedtoobtainIbias.Notethatinthisanalysisweneglectedtheeffectsofchannellengthmodulation(i.e.,we
assumedthatIDisindependentofVDS).
AnalternativeversionofthebiascircuitshowninFig.3.3thatusesthebaseemittervoltage(VBE)ofabipolartransistorasthereferencevoltageisshowninFig.3.4a.
InaCMOSprocess,thesubstrate,well,andthesourcedrainjunctioninsidethewellcanbeusedtoformaverticalbipolartransistor.Forexample,Fig.3.4b

Figure3.4
(a)VBEbasedsupplyindependentbiascircuit
(b)verticalpnpbipolartransistorinannwell
CMOSprocess.

Page52

showsaverticalpnpdevicethatisformedinannwellprocess.Thecollectorofthispnpdeviceisthep substratethatispermanentlyconnectedtothemostnegative
voltageonthechip.Forthebipolartransistor,thecollectorcurrentisgivenby

whereVBEisthebaseemittervoltage,VT=kT/q,andIsisaconstantcurrent,whichisproportionaltothecrosssectionalareaoftheemitter,whichisusedtodescribe
thetransfercharacteristicofthetransistorintheforwardactiveregion.
InFig.3.4a,asinFig.3.3,if(W/L)1=(W/L)2and(W/L)3=(W/L)4,equalcurrentsareforcedthroughthetwobranchesofthebiascircuitandthevoltagedropacross
resistorRequalsVBE.Thusthebiascurrentisgivenby

CombiningEqs.(3.5)and(3.6),wehave

ThisequationcanbesolvediterativelyforIbias.
Bothsupplyindependentbiascircuitshaveasecondtrivialsteadystatecondition,cutoffwhenIbias=0.Topreventthebiascircuitfromsettlingtothewrongsteady
statecondition,astartupcircuitisnecessaryinallpracticalapplications.ThecircuittotherightofthedashedlineinFig.3.5functionsasastartupcircuit.IfIbias=0,Q5
isoffandthevoltageatnodeAishigh,causingQ6toturnonanddrawacurrentthroughQ3,forcingthecircuittomovetoitsotherequilibriumstate.Oncethecircuit
settlesinthedesiredstate,Q5turnsonandnodeAgoeslow,turningoffQ6.Atthisstatethestartupcircuitisessentiallyoutofthepicture.

Figure3.5
Supplyindependentbiascircuitwithstartup.

Page53

Anotherimportantperformanceaspectofthebiascircuitsistheirtemperaturedependence.Unfortunately,supplyindependentbiascircuitsarenotnecessarily
temperatureindependent,becausethebaseemittervoltage(VBE),andgatetosourcevoltage(VGS)arebothtemperaturedependent.IfthetemperaturecoefficientTCF
isdefinedastherelativechangeofthebiascurrentperdegreeCelsiustemperaturevariation,wehave[1]

UsingthedefinitionaboveandEq.(3.6),therelativetemperaturecoefficientoftheVBEbasedbiasgeneratorcanbecalculated:

Sincethetemperaturecoefficientofthebaseemitterjunctionvoltageisnegative(2mV/C)whileresistorstypicallyhaveapositivetemperaturecoefficient,thetwo
termsinEq.(3.9)add,resultinginanetTCFthatisquitehigh.ThetemperaturebehaviorofthethresholdbasedbiasgeneratorofFig.3.3issimilartotheVBEbased
circuit.
Analternativesupplyindependentbiasgeneratoristhe VBEbasedcircuitshowninFig.3.6a.Theoperationofthiscircuitisbasedonthedifferencebetweenthe
baseemittervoltagesoftwotransistorsoperatedatdifferentcurrentdensities.InFig.3.6a,asinFigs.3.3and3.4,(W/L)1=(W/L)2and(W/L)3=(W/L)4.Therefore,
equalcurrentsflowthroughthetwobranchesofthecircuitandVGS1=VGS2.Also,thepnptransistorM1,hasanemitterareathatismtimestheemitterareaof,M0.The
voltageacrosstheresistorRis VBE=VBE0VBE1.FromEq.(3.5),

VBEappearsacrossRandproducesacurrentofvalue

Obviously,theresultingbiascurrentisindependentofthepowersupplyVDD.Thiscircuitalsohastwooperatingstates:oneatthedesiredoperatingcurrentgivenby
Eq.(3.13)andtheotheratzero.Topreventthecircuitfromoperatinginthecutoffstate,astartupcircuitsimilartotheoneshowninFig.3.5isrequired.

Page54

Figure3.6
(a) VBEbasedsupply
independentbiasgenerator(b)
highperformance V based
BE

supplyindependentbiasgenerator.

ThetemperaturecoefficientofthebiascurrentcanbecalculatedfromEq.(3.13):

Page55

Since VT/ Tand R/ Tarebothpositive,thetwotermsinthetemperaturecoefficientstendtocanceleachother.ThuscomparedtoVBEorthresholdbasedbias

circuits,the VBEbasedbiascircuitcanproduceamuchsmallertemperaturecoefficient.
Onedrawbackofthe VBEbasedbiasgeneratoristhestrongdependenceofIbiasonthemismatchesbetweenQ3Q4andQ1Q2devicepairs.Themismatchbetween
Q3Q4willresultindifferentcurrentstoflowinthetwobranchesofthecircuit.If1+ representstheratioofthetwocurrents, VBEwillbecome

whichisequivalenttomodifyingm,theratiooftheemitterareas,by1+ .ThemismatchbetweenQ1andQ2andthecurrentdifferenceduetothemismatchofQ3and
Q4willmaketheVGSvaluesofQ1andQ2different.ThisisequivalenttoadcoffsetvoltageVos= VGS,whichmodifiesEq.(3.13)to

Assumingthatm=8, =0.01,andVT=26mVatroomtemperature, VBE=261n[8(1+0.01)]=54.3mVresults.Fora VGS=5mVoffsetvoltage,fromEq.

(3.17),Ibiaswillchangeby10%.ToreducethisvariationspecialcareshouldbetakeninthelayoutofQ1Q4.Forbettergeometricalmatching,thesedevicesshoulduse
acommoncentroidlayoutstrategy[2].
ThecurrentmatchingaccuracyofthebiasgeneratorofFig.3.6aisfurtherdegradedduetothemismatchbetweenthedraintosourcevoltagesofQ3Q4andQ1Q2
transistorpairs.Thecircuitcanbemadesymmetrical,andthedraintosourcevoltagedropsequalized,byaddingtransistorsQ5toQ8tothetwobranchesofthecircuit
(Fig.3.6b).Theimprovedconfigurationalsousesthecascodecurrentmirrorprinciple,describedinSection3.2,toimprovethepowersupplyrejection.Ontheother
hand,theminimumpowersupplyvoltageisincreasedcomparedtothecircuitofFig.3.6a,duetotheextravoltagedropsrequiredbythetwocascodedevices.This
becomesamajorshortcominginadvancedsubmicronprocesstechnologies,orinlowpower/lowvoltageapplicationswherethepowersupplyvoltageislimitedto
3.3V.
3.2
MOSCurrentMirrorsandCurrentSources
Aswillbeseeninlatersections,constantcurrentsourcesandcurrentmirrorsareimportantcomponentsinMOSamplifiers.TheMOScurrentsourcesarequite
similartothebipolarsources[1,3],wherethecurrentmirrorsworkontheprinciplethatidenticaldeviceswithequalgatetosourceanddraintosourcevoltagescarry
equal

Page56

Figure3.7
(a)nchannelcurrentmirror(b)outputvoltagecurrentrelationship
andusefuloutputrangeofthecurrentsource.

draincurrents.AnNMOSrealizationofacurrentmirrorisshowninFig.3.7a.InthiscircuitQ1isforcedtocarryacurrentI1,sinceitsinputresistanceatitsshorted
gatedrainterminalsislow(muchlowerthanr0),anditsgatepotentialVD1adjustsaccordingly.IfQ1andQ2areinsaturation,theirdraincurrentsI1andI2are
determinedtoalargeextentbytheirVGSvalues.SinceVGS1=VGS2=VG,thecondition

willthereforehold.Moreaccurately,sincedrainsaturationcurrentisgivenby

ifthetransistorshavethesame ,k andVT,then

ThecurrentI1isthus''mirrored"inI2.
UsingEq.(3.19)andignoringtheeffectof ,thegatevoltageVGisgivenby

Forthetransistorstooperateinthesaturationregion,VD VGVTmusthold.UsingEq.(3.21),therefore,thedrainsaturationvoltageis

whereVDsatistheminimumdrainvoltagethatkeepsthetransistorsinsaturation.

Page57

Figure3.8
SmallsignalequivalentcircuitoftheMOScurrentmirror.

FortheMOScurrentsourceofFig.3.7a,theoutputvoltagev outhastobegreaterthanVDsattokeepQ2inthesaturationregion.Figure3.7bshowstheoutputvoltage
currentrelationshipofthecurrentsourceofFig.3.7a.
Forsmallsignalanalysis,theequivalentcircuitofFig.2.14canbeusedtomodelQ1andQ2.TheresultingcircuitisshowninFig.3.8.Herer0istheincremental
resistanceofthecurrentsourceI1andv inisthetestvoltageconnectedtothedrainofQ2formeasuringtheoutputimpedanceofthecircuit.Thesmallsignaloutput
impedanceissimply

whereEq.(3.19)wasused.
Clearly,thecurrentsourceofFig.3.7ahasanoutputimpedancethatisnotbetter(i.e.,higher)thantheoutputimpedanceofasimpleMOStransistor,alsoinaccurate
currentmatchingduetothevariationofthedrainvoltageofQ2withtheoutputvoltage,andfinallyareasonablywideoutputvoltagerange,whichislimitedatthelower
endbyVDsat.
Theoutputimpedanceroutcanbeincreased,andthusthecircuitmadetoperformmorelikeanidealcurrentsource,byaddingonemoredeviceandmodifyingthe
connectionsslightly.Theresultingcircuit(Fig.3.9)istheMOSequivalentofWilson'scurrentsource[1,3].Inthiscircuit,ifI2increases,Q2causesv 1tobecome
larger.Thisresultsinadropofv 3whichthencounteractstheincreaseofI2.Thusanegativefeedbackloopexists,whichtriestoholdI2constant.Thesmallsignal

Figure3.9
MOSversionofWilson's
currentsource.

Page58

Figure3.10
SmallsignalequivalentcircuitofWilson'scurrentsource.

equivalentcircuitisshowninFig.3.10asimplifiedcircuitisshowninFig.3.11.Thelatterwasobtainedbycombiningr0andrd1into
by
replacingtheselfcontrolledcurrentsourcegm2v 2byaresistor1/gm2,andbyneglectingrd2,whichisnowparallelwiththe(usuallymuchsmaller)resistor1/gm2.Solving
foriininFig.3.11gives

Typicalvaluesforgmarearound1mA/V,whilerdisontheorderofhundredsofkiloohms.Hence

Then,fromEq.(3.24),

Here,ontherighthandsidethevalueofthefirstfactorisaround100,whilethatofthesecondisaround1.Hencetheoutputimpedanceroutistwoordersof
magnitudelargerthanrd3.TheoutputimpedanceofthecurrentsourcedropsassoonastransistorQ3entersthelinear(triode)region.Theminimumleveloftheoutput
voltageswingoftheWilson'scurrentsourceisthuslimitedtoVmin=VGS2+VDsat3.Insummary,thecharacteristicsofWilson'scurrentsourcearethefollowing:high
outputimpedance,restrictedoutputvoltageswing,andpoorcurrentmatchingaccuracy,duetothemismatchbetweenthedraintosourcevoltagesoftransistorsQ1
andQ2.

Figure3.11
Simplifiedsmallsignalequivalentcircuitof
Wilson'scurrentsource.

Page59

Figure3.12
ImprovedMOSWilson's
currentsource.

Thecircuitcanbemadesymmetrical,andthedrainsourcevoltagedropsofQ1andQ2equalized,byaddinganothertransistor,Q4(Fig.3.12).Itcaneasilybeshown
thattheoutputimpedanceoftheresultingimprovedMOSWilson'scurrentsourceisagaingivenbyEq.(3.25).Thedetailedanalysisofthecircuitislefttothereader
(Problem3.6a).
AslightlybetterversionofthecircuitofFig.3.12(oftencalledcascodecurrentsource)isshowninFig.3.13a.ItssmallsignalequivalentcircuitisshowninFig.
3.13bandinasimplifiedforminFig.3.13c.ThiscircuitalsousesfeedbacktomaintainI2constant,anditalsoequalizesthedrainpotentialsofQ1andQ2,thus
improvingthecurrentmatchingpropertiesofthecurrentmirror.Itcaneasilybeshown(Problem3.6b)thatnow

Hencethereisagaina100foldincreaseoverthesingleMOSFEToutputresistance.Inaddition,nowtheinternalimpedanceroofthecurrentsourceI1isinparallel
with1/gm1+1/gm4,alowinputimpedance,ratherthanwithrd1.Henceitsloadingeffectismuchreduced.
ThecascodecurrentsourceissimilartotheimprovedWilson'scurrentsource:Itischaracterizedbyhighoutputimpedanceandaccuratecurrentmirroringcapability.
However,acommondisadvantageofbothcircuitsisthattheminimumleveloftheoutputvoltageswingishigherthanthatofthesimplecurrentmirrorofFig.3.7.This
reducestheavailablevoltageswingofthestage(s)drivenbythemirror.ForthecircuitofFig.3.13,theminimumvoltageswingbeforeQ3makesthetransitionfromthe
saturationregiontothelinearregionis

Page60

Figure3.13
(a)Cascodecurrentsource(b)equivalentsmallsignalcircuit
ofthecascodecurrentsource(c)simplifiedsmallsignalcircuit
ofthecascodecurrentsource.

TheoutputvoltagecurrentplotforthecascodecurrentsourceisshowninFig.3.14.Theplotshowsthreeoperatingregions.IntheregionwherebothQ2andQ3are
insaturation(VD VT+2VDsat)theoutputimpedancehasthehighestvalue.IntheregionwhereQ2isinsaturationandQ3isthelinearregion(2VDsat VD<VT+2VDsat),
theoutputimpedanceissubstantiallylower.WhenVD<2VDsat,bothtransistorsareintheirlinearregions,andtheoutputimpedanceisverylow.

Page61

Figure3.14
Outputvoltagecurrentrelationshipforcascode
currentsource.

Asmentionedearlier,amajordrawbackofthecascodecurrentsourceisitslimitedoutputvoltageswing.AsEq.(3.27)shows,theminimumvoltageattheoutputof
thecurrentsourcethatkeepsbothQ2andQ3insaturationisnowVT+2VDsat.Thislossofvoltageswingisespeciallyimportantwhenthecurrentsourceisusedasthe
loadofagainstage.Toreducethelossandincreasetheoutputswing,wecanbiasthedrainofthelowertransistorQ2attheedgeofthesaturationregion.The
resultinghighswingcascodecurrentsourceisshowninFig.3.15[4].
Inthiscircuitasourcefollower(Q5andQ6)hasbeeninsertedbetweenthegatesofQ3andQ4inFig.3.13a,andtheW/LratioofQ3hasbeenreducedbyafactorof4.
UsingthesimplifiedMOSIVequationID=k W/L(VGSVT)2forthesaturationregion,andtheW/LratiosgiveninFig.3.15,wehave

Figure3.15
Highswingcascodecurrentsource.

Page62

Figure3.16
Highswingimprovedcurrentsource.

where

FromFig.3.15,thenodevoltagesVA,VB,andVDS2canbefound:

Q2isthereforebiasedattheedgeofsaturation.Thelowestleveloftheoutputvoltageswingisnowlimitedto2VDsat,whichisamajorimprovementcomparedtothatof
thecircuitofFig.3.13a.Thehighswingcascodecurrentsourceexhibitsahighoutputimpedance,similartothatofthecascodecurrentsource,andanimproved
outputvoltageswing.Thecurrentmatching,however,suffersduetothemismatchinthedraintosourcevoltagesofthemirrortransistorsQ1andQ2.ForQ1,VDS1=VT
+VDsat,whileforQ2,VDS2=VDsat.
Animprovedhighswingcascodecurrentsource,alongwithitsbiasingcircuit,isshowninFig.3.16.Herenisapositiveintegernumber[5,p.560].Onceagain,using
thesimplifiedMOSIVequationresultsin

where(VDsat)W/ListheminimumdraintosourcevoltagerequiredtokeepdevicesQ1andQ3withacurrentIandaspectratioW/Linsaturation.FordevicesQ3andQ5
wehave

Page63

UsingEq.(3.31)yields

Clearly,sinceVDS1=VDS2=(VDsat)W/L,bothQ1andQ2arebiasedattheedgeoftheirsaturationregions.Also,assumingthatVDS3=VT VDsat3=n(VDsat)W/L,Q3willbe
biasedinthesaturationregion.Asaresult,thecircuitwillhaveahighoutputimpedance.Noticethattheoutputnodev outhashighswingcapability.Actually,aslongas
v outisgreaterthan(n+1)(VDsat)W/L,theoutputwillmaintainitslargeoutputimpedance.FortheimprovedcurrentmirrorthedevicesQ1andQ2haveequalVGSaswellas
equalVDSvaluesandthereforegoodcurrentmatchingcapability.
Theformulasandnumericalestimatesgivenforthecurrentsourcesaresomewhatoptimisticsincetheyneglectthebodyeffectofthefloatingdevices(transistorsQ3
andQ4inFigs.3.13to3.16).Also,realMOStransistorsdonotdisplayanabrupttransitionfromthesaturationtolinearregion.Therefore,itisnecessarytobiasthe
drainvoltagesofthemirrordevicesQ1andQ2slightlyabovetheidealsaturationvoltageproducedby
derivedearlier.

toachievethehighoutputimpedance

3.3
MOSGainStages[68]
AsimpleNMOSgainstagewithresistiveloadisshowninFig.3.17.Q1isbiasedsothatitoperatesinitssaturationregion.Thelowfrequencysmallsignalequivalent
circuitisshowninFig.3.18.Thevoltagegainofthestageisclearly

Inintegratedcircuitrealization,theresistorRLisundesirablesinceitoccupiesalargeareaandintroducesalargevoltagedropandhenceisusuallyreplacedbya

Figure3.17
ResistiveloadMOS
gainstage.

Page64

Figure3.18
Smallsignallowfrequencyequivalent
circuitoftheresistiveloadgainstage.

secondMOSFET.IfanNMOSenhancementmodedeviceisusedasaload,thecircuitofFig.3.19results.ThedrainandgateofQ2areshortedtoensurethatv ds>
v gsVT,andhencethedeviceisinsaturation.ThesmallsignalequivalentcircuitoftheloaddeviceQ2aloneisshowninFig.3.20.Herethevoltagecontrolledcurrent
sourcegmv dsisacrossthevoltagev dshenceitbehavessimplyasaresistorofvalue1/gm.Similarly,sincev sb=v out,thesourcegmbv sbcorrespondstoaresistor1/|gmb|
[recallthatbyEq.(2.19),gmb<0!].Inconclusion,Q2behaveslikearesistorofvalue1/(gm2+|gmb2|+gd2).ReplacingRLinFig.3.17bythisresistorandneglectinggd1
andgd2incomparisonwithgm2+|gmb2|gives

Ifthebodyeffectissmall,sothat|gmb2| gm2,thenusingEq.(2.18),

results.Herethechannelmodulationterms

utilized.

ThesadmessageconveyedbyEq.(3.35)isthatalargegaincanbeobtainedonlyiftheaspectratioW/LofQ1ismanytimesthatofQ2.If,forexample,againof10is
required,(W/L)1=100(W/L)2musthold.Thisispossibleonlyifalargesiliconareaisused.Inaddition,thebodyeffectalsoreducesthegainsignificantly.

Figure3.19
Enhancementload
NMOSgainstage.

Page65

Figure3.20
Smallsignalequivalentcircuitofthe
enhancementloaddeviceQ2.

Includingbodyeffect(butstillneglectingchannellengthmodulation),usingEqs.(2.12),(2.19),and(3.34),

results.For| p|=0.3V,

,and =1,thedenominatoris1.21hencethegainisreducedfrom10to8.26.

Inconclusion,theNMOSenhancementloadgainstageprovidesalowgain.Thisstageisnonethelessoftenusefulinwidebandamplifiers,wherealowbutpredictable
gaincanbetoleratedandthegainstageexhibitsawidebandwidthduetothelowresistanceoftheload.Forhighgainapplications,however,thestageneedsalarge
siliconareaandsincetheloaddevicehasahighresistance(smallW/Lratio),ithasalargedcvoltagedropacrossitwhichreducesthesignalhandlingcapabilityand
hencethedynamicrangeofthestage.
ToimprovetheperformanceandincreasethegainoftheMOSamplifiers,acurrentsourceloadcanbeused.Anyofthecurrentsourcesdescribedintheearlier
sectionscanserveasaload.AcommonsourceMOSgainstagethatusesanNMOSinputdeviceandthepchannelversionofthesimplecurrentsourceofFig.3.7a
isshowninFig.3.21.TheoperationofthiscircuitissimilartotheresistiveloadgainstageofFig.3.17,buttheresistiveloadisreplacedbythesmallsignaloutput
impedancerd2ofthePMOScurrentsource.UsingEq.(3.33),thegainoftheCMOSamplifiesstageis

Forgm1=0.2mA/Vandrd1=rd2=1M ,thesmallsignallowfrequencygainisAv=100.Obviously,thegainisproportionaltothetransconductanceofthe

Figure3.21
Commonsourcegain
stagewithNMOSinput
andpchannelcurrent
sourceasactiveload.

Page66

Figure3.22
Enhancementloadgainstage
withcapacitiveload.

inputdeviceandthesmallsignaloutputresistanceofthestager0=rd1||rd2.Since
foragivensizeoftheloaddevice,largevaluesofgaincanbeachievedina
moderatelysmallsiliconarea.Usingacascodecurrentsourcewithsignificantlyhigheroutputimpedancewillnotincreasethegainoftheamplifierdirectly,becausethe
outputresistanceofthestageislimitedbytheoutputimpedanceoftheinputdevice.
ForthegainstageofFig.3.21tooperateproperly,bothinputandloaddevicesshouldoperateintheirsaturationregions.TheoutputsignalswingisthuslimitedtoVDD
|VDsat2|andVDsat1onthepositiveandnegativeside,respectively.Theoutputsignalmustthereforeremainintherange

andthetotaloutputswingis

Forhighfrequencyapplications,allgainstagesdiscussedsofarhaveacommonshortcoming.ConsiderthecircuitofFig.3.22,whichincludesthesourceresistanceRS
andthecapacitiveloadCLofthegainstage.Includingtheparasiticcapacitancesinthesmallsignalequivalentcircuit,thediagramshowninFig.3.23aisobtained.
Combiningparallelconnectedelements,thecircuitofFig.3.23bresults,where

ThenodeequationsfornodesAandBare

whereallvoltagesareLaplacetransformedfunctions.

Page67

Figure3.23
(a)EquivalentcircuitoftheMOSgainstage
(b)simplifiedequivalentcircuitoftheMOSgainstage.

SolvingEq.(3.41)gives

Toobtainthefrequencyresponse,smustbereplacedbyj .Formoderatefrequencies,

hold.Thenagoodapproximationis

Page68

Figure3.24
Approximateequivalentcircuitofthe
MOSgainstage.

HereA0v=g m1/GLeqisthedcvalueofAv(j ),and

Av(j )inEq.(3.43)canberecognizedasthetransferfunctionofthecircuitshowninFig.3.24.ThusthecapacitorCgd1whichisconnectedbetweentheinputand
outputterminalsofthegainstage(Fig.3.23a)behaveslikeacapacitance
reducedbythisphenomenon.

thehighfrequencygainwillbeseriouslyaffectedandthebandwidthconsiderably

TopreventtheMillereffect,thecascodegainstageofFig.3.25canbeused.HereQ2isusedtoisolatetheinputandoutputnodes.Itprovidesalowinputresistance
1/gm2atitssourceandahighoneatitsdraintodriveQ3.Ignoringthebodyeffect,thelowfrequencysmallsignalequivalentcircuitisintheformshowninFig.3.26.
Neglectingthesmallgdadmittances,clearly

Hence,forlowfrequencies,

Figure3.25
Cascodegainstagewith
enhancementload.

Page69

Figure3.26
Lowfrequencysmallsignalcircuitof
cascodegainstage.

ThegatetodraingainofQ1isgm1/gm2,andthereforetheCgd1ofthedrivertransistorQ1isnowmultipliedby(1+gm1/gm2).Choosinggm1=gm2,thisfactorisonly2.
Theoverallvoltagegaingm1/gm3,however,canstillbelarge,withoutintroducingsignificantMillereffect,sincethereisnoappreciablecapacitancebetweentheinput
andoutputterminals.
Asbefore,thegainofthecascodegainstagecanbeincreasedbyusingacurrentmirrorasanactiveloaddevice.Acascodeamplifierwithapchannelcurrentsource
asactiveloadisshowninFig.3.27.Itcanreadilybeshownthatthelowfrequencyvoltagegainofthiscircuitisgivenby

where,asderivedearlier[cf.Eqs.(3.23)and(3.26)],

Thevalueofrout2ismuchlargerthanrout1becauseofthelocalfeedback.Theeffectiveoutputimpedanceisthereforegivenby

andthegainofthestageis

Figure3.27
Cascodestagewithpchannel
currentsourceasactiveload.

Page70

Figure3.28
Cascodestagewithpchannel
cascodecurrentsourceas
activeload.

Toexploitfullytheavailabilityofthehighoutputimpedancerout2forhighgain,acascodecurrentsourcemustbeusedfortheactiveload.Acascodegainstagewitha
pchannelcascodecurrentsourceasactiveloadisshowninFig.3.28.Thevalueoftheloadresistancerout1isgivenby

Assumingthatrout1=rout2,wehave

andthegainisgivenby

Sinceroismuchlargerthanro3,thegainAvcanbemuchlargerthanthegainofastagewithasimplecurrentsource.
Toimprovetheoutputsignalswing,abiasingstrategysimilartothehighswingcascodecurrentsourceshouldbeused,sothatbothQ1andQ3arebiasedonlyslightly
abovethesaturationregion.Themaximumoutputsignalswingisgivenby

TheuseofacascodecurrentsourceasanactiveloadinthegainstageofFig.3.28providesahighvoltagegainthatissufficientforthemajorityoftheapplications.

Page71

Figure3.29
Gainstagewithdoublecascode
inputanddoublecascodeload.

However,incaseswhereanextremelyhighgainisrequired,thecascodingconceptforthecurrentsourcescanbeextendedbystackingmoredevicesinthecascode
configuration,whichincreasestheoutputimpedanceandhencethevoltagegain.AdoublecascodegainstagewithdoublecascodeactiveloadisshowninFig.3.29.
ComparedtoFig.3.28,twoadditionaldevicesinacommongateconfigurationhavebeenaddedtothecascodeinputandcascodeload.Usingtheresultsexpressed
inEq.(3.51),theoutputimpedancerout3canbecalculatedas

CombiningEqs.(3.51)and(3.55),wehave

Similarly,rout4canbecalculatedas

Onceagainifweassumethatrout3 rout4,thevoltagegainbecomes

Theresultinggainisquitehighandisproportionaltogmroraisedtothethirdpower.Thehighgainisachievedatthecostofreducedoutputswing.Tomaximizethe

Page72

outputvoltageswing,onceagainQ1,Q2,Q3,andQ4shouldbebiasedslightlyabovethesaturationregion.Thebiasvoltagesarethereforegivenby

SimilarequationscanbederivedforVbias3andVbias4.Usingtheseresults,themaximumoutputsignalswingislimitedtothefollowingrange:

AnothertechniquetoimprovetheoutputimpedanceofthecascodecurrentsourceofFig.3.28istoplaceQ2inafeedbackloopthatsensesthedrainvoltageofQ1
andadjustthegateofQ2tominimizethevariationofthedraincurrent.AsimplifiedformofthiscircuitisshowninFig.3.30,wherethegainstagereducesthefeedback
fromthedrainofQ2tothedrainofQ1[9].Thustheoutputimpedanceofthecircuitisincreasedbythegainoftheadditionalgainstage,A:

Similarly,theoutputimpedancerout1canbecalculatedas

Assumingthatrout1 rout2,thevoltagegainofthestageisgivenby

whichhasbeenincreasedbyseveralordersofmagnitude.
AsimpleimplementationofthecircuitofFig.3.30isshowninFig.3.31,wherethefeedbackamplifierisrealizedasacommonsourceamplifierconsistingoftransistor
Q5andthecorrespondingcurrentsourceIB1[10].TheoperationprincipleofthecircuitofFig.3.31isdescribedbrieflyasfollows.ThetransistorQ1convertstheinput
voltagev iintoadraincurrentthatflowsthroughQ1andQ2totheoutputterminal.ForhighoutputimpedancethedrainvoltageofQ1mustbekeptstable.Thisis
accomplishedbythefeedbackloopconsistingoftheamplifier(Q5andIB1)andQ2asasourcefollower.InthiswaythedrainsourcevoltageofQ1isregulatedtoa
fixedvalue.ThedisadvantageofthecircuitofFig.3.31isthatitlimitstheoutputswing,becausethedrainvoltageofQ1isVGS5,whereasitcanbeaslowasVDsat1=
VGS1VT.Additionally,thegatetodraincapacitanceofQ5multiplied

Page73

Figure3.30
Cascodegainstagewith
enhancedoutputimpedance.

bythegainofthefeedbackamplifier(Q5andIB1)formsalowfrequencypolewith1/gm2,whichdegradesthehighfrequencyperformanceofthemainamplifierstage.
Foldedcascodeopamps,presentedinChapter4,canbeusedforthefeedbackamplifier.OneexampleofthistypeofimplementationisshowninFig.3.32,where
PMOSandNMOSinputfoldedcascodeopampshavebeenusedtoenhancetheoutputimpedanceoftheNMOSandPMOScascodestages[9].Tomaximizethe
outputvoltageswing,Vbias1=VGS1VTnandVbias3=VDD+(VGS4VTp)shouldhold.FoldedcascodeopampsaredescribedindetailinChapter4.

Figure3.31
SimpleimplementationofFig.3.30.

Page74

Figure3.32
Completecircuitdiagramofagainenhancedcascode
amplifieremployingfoldedcascodeopampsas
feedbackamplifiers.

3.4
MOSSourceFollowers[58]
MOSsourcefollowersaresimilartobipolaremitterfollowers.Theycanbeusedasbuffersorasdclevelshifters.Thebasicsourcefollower,withanNMOSinput
deviceandanNMOScurrentsourceasanactiveload,isshowninFig.3.33anditssmallsignallowfrequencyequivalentcircuitinFig.3.34.Thenodecurrent
equationfortheoutputnodeis

Substitutingv gs1=v inv outandsolvingyields

Page75

Figure3.33
BasicstructureofMOS
sourcefollower.

Theoutputimpedanceofthesourcefollowercanbecalculatedbyapplyingatestsourcev xatitsoutput(Fig.3.35).Thecurrentlawgives

Herev gs1=v x,andhenceEq.(3.67)gives

sinceusually

and|gmb1|.ThusRouthasarelativelylowvalue,ontheorderof1k .

ThedcbiascurrentofthestageisdeterminedbythecurrentsourceQ2,whichdrivesQ1atitslowimpedancesourceterminal.ThusthedcdropVGS1betweentheinput
andoutputterminalsisdeterminedbyVbiasandthedimensionsofQ1andQ2theseparameterscanbeusedtocontrolthelevelshiftprovidedbythestage.
ThegateoftheloaddeviceQ2maybeconnectedtoitsdraintoeliminatethe

Figure3.34
Smallsignallowfrequency
equivalentcircuitofthe
sourcefollower.

Page76

Figure3.35
Equivalentcircuittocalculatetheoutput
impedanceofthesourcefollower.

gatebiasvoltage(Fig.3.36).Analysisshowsthatfor gm2,whichasdiscussedinconnectionwithFig.3.35,requiresalargeareaforthestage.Hencethisstageis
rarelyused.
Thelargesignaloperationofthecircuitcanbeanalyzedsimplyiftheloaddeviceisregardedasacurrentsource.Figure3.37showstheredrawncircuitroisthe
averagelargesignaloutputresistanceofthecurrentsourceandRListheloadresistor.FromEq.(2.9),ignoringthebodyeffect,

sothatthecircuitoperatesasalinearbufferwithaconstantoffset.Toachievethis,(W/L)1mustbesufficientlylarge.
Amajordisadvantageofthisstageisthefollowing.Ifv out<0,theloadsupplies

Figure3.36
Enhancementload
sourcefollower.

Page77

Figure3.37
Sourcefollowerwithacurrent
sourceasload.

currenttotheoutputstage.However,thelattercansink(absorb)anoutputcurrentonlyifitislessthanIo.Thisrepresentsaseriouslimitation.Also,forv out>0,Q1
mustsupplytheoutputcurrentplusIo.Inaddition,thereisavoltagedropgreaterthenVT1betweentheinputandoutputterminals.Thusifv incomesfromagainstage
suchasthatshowninFig.3.19,wheretheoutputvoltagemustbelessthanVDDVT2,themaximumpositiveoutputvoltageswingisVDD2VT.Thenegativeswingis
limitedbytherequirementthatthedevice(s)inthecurrentsourcemustremaininsaturationforthesmallestoutputvoltage.
3.5
MOSDifferentialAmplifiers
Theinputstageofanoperationalamplifiermustprovideahighinputimpedance,largecommonmoderejectionratio(CMRR)andpowersupplyrejectionratio
(PSRR),lowdcoffsetvoltageandnoise,andmost(orall)oftheopamp'svoltagegain(accuratedefinitionsofthesetermsaregiveninChapter4).Theoutputsignal
oftheinputstageismuchlargerthantheinputoneandsoisnolongerassensitivetonoiseandoffsetvoltagegeneratedinthefollowingstages.(Notethatalarge
commonmoderejectionisdesirableevenifthenoninvertingterminalisgroundedinnormaloperation,tosuppressnoiseinthegroundline.)
TherequirementsabovecanoftenbemetbyusingthesourcecoupledstageshowninFig.3.38.Sincethiscircuitoperatesinadifferentialmode,itcanprovidehigh
differentialgainalongwithalowcommonmodegainandhenceensurealargeCMRR.ThedifferentialconfigurationalsohelpsinachievingalargePSRR,since
variationsofVDDare,toalargeextent,canceledinthedifferentialoutputvoltagev o1v o2.
Anapproximateanalysisoftheamplifiercanreadilybeperformed.WeassumethatthecurrentsourceIisideal,thatis,thatitsinternalconductancegiszero.Wealso
assumeidealsymmetrybetweenQ1andQ2andQ3andQ4,andalldevicesoperateinsaturation.Thentheincrementaldraincurrentssatisfyid1 gmi(v in1v),id2 gmi
(v in2v),andid1+id2 0.Thisgivesv (v in1+v in2)/2forthe

Page78

Figure3.38
Sourcecoupleddifferentialstagewith
diodeconnectedNMOSloaddevices.

sourcevoltagesofQ1andQ2,andid1 id2 gmi(v in1v in2)/2fortheirdraincurrents.Hencetheoutputvoltagesarev o1 v o2=id1/gl=gmi(v in1v in2)/2gl,wheregl

istheloadconductance.Definingthedifferentialgainby
v o2)/(v in1v in2),weobtainthesimpleresultAdm gmi/gl.Thusthedifferentialgainisthesameas
forasimpleinverterhowever,thestagealsoprovidesarejectionofcommonmodesignalsandofnoiseinthepowersuppliesVDDandVSS,allofwhicharecanceled
(or,foractualcircuits,reduced)bythedifferentialoperationofthestage.Amoredetailedanalysisfollows.
ThelowfrequencysmallsignalequivalentcircuitofthesourcecoupledstageisshowninFig.3.39.Inthecircuit,thebodyeffecttransconductancesoftheinput
devicesQ1andQ2areignoredtosimplifythediscussions.Itwillalsobeassumedthatthecircuitisperfectlysymmetrical,sothattheparametersofQ1andQ2are
identical,asarethoseofQ3andQ4.TheloadconductanceglofQ3andQ4canbefoundaswasdoneinconnectionwithFig.3.20:theresultis

Figure3.39
Smallsignalequivalentcircuitofthe
sourcecoupledpair.

Page79

ApplyingthecurrentlawatnodesAandB,

result.(Herethesubscriptsiandlrefertotheinputandloaddevices,respectively.)ThecurrentlawatnodeCgives

Equations(3.72)and(3.73)representthreeequationsinthethreeunknownsv o1,v o2,andv.Solvingthemforv o1andv o2,weget

Thedifferentialandcommonmodeinputvoltagesare

Thedifferentialandcommonmodeoutputvoltagescanbedefinedsimilarly:

ThenthedifferentialmodegaincanbeobtainedfromEq.(3.74):

Page80

Forg=0andgdi gl,Adm gmi/gl,aspredictedearlier.Similarly,thecommonmodegaincanbefound:

Hencethecommonmoderejectionratiois

Normally,g,gdi gl,gmi,andapproximations

canbeused.Clearly,toobtainalargeCMRR,gmustbesmallthatis,thecurrentsourceshouldhavealargeoutputimpedance.Thecircuitsdescribedearlierand
showninFigs.3.7to3.16aresuitabletoachievethis.All,however,requireadcvoltagedropforoperationwhichlimitstheachievableoutputvoltageswing.
AsEq.(3.80)indicates,withthedescribedapproximation(includingtheassumedabsenceofthebodyeffect),thedifferentialgaincanbeobtainedfrom

Obviously,alargegaincanbeachievedonlyiftheaspectratio(W/L)ioftheinputdevicesismanytimesthatoftheloaddevices(W/L)l.Asomewhatimprovedversion
ofthedifferentialstageofFig.3.38canbeobtainedbyusingPMOSdevicesQ3andQ4asloads(Fig.3.40).ForthiscircuitEqs.(3.77)to(3.80)remainvalid
however,thedifferentialgainAdmislargerandisgivenby

wherenandparethemobilitiesoftheNMOSandPMOSdevices,respectively.
ThegainofthedifferentialstageofFig.3.40canbeincreasedbyusingacon

Page81

Figure3.40
SourcecoupledCMOSdifferentialstage
withdiodeconnectedPMOSloaddevices.

trolledamountofpositivefeedbacktoincreasethetransconductanceoftheinputdevice[11].TheresultingcircuitisshowninFig.3.41andthedifferentialgaincanbe
derivedas

where =(W/L)5/(W/L)3.Asanexample,if =,thedifferentialgainwillbeincreasedbyafactorof4.

Allthedifferentialstagesdescribedthusfarhavelowgainandadifferentialoutputvoltage.ForhighgainthecircuitofFig.3.42acanbeused.Thiscircuithas
differentialinputbutsingleendedoutput.Henceitperformsasacombinationofadifferentialgainstageandadifferentialtosingleendedconverter.InFig.3.42a
transistorsQ1Q2andQ3Q4formmatchedtransistorpairs.TheyhaveequalW/Lratios.AllcurrentlevelsaredeterminedbythecurrentsourceIo,halfofwhichflows
throughQ1Q3andtheotherhalfflowsthroughQ2Q4.Alltransistorshavetheirsubstratesconnectedtotheirsourcestoeliminatebodyeffectandimprovematching.

Figure3.41
SourcecoupledCMOSdifferentialstage
withpositivefeedbacktoincreasegain.

Page82

Figure3.42
(a)CMOSdifferentialstagewithactiveload(b)small
signalequivalentcircuitforCMOSdifferentialstage.

Anapproximateanalysisofthecircuitcanreadilybeperformedasfollows.AssumingthatthecurrentsourceI0isideal,theincrementaldraincurrentsofQ1andQ2
mustsatisfyid1+id2=0.Also,ifbothQ1andQ2areinsaturation,thenid1 gmi(v in1v 1)andid2 gmi(v in2v 1).Combiningtheseequations,v 1 (v in1+v in2)/2results.
Henceid1=id2 gmi(v in1v in1)/2.Thecurrentid1iseasilyimposedonQ3byQ1,sincetheimpedanceatthecommonterminalofthegateanddrainofQ3isonly1/gm3.
TransistorsQ3andQ4formacurrentmirrorsimilartothatshowninFig.3.7a,andhencethecurrentthroughQ4satisfiesid4=id3=id1.ThusbothQ2andQ4senda
currentid1=gmi(v in1v in2)/2intotheoutputterminal.SincetheoutputisloadedbythedrainresistancesofQ2andQ4,thedifferentialgainisthus
gmi/(gdi+gdl).Amoreexactanalysisfollowsnext.

v out/(v in1v in2)

ThesmallsignalequivalentcircuitofthestageisshowninFig.3.42b.ItwasdrawnundertheassumptionthatbothinputdevicesQ1andQ2havethesame
conductancesgmiandgdi,andthatbothloaddeviceshavetheparametersgmlandgdlalso,

Page83

thatseparate''wells"areprovidedforthePMOSdevices.Thenv BS=0foralldevices,andhencenobodyeffectoccurs.Theoutputconductanceofthecurrent
sourceisdenotedbygo.
WritingandsolvingthecurrentlawequationsfornodesA,B,andC(Problem3.11),weobtain

where
D=(gdi+gmi)[gdlgdi+2gml(gdl+gdi)]+go(gdi+gml)(gdl+gdi).
Wedefine,asbefore,thedifferentialandcommonmodeinputsignalsbyEq.(3.75).ThenthedifferentialgainAdmandthecommonmodegainAcmcanbedefinedby

FromEqs.(3.84)and(3.85),

Forgmi,gml go,gdi,andgdl,theapproximations

canbeused.NotethatAdmisthesameasthatobtainablefromaCMOSdifferentialinput/differentialoutputstage(Problem3.12).Thusthesingleendedoutputsignal

Page84

Figure3.43
Equivalentcircuitoftheoutputimpedance
oftheCMOSdifferentialstage.

doesnotresultinlowergainforthestage.Bycontrast,theCMRRishigherbyafactorofgml/gdi,which(forusualvalues)ismuchgreaterthan1.
TocalculatethesmallsignaloutputimpedanceoftheCMOSstage,atestsourceiocanbeappliedattheoutputofthesmallsignalequivalentcircuitandtheinput
voltagesv in1andv in2settozero(Fig.3.43).Analysisshows(Problem3.13)that

whereDisdefinedinEq.(3.84).
Forgmi,gml go,gdi,gdl,theapproximation

canbeused.
3.6
FrequencyResponseofMOSAmplifierStages
Inprevioussectionsthelinearized(smallsignal)performanceofMOSamplifierstageswasanalyzedatlowfrequencies.Thustheparasiticcapacitancesillustratedin
theequivalentcircuitofFig.2.16wereignored.Forhighfrequencysignals,however,theadmittancesofthesebranchesarenolongernegligible,andhenceneitherare
thecurrentswhichtheyconduct.Thenthegainsandtheinputimpedancesofthevariouscircuitsallbecomefunctionsofthesignalfrequency .Theseeffectsare
analyzednext.
ConsideragaintheallNMOSsingleendedamplifier(Fig.3.22),discussedinSection3.3.UsingtheequivalentcircuitofFig.2.16,thehighfrequencysmallsignal
equivalentcircuitofFig.3.23aresulted.Inthecircuit,Rsistheoutputimpedanceof

Page85

Figure3.44
SimplifiedequivalentcircuitoftheMOSgainstage
usingMiller'stheorem.

thesignalsourceandCListheloadcapacitance.ThiscircuitwasthensimplifiedtothatofFig.3.23b,which(intheLaplacetransformdomain)wasshowntohavethe
frequencyresponsegiveninEq.(3.42).Withtheapproximationsgm1 (Cgd1+CLeq),thefrequencyresponseofEq.(3.49)resulted.Itcorrespondedtothe
simplifiedequivalentcircuitofFig.3.24,whichwasthenusedtointroducetheMillereffect.
TheaccuracyofthesimplifiedcircuitcanbeimprovedbyrestoringthetwocapacitancesCLeqandCgd1whichloadtheoutputnodeintheexactcircuitofFig.3.23b.
Also,inthenumeratorofEq.(3.42),thetermsCgd1wasneglectedincomparisonwithgm1.Athigherfrequencies,thisisnolongerjustified.TorestorethesCgd1term,
thegainofthecontrolledsourcegm1canbechangedtogm1sCgd1intheequivalentcircuit.TheresultingcircuitisshowninFig.3.44.Thecorrespondingtransfer
functionis

whereCinisgivenbyEq.(3.44).Thisfunctionhasarighthalfplane(positive)realzeroat

andtwolefthalfplane(negative)polesat

Normally,Cgd1issmall.Hencesz |sp1|.Thensp1isclosesttothej axisandisthereforethedominantpoleofthecircuit.

Page86

ThefrequencyresponseAv(j )canbeobtainedsimplybyreplacingsbyj in(3.91).Itcanbearrangedintheform

If|sp1|

timesitsdcvalue)is

Forhighgain,anactive(currentsource)loadcanbeused.ACMOSgainstagewithapchannelcurrentsourceasactiveloadandcapacitiveloadingisshowninFig.
3.45athecorrespondinghighfrequencylinearequivalentcircuitinFig.3.45b.Defining

thesimplifiedcircuitofFig.3.45cresults.
UsingtheapproximationyieldingFig.3.44fortheNMOSgainstage,thecircuitofFig.3.45dcanbeobtained.Obviously,thecircuitinFig.3.45disidenticaltothatin
Fig.3.44d,andhencethetransferfunctionofEq.(3.91)isalsovalidforthecircuitofFig.3.45d.ThepolesandthezeroarealsogivenbyEqs.(3.92)and(3.93).The
dominantpoleisnormallysp1=Gs/Cin.Notice,however,thatGLeqinFig.3.45isgd1+gd2,whileinFig.3.44itisgd1+gd2+gm2+gmb2.Sincetheformerismuch
smaller,sp2forthecircuitofFig.3.45isatamuchlowerfrequencythanthatofFig.3.44.
Figure3.46ashowsaCMOScascodegainstagewithanactiveload.CLrepresentsthecapacitiveloadofthestage.Figure3.46bandcshowthedetailedand
simplifiedhighfrequencylinearizedequivalentcircuits,respectively.UsingMiller'stheorem,thecircuitofFig.3.46dresults,where

Page87

Figure3.45
(a)CMOSgainstagewithactiveloadandcapacitiveloading
(b)equivalentcircuitoftheCMOSgainstage(c)simplified
equivalentcircuitofCMOSgainstage(d)simplified
equivalentcircuitofCMOSgainstageusingMiller'stheorem.

Page88

Figure3.46
(a)Activeloadcascodestagewithcapacitiveloading(b)high
frequencyequivalentcircuitofthecascodestage(c)simplified
highfrequencyequivalentcircuitofthecascodestage(d)simplified
equivalentcircuitofthecascodestageobtainedusingMiller'stheorem.

Page89

ThecircuitofFig.3.46dcaneasilybeanalyzed(thankstotheMillerapproximation,whichneatlypartitioneditintobufferedsections).Theresultis

fromwhichthezeroandthepolescanberecognizeddirectly:

Forpracticalvalues,usually

Thensp1isthedominantpole,andthe3dBfrequencyisgivenby

Typically,gm1=gm2thenC1=Cgs1+2Cgd1andf 3dB Gs/[2 (Cgs1+2Cgd1)].Bycontrast,forthesimpleinverterstageofFig.3.45athecorrespondingvalueisGs/{2

[Cgs1+(1+gm1/GLeq)Cgd1]},asEqs.(3.91)and(3.52)show.Sincegm1/GLeqisthemagnitudeofthedcgainofthestage,itisusuallylarge.Hencethedominantpole
(andthusthe3dBfrequency)ismuchsmallerforthesimplegainstagethanforthecascodecircuit.Thisconfirmstheeffectivenessofthelatterforhighfrequency
amplification.
TheanalysisoftheNMOSsourcefollowerisstraightforward.Figure3.47ashowstheactualcircuitFig.3.47bandcshowthehighfrequencysmallsignalequivalent
circuits.Thetransferfunctioncanbereadilyderived(Problem3.15)theresultis

Page90

Figure3.47
(a)NMOSsourcefollowerwithcapacitiveloading
(b)equivalentcircuitoftheNMOSsourcefollower
(c)simplifiedequivalentcircuitoftheNMOS
sourcefollower.

Page91

Figure3.48
CMOSdifferentialstagewithcapacitive
loading.CircuitforProblem3.2.

Thezeroandthepolearehence

ChoosingGLeq/gm1 Cgs1/(Cgs1+CLeq),andhencethegainisconstantuptoveryhighfrequencies,wherehigherordereffectscauseittodrop.Intheactual
implementation,inordertomeettheconditiononCLeq/Cgs1,itmaybenecessarytoconnectacapacitorCinparallelwithCgs1,thatis,betweentheinputandoutput
terminals.ThenCgs1shouldbereplacedbyCgs1+Cintherelationsabove.
ThesmallsignalanalysisofthedifferentialamplifierstageofFig.3.42acan,inprinciple,beperformedsimilarly.Thusinthesmallsignalequivalentcircuitofeach
transistorthestraycapacitancescanbeincludedandanodalanalysisperformedintheLaplacetransformdomain.Theprocessbecomesquitecomplicated,however,
sincethenumbersofbothnodesandbranchesarehigh.
ConsidernowtheCMOSdifferentialstageshowninFig.3.48.IfonlyQ1hasaninputvoltage,whiletheoutputvoltageisusedonlyatnodeB,theloadcapacitances
usuallysatisfyCLB gm3.Bycontrast,theconductanceconnectedtonodeBisgd2+gd4,asmallvalue.HencethetimeconstantoftheadmittanceconnectedtonodeB,
=CLB/(gd2+gd4),islikely
B

Page92

tobeseveralordersofmagnitudelargerthanthatatnodeA, A CLA/gm3.ThetimeconstantatnodeCisalsosmall,sinceQ1andQ2loadthisnodewiththelarge
conductancegm1+gm2.
Clearly,inasituationlikethatrepresentedbythecircuitofFig.3.48,thegeneralnodalanalysisisverycomplicated.Thuseitheracomputerprogram(suchasSPICE)
thatcanperformthefrequencyanalysisoflinearizedMOScircuitsshouldbeusedorsomesimplifyingassumptionsmadeinthetheoreticalanalysis.Forthecircuitof
Fig.3.48,itwasverifiedabovethatthedominantpoleisthatcorrespondingtothelargesttimeconstant B:itsvalueis|sp1| (gd2+gd4)/CLB.Therefore,forexample,
thedifferentialmodevoltagegaincanbeapproximatedby

HereitwasassumedthatQ1andQ2aswellasQ3andQ4arematcheddevices,andEq.(3.88)wasused.The3dBfrequencycanalsobe(approximately)predicted
fromEq.(3.104)as(gdi+gdl)/2 CLB.
Thesameapproximationcanbeusedtofindthecommonmodevoltagegain:

Heregistheoutputconductanceofthecurrentsource.InaCMOSopamp,thecommonsourceofthepchanneldevicesistiedtoannwell.Thereisalargestray
capacitanceCbetweenthenwellandtheVDDlead,whichreducestheimpedancebetweennodeCandgroundathighfrequencies.TheeffectofCcanbe
incorporatedin(3.105)simplybyreplacinggbyg+sC.Then

results.Thezeroats=g/Cwillcause|ACm/Adm|toincreaseby20dB/decadeathighfrequencies,thuscausingareducedCMRR.
Problems
3.1.ForthecircuitofFig.3.49, =2V1/2,| p|=0.3V,VT=2V,VDD=10V,andVoi=2.5i,i=1,2,3.FindtheW/LvaluesforQ1,Q2,Q3,andQ4ifthecurrents
drawnatthenodesVo1,Vo2,Vo3,Vo4arenegligible.

Page93

Figure3.49
NMOSvoltagedivider.

3.2.DerivetheformulasfortheW/LratiosofFig.3.49ifthecurrentsdrawnatthenodesVo1,Vo2,andVo3arenotnegligible.
3.3.ProveEq.(3.7)forthecircuitofFig.3.3.
3.4.ProveEq.(3.25)forthecircuitofFig.3.11.
3.5.InFigs.3.10and3.11,assumethatro rd1andgm2=gm3.ShowthattheoutputresistanceisincreasedbytheopencircuitvoltagegainofQ1.
3.6.(a)ProvethatEq.(3.25)holdsforthecircuitofFig.3.12.(b)AnalyzethecircuitofFig.3.13.Howmuchisrout?ShowthattheoutputresistanceisthatofQ2,
magnifiedbythevoltagegainofQ3.
3.7.CalculatethegainofthecircuitofFig.3.23withoutneglectingtherdi.
3.8.ProveEqs.(3.56)and(3.57)forthecircuitofFig.3.29.
3.9.ProveEq.(3.64)forthecircuitofFig.3.30.
3.10.(a)Derivetherelationsforv o,dandv o,cofthesourcecoupledstage(Fig.3.38)ifthecircuitisnotexactlysymmetrical.(b)Rewriteyourrelationsintheform
v o,d=Addv in,d+AdcVin,c,
v o,c=Acdv in,d+Ac cVin,c.
WhatareAdd,Adc,andAcd,andAc c?(c)Letthemaximumdifferencebetweensymmetricallylocatedelementsinthesmallsignalequivalentcircuitbe1%.Howmuch
arethemaximumvaluesof|Acd|and|Adc|?

Page94

3.11.DeriveEq.(3.84)forthecircuitofFig.42a.(Hint:WriteandsolvethecurrentequationsfornodesA,B,andC.)
3.12.ModifytheCMOSdifferentialstageofFig.3.42sothatithasdifferentialoutputsignals.Comparethedifferentialgainwiththatoftheoriginalcircuit!
3.13.ProvethatthesmallsignaloutputimpedanceofthecircuitofFig.3.43isgivenbyEq.(3.89).(Hint:WriteandsolvethecurrentlawfornodesA,B,andC.)
3.14.AnalyzetheCMOSgainstageofFig.3.45intheLaplacedomain.(a)FindtheexacttransferfunctionAv(s)fromFig.3.45c.(b)UseMillereffectapproximation
toderivethesimplifiedcircuitofFig.3.45danalyzethesimplifiedcircuittoverifyEq.(3.91).
3.15.AnalyzetheNMOSsourcefollowerofFig.3.47verifyEq.(3.101).
3.16.AnalyzethecascodegainstageofFig.3.46intheLaplacetransformdomain.(a)VerifytheequivalentcircuitsofFig.3.46btod.(b)ShowthatEq.(3.98)
holdsforthecircuitofFig.3.46d.
References
1.P.R.GrayandR.J.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,Wiley,NewYork,1993.
2.J.L.McCrearyandP.R.Gray,IEEEJ.SolidStateCircuits,SC10(6),371379(1975).
3.D.J.HamiltonandW.G.Howard,BasicIntegratedCircuitEngineering,McGrawHill,NewYork,1975.
4.T.C.Choietal.,IEEEJ.SolidStateCircuits,SC18(6),652664(1983).
5.Y.TsividisandP.Antognetti,DesignofMOSVLSICircuitsforTelecommunications,PrenticeHall,UpperSaddleRiver,N.J.,1985.
6.P.R.Gray,PartII,IEEEPress,NewYork,1980.
7.Y.Tsividis,IEEEJ.SolidStateCircuits,SC13(3),383391(1978).
8.D.Senderowicz,D.A.Hodges,andP.R.Gray,IEEEJ.SolidStateCircuits,SC13(6),760766(1978).
9.K.BultandG.J.Geelen,IEEEJ.SolidStateCircuits,SC25(6),13791384(1990).
10.E.SackingerandW.Guggenbuhl,IEEEJ.SolidStateCircuitsSC25(1),289298(1990).
11.D.Allstot,IEEEJ.SolidStateCircuits,SC17(6),10801087(1984).

Page95

Chapter4
CMOSOperationalAmplifiers
TheCMOSoperationalamplifieristhemostintricate,andinmanywaysthemostimportant,buildingblockoflinearCMOSandswitchedcapacitorcircuits.Its
performanceusuallylimitsthehighfrequencyapplicationandthedynamicrangeoftheoverallcircuit.Itusuallyrequiresmostofthedcpowerusedupbythedevice.
Withoutathoroughunderstandingoftheoperationandthebasiclimitationsoftheseamplifiers,thecircuitdesignercannotdetermineorevenpredicttheactual
responseoftheoverallsystem.Hencethischapterincludesafairlydetailedexplanationoftheusualconfigurationsandperformancelimitationsofoperational
amplifiers.
Thetechnology,andhencethedesigntechniquesusedforMOSamplifiers,changerapidly.Therefore,themainpurposeofthediscussionistoillustratethemost
importantprinciplesunderlyingthespecificcircuitsanddesignprocedures.Nevertheless,thetreatmentisdetailedenoughtoenablethereadertodesignhigh
performanceCMOSoperationalamplifierssuitableformostlinearCMOScircuitapplications.
4.1
OperationalAmplifiers[1,Chap.102,Chap.6]
Inswitchedcapacitorcircuitsinfact,inalllinearCMOScircuitsthemostcommonlyusedactivecomponentistheoperationalamplifier,usuallysimplycalledthe
opamp.Ideally,theopampisavoltagecontrolledvoltagesource(Fig.4.1)withinfinitevoltagegainandwithzeroinputadmittanceaswellaszerooutput
impedance.Itisfreeoffrequencyandtemperaturedependence,distortion,andnoise.Needlesstosay,practicalopampscanonlyapproximatesuchanidealdevice.
Themaindifferencesbetweentheidealopampandtherealdevicearethefollowing[2,Chap.6]:

Page96

Figure4.1
(a)Symbolforidealopamp
(b)equivalentcircuit.

1.FiniteGain.Forpracticalopamps,thevoltagegainisfinite.TypicalvaluesforlowfrequenciesandsmallsignalsareA=103to105,correspondingto60to100
dBgain.
2.FiniteLinearRange.Thelinearrelationv o=A(v av b)betweentheinputandoutputvoltagesisvalidonlyforalimitedrangeofv o.Normally,themaximumvalue
ofv oforlinearoperationissomewhatsmallerthanthepositivedcsupplyvoltagetheminimumvalueofv oissomewhatpositivewithrespecttothenegativesupply.
3.OffsetVoltage.Foranidealopamp,ifv a=v b(whichiseasilyobtainedbyshortcircuitingtheinputterminals),v o=0.Inrealdevices,thisisnotexactlytrue,anda
voltagev o,off 0willoccurattheoutputforshortedinputs.Sincev o,offisusuallydirectlyproportionaltothegain,theeffectcanbemoreconvenientlydescribedinterms
oftheinputoffsetvoltagev in,off,definedasthedifferentialinputvoltageneededtorestorev o=0intherealdevice.ForMOSopamps,v in,offistypically2to10mV.
Thiseffectcanbemodeledbyavoltagesourceofvaluev in,offinserieswithoneoftheinputleadsoftheopamp.
4.CommonModeRejectionRatio(CMRR).Thecommonmodeinputvoltageisdefinedby

ascontrastedwiththedifferentialmodeinputvoltage

Accordingly,wecandefinethedifferentialgainAD(whichisthesameasthegainAdiscussedearlier),andalsothecommonmodegainAC,which

Page97

Figure4.2
Opampwithonlycommonmode
inputvoltage.

canbemeasuredasshowninFig.4.2,whereAC=v o/vin,c.Herev in,off=0isassumed|AC|isusuallyaround1 10.

TheCMRRisnowdefinedasAD/ACor(inlogarithmicunits)CMRR=20log10(AD/AC)indecibels.TypicalCMRRvaluesforCMOSamplifiersareintherange60to
80dB.TheCMRRmeasureshowmuchtheopampcansuppressnoise,andhencealargeCMRRisanimportantrequirement.
5.FrequencyResponse.Becauseofstraycapacitances,finitecarriermobilities,andsoon,thegainAdecreasesathighfrequencies.Itisusualtodescribethiseffect
intermsoftheunitygainbandwidth,thatis,thefrequencyf 0atwhich|A(f 0)|=1.ForCMOSopamps,f 0isusuallyintherange1to100MHz.Itcanbemeasured
withtheopampconnectedinavoltagefollowerconfiguration(Problem4.13).
6.SlewRate.Foralargeinputstepvoltage,sometransistorsintheopampmaybedrivenoutoftheirsaturationregionsorcutoffcompletely.Asaresult,theoutput
willfollowtheinputataslowerfiniterate.Themaximumrateofchangedvo/dtiscalledtheslewrate.Itisnotdirectlyrelatedtothefrequencyresponse.Fortypical
CMOSopamps,slewratesof1to20V/scanbeobtained.
7.NonzeroOutputResistance.ForarealCMOSopamp,theopenloopoutputimpedanceisnonzero.Itisusuallyresistiveandisontheorderof0.1to5k for
opampswithanoutputbufferitcanbemuchhigher( 1M )foropampswithunbufferedoutput.Thisaffectsthespeedwithwhichtheopampcanchargea
capacitorconnectedtoitsoutput,andhencethehighestsignalfrequency.
8.Noise.AsexplainedinSection2.7,theMOStransistorgeneratesnoise,whichcanbedescribedintermsofanequivalentcurrentsourceinparallelwiththechannel
ofthedevice.Thenoisytransistorsinanopampgiverisetoanoisevoltagev onattheoutputoftheopampthiscanagainbemodeledbyanequivalentvoltagesource
v n=v on/Aattheopampinput.Unfortunately,themagnitudeofthisnoiseisrelativelyhigh,especiallyinthelowfrequencyband,wheretheflickernoiseoftheinput
devicesishighitisabout10timesthenoiseoccurringinanopampfabricatedinbipolartechnology.Inawideband(say,intherange10Hzto1MHz),the
equivalentinputnoisesourceisusuallyontheorderof10to50Vrms,incontrasttothe3to5Vachievableforlownoisebipolaropamps.
9.DynamicRange.Duetothelimitedlinearrangeoftheopamp,thereisamaximuminputsignalamplitudev in,maxwhichthedevicecanhandlewithout

Page98

Figure4.3
Noisyfeedbackamplifier.

generatinganexcessiveamountofnonlineardistortion.IfthepowersupplyvoltagesoftheopampareVCC,anoptimisticestimateisv in,max VCC/A,whereAisthe

openloopgainoftheopamp.Duetospurioussignals(noise,clockfeedthrough,lowleveldistortionsuchascrossoverdistortion,etc.)thereisalsoaminimuminput
signalvin,minwhichstilldoesnotdrowninnoiseanddistortion.Usually,v in,minisonthesameorderofmagnitudeastheequivalentinputnoisev noftheopamp.The
dynamicrangeoftheopampisthendefinedas20log10(v in,max/v in,min)measuredindecibels.Whentheopampisinopenloopcondition,v in,max VCC/A,whichisonthe
orderofamillivolt,while
whichisaround30V.Thustheopenloopdynamicrangeoftheopampisonlyaround30to40dB.However,thedynamic
rangeofacircuitcontainingopampsinnegativefeedbackconfigurationcanbemuchlarger.Asasimpleillustration,considerthefeedbackamplifiershowninFig.4.3.
Itiseasytoshow(Problem4.1)thattheoutputduetothenoisesourcev nactingalonehasthermsvalue

Thevoltagegainofthe(noiseless)feedbackcircuitis

Theminimuminputsignalv in,mingivesrisetoanoutputvoltageapproximatelyequaltov on.Hence

Page99

Hencethedynamicrangeisgivenby

wheretheindicatedapproximationinusuallyvalidforA

adynamicrangeofabout90dBresultsfortheoverallcircuit.

InlinearCMOScircuits,dynamicrangevaluesaround80to90dBarereadilyachievable.Evenhighervalues(upto100dB)arepossibleifthelargelowfrequency
noise(1/fnoise)iscanceledusingadifferentialcircuitconfigurationandchopperstabilization[3].
10.PowerSupplyRejectionRatio(PSRR).Ifapowersupplyvoltagecontainsanincrementalcomponentvduetonoise,hum,andsoon,acorrespondingvoltage
Apvwillappearattheopampoutput.ThePSRRisdefinedasAD/Ap,whereAD=Aisthedifferentialgain.ItiscommontoexpressthePSRRindecibelsthenPSRR
=20log10(AD/Ap).UsualPSRRvaluesrangefrom60to80dBfortheopampaloneforaswitchedcapacitorcircuit,30to50dBcanbeachieved.
11.DCPowerDissipation.Idealopampsrequirenodcpowerdissipatedinthecircuitrealonesdo.TypicalvaluesforaCMOSopamprangefrom0.25to10
mWdcpowerdrain.
Toobtainnearidealperformanceforapracticalopamp,thegeneralstructureofFig.4.4isusuallyemployed[1,Chap.10].Theinputdifferentialamplifier(first
block)isdesignedsothatitprovidesahighinputimpedance,largeCMRRandPSRR,lowoffsetvoltage,lownoise,andhighgain.Itsoutputshouldpreferablybe
singleended,sothattherestoftheopampneednotcontainsymmetricaldifferentialstages.Sincethetransistorsintheinputstage(andinsubsequentstages)operate
intheirsaturationregions,thereisanappreciabledcvoltagedifferencebetweentheinputandoutputsignalsoftheinputstage.
ThesecondblockinFig.4.4mayperformoneormoreofthefollowingfunctions:
1.LevelShifting.Thisisneededtocompensateforthedcvoltagechangeoccurringintheinputstage,andthustoassuretheappropriatedcbiasforthefollowing
stages.

Figure4.4
Blockdiagramforapracticalopamp.

Page100

2.AddedGain.Inmostcasesthegainprovidedbytheinputstageisnotsufficient,andadditionalamplificationisrequired.
3.DifferentialtoSingleEndedConversion.Insomecircuitstheinputstagehasadifferentialoutput,andtheconversiontosingleendedsignalsisperformedina
subsequentstage.
Thethirdblockistheoutputbuffer.Itprovidesthelowoutputimpedanceandlargeroutputcurrentneededtodrivetheloadoftheopamp.Itnormallydoesnot
contributetothevoltagegain.Iftheopampisaninternalcomponentofaswitchedcapacitorcircuit,theoutputloadisa(usuallysmall)capacitor,andthebufferneed
notprovideaverylargecurrentorverylowoutputimpedance.However,iftheopampisatthecircuitoutput,itmayhavetodrivealargecapacitorand/orresistive
load.Thisrequireslargecurrentdrivecapabilityandverylowoutputimpedance,whichcanonlybeattainedbyusinglargeoutputdeviceswithappreciabledcbias
currents.Thusthedcpowerdrainwillbemuchhigherforsuchoutputopampsthanforinteriorones.
Asmentionedearlier,theidealopampdefinedinFig.4.1isavoltagecontrolledvoltagesource,withzerooutputimpedance.Infact,forpracticalopamps,whichdo
nothaveanoutputbuffer,theoutputimpedancemaybeveryhigh,ontheorderofmegohms.Forsuchanamplifier,abetteridealrepresentationcanbefoundasa
voltagecontrolledcurrentsource,withatransconductionGmvaluethatisinfinitelylarge.Thisidealmodeliscalledanoperationaltransconductanceamplifier
(OTA).Iftheopamphassufficientlyhighvoltagegainandisinastablefeedbacknetwork,itsoutputimpedanceisreducedtoaverylowvalue,andthedifference
betweentheperformancesofanopampandOTAcanbeneglected.
Inaclassofcontinuoustimefilters,afiniteGmtransconductanceisrequired.HerealowbutaccuratelycontrolledvalueofGmneedstobeachieved.The
correspondingactivedeviceiscalledatransconductoritisnottobeconfusedwithanOTA.Intheremainderofthischapter,thepropertiesoftypicalCMOSop
ampsandOTAsaredescribed,andanalysisanddesigntechniquesaregivenforthem.Unlessotherwisepostulated,weassumethatalldevicesareoperatedinthe
saturationregion.TheniDistoagoodapproximationindependentofv DandisgivenbyiD k (W/L)(v GSVT)2.Here,duetobodyeffect,VTdependsonthesource
tobodyvoltage.
4.2
SingleStageOperationalAmplifiers
ApracticalblockdiagramofanMOSopampwasshowninFig.4.4andisreproducedinmoredetailinFig.4.5.Thevoltagegainrequiredisobtainedinthe
differential(G1)andsingleended(G2)gainstages.Theoutputstage(G3)isusuallyawidebandunitygainlowoutputimpedancebuffer,capableofdrivinglarge
capacitiveand/orresistiveloads.Iftheopampisusedinaninternal(asopposedtooutput)stageofaswitchedcapacitorcircuit,theloadmaybeonlyasmall
capacitor,2pForless.Insuchasituation,theoutputbuffer(G3)maybeomitted,andtheloadmay

Page101

Figure4.5
Basicbuildingblocksofanoperationalamplifier.

thenbeconnecteddirectlytotheoutputofG2.Itwillthenfunctionasanoperationaltransconductanceamplifier(OTA).InFig.4.5,ifthecombinationofthe
differentialstageanddifferentialtosingleendedconverterprovidesadequategainandoutputvoltageswing,G2canalsobeomittedandtheloadmaybedriven
directlybythedifferentialstage.Again,thecircuitwillthenrealizeanOTA.
TheCMOSdifferentialstagewithanactiveloadisshownagaininFig.4.6.ItwasintroducedinChapter3.Thisstagecombinesthefunctionsofadifferentialamplifier
anddifferentialtosingleendedconverter.Theroleofthedifferentialamplifieristoamplifythedifferencebetweenthetwoinputvoltages,
was
derivedinChapter3andisgivenby

Inthisequation,1/(gd2+gd4)istheoutputimpedanceseenattheoutputofthedifferentialstage,andgmiisthetransconductanceoftheinputdevicesQ1andQ2.

Figure4.6
CMOSdifferentialstagewithactiveload.

Page102

ThedifferentialstageofFig.4.6usedasasinglestageopamphastwomajorshortcomings.First,thetotalvoltagegainislimitedtothegainofasinglestageamplifier,
whichistypicallyabout50.Second,theoutputvoltageswingislimitedtotherange

wherev incisthecommonmodeinputvoltagedefinedas
andVTPisthethresholdvoltageofthepchanneldevices.Obviously,inmostcasesthe
lowvoltagegainandthenarrowoutputswingpreventthedifferentialstageofFig.4.6frombeingusefulasasinglestageopamp.
Thegainofthedifferentialstagecanbeincreasedintwoways,byincreasingthetransconductanceoftheinputdevicesQ1andQ2,orbyincreasingtheoutput
impedanceseenattheoutputofthestage.Ascanbeseenfromtherelationgmi=
,transconductancecanbeincreasedbyincreasingthewidthofthe
inputdevicesand/orbyincreasingthebiascurrent.NoticethatreducingL,thechannellengthoftheinputdevices,canalsoincreasethetransconductance.This,
however,alsohastheoppositeeffectofreducingtheoutputimpedance1/gdioftheinputdevices(duetochannellengthmodulationeffect),andhencebyEq.(4.8)
reducesthegain.Increasingthewidthorthecurrentofthestagewillincreasethesizeorthepowerdissipationofthecircuit.Therefore,amoreefficientwayto
increasethegainistoincreasetheoutputimpedancero.
AsisevidentfromFig.4.6,toincreasetheoutputimpedancero,bothrd2andrd4havetobeincreased.Thiscanbeachievedbyusingthecascodecurrentsourceas
load.Figure4.7illustratesadifferentialstagethatusescascodetransistorstoincreasethevoltagegainbyincreasingtheoutputimpedance.HeredevicesQ1,Q1cand
Q2,Q2cformtwosourcecouplecascodeamplifiers,whileQ3,Q3c,Q4,andQ4c

Figure4.7
CMOSdifferentialstagewith
cascodeload.

Page103

Figure4.8
CMOSdifferentialstagewith
cascodeloadandcommon
modebiasingscheme.

formacascodecurrentsourcethatactsasanactiveload.Forsymmetricaldimensions(W/L)1=(W/L)2,(W/L)3=(W/L)4,(W/L)1c=(W/L)2c,and(W/L)3c=(W/L)4cthe
outputimpedanceofthestageis,

wherer1||r2denotesparallelconnectedr1andr2(Problem4.3).Sincegm2crd2candgm4crd4carenormallymuchgreaterthan1,
impedanceofthedifferentialstageofFig.4.6.ThedifferentialvoltagegainofthestageofFig.4.7isgivenby

whichistheoutput

Theuseofcascodingincreasesthegainofthedifferentialstagesubstantially.Thedisadvantageis,however,thatthevoltagedropsacrosstheadditionaltransistorsQ1c
andQ3cresultinareductionintheallowableinputcommonmoderangeandoutputvoltageswing.Theswingperformancecanbeimprovedbyusinghighswing
biasingofthecascode,asdiscussedinSection3.3.Theinputcommonmoderangecanalsobeimproved,byusingabiasvoltageforQ1candQ2cthattrackstheinput
commonmodevoltage.OnecircuitthataccomplishesthisisshowninFig.4.8,whereQbandIchavebeenaddedtobiasthegatesofQ1candQ2c.TheW/LratioofQb
andthevalueofcurrentIccanbeselectedinsuchawaythatQ1andQ2remainbiasedattheedgeofthesaturationregionastheinputcommonmodevoltagechanges.
Obviously,thebiasvoltageVbiaswillbeoneVGSdrop(ofQb)belowthevoltageVcofthecommonsource.EventhoughtheperformanceofthecircuitofFig.4.8
improvedoverthatofFigs.4.6and4.7,duetotheverylimitedoutputvoltageswingthestageisnormallynotusefulasasinglestageopamp.

Page104

Figure4.9
Foldedcascodeopampconsistingofacascadeof
commonsourceandcommongateamplifiers.

SomeoftheproblemsdescribedwiththedifferentialstageofFig.4.8canbeeliminatedbyusingthefoldedcascodeconfiguration[4].ConsiderthecircuitofFig.4.8
letthebottomterminals(i.e.,thesourcesofQ3andQ4)ofthecompositeloadQ3,Q4andQ1ctoQ4cbedisconnectedfromVSS,foldedup,andconnectedtoVDD
instead.Toassureproperdcbiascurrents,allNMOSdevicesmustbereplacedbyPMOStypes,andviceversainthecascodeloadsalso,twoadditionalcurrent
sources(Q5andQ6)mustbeaddedbetweenVSSandthedrainsofQ1andQ2tosupplybiascurrentstotheseinputdevices.Theresultingsinglestageopampisshown
inFig.4.9.Thebasicoperationofthecircuitisasfollows.ThedccurrentI0ofthecurrentsourceQ7issharedequallybyQ1andQ2.Also,thematchedsourcesQ5and
Q6drawequalbiascurrents ofQ5andQ6remainunchanged,thecurrentsofQ1candQ2c(whicharedrivenattheirlowimpedancesourceterminals)willalsochange
by I0.ThecurrentmirrorQ3,Q4,Q3c,andQ4ctransfersthecurrentchangeinQ3andQ3ctoQ4andQ4c.HencetheoutputvoltageincrementisgmiR0 v in,whereR0is
theoutputimpedanceatnodeD.Itcanbeshown(Problem4.4)that

Theincrementalgainisthen

Adisadvantageofthefoldedcascodeopampisthereducedoutputvoltageswingduetothemany(four)cascodeddevicesintheoutputbranches.Theswingcanbe

Page105

Figure4.10
Foldedcascodeopampwithimprovedbiasingfor
maximumoutputvoltageswing.

increasedifoneofthebiascircuitsofFig.3.15or3.16isusedtoestablishthegatevoltagesofQ1ctoQ4csuchthatthedraintosourcevoltagesofQ3toQ6areonly
slightlylargerthanVDsat.InFig.4.10thebiascircuitsofFig.3.16hasbeenaddedtotheopamp.Itcanbeshown(Problem4.5)thatthenecessaryaspectratiosare
givenby

Forthiscircuititcanalsobeshownthatthemaximumoutputvoltageswingiswithintherange

Thustherangelostatboththeupperandlowerlimitsisonly2|VDsat|.ThecascodeopampshowninFig.4.10hasalargevoltagegainandareasonablylargeoutput
voltageswing.HenceitcanbeusedasasinglestageOTA.
ConsidernextthehighfrequencybehaviorofthecircuitofFig.4.10.ThepolesofthegainstagearecontributedbythestraycapacitancesloadingnodesA,B,C,and
D.Thedominantpolesp1ofthecircuitisduetotheloadcapacitanceCLinparallelwiththeoutputimpedanceR0givenbyEq.(4.12)henceitsvalueis

Page106

Figure4.11
Smallsignallowfrequency
representationofthefolded
cascodeopamp.

TheresistanceseenatnodeAisapproximately1/gm1catnodeBitisapproximately1/gm2candatnodeCitisapproximately1/gm3.Since1/gmisontheorderof1k
andstraycapacitancesaremuchsmallerthenCL,thecorrespondingpolessp2,sp3,andsp4areusuallyatmuchhigherfrequenciesthensp1.Theapproximatelow
frequencyequivalentcircuitisthereforethatshowninFig.4.11.HeretheinputstageisrepresentedbyitssimpleNortonequivalentcircuit,obtainedusingEqs.(4.12)
and(4.13).Theoveralltransferfunctionistherefore

Thefrequencyresponseisobtainedbyreplacingsbyj .
4.3
TwoStageOperationalAmplifiers
ThesinglestageoperationalamplifierwasdiscussedinSection4.2.AnotherwidelyusedCMOSopampusesthetwostageconfigurationbasedonthesystemof
Fig.4.5.Thisimplementationisderiveddirectlyfromitsbipolartransistorcounterpart[5].AsimpletwostageCMOSimplementationoftheschemeofFig.4.5is
showninFig.4.12,wherethesecondgainstage,G2,drivesasourcefollower.Inthiscircuit

Figure4.12
UncompensatedtwostageCMOSoperationalamplifier.

Page107

Q5actsasasimplecurrentsource,anddevicesQ1toQ5formadifferentialstage(cf.Fig.4.6)withasingleendedoutput.TransistorsQ6(actingasthedriverdevice)
andQ7(actingastheload)formthesecondgainstage,whichalsoactsasalevelshifter.Finally,thesourcefollowerconsistingofQ8asdriverandQ9asloadrealizes
theoutputbuffer.ThelowfrequencydifferentialmodegainoftheinputstagecanbeobtainedfromEq.(4.8):

wherethesubscriptireferstoinput,andltoloaddevice.
HereitisassumedthatQ1ismatchedtoQ2,andQ3toQ4.ThelowfrequencygainoftheinverterformedbyQ6andQ7isclearly

TheoverallvoltagegainAvisAv1Av2.Fortypicalbiasingconditionsanddevicegeometries,Av=10,000to20,000canbeachieved.TheoutputterminalsAandBof
bothstagesarehighimpedancenodesthelowfrequencyoutputimpedanceoftheinputstagedrivingnodeAis

thatofthesecondstage(Q6,Q7)is

AnequivalentcircuitshowingtheseimpedancesandalsotheparasiticcapacitancesCAandCBloadingnodesAandB,respectively,isshowninFig.4.13.Itis

Figure4.13
Blockdiagramshowingtheoriginofthedominantpoles.

Page108

evidentfromthefigurethatthetransferfunctionoftheamplifier

willcontainthefactors

wherethepolesaresA=1/Ro1CAandsB=1/Ro2CB.SinceRo1andRo2arelarge,sAandsBwillbeclosetothej axisinthesplane.Hencetheywillbethedominant
polesoftheamplifier.Theeffectsofotherpoleswillbenoticeableonlyatveryhighfrequencies.
Iftheopampisrequiredtodrivesmallinternalcapacitiveleadsonly,theoutputsourcefollower(Q8,Q9)maybeeliminatedandtheoutputtakendirectlyfromnodeB.
However,evenforsuchcapacitiveloads,themaximumoutputcurrentthatcanbesourcedislimitedbythecurrentsourceQ7.
Forveryhighgainapplications,thecascodedifferentialamplifierofFig.4.8canbeusedasthefirststageoftheopamp.Atwostageopampwiththecascode
differentialstageisshowninFig.4.14.TransistorsQ8andQ9formalevelshifterbetweentheoutputofthefirststageandtheinputofthesecondstage,tobalancethe
dclevelbetweenthesignalpath.ThegainofthefirststageisgivenbyEq.(4.11),andthetotalgainis

whereRo1isgivenbyEq.(4.10).ThefrequencyresponsegivenbyEq.(4.23)isstillvalid,withsA=1/Ro1CA,whereRo1isreplacedbyitsnewvaluegivenbyEq.
(4.10).

Figure4.14
Twostageopampwithcascodedifferentialstage.

Page109

Figure4.15
ImproveduncompensatedCMOSoperationalamplifier.

AnimprovedCMOSopamp[6]withincreasedoutputrangeandcurrentdrivecapabilityisshowninFig.4.15.TheoutputstageconsistsofdevicesQ6toQ9,withQ6
andQ7actingasalevelshifterandQ8andQ9actingasaclassBpushpulloutputstage.ThedcbiasingisdesignedsothatQ8andQ9haveequalvaluedsmallgateto
sourcedcbiases.Thismaximizesthelinearv outrange.TheconceptualformoftheCMOSgainstagewiththelevelshifterisshowninFig.4.16.
ThelowfrequencysmallsignalgainofthesecondstagecanbefoundfromtheequivalentcircuitofFig.4.17.Thenodeequationis

Sincegmcanbe100timeslargerthangd,thegainishigh.ThelowfrequencysmallsignaldifferentialgaincaneasilybefoundfromEqs.(4.19)and(4.26):

Thus|Av|canbeashighas20,000.However,ifthecircuithastodrivearesistiveloadGL,thengd8+gd9isreplacedbygd8+gd9+GL,whichnormallyreducesthegain
significantly.Also,foralargeloadcapacitanceCL,thepoleofthecompensatedopampinafeedbackarrangementresultingfromthetimeconstantCL/(gd8

Page110

Figure4.16
CMOSgainstagewith
levelshifter.

+gd9)maymovesoclosetothej axisthatinstabilityoccurs.Hencethisopampisagainsuitedonlyfordrivingsmalltomoderatesizedinternalcapacitiveloads.
IfthecircuitofFig.4.15istobeusedtodriveresistiveloads,anoutputbufferstagemustbeadded.Thismaybesimplyasourcefollower,similartothatinFig.3.33.
However,betteroutputcurrentsourcingandsinking,andloweroutputimpedance,canbeobtainedusingmoreelaborateCMOSoutputbuffers.Thesearediscussed
inSection4.9.
ConsidernowthehighfrequencybehaviorofthecircuitofFig.4.15.Asbefore,nodesAandBareatahighimpedancelevelandareresponsibleforthedominant
poles.TheapproximateequivalentcircuitisshowninFig.4.18.Here,theinputstageisrepresentedbyasimpleNortonequivalent,obtainedusingEqs.(4.19)and
(4.21).Similarly,theNortonequivalentoftheoutputstagecanbefoundfromEqs.(4.26)and(4.22).Asbefore,thetransferfunctioncontainsafactorsimilartothat
giveninEq.(4.23),wherenowsA=(gd2+gd4)/CAandsB=(gd8+gd9)/CL.Theoveralltransferfunctionistherefore

Figure4.17
Smallsignalequivalentcircuit
oftheCMOSgainstage.

Page111

Figure4.18
TwostagerepresentationoftheCMOSoperational
amplifierofFig.4.15.

Thefrequencyresponseisobtainedbyreplacingsbyj .Forlowfrequencies( |sA|,|sB|),

Forhighfrequencies( |sA|,|sB|),

Hence,forhighfrequencies,theamplifierinvertstheinputvoltage.InswitchedcapacitorapplicationstheopampalwayshasafeedbackcapacitorCconnected
betweenitsoutputanditsinvertinginputterminals.AtypicalcircuitisshowninFig.4.19.AsinewavesignalVin(j )appearingattheinvertinginputterminalwillthus
beamplifiedbyAv(j )andfedbacktotheinputviacapacitivedividerCandC1hereC1representstheoverallcapacitanceoftheinputcircuitdrivingtheopamp,
includingstraycapacitances,andsoon.
TheopampandcapacitorCandC1formafeedbackloop,withaloopgain

Figure4.19
Operationalamplifierwithfeedback
capacitorCandinputcapacitorCin.

Page112

Inadditiontotheinputvoltagev in,thecircuitalsocontainsthevoltagev n,representingthenoisegeneratedin(orcoupledto)theopamp.Thecircuitcanbeanalyzed

byusingthenodeequationatnodeA:

andtheopampgainrelation:

Thisgives

Theoutputvoltagecanbecome(intheory)infiniteiftheinputsignalornoisecontainsasinewavecomponentwithafrequency 1,suchthat

ByEq.(4.31)thiscorrespondstoaloopgainofAL=1,aconditionforoscillation.
AtdcandverylowfrequenciesEq.(4.29)showsthatAv(j )ispositive,andhenceEq.(4.35)cannotbevalid.However,athighfrequencies,byEq.(4.30),Av(j )
becomesnegativereal,andatsome 1itmaysatisfyEq.(4.35).Whenthisoccurs,thecircuitwillbecomeunstable,anditwilloscillatewithafrequency 1.Intheory,
forourtwopolemodel,Av(j )becomesnegativerealonlyfor 'however,forlargeloopgainthecircuitisonlymarginallystableforhighfrequencies,sothatany
additionalsmallphaseshiftduetothehighfrequencypolesneglectedinFig.4.18maycauseoscillation.Evenifstabilityisretained,thetransientresponsecontainsa
lightlydampedoscillation,whichisunacceptableinmostapplications.
Topreventoscillationinfeedbackamplifiers,andtoensureagoodtransientresponse,anadditionaldesignstep(calledfrequencycompensation)isneeded.Itis
basedonthestabilitytheoryoffeedbacksystemsandisdiscussedbrieflyinthenextsection.
4.4
StabilityandCompensationofCMOSAmplifiers
InSection4.3itwasshownthattheCMOSopampofFig.4.15isonlymarginallystablewhenusedinafeedbackcircuit.Inthissectiontheanalysisofstabilityand
thedesignstepsrequiredtoensurestablefeedbackopampsarediscussed.
AsystematicinvestigationofstabilitycanbebasedonthegeneralblockdiagramofFig.4.20,whichshowsanopampinanegativefeedbackconfiguration.Itis

Page113

Figure4.20
Operationalamplifierwithnegativefeedback.

assumedthatkandaarepositiveconstants,andk 1.Thevoltageattheinvertinginputterminalis

andtheoutputvoltageis

Hencethevoltagegainis

Avfisoftencalledtheclosedloopgain,AvistheopenloopgainofthesystemandkAvistheloopgain.
WeassumenextthatallpolessiofAv(s)areduetostraycapacitancestogroundinanotherwiseresistivecircuit.(Thisisanacceptableapproximationifinductive
effectsarenegligible,andallcapacitancesloadingthehighimpedancenodesareconnectedbetweenvoltagesthatareinphaseor180outofphaseofeachother.)
Thenallsiarenegativerealnumbers,andAv(s)isintheform

Fors=j ,Av(j )givesthefrequencyresponseoftheopamp.Itsmagnitudeis

anditsphaseisgivenby

Notethatboth|Av(j )|and Av(j )aremonotonedecreasingfunctionsof .

Page114

ThenaturalfrequenciesoftheoverallfeedbacksystemarethepolesspofAvf(s),whichbyEq.(4.38)satisfytherelation

Forstability,allspmustbeinthenegativehalfofthesplanethatis,therealpartsofallpolesmustbenegative.NowassumethatRe[kAv(j )]>1forallrealvalues
of .ThenkAv(j ) 1,andhencenospcanoccuronthej axisfurthermore,itcaneasilybeproventhatifAv(s)hasonlypoleswithnegativerealparts,thenunder
thestatedassumption,sowillAvf(s).TheproofisimpliedinProblem4.26.Thusthecondition

issufficienttoensurestability.Itisnot,however,anecessarycondition.Twoothersufficientconditionsforstabilitycanalsoreadilybestated.Let
frequencyatwhichthemonotonedecreasingphaseofkAv(j )reaches180thatis,

Ifnow|kAv(j

bethe

180

)|<1,Eq.(4.42)cannotholdonthej axis,andhencethecircuitisstable.Ameasureofitsstabilityisthegainmargin,definedas

180

Thegainmarginmustbenegativeforstabilitythemorenegativeitis,thelargerthemarginofstabilityofthecircuit.Normally,amarginofatleast20dBisdesirable.*
Next,let|kAv(j 180)|,whichalsodecreasesmonotonicallywith ,reachthevalue1(i.e.,0dB)attheunitgainfrequency 0.Then,ifthephaseat 0satisfies kAv
(j 0)>180,thesystemwillbestable.ThephasemarginPM,definedas kAv(j 0)+180,isameasureofitsstabilitythelargerthephasemargin,themore
stablethecircuit.Usually,atleasta60(andpreferablylarger)marginisrequired.Thiswillalsogiveadesirable(i.e.,nonringing)stepresponsefortheclosedloop
amplifier.Theovershoot,OS,ofthestepresponseofthefeedbacksystemdecreasesrapidlywithincreasingphasemargin:forPM=60,OS=8.7%forPM=70,
OS=1.4%,andforPM=75,OS=0.008%.
AllthestabilityconditionsabovecanreadilybevisualizedandcheckedusingBodeplots.Theseshow|kAv(j )|(indecibels)and kAv(j )(indegrees)asfunc
*

Thegainmarginishardertocontrol,andhencemuchlessoftenused,thanthephasemargindescribednext.

Page115

Figure4.21
Bodeplotforthreerealpoles.

tionsof onalogarithmicscale.TypicalplotsareshowninFig.4.21(dashedcurves)forthethreepoleloopgain:

withA0=105,s1=10rad/s,s2=102rad/s,ands3=103rad/s.Drawingthemagnitudeplotissimplifiedbyusinganasymptoticapproximationtothelogarithmic
magnitudeofthegeneraltermai(j )=1/(1j /s1):

Clearly,20log10|ai| 0for| | |si,|,20log10|ai|approachesastraightlinewithaslopeof6dB/octave(i.e.,decreasesby6dBforeachdoublingof ),while ai

approaches90inthissameregion.Inparticular,| ai| 90for >5|si|.Also,| ai| 30for <0.5|si|thisfactwillbeusedlater.

Page116

Figure4.22
Gainandphaseresponsesfora
factora i(j )=(1j /si)1.

Thelogarithmicformoftheloopgainsatisfies

Therefore,attheunitygainfrequency 0theslopeofthelogarithmicloopgainversuslogarithmicfrequencyisapproximately6mdB/octave,whileitsangleisaround
90mdegrees.Here,misthenumberofthosepoleswhosemagnitude|si|islessthan 0.Clearly,forasubstantialpositivephasemargin(say60,sothat kAv(j 0)
>120),mshouldbelessthan2.Ideally,mis1(i.e.,thereisonlyonepolesatisfying|si|< 0),andtheotherpoleshavemuchlargermagnitudesthan 0.Thenthe
phasemarginiscloseto90.(For
m=0isimpossible.)
ReturningtotheexampleofFig.4.21,thesolidlinesshowtheasymptoticapproximationtothelogarithmicmagnitudeofkAv(j ).Thecurvesindicatethatattheunity
gainfrequency 0 4krad/s,thephaseofkAv(j )isabout270.Hencethephasemarginisnegative,andthefeedbacksystemispotentiallyunstable.
ThemodificationofkAv(s),whichchangesanunstablefeedbacksystemintoastablesystem,iscalledfrequencycompensation.Itspurposeisusuallytoachievethe
idealsituationdescribedabovethusweaimtorealizealoopgainthatcontainsexactlyonepolesmallerinmagnitudethan 0,whileallothersaremuchlarger.Since
thefeedbackfactorkcanbeanywhereinthe0<k 1range,andk=1representstheworstcase(i.e.,thelargest 0andhencethesmallestphasemargin),thiswill
beassumedfromhereon.Notethatk
inFig.4.19andk=1representsashortcircuitbetweentheoutputandtheinvertinginputoftheamplifier.Sucha
circuitisshowninFig.4.77inconnectionwithProblem4.13.
ItwillnextbeshownhowtocarryoutthecompensationfortheopampofFig.4.15.Referringtoitsequivalentsmallsignalrepresentation(Fig.4.18),wewillfirst

Page117

Figure4.23
TwostagerepresentationofaCMOSoperational
amplifierwithapolesplittingcapacitorCc .

attempttoachievecompensationbyconnectingacompensatingcapacitorCcbetweenthehighimpedancenodesAandB,asshowninFig.4.23.Itiswellknown
(seeRef.2,Sec.9.4)thatforbipolaropampstheadditionofsuchcapacitormovesthepoleassociatedwithnodeAtoamuchlowerfrequency,whilethat
correspondingtonodeBbecomesmuchlarger.Itisthereforeoftencalledapolesplittingcapacitorand(forbipolaropamps)accomplishesthedesired
compensation.ThesituationislessfavorableforMOSopamps,aswillbeshownnext.ThenodeequationsfornodesAandBinFig.4.23are

SolvingforVout,thevoltagegain

results.Hencethedcgainis

andthezerois

Page118

Thecalculationofthepolesissimplifiedifitisaprioriassumedthat|sp2| gd2+gd4orgd8+gd9.Then,aftersomecalculation[2,p.519](seeProblem4.6),

whereA0isthedcgaingivenin(4.52).
Physically,Cc(multipliedbytheMillereffect)isaddedinparalleltoCA,thusreducing|sp1|byaverylarge(ca.103)factor,whileatthesametimeitincreasesthe
secondpolefrequency|sp2|viashuntfeedback.
Clearly,|sp1|decreases,while|sp2|increaseswithincreasingvaluesofCc.ThusCcindeedsplitsthepolesapart,asoriginallyintended.Unfortunately,thedesired
compensationisneverthelessusuallynotachieved,duetothepositive(righthalfplane)zerosz.Fortheusualcaseof1/Cc 1/CA+1/CL,theinequalities

hold.Thelogarithmicmagnitudeofthefactor(1j /sz)isnearzerofor| | sz,whileitincreasesbyabout6dB/octavefor| | sz.Thephaseofthefactoristan1

( /sz)itdecreasesfrom0to90as growsfromzerotoinfinity.Asaresult,theplotsshowninFig.4.24areobtained.Clearly,attheunitygainfrequency 0the
phaseislessthan180.Henceinafeedbackconfigurationtheamplifier

Figure4.24
AmplitudeandphaseplotsoftheCMOSopamp.

Page119

Figure4.25
Unitygainbufferarrangementusedtoeliminatetherightplanezero.

canbecomeunstable.Notethatifgm8+gm9wouldbeincreased,sz/|sp1|A0would,byEqs.(4.52)to(4.54),increaseproportionally.ItisclearfromFig.4.24thatif
sz/|sp1|(inoctaves)isgreaterthanA0(indB)/6,theunitygainfrequency 0islessthansz,andthephasemarginispositive.Thus,forsufficientlyhighgmvalues(suchas
areaffordedbybipolartransistors),theinclusionofCcaccomplishesthedesiredstabilization.Unfortunately,thetransconductanceofMOSFETsisnormallynothigh
enoughforthepurpose,andotherarrangementsmustbefoundtoeliminatesz.
Oneschemeforgettingridofszistoshiftittoinfinitefrequency.Physically,thezeroisduetotheexistenceoftwopathsthroughwhichthesignalcanpropagatefrom
nodeAtonodeB.ThefirstisthroughCc,whilethesecondisbywayofthecontrolledsource(gm8+gm9)AA.Fors=szthetwosignalsfromthesepathscancel,anda
transmissionzerooccurs.ThezerocanbeshiftedtoinfinitefrequencybyeliminatingthefeedforwardpaththroughCc,atthecostofanextraunitygainbuffer(Fig.
4.25).Adetailedanalysisshows(Problem4.7)thatthenumeratorofAv(s)isnowsimplyA0,whilethedenominatorremainsnearlythesameasinEq.(4.51).Acircuit
implementingthisschemeisshowninFig.4.26,whereQ10/Q11formthebuffer.

Figure4.26
InternallycompensatedCMOSopampwithunitygain
bufferusedtoavoidtherighthalfplanezero.

Page120

Analternative(andsimpler)scheme[7]canalsobeused.ConsiderthecircuitshowninFig.2.27.Nodalanalysisshows(Problem4.8)thatitstransferfunctionis

HereA0,sp1,andsp2are(asbefore)givenbyEqs.(4.52),(4.54),and(4.55),whilenow

AsEq.(4.58)shows,itisagainpossibleforthiscircuittoshiftsztoinfinity,ifRc=1/(gm8+gm9)ischosen.Then,choosingasufficientlylargevalueforCccansplitthe
poles.Toquantifythis,itisreasonabletorequirethat|sp2|> 0,theunitygainfrequency.Forthischoice,sinceinthefrequencyregionbetween|sp1|and|sp2|

holds,theapproximation 0 A0|sp1|canbeused.Thus|sp2|>A0|sp1|maybespecified.FromEq.(4.55),with1/CA (1/Cc+1/CL),werequire

sothatafeedbackcapacitorsatisfying

isneeded.SinceexperienceindicatesthatnormallyCc~CLisagoodchoice,werequirethatgm1<gm8+gm9.AnotherwayofeliminatingszforthecircuitofFig.4.27
isbypolezerocancellation.Choosingsz=sp2,fromEqs.(4.55)and(4.58),

isobtained.Theresultingcancellationleavestheopampwithatwopoleresponse.

Page121

Figure4.27
SmallsignalequivalentcircuitofCMOSopampwith
nullingresistorforcompensation.

Compensationnowrequiresthat|sp3|>A0|Sp1|.UsingEqs.(4.55),(4.59),and(4.61),thisconditioncanberewrittenintheform

Here

inEq.(4.64)isusuallymuchsmallerthan1hence,nowasmallerCccanbeused.Itsvaluecanbeobtainedfromthebound*

TheactualimplementationoftheschemeofFig.4.27intheCMOSopampofFig.4.15isshowninFig.4.28.Theparallelconnectedchannelsofthecomplementary
transistorsQ10andQ11formRc.ThispushpullarrangementhelpstosuppressevenharmonicsandthusimprovesthelinearityoftheresistorRc.
NotethattheconditionRc=1/(gm8+gm9)iseasilyobtainedbymatchingQ10andQ11toQ9andQ10,respectively.SatisfyingEq.(4.63)issomewhatharderhowever,
theaccuracyisnotcritical,andasexplainedabove,thischoiceforRcresultsinasmallervalueforCc.
Thepolesplittingfrequencycompensationtechniquedescribedsofarisapplicabletoatwostagetopologywheretheoutputstageisacommonsourcegainstage
precededbyadifferentialstagepreamplifier.Iftheopampisloadedwithaverysmallresistance,thegainoftheoutputstagecanbecomesosmallthatthetwostage
solutionmaynothaveenoughdcgain.Inthiscase,usingthecascodeloaddifferentialamplifiershowninFig.4.7canincreasethegainofthetwostageamplifier.
Alternatively,thefoldedcascodetopologyofFig.4.10canalsobeusedastheinputstage
*

Inpractice,itisusualtochooseCc CL.ThischoicesatisfiestheconstraintsofEqs.(4.64)and(4.65)withalargemargin.

Page122

Figure4.28
ImprovedinternallycompensatedCMOS
operationalamplifier.

inwhichcasetheopampcanbefrequencystabilizedwithapolesplittingcapacitorthatisconnectedbetweenthetwohighimpedancenodes.Anothermethodto
enhancetheopampgainistouseamultistageconfiguration.Thesimplestapproachwouldbetoinsertapositivegainintermediatestagebetweentheinputandoutput
stages.ThisisshowninsimplifiedforminFig.4.29.Thethreestageamplifierhasthreedominantpoles,oneattheoutputofeachgainstage.Thesimplepolesplitting
doesnotremovethethirdpole,andtostabilizesuchatopologyanestedMiller[8]compensationmustbeused.Thiscompensationtechniqueusesthetwocapacitors
Cc1andCc2showninFig.4.29.Cc1isconnectedbetweenthefinaloutputandtheoutputoftheintermediatestage.Cc2isconnectedbetweenthefinaloutputandthe
outputofthedifferentialstage.Figure4.30showsthethreestageopampofFig.4.29inmoredetail.ItconsistsofapchannelinputdifferentialpairQ1Q4,followed

Figure4.29
NestedMillercompensationschemeforathreestageopamp.

Page123

Figure4.30
Simplifiedcircuitdiagramofathreestageopampwith
nestedMillercompensation.

bythedifferentialpairQ5Q8,thatservesasthepositivegainintermediatestage.TheoutputstageisacommonsourceamplifiermadeoftransistorsQ9andQ10.The
opampisstabilizedbycapacitorsCc1andCc2.ThesmallsignalequivalentcircuitofthethreestageamplifierusingthenestedMillercompensationschemeisshownin
Fig.4.31[8].
Theopenloopgainoftheuncompensatedopamphasthreedominantpolessp1,sp2,andsp3.Thelocationofthethreepolesaregivenby

whereReq=ro3||RListheequivalentoutputimpedanceofthethirdstage.

Figure4.31
Smallsignalequivalentcircuitofthethreestageopamp.

Page124

Thetransferfunctionoftheuncompensatedopampis

whereA0isthedcopenloopgaingivenby

ThemagnitudeplotofthecombinedintermediateandoutputstagegainisshowninFig.4.32a,wheref 2=1/(2 ro2C2)andf 3=1/(2 ReqCL)arethepole

frequencies.ThecombinationoftheintermediateandoutputstagesiscompensatedbythefirstMillercapacitorCc1.Theinsertionofthiscapacitorsplitsthepolessuch
thatf 3isshiftedtoahigherfrequency,

Thenewlocationofthepolesisgivenby

ItisworthnotingthattheinsertionofCc1splitssp2andsp3tothesamelocation,aswasthecasewiththepolesofthetwostageopampdescribedearlierinthis
chapter.Also,thelocationofthepolesp1,correspondingtotheinputstage,remainsunaltered.
ThefrequencycharacteristicofthecompletethreestageopampisshowninFig.4.32bwherethethirdpolesp1correspondingtotheinputstagehasbeenadded.The
resultofinsertingthefirstcompensationcapacitorCc1isafrequencyresponsethatcontainsthetwodominantpolessp1and

uptotheunitygainfrequency.

InsertingthetwonestedMillercompensationcapacitorsCc1andCc2,asinthecaseofthetwostageopamp,introducesrighthalfplanezeros.Similarstrategies
describedearlierinthissection,suchasthezeroblockingtechniqueorplacingaresistorinserieswiththeMillercapacitortocancelthezero,canbeusedtoeliminate
theeffectoftheunwantedzeros.
Next,thestabilityconditionsofthesinglestagefoldedcascodeopampshowninFig.4.10willbeconsidered.Theapproximatelowfrequencyequivalentcircuitof
thisopampisshowninFig.4.11,andtheoverallfrequencyresponseisdescribedbyafirstordertransferfunctiongivenbyEq.(4.18).Heresp1=1/RoCListhe
dominantpole,duetotheloadcapacitanceCLinparalleltotheoutputimpedanceRo.Figure4.33illustratesthegainandphaseresponseoftheopampfortwo
different

Page125

Figure4.32
(a)Frequencyresponseoftheintermediateandoutputstagesbeforeand
afterinsertingC 1(b)frequencyresponseofthecompletethreestage
c

opampbeforeandafterinsertingthenestedMillercompensation
capacitorsCc 1andCc 2.

Page126

Figure4.33
LossandphaseresponsesoftheopampofFig.4.10fortwo
differentvaluesoftheloadcapacitanceCL.

valuesofCL.Thecontributionofthenondominantpolesonthephaseandamplituderesponsesisshownathigherfrequencies.Asthefigureillustrates,thelargerCL,
thegreaterthephasemarginoftheopamp.Thisistheoppositeoftheconditionsofthetwoorthreestageopamp,whereCLcontributestoanondominanthigh
frequencypole.There,increasingCLreducesthedistancebetweenthedominantandnondominantpoles,andthusdecreasesthephasemargin.Thusthefolded
cascodeopampofFig.4.10isparticularlysuitableforachievingwideandstableclosedloopbandwidthswithlargecapacitiveload,suchasrequiredinhigh
frequencyswitchedcapacitorcircuits.
Inaddition,thecompensationinthiscircuitisachievedwithoutcouplinghighfrequencynoisefromthepowersuppliestotheoutputasinmultistageopamps.Hence
thehighfrequencyPSRRcanbehigh.
4.5
DynamicRangeofCMOSOPAMPs
Amongthemostimportantcharacteristicsofanopamparetheinputstagecommonmoderange(CMR)andtheoutputstagevoltageswing.Theinputcommon
moderangespecifiestherangeofthecommonmodeinputvoltagevaluessuchthatthe

Page127

Figure4.34
(a)Opampcircuitwithoutcommonmodesignal
(b)unitygainopampconfigurationwithcommonmodesignal.

differentialstagecontinuestoamplifythedifferentialinputvoltagewithapproximatelythesamedifferentialgain.Theoutputvoltageswingistherangeoverwhichthe
outputvoltagecanvarywithoutexcessivedistortion.TwopossibleconfigurationsofanopampareshowninFig.4.34aandb.InFig.4.34atheopampisusedwith
twoexternalresistorsasaninvertingbuffer.Sinceoneinputoftheopampisconnectedtoground,thecommonmodeacinputiszero.InFig.4.34b,theopampis
connectedasaunitygainbuffer.Alloftheacinputsignalisnowappliedasacommonmodeinputtotheopamp.Whiletheoutputvoltageswingisimportantforboth
cases,theinputcommonmoderangeisimportantonlyfortheunitygainbufferofFig.4.34bandisnotimportantfortheinvertingbufferofFig.4.34a.
Figure4.35illustratesapchannelinputCMOSdifferentialstage.Thisstagewillbeusedasanexampletodiscusstheinputcommonmoderange.Thedrainto
sourcedcvoltageoftransistorQ1(andQ2)isgivenby

TheminimumallowablecommonmodeinputvoltageoccurswhenQ1andQ2are

Figure4.35
ApchannelinputCMOS
differentialstageusedto
calculatecommonmoderange.

Page128

attheedgeoftheirsaturationregions.ItcanbeobtainedbysettingVDS1=VDsat1inEq.(4.73):

SinceVTP 0andVTn|VTp| 0,theminimumcommonmodeinputvoltageisapproximatelyequaltoVSSplusthedraintosourcesaturationvoltageoftransistorQ3.

Asimilaranalysiscanbeperformedtodeterminethehighestcommonmodeinputvoltage.Astheinputvoltageisincreased,thedraintosourcevoltageofQ5is
reduced.ThemaximumcommonmodevoltageisachievedwhenQ5isabouttoleavethesaturationregion,orVDS5=VDsat5.ThedraintosourceofQ5isgivenby

SinceVDsat5,VDsat1,andVTpareallnegative,wehave

CombiningEqs.(4.75)and(4.78),theinputcommonmoderangeisfound:

NotethattypicalvaluesareVTp=0.8Vand|VDsat1|=|VDsat5|=0.3V.SofromEq.(4.79)itisclearthatwhilethepchannelinputdifferentialstageofFig.4.35hasa
reasonablygoodnegativecommonmodeswing,thepositivecommonmodeswingispoorandislimitedtoatleast1.4to1.6Vbelowthepositivepower

Page129

Figure4.36
AnnchannelinputCMOS
differentialstage.

supplyvoltage.Asimilaranalysiscanbecarriedoutforthedifferentialstagewithnchannelinputs,showninFig.4.36.Thecommonmoderangecanbederivedas

Forthiscasethepositiveinputcommonmodelimitisapproximatelyone|VDsat3|belowthepositivesupplyvoltageforVTn|VTp| 0.Thenegativelimitoftheinput
commonmodevoltageis1.4to1.6Vabovethenegativesupplyvoltage.TheinputcommonmoderangesofthetwodifferentialstagesofFigs.4.35and4.36are
complementary.Whilethepchannelinputdifferentialstagehasgoodnegativeandpoorpositiveinputcommonmodeswing,thenchannelinputhasthe
complementaryrange.Opampswithwidepositiveandnegativeinputcommonmoderangescanthereforebeobtainedusingacombinationofpandnchannel
differentialstages.TheyarediscussedinSection4.10.
Theoutputvoltageswingofthetwostageopampisdiscussednext.SuchanopampwithapchanneldifferentialinputisshowninFig.4.37.Theoutputvoltage
swingislimitedbytherequirementthattransistorsQ6andQ7mustremaininthesaturationregion.Itcanbeeasilyshownthatthisresultsinthecondition

IftheoutputswingsbeyondtherangespecifiedbyEq.(4.81),transistorsQ6andQ7willleavethesaturationregion,reducingthegainoftheoutputstage.Further
increaseoftheoutputvoltagewillbelimitedbythepowersupplyvoltages.
AsinglestagefoldedcascodeopampwithpchannelinputdevicesandanimprovedbiasingschemewasdiscussedearlierandwasshowninFig.4.10.First,

Page130

Figure4.37
TwostageCMOSopamp.

considerthelowerlimitoftheinputcommonmoderange.Withtheimprovedbiasingscheme,transistorsQ5andQ6arebiasedslightlyabovethesaturationregion,so

Asbefore,thedraintosourcevoltageofQ1isgivenby

SettingVDS5=VDsat5andVGS1=VDsat5+VTpinEq.(4.83),wehave

ForQ1attheedgeofsaturation,theminimumvalueofVDS1isVDsat1:

Rearrangingyields

SinceVTP<0andVDsat5>0,wecanrewriteEq.(4.86)as

Normally,VDsat5<|VTp|.Hence

<VSS,andtheinputcommonmodesignalcangobelowVSS.

Page131

Tofindthemaximuminputcommonmodevoltage,wenotethattheperformanceofthecircuitissimilartothatofthedifferentialstageshowninFig.4.35.Thisleads
to

SinceVDsat1,VDsat7andVTpareallnegativenumbers,Eq.(4.88)gives

CombiningEqs.(4.87)and(4.89)theinputcommonmoderangecanbewrittenas

AsEq.(4.90)shows,theinputstageofthesinglestagefoldedcascodeopampofFig.4.10hasanexcellentlowerlimitforitscommonmoderange,lowerthanthe
negativesupplyvoltage.Theupperlimitofthecommonmoderangeis,however,byasmuchas1.4to1.6Vbelowthepositivesupplyvoltage.Acomplementary
cascodeopampwithnchannelinputdeviceswillbecharacterizedbyexcellentpositiveinputcommonmoderange(whichincludesthepositivesupplyvoltage)anda
minimuminputcommonmodelimitthatis1.4to1.6Vabovethemostnegativesupplyvoltage.
TheopampofFig.4.10usesanimprovedbiasingschemesuchthatbothQ6andQ4arebiasedattheedgeofsaturation:

ThemaximumoutputvoltageswingwasderivedearlierandisgivenbyEq.(4.16).Fromthatequation,theoutputvoltageswingislimitedtoarangethatisatleast
2VDsataboveVSSand2VDsatbelowVDD.Ofcourse,v outcanswingbeyondtherangedescribedin(4.16)however,astheoutputcrossesthespecifiedupper(lower)
limit,firsttransistorsQ2c(Q4c)leavethesaturationregion,and(asillustratedinFig.3.14)theoutputimpedancedrops,resultinginareductionintheoverallgain.
Further,increase(decrease)ofv outcausesQ4(Q6)toleavethesaturationregionandresultsindrasticreductionintheoutputimpedanceandhenceinthegain.Inthis
regiontheopamphasverylittledifferentialgainandtheoutputsignalwillbeseverelydistorted.
Insummary,thesinglestagefoldedcascodeopampofFig.4.10hasanexcellentnegativeinputcommonmoderangebutapoorpositivecommonmoderange.It
has

Page132

Figure4.38
InternallycompensatedCMOSoperationalamplifier.

areasonablywideoutputvoltageswingtheoutputvoltagecanreachtowithin0.5to1Vofthesupplyvoltageswithoutseriousdistortionordropingain.
4.6
FrequencyResponse,TransientResponse,andSlewRateofCompensatedCMOSOPAMPs[9,10]
Next,anapproximatingfrequencyandtimedomainanalysisofthecompensatedCMOSopampofFig.4.38willbegiven.Forsmallinputsignalsv inthetransistors
willoperateintheirsaturationregions,andtheirsmallsignalmodelscanbeused.Then,formoderatefrequencies(i.e.,for|sp1| 0,thephaseofAvat 0willthusbe
closeto90.ThiscanbeobtainedbychoosingCcsufficientlylarge.

Figure4.39
SmallsignalmodeloftheCMOSopamp
usedtocalculateitsfrequencyresponse.

Page133

Figure4.40
SlewingresponseoftheCMOSopamp
connectedintheinvertingmode:(a)circuit
(b)inputsignal(c)smallsignaloutput
waveform(d)largesignaloutputwaveform.

ConsidernextthevoltageinvertershowninFig.4.40a.Assumeagainthattheamplifieriscompensated,sothatitsvoltagegaincanbeapproximatedby

Henceforaninputstepv in(t)=V1u(t),theoutputvoltageisintheform

(Problem4.11).Thus,forasquareinputvoltage(Fig.4.40b)theexponentiallyvaryingwaveformofFig.4.40cshouldoccurattheoutput.*IftheamplitudeV1issmall
(say,muchlessthan1V),thisisinfactwhathappens.If,however,theinputvoltageislarge(e.g.,V1=5V),theexperimentallyobservableoutputvoltageisofthe
formshowninFig.4.40d.Thenearlylinear(ratherthanexponential)riseandfallofv out(t)iscalledslewing,andthenearlyconstantslopedvout/dtofthecurveiscalled
theslewrate.Slewingisanonlinear(largesignal)phenomenon,andhenceitmustbeanalyzedintermsofthelargesignalmodeloftheopampshowninFig.
*

Thetimeconstantist 0=2/(A0|sp1|)=2/

Page134

Figure4.41
Largesignalmodelforcalculatingtheslewrateofa
CMOSopampintheinvertingmode.

4.41.Priortothearrivaloftheinputstep,v in=0,andthecurrentsinQ1andQ2arebothequaltoIo/2.Afterthelargestepoccursattheinput,Q1conductsmore
currentandcutsoffQ2.HencethecurrentconductedbyQ1andQ3isnowIo(Fig.4.41).SinceQ3andQ4formacurrentmirror,thecurrentinQ4(whichchargesCc)is
alsoIo.AssumingthattheoutputstageA2cansinkthecurrentIo,theslewrateis

whereQcisthechargeinCc.HereCc=gmi/ 0,where[fromEq.(2.18)]thetransconductanceoftheinputstageis

and 0istheunitygainfrequencyoftheopamp.Combiningtheserelations,weobtain

Thustheslewratecanbeincreasedbyincreasingtheunitygainbandwidthandthebiascurrentoftheinputstage,andbydecreasingtheW/Lratiooftheinput
transistors.
ItshouldbenotedthatthetransconductanceofMOSFETsismuchlowerthanthatofbipolardevices.Thisisordinarilyamajordisadvantagehowever,itresultsin
significantlyhigherslewratesforMOSopampsthanforbipolaronesforagivenunitygainbandwidthsinceCccanbesmaller.

Page135

Figure4.42
Slewinginavoltagefollower:
(a)opampusedasavoltagefollower
(b)largeinputsignal(c)outputresponse.

Thenegativeslewingofv outcontinuesuntilitreachesV1.AtthattimethegatevoltageofQ1[which,duetothetworesistorsR,equals(v in+v out)/2]reacheszero

voltage.Henceatthattimethequiescentbiasconditionsarerestored,andQ1toQ4allcarryacurrentIo/2.Therefore,thechargingofCcandthedecreaseoftheoutput
voltagecease.
Thecomplementaryprocesstakesplacewhenv indropsbacktozeroatt=t 2.NowQ1cutsoff,sincev out=V1stillholdsandhenceitsgatevoltagedropstoV1/2.
ThusQ3andQ4cutoff,andCcisdischargedthroughQ2withacurrentIo,providedthatA2cansourceatleastthesamecurrent.Theslewrateofv outishenceagain
Io/Cc.Theprocessstopswhenv out(andhencethegatevoltageofQ1)reacheszerovoltage.
InFig.4.41,theopampoperatesintheinvertingmode.Figure4.42aillustratestheuseoftheopampasaunitygainvoltagefollower.Figure4.42bshowsaninput
pulsewaveformFig.4.42cshowsthecorrespondingoutputresponseunderlargesignalconditions.Asthediagramshows,therisingedgecontainsapositivestep
followedbyafastslewingrise,whilethefallingedgeisarelativelyslowlinearslope.
ThebehavioroftherisingedgecanbeunderstoodbyconsideringtheequivalentcircuitshowninFig.4.43.Inthecircuit,thestraycapacitanceCwacrosstheinput
stagecurrentsourceIoisincluded.NotethatCwisquitelargeinCMOSopampswherethecommonsourcesoftheinputdevicesQ1andQ2areconnectedtothep
well,sincethiscreatesalargecapacitancebetweenthesourceandthesubstrate.
Alargeinputsignalv in(t)=V1u(t)turnsQ2fullyon.Thereforeitssourcevoltagev wrisesandhenceQ1andQ3areturnedoff.ThusQ2carriesthefullcurrentIo+iw,
whereiw(t)isthecurrentthroughCw.Sincenormallythecombinedimpedance

Page136

Figure4.43
Equivalentcircuitofthevoltagefollowerusedtocalculatethe
largesignalbehaviorforpositiveinputs.

ofCwandthecurrentsourceIoismuchlargerthanthedrivingimpedance(1/gm2)ofQ2,theincrementalsourcevoltageisv w(t) v in(t).Hence

whichistheimpulsefunctionV1Cw (t).Theoutputvoltagesatisfies

Thefirsttermrepresentsthelinearrise,withaslewrateIo/Cc,whilethesecondrepresentsthesmallpedestalseenatthebeginningoftherisingedge.
Foranegativestep,theequivalentcircuitofFig.4.44applies.NowtheinputsignalturnsQ2off,andQ1,Q3,andQ4allcarrythecurrentIoiw.Consideringnextthe
twocapacitorsCcandCw,wenotethatCcisconnectedbetweenv out(t)and(virtual)ground,whileCwisconnectedbetweenv wand(true)ground.Nowv w(t)follows
thegatevoltagev out(t)ofQ1,andhencev w v out,sothat

Therefore,iw=IoCw/(Cc+Cw)and

Page137

Figure4.44
Equivalentcircuitofthevoltagefollowerusedtocalculatethe
largesignalbehaviorfornegativeinputs.

ThusthenegativeslewrateisreducedbythepresenceofCw,fromIo/CctoIo/(Cc+Cw),thatis,byafactor1+Cw/Cc.
4.7
NoisePerformanceofCMOSOPAMPs
NoiserepresentsafundamentallimitationoftheperformanceofMOSopamps:theequivalentnoisevoltagemaybeseveraltimesgreaterthanacomparablebipolar
amplifier.ThenoiseperformanceofanMOSopampisduetoboththermaland1/fnoisesources.Thedominatingnoisesourcedependsonthefrequencyrangeof
interest.Atlowfrequenciesthe1/fnoisedominates,whereasathighfrequenciesthethermalnoiseismoreimportantandthe1/fnoisecanbeignored.Henceitis
importanttoanalyzethecausesofnoiseandthepossiblemeasuresthatcanreduceit.Asanexample,thenoiseofatwostageCMOSopampwillbeanalyzedand
thenoisecontributionofeachtransistortothetotalinputreferrednoisewillbepresented.Asimilaranalysiscanbecarriedoutforfoldedcascodeorothertypesof
opamps.
Figure4.45showsanuncompensatedCMOSopamp,withthenoisegeneratedbyeachdeviceQirepresentedsymbolicallybyanequivalentvoltagesourcev ni
connectedtoitsgate.*(Thecalculationofthegatereferrednoisevoltagesv niwasdescribedbrieflyinSection2.7.)Wecannextcombinethenoisesourcesv n1tov n4
inthedifferentialinputstageintoasingleequivalentsourcev ndconnectedtotheinputofanotherwisenoiselessinputstage,asshowninFig.4.46.(Notethatthenoise
ofQ5isacommonmodesignalandishencesuppressedbytheCMRRofthe
*

Suchasourceindicatesthatanoisecurrentg mivniflowsinQi.

Page138

Figure4.45
NoisesourcesinaCMOSoperationalamplifier.

opampitisthereforeomittedinFig.4.45.)Thevoltagegainfromthenoisesourcesv n1andv n2totheoutputnodeAoftheinputstagecanbecalculatedusingitslow

frequencyequivalentcircuit.Thisgives

Thisisthesameasthedifferentialsignalgainofthestage.Similarly,thegainbetweensourcesv n3andv n4andnodeAcanbecalculated.Physically,thenoisesourcev n3

introducesanoisecurrentgm3v n3intoQ3,whichismirroredinQ4.Hencev n3causescurrentsofQ3andQ4tochangebygm3v n3,andthusv Abygm3v n3/(gd2+gd4).The
effectofv n4issimilar.Thegainistherefore

Figure4.46
BlockdiagramofathreestageCMOSoperational
amplifierwithnoisesources.

Page139

Sincethesesourcesarealluncorrelated,theyresultinameansquarevoltage

atnodeA.Hencetheequivalentinputnoisevoltagev nd=v A/Adhasthemeansquarevalue

Hence,tominimize
Theformer,bythediscussionsofSection2.7,requiresthatthearea(W/L)andtransconductance(gm)ofQ1andQ2belarge.Toobtain
largegm,thebiascurrentandW/Lratioshouldbelargethis,however,requireslargedevicesandhighpowerdissipation.
Thenoisecontributionoftheloaddevicescanbereduced,as(4.104)shows,bymakingtheirtransconductancesassmallastheirbiasingconditionspermit.Thiscan
beachievedbyincreasingtheirlengthsL.Thus,assumingthattheareasoftheinputandloaddevicesaregiven,theW/LratiosoftheinputdevicesQ1andQ2shouldbe
aslarge,andthoseoftheloaddevicesQ3andQ4assmallasotherconsiderationspermit.Also,ithasbeenfoundexperimentally[11]thatthermsequivalent1/fnoise
voltagev nisaboutthreetimeslargerforannchanneldevicethanforapchanneldevice.SinceinEq.(4.104)(gm4/gm1)2 1,itishenceadvantageoustousep
channelinputdeviceswithnchannelloads,ratherthantheotherwayaround,asshowninFig.4.45.Applyingalltheseprinciples,theequivalentinputnoisevoltagev nd
canbereducedappreciably[11].
Similarly,thenoisesourcesofthesourcefollower(Q6,Q7)canbereplacedbyanequivalentsourcev ns(Fig.4.46).Fromthelowfrequencysmallsignalequivalent
circuit,

Referring

backtotheinputoftheopamp,thetotalequivalentinputnoisevoltagebecomes

Forlowfrequencieswhere
theeffectofv nsisnegligiblehowever,athigherfrequenciesthiswillnolongerbetrue.SinceQ6andQ7areusedasalevelshifter,
thegatesourcevoltagedropofQ6mustbelarge.ByEq.(2.9)thiswillbeachieved

Page140

foragiveniD6ifk 6=k (W/L)6issmall.HenceQ6isalongthindevice,and

Atfrequencieswhere|Ad( )| gm7/gm6,theeffectofv n7iscomparabletothatof
v n1andv n2.HencecaremustbetakeninthedesignofQ7tomakeitalownoisedevice.
Theeffectofthenoisesourcesv n8andv n9canbeanalyzedsimilarlyandcanberepresentedbyanequivalentsourcev n0.However,theyusuallydonotaffectthetotal
equivalentinputnoisevoltagesignificantly.
Normally,allv nicontaina1/fnoisecomponentthatdominatesitatlowfrequencies.Hencetheequivalentinputnoisevoltageisgreatestatlowfrequencies(below1
kHz),where

ThustheinputdevicesQ1andQ2tendtobethedominantnoisesources,andtheiroptimizationisthekeytolownoisedesign.

Usingchopperstabilizeddifferentialconfiguration,thelowfrequency1/fnoiseoftheopampcanbecanceled,andalarge(over100dB)dynamicrangeobtainedfor
anintegratedMOSlowpassfilter.Forwidebandoperationalamplifiersandalowclockfrequency,aliasingcanincreasetheeffectofthehighfrequencynoisetothe
pointwhereitoverwhelmsthe1/fnoise.Hencetheunitygainfrequency 0shouldbekeptaslowasispermittedbytheapplicationathand.
4.8
FullyDifferentialOPAMPs
Incaseswhenpowersupplyandsubstratenoiserejectionisanimportantconsideration,theuseoffullydifferential(balanced)signalpathsmaybeadvantageous.In
suchcircuitstheinputvoltagesaresymmetricalwithrespecttothecommonmodeinputvoltageVcmi,andtheoutputvoltagesaresymmetricalwithrespecttothe
commonmodeoutputvoltageVcmo.Thisallowsthedesignertochoosethevaluesofinputandoutputcommonmodevoltages(VcmiandVcmo)independently,for
optimumperformance.Althoughformaximumswing,Vcmoshouldbeequaltohalfthetotalsupplyvoltage,thesamemaynotbethecaseforVcmi.Thismakesthe
designoffullydifferentialcircuitsmorecomplicatedandtherequiredchiparea50to100%largerthanthesingleendedrealizationofthesamenetwork.However,
therearemanycompensatingadvantagesintermsofnoiseimmunity.Infullydifferentialopamps,powersupplyandsubstratenoiseappearascommonmodesignals
andarehencerejectedbythecircuit.Inaddition,aswillbeshown,theeffectiveoutputvoltageswingisdoubledbythebalancedopampconfiguration,whiletheinput
circuit(andhencemostofthenoise)remainsthesameasforthesingleendedopamps.
Additionaladvantagesalsoexist.Figure4.47showsthecircuitofafullydifferentialswitchedcapacitor(SC)integrator.Inthiscircuittheswitchesillustrated
schematicallyinthefigureintroduceaclockfeedthroughnoiseintothecircuit.Thiscanbeminimizedbythedifferentialconfiguration,since(justasthepowersupply
noise)itwillappearasacommonmodesignal.Thesymmetryofthecircuitshouldbefullypreservedinthephysicallayouttoobtaingoodrejectionofcommonmode
signalseveninthepresenceofstrayelementsandnonidealities.Thedifferentialconfigurationalsoeliminatessystematicoffsetvoltages.

Page141

Figure4.47
Fullydifferentialswitchedcapacitorintegrator.

Thenoiserejectionpropertiesofthefullydifferentialcircuitsinactualimplementationarenotaseffectiveasthetheorypredicts.Thisispartlybecausethenoise
coupledfromthepowersuppliesorsubstrateisnotfullysymmetrical.Alsotheclockfeedthroughnoisefromswitcheshasavoltagedependentcomponentthat
couplestoonesignalpathmorethantheother.However,byusingcarefulandsymmetricallayoutmethodologiesitisalmostguaranteedthatthenoiserejection
propertiesoffullydifferentialcircuitsarefarsuperiorthanthoseofsingleendeddesigns.
ThecircuitdiagramofafullydifferentialsinglestagefoldedcascodeopampisshowninFig.4.48.ThiscircuitisobtainedbymodifyingtheopampofFig.4.10and
replacingthepchannelcurrentmirrorswithtwocascodecurrentsourcesQ3,

Figure4.48
Circuitdiagramofafullydifferentialsinglestage
foldedcascodeopamp.

Page142

Figure4.49
Circuitdiagramofatwostagefullydifferentialopamp.

Q3candQ4,Q4c.Figure4.49showsanalternativetwostagefullydifferentialopamp[12].ThedifferentialinputstageconsistsoftransistorsQ1A,Q1B,Q2A,Q2B,Q9A,
Q9B,andQ5.ThecommongatedevicesQ9AandQ9Bhavebeenaddedtoincreasethegainoftheoperationalamplifierandtoreducethedifferentialinputcapacitance.
Thetwodifferentialoutputstagesareformedwiththetwocommonsourceamplifiers,consistingoftransistorsQ3A,Q4A,Q3B,andQ4B.Acommonmodefeedback
(CMFB)circuithasbeenaddedtobothopamps.TheCMFBcircuittakesitsinputsfromthedifferentialoutputoftheopampandprovidesacommonmode
feedbacksignal.Thisisnecessary,sinceinafullydifferentialopampthecommonmodeoutputvoltagemustbeinternallyforcedtogroundortosomeotherreference
potential.Bycontrast,inasingleendedopamponeoftheinputterminalsisusuallygroundedandtheotherbecomesvirtualgroundduetoanexternallyapplied
negativefeedback.Thisstabilizesthecommonmodevoltagesatbothinputandoutputterminals.
OneofthemaindrawbacksassociatedwiththefullydifferentialopampistheneedfortheCMFBcircuit.Besidesrequiringextraareaandpower,theCMFBcircuit
limitstheoutputswing,increasesnoise,andslowsdowntheopamp.ThedesignofagoodCMFBcircuitisoneofthemostcomplicatedpartsofthefullydifferential
opampdesign.TherearetwomajordesignapproachesfortheCMFBcircuits,theswitchedcapacitorapproach[13]andthecontinuoustimeapproach[12,14].
Theswitchedcapacitorapproachisnormallyusedinswitchedcapacitorcircuits,whilethecontinuoustimeapproachisusedinnonsampleddataapplications.

Page143

Figure4.50
Fullydifferentialfoldedcascodeopampwith
continuoustimeCMFBcircuit.

Figure4.50showsthesinglestagefullydifferentialfoldedcascodeopampofFig.4.48withacontinuoustimeCMFBcircuitadded[15,16].Thecommonmode
feedbackoperatesthefollowingway.SincethegatevoltagesofQ5andQ6arefixedatVb1andtheircurrentsareI+I0/2,theirsourcevoltagesarealsostabilized.This
fixesthedraintosourcevoltagesv DS7andv DS8ofQ7andQ8.ThevalueofVb1ischosensuchthat|v DS7| Thecommonmodevoltagev out,cisthusincreased.Thegain
ofthenegativefeedbackloopisreadilyseentobegm7rd7gm5rd5gm1crd1c,whichcanbeveryhigh.Thisfeedbackloopalsostabilizesv out,cagainsttransistorparameter
variationsarisingfromfabricationimperfections.
SinceQ7andQ8operateintheirlinear(ohmic)regions,theirdraincurrentsarelinearfunctionsoftheirgatevoltages.Thusitcanreadilybeshown(Problem4.16)that
adifferentialvoltagevattheoutputterminalsdoesnotaffecttheoveralldrainsourceresistanceoftheparallelcombinationofQ7andQ8.Thusthecommonmode
outputvoltagedoesnotchangeifadifferentialinputsignalisappliedthisis,ofcourse,adesirablefeature.

Page144

Usingsmallsignalanalysis,itcanbeshown(Problem4.17)thatthedifferentialgainofthestageis

whereRoistheoutputimpedanceateitheroutputnode:

Sincethecircuitisafoldedcascode,itdoesnotrequirealevelshifter.Also,sincethedesiredoutputisadifferentialsignal,nodifferentialtosingleendedconversionis
required.Thusthenondominantpolesintroducedbythesestagesdonotappear.Theonlyhighimpedancenodesaretheoutputterminals,andthecorresponding
dominantpolesarethoseduetothetimeconstants .Sincenointernalcompensationisrequired,theopampcanhaveafastsettlingtimeandishencewellsuited
fortheimplementationofhighfrequencyswitchedcapacitorfilters.
Sincetheoutputimpedancesofthecircuitcanbemadeveryhigh,thedcdifferentialgainADcanbelarge,comparabletothatofabasictwostageopamp.Apossible
biaschaincircuitfortheopampofFig.4.50isshowninFig.4.51.ChoosingI=Io/2,theaspectratioscanbefoundas

(W/L)19shouldbechosen(inconjunctionwiththeotheraspectratiosinthebiaschain)tosetIotoitsdesiredvalue.Forthisbiascircuitwiththeaspectratiosgiven
above,thedccurrentsofQ7,Q8,andQ14areequal.Also,theirdcdrainvoltagesareapproximatelythesame.Hencetheirgatetosourcedcbiasvoltagessatisfy

ThisshowsthatVG7=VG8 VG14=Vcm.ThustheoutputcommonmodevoltageisequaltoVcmwhenthisbiascircuitisdesignedusingEq.(4.109).

Page145

Figure4.51
Biaschainforthe
fullydifferentialop
ampofFig.4.50.

AnalternativeformofcontinuoustimecommonmodefeedbackcircuitisshowninFig.4.52[17,pp.287291].Thiscircuitcanbeusedtoprovidecommonmode
feedbackforthefoldedcascodedifferentialopampofFig.4.48.ThefeedbackvoltageVFBwillbiastransistorsQ3andQ4.Intheabsenceofadifferentialvoltage
hasavaluethatisexactlythenegativeof

Figure4.52
AlternativeformofcontinuoustimeCMFBcircuit.

Page146

(withrespecttoVcm),thecurrentinQ8willincrease(decrease)whilethecurrentinQ13willdecrease(increase),keepingthecurrentinQ15unchanged.The
commonmodevoltagewillbekeptclosetoVcmaslongasthedifferentialvoltageisnotsolargethatthetransistorsinthecommonmodefeedbackcircuit(Q8,Q13)
turnoff.Thesizesofthetransistorsinthedifferentialpaircanbeselectedinsuchawaythattheirgatesourcevoltagesaremaximized,henceextendingtheoperating
range.Theinputrange,however,isamajorlimitationofthiscircuit.
Otherthanthelimitedinputdifferentialrange,thecommonmodefeedbackcircuitsdescribedsofarhavetwoadditionaldrawbacks.Firstthecircuitthatdetectsthe
outputcommonmodesignalhasanonlinearcharacteristic.Second,theopenloopgainofthecommonmodefeedbackmaynotbesufficientlylarge,duetoits
inherentlimitations.Thefirstproblemcanbeavoidedbyusinglinearcommonmodedetectorssuchasapairofidenticalresistorsorthecorrespondingswitched
capacitorequivalentforsampleddatacircuits.Toreducetheeffectofthesecondproblem,theoutputcommonmodefeedbackcircuitshouldhaveadcgainand
bandwidthaslargeastherespectivedifferentialmodecircuitry.Thiscanbeaccomplishedbyhavingthedifferentialandoutputcommonmodepathsshareasmuch
circuitryaspossible,thustreatingbothsignalsasequallyaspossible[12].Theseconceptscanbeappliedtothecommonmodefeedbackcircuitofthetwostagefully
differentialopampofFig.4.49.ThecompletecircuitdiagramoftheopampisshowninFig.4.53.ThecommonmodefeedbacksignalVcisformedwithtwoequal
valuedresistorsthatareconnectedbetweenthetwodifferentialoutputsandisgivenby
Thecommonmodefeedbackcircuitconsistingof
transistorsQ6A,Q6B,Q6C,Q8,andQ7ismergedwiththedifferentialmodecircuitryatthe

Figure4.53
Schematicdiagramofatwostagefullydifferentialopampwith
acommonmodefeedbackcircuit.

Page147

Figure4.54
Conceptualrepresentationofthe
resistivedividercommonmode
signaldetectorofFig.4.53.

veryfrontendoftheoperationalamplifier.Therefore,anequallyamplifiedcommonmodefeedbacksignalanddifferentialmodeinputsignalarecombinedascurrents
intotheloadsQ2AandQ2B.Fromthereontotheoutputs,thesignalssharethesamecircuitry,includingthecompensationnetworksconsistingofRCA,CCA,RCB,andCCB.
Onepotentialdrawbackofthiscircuitistheresistorsinthecommonmodesignaldetector,whichloadstheopampdifferentialoutputstagesandhencedegradesthe
amplifierdcgain.ThiseffectcanbereducedbydesigningtheoutputstagetransistorsQ3A,Q3B,Q4A,andQ4BtohavelargeW/Lratiosandlargecurrents,hence
increasingtheirtransconductances.
TheuseofresistivedividercommonmodesignaldetectorisshownconceptuallyinFig.4.54.Insampledanalogsystemssuchasswitchedcapacitorcircuits,thesame
methodusedforprocessingthedifferentialsignalscanbeusedforthecommonmodedetectorcircuit.Figure4.55showsthesymbolicrepresentationofthedifferential
switchedcapacitorintegratorofFig.4.47withaswitchedcapacitorcommonmodedetector.InthiscircuitapairofintegratingcapacitorsCc1andCc2andapairof
switchedcapacitorresistors 1Cc1and 1Cc2implementsthecommonmodesignaldetector.ThiscircuitisequivalenttoaparallelRCcircuitwhichtakestheaverage

Figure4.55
Fullydifferentialintegratorwithswitchedcapacitor
commonmodefeedbackcircuit.

Page148

Figure4.56
Fullydifferentialfoldedcascodeoperationalamplifierwith
switchedcapacitorcommonmodefeedback.

ofthetwovoltages .Forproperoperation,thetimeconstantoftheequivalentRCshouldbemuchfasterthantheoneinthedifferentialsignalpath[13,18].
Normally,thesizesof 1Cc1and 1Cc2arebetweenonefourthandonetenthofthatofthenonswitchedcapacitors.
ThecircuitdiagramofafullydifferentialfoldedcascodeoperationalamplifierwithswitchedcapacitorcommonmodefeedbackisshowninFig.4.56.Thecommon
modeoutputleveloftheamplifierismaintainedbytheswitchedcapacitorfeedbackcircuitry.CapacitorsC1andC2inFig.4.56haveequalvaluesandformavoltage
divider.AbiasvoltageisgeneratedacrossthesecapacitorsbasedontheaveragevoltageofthedifferentialoutputsandisusedtocontrolthegatesoftheNMOS
transistorsintheoutputstage(nodeA).ThedcvoltagesacrossCc1andCc2areestablishedbytheswitchedcapacitors 1Cc1and 1Cc2.Thesecapacitorsarefirst
chargedbetweenthedesiredoutputcommonmodevoltageandafixedbiasvoltageandaresubsequentlythrowninparalleltoCc1andCc2.Thefixedbiasvoltageis
equaltothedesiredvoltageusedtobiastheoutputstagecurrentsources.OnlychangesinthecommonmodeoutputarecoupledtonodeA,whichreturnsthe
commonmodeoutputvoltagetothedesiredlevelthroughnegativefeedback.Duringtheperiodthattheswitchescontrolledby 1areon,correctivechargesare
transferredtoCc1andCc2throughtheswitchedcapacitorstopreventanydriftinthecommonmodeoutputvoltage.Theswitchedcapacitorcommonmodefeedback
circuithasawideoutputvoltageswingandisthepreferredchoiceinapplicationswheretheopampisusedinafullydifferentialcircuitinvolvingswitchedcapacitors.

Page149

4.9
CMOSOutputStages
Themainobjectiveoftheoutputstageofanoperationalamplifieristobeabletodrivealoadconsistingofalargecapacitance(uptoseveralnanofarads)and/ora
smallresistance(downto50 orless)withanacceptablylowlevelofsignaldistortion.Itisalsodesirabletohavealargeoutputvoltagerange,preferablyfromrailto
rail.Toachievetheextendedvoltageswing,theoutputtransistorsshouldbeconnectedinacommonsourceconfiguration.Infact,inCMOSoperationalamplifier
designpracticeapushpullstageisoftenusedasanoutputstage,asshowninFig.4.57.Thepushpullstageconsistsoftwocomplementarycommonsource
transistorsQ1andQ2,allowingrailtorailoutputvoltageswing.Thegatesofthetwooutputtransistorsarenormallydrivenbytwoinphaseacsignalsseparatedbya
dcvoltage[19,20].Whentheinputsignalsareabovetheircorrespondingdcvalues,thedraincurrentoftheNMOSdevicewillbelargerthanthedraincurrentofthe
PMOStransistor,andhencetheoutputstagepullsacurrentfromtheload.If,ontheotherhand,theinputsignalsarebelowtheirdcvalues,theoutputstagesources
morecurrentthanitsinksandthusitpushesacurrentintotheload.
Anotherimportantfeatureoftheoutputstageistheefficiency,whichrequiresahighratiobetweenthemaximumsignalcurrentthatcanbedeliveredtotheloadandthe
quiescentcurrentoftheoutputstage.Toachievethisrequirement,aclassBbiasingschemecanbeused.Becauseanoutputstageusingthistypeofbiasingwill
providealargeoutputcurrentwithaquiescentcurrentthatisapproximatelyzero.Thedrawback,however,isthatoutputstageswithclassBbiasingintroducealarge
crossoverdistortion.ThedistortioncanbereducedbyusingaclassAbiasingscheme.However,themaximumoutputcurrentofaclassAbiasedoutputstageisequal
toitsquiescentcurrent,whichresultsinpoorpowerefficiencyforarailtorailoutputsignal.
AcompromisecanbeachievedbetweencrossoverdistortionandquiescentpowerdissipationbyusinganoutputstagethatisbiasedbetweenclassAandclassB.
ThisiscalledtheclassABbiasingscheme.InthepushpulloutputstageofFig.4.57,theclassABbiasingschemecanbeaccomplishedbykeepingthevoltage
between

Figure4.57
PushpullCMOS
outputstagewith
railtorailoutput
swing.

Page150

Figure4.58
PushpullCMOSoutput
stagewithclassABbiasing.

thegatesoftheoutputtransistorsconstant.ThisprincipleisshowninFig.4.58.Tomakethequiescentcurrentandtherelationbetweenthepushandpullcurrents
independentofthesupplyvoltageandprocessvariations,thevoltagesourceVABinFig.4.58hastotracktheseparameters.Figure4.59showsthedesiredclassAB
transferfunctionwheretheoutputtransistorsarebiasedwithasmallquiescentcurrent,whichimprovesthecrossoverdistortioncomparedtoaclassBbiasedoutput
stage.Alsoshownisthemaximumoutputcurrent,whichismuchlargerthanthequiescentcurrentandincreasesthepowerefficiencycomparedtoaclassAbiased
outputstage.Tofurtherreducethecrossoverdistortion,thetransistorthatisnotdeliveringtheoutputcurrentshouldbebiasedwithasmallamountofresidualcurrent.
Thiscurrentwilleliminatetheturnondelayofthenonactiveoutputdevice,hencereducingthecrossoverdistortion[21].ThisminimumcurrentisrepresentedbyIminin
Fig.4.59.
TwootherimportantparametersofthepushpullrailtorailoutputstageofFig.4.58aretheoutputvoltagerangeandthemaximumoutputcurrentthatissuppliedto
theload.Todeterminetheoutputvoltagerange,firstassumethattheinputsignalvoltageinFig.4.58isincreasing.ThiswillcausetheNMOStransistortopullmore
currentfromtheload,andthustheoutputvoltagedecreases.ThisprocesscontinuesuntiltheNMOSdeviceendsupinthetrioderegionandtheoutputvoltage
becomes

Figure4.59
OutputstagecurrentforclassABbiasing.

Page151

Figure4.60
Multistagelowoutputimpedanceopamp.

limited.ThesamehappensforthePMOSdevicewhentheinputsignaldecreases.Theoutputvoltageswingcanbeextendedbymaximizingthegatetosourcevoltage
swingandbychoosingthelargestpossibleW/Lratiofortheoutputdevices.Theallowablegatetosourcevoltagedriveandthedimensionsoftheoutputtransistors
alsodeterminethemaximumoutputcurrentoftheoutputstage.Inconclusion,anadequatelydesignedclassABoutputstageshouldallowthegatetosourcevoltage
oftheoutputtransistorstogetasclosetothesupplyrailsaspossible.
Operationalamplifiersthatarerequiredtodriveaheavyloadattheoutput(especiallyasmallresistance)useamultistagestructure,asshowninFig.4.60[22].The
firststageistypicallyatransconductancepreamplifier,whichprovidesdifferentialinputandalargegain.TheoutputstageisaclassABbiasedpushpullcircuitthat
provideslowoutputimpedanceandalargecurrentdrivingcapability.Inthefollowingavarietyofoutputstagesarepresentedanddiscussed.
ThefirstcircuitconsideredisshowninFig.4.61[22].Forazeroapplieddifferentialinputsignal
thetwomatchedcurrentsourcesI,madeofdevices
Q10andQ11,uniquelydefinethecircuitquiescentcurrentlevel.ForsimplicityletusassumethatthefourNMOSinputtransistorsQ1,Q2,Q5,andQ6andthefour
PMOSinputtransistorsQ3,Q4,Q7,andQ8areidenticaldevices.ThenVGS1=VGS2=VGS5=VGS6andVGS3=VGS4=VGS7=VGS8,whichresultsinI1=I2=I.Underthis
conditionthecurrentinoutputdevicesQ14andQ15isalsodeterminedbythecurrentsourcedevicesQ10andQ11andtheW/LratioofthetwocurrentmirrorsQ12,Q14
andQ13,Q15.Itfollows,therefore,thattheclassABbiasingscheme

Figure4.61
SchematicofclassABamplifier.

Page152

makesthequiescentpowerconsumptionofthecircuitbecontrolledpreciselybythetwomatchedcurrentsourcesintheinputstage.
Whenthedifferentialinputsignalispositive( ,whilethedropacrossQ1andQ4isdecreasedbythesameamount.Consequently,thecurrentthroughQ13isincreased
whilethecurrentinQ12isreducedclosetozero,andacurrentmuchlargerthanthequiescentlevel,determinedbytheW/LratioofQ13andQ15,isavailablethroughQ15
tobedeliveredtotheload.
ThepeakvalueforcurrentsI1andI2andhencetheoutputcurrentisafunctionoftheappliedinputvoltage.Inpractice,however,asthecurrentlevelincreases,thesum
ofthevoltagedropsacrossQ1,Q4,andQ12(Q3,Q2,andQ13)alsoincreases,untilitisequaltothetotalsupplyvoltage.AtthispointdevicesQ1andQ4(Q2andQ3)or
bothenterthelinearregionofoperation,andthecurrentlevelbecomespracticallyconstantindependentoftheappliedinputvoltage.
ThecircuitofFig.4.61canbeusedasastandalonesinglestageopamp.Itisalsosuitableforadifferentialoutputopampsinceitcanproduceacomplementary
outputsimplybyaddingtwoadditionalcurrentmirrorssymmetricalwithrespecttoQ12,Q14andQ13,Q15.Figure4.62showstheentirefullydifferentialamplifier
schematicwherecascodetransistorscanbeaddedtotheoutputstagetoincreasetheoutputimpedanceandhencethegain[14].Acommonmodefeedbackshould
beaddedtoVcminFig.4.62forproperoperation.TheamplifierofFig.4.61canalsobeusedastheoutputsectionforatwostageamplifier.Figure4.63showsthe
schematicofatwostagelowoutputimpedanceopamp,wherethefirststagetransconductanceamplifierismadeofasimplefoldedcascodedifferentialamplifier.
Notethatinthisconfigurationoneinputofthedifferentialoutputstageisconnectedtoanappropriatedcpotential(Vbias4),suchashalfwaybetweenthetwosupplies.It
is

Figure4.62
Simplifiedschematicoffullydifferential
opamp.

Page153

Figure4.63
Twostagelowoutputimpedanceopamp.

alsopossibletoconnectthedifferentialinputoftheoutputstagetothedifferentialoutputofafullydifferentialfoldedcascodetransconductanceamplifier.Thisisshown
inFig.4.64,whereacommonmodefeedbackisusedtostabilizethedifferentialoutputofthefirststage[14].Thistechniqueisdiscussedinmoredetaillaterinthe
section.
AsimplifiedversionoftheclassABoutputstageofFig.4.61isshowninFig.4.65a[23].ComparedtotheamplifierofFig.4.61,thepositiveinputandallthe

Figure4.64
Alternativeformoftwostagelowoutputimpedanceopamp.

Page154

Figure4.65
(a)ClassABoutputstage
(b)widebandclassABoutputstage.

Page155

correspondingdevicesareeliminated.Theinputv inisintentionallybiasedoneVGSbelowthepositivesupplyanditdirectlydrivesthegateofthepchanneloutput
device.Thenchanneloutputtransistorisdrivenbytheoutputofthecommongateamplifier,consistingofdevicesQ12,Q13,andQ14.Assumingthat

theninquiescentcondition,

and
I1=pIQ,
Io=mpIQ.
Also,fromEqs.(4.111)(4.114)andEq.(4.115)itisclearthatinquiescentconditions

Undertheseconditions,thebiasvoltageofv inissettoVDDVGS15.Theinputvoltagev ininthenegativedirectioncanswingfromVDDVGS18allthewaydowntoVSS,

causingQ18toprovidealargesourcingcurrent.Themaximumsourcingcurrentisgivenby

Inthepositivedirection,v incanswingfromVDDVGS18toVDD.Themaximumsinkingcurrentisgivenby

wherek i= (W/L).

Page156

ReferringtoFig.4.65a,theoperationofthecircuitisasfollows.Tosourceanoutputcurrent,v ingoeslowanddrivesthegateofQ18morenegative,whichincreasesits
draincurrent.Atthesametime,theoutputofthepositivegaincommongateamplifierconsistingofdevicesQ12,Q13,andQ14alsogoeslow,reducingthecurrentof
Q19.Tosinkcurrent,v ingoeshighitshutsoffQ18byreducingitsgatedriveandalsopullsthegateofQ19high,whichinturnincreasesitsdraincurrent.Themaximum
sourceandsinkcurrentsaregivenbyEqs.(4.119)and(4.120).
Todrivesmallresistiveloads,thedevicesusedintheoutputstageareverylarge.Sincethetransistorparasiticcapacitancesincreasemuchfasterthanits
transconductance,thefrequencyresponseoftheoutputstageandthereforetheentireopampdeteriorates.Morespecifically,asaresultofadramaticincreasein
CGS19,thenondominantpoleatnodeAmovesclosertothedominantpoleandhencemakesthefrequencycompensationverydifficult.Analternativewidebandcircuit
isshowninFig.4.65b,whereasourcefollowerQ21hasbeenaddedtobiasnodeA,andtheimpedancehasbeenreducedfrom1/gm14inFig.4.65ato1/gm21inFig.
4.65b.
ThecompletecircuitschematicofthetwostagelowoutputimpedanceopampthatusestheoutputstageofFig.4.65bisshowninFig.4.66.Theinput
transconductancestageismadeofafoldedcascodedifferentialamplifier.ThebiascurrentissetbyresistorRBandthethreediodeconnecteddevicesQ31toQ33,
whichareconnectedinseriesbetweenVDDandthenegativesupply.Thefrequencyresponseofthecircuitexhibitsseveralrealpoles.Ithastwodominantpoles,which
areduetotheoutputimpedanceandthecorrespondingloadcapacitancesofthefoldedcascodedifferentialamplifierandtheoutputstage.Theremainingnondominant
polesareatnodesAtoH,whicharelocatedatmuchhigherfrequenciesthanarethedominantpoles.Thisisbecausetheimpedancelevelsatallthesenodesare
determinedbythe1/gmvalueofalargeMOSdevice,whichismuchsmallerthantheoutputimpedanceatthetwonodesthatdeterminethetwodominantpoles.The
opampthereforecanbecompensatedusingtheMillercapacitanceCcinserieswithazeronullingNMOSdeviceoperatingintrioderegion,whichisconnected
betweenthetwohighimpedancenodes.
AnotherapproachforaclassABpushpulloutputstageisillustratedinFig.4.67[24].HerethetwolargecommonsourceoutputtransistorsQ1andQ2aredrivenby
twoerroramplifiers,A1andA2.ThefeedbacklooparoundA1(A2)andQ1(Q2)ensureslowoutputimpedance.Inthisconfigurationtheerroramplifiersmustsatisfya
numberofrequirementsforproperoperationoftheoutputstage.First,sincetheerroramplifiershaveaninputreferreddcoffsetvoltageontheorderofseveral
millivolts,theymusthaveareducedvalueofopenloopgainontheorderof10.Otherwise,inthecaseofalargegain,theinputreferredoffsetvoltage,whenreferred
totheoutput,willcauseunacceptablevariationsofthequiescentcurrentsinQ1andQ2.Asecondrequirementisthattheerroramplifiersmusthavearailtorailoutput
andinputswingsothattheycanprovidegooddrivecapabilityfortheoutputtransistors.Finally,theymustbebroadband,topreventcrossoverdistortion.Thismay
becomedifficulttoachieve,however,duetostabilityconstraints.
AnalternativeformoftheoutputstageofFig.4.67canbeachievedbyconsideringtheCMOSclassABcomplementarysourcefollowerstageofFig.4.68,whichis
a

Page157

Figure4.66
TwostagelowoutputimpedanceopampthatusestheoutputstageofFig.4.65b.

Page158

Figure4.67
BlockdiagramofCMOSopampwith
classABpushpulloutputstage.

directanalogofitsbipolarcounterpart.Inthecircuit,Q1andQ4formagainstage,whileQ5andQ6drivetheloadRLandQ2andQ3provideavoltagedropbetween
thegatesofQ3andQ6toreducecrossoverdistortion.ThesizesofQ2andQ3arechosensuchthatthegatetosourcevoltagesofQ5andQ6areslightlylargerthantheir
thresholdvoltages.Theprimarydrawbackofthiscircuitisthatthegatetosourcevoltageoftheoutputtransistorslimitstheoutputvoltageswing.Themaximumoutput
voltageforRL isVDDVT5andtheminimumisVSS|VT6|,whereVT5(VT6)isthethresholdvoltageofQ5(Q6).IfRLdrawscurrentfrom,say,Q5,thedevicemust
provideadraincurrentv out/RLandhenceneedsagatetosourcevoltage
ThisincreasesrapidlywithdecreasingRLandhencerepresentsan
importantlimitationontheachievablepositiveoutputvoltageswing.Similarconsiderationshold,ofcourse,fornegativeswings,duetothenecessaryVGS6.
ManyoftheproblemsoftheoutputstagesofFig.4.67and4.68areeasilysolved

Figure4.68
CMOSclassABpushpulloutput
stagebasedonthetraditional
bipolarimplementation.

Page159

Figure4.69
CombinedclassABandclassBoutputstage.

bymergingthetwooutputstagesasshowninFig.4.69.TheproblemofquiescentcurrentcontrolissolvedbydeliberatelyintroducinganoffsetvoltageintoA1andA2
insuchawaythattransistorsQ7andQ8arenotcarryinganycurrentinthequiescentstate.TransistorsQ5andQ6thereforecontrolthequiescentoutputcurrent.The
quiescentoutputcurrentwillbeproportionaltothecurrentthroughQ2andQ3andisafunctionoftheW/LratiosofQ5toQ3andQ6toQ2.InsteadystatetheclassAB
circuitconsistingoftransistorsQ5andQ6carriestheentireoutputcurrent.TheclassBoutputstage,consistingofopampsA1andA2,hasaverylargecurrentdriving
capabilitybutiskeptoffinquiescentconditions.Whendrivingsmallresistiveloads,theclassBoutputstagetakesoveroperationofthestage.
Besidestheirusefulnessinquiescentcurrentcontrol,transistorsQ5andQ6provideahighfrequencyfeedforwardpathfromtheinputtotheoutputofthepushpull
stageandreducetheexcessphaseshiftintroducedbyopampsA1andA2.Theopampsstillrequiresomenominalphasecompensationtomakethemstableinthe
closedloopunitygainmode.ThefrequencycharacteristicoftheoverallamplifierisdeterminedlargelybyQ5andQ6ratherthanthatofthecompositeoutputstages.
AnotherclassABbiasedpushpulloutputstageisshowninFig.4.70inblockdiagramform[14].Inthiscircuittheoutputstage,consistingofdevicesQ1andQ2is
precededbyafullydifferentialpreamplifiedstageA1.Theoutputstagehasseveralimportantproperties:Ithaslowstandbypowerdissipation,whichcanbecontrolled
byasupplyindependentcurrentsource,ithasagoodcurrentdrivingcapability,andithasasimpleconfiguration,soitavoidsadditionalparasiticpoles.Theoutput
stageconsistsofdevicesQ1toQ4,andthequiescentcurrentlevelattheoutputstageiscontrolledbythecommonmodevoltageofthepreamplifierstage.Heresince
theoutputstageisdrivenbyafullydifferentialoutputpreamplifierstage,anadditionalcommonmodefeedback(CMF)isnecessarytosetthedcvoltagevaluesofthe

Page160

Figure4.70
ClassABpushpulloutputstagewith
commonmodefeedback.

differentialoutput(i.e.,v o1=v o2=Vn=Vb).Therefore,assumingthat(W/L)1/(W/L)3=(W/L)2/(W/L)4,thecurrentIointheoutputdevicesisgivenby

whichcanbemadesupplyindependent.
Forthiscircuit,assumingthattheinputstagedoesnotimposealimitontheoutputstage,whenitneedstosinkthemaximumavailablecurrent,v o1=Vncanswingall
thewayuptoVDD,resultinginarailtorailgatetosourcevoltagedriveforQ2.Tosourcecurrent,v o2swingstoVDD,forcingQ4intothelinearregion.Thisinturn
causesVptomoveclosetoVSS,resultinginalargeVGSforQ1.Becauseofthecomplementarynatureofthedifferentialoutputsoftheinputstageswhenoneofthe
outputsisclosetoVDD,theotheroneisclosetoVSS.Asaresult,theoutputstagedeliversapushpulldrivetotheoutputtransistorsQ1andQ2insuchawaythatwhen
oneofthedevicesisheavilyconducting,theotheroneisturnedoff.Also,sincetheVGSdrivesoftheoutputtransistorscanbeashighasthefullsupplyvoltage,they
cansupplyalargeamountofoutputcurrentwithrelativelysmalldevicesizes.
ThecircuitdiagramofthecompleteopampisshowninFig.4.71.TransistorsQ40toQ47,alongwithresistorRB,constitutethebiasingsection.TransistorsQ14toQ25
realizethedifferentialoutputfoldedcascodepreamplifierstage.TransistorsQ43andQ46establishbiasvoltagesforthehighswingcascodecurrentsources.Transistors
Q5toQ13,whichestablishabiasvoltageequaltoVbattheoutputofthedifferentialstage,achievethecontinuoustimecommonmodefeedback.Intheconceptual
blockdiagramrepresentationofthepreamplifierstageshowninFig.4.70,thecommonmodefeedbacksetsthevoltagevaluesofthetwodifferentialoutputsas

InFig.4.71thecommonmodefeedbackisrealizedbydevicesQ8toQ13,whileQ5andthecurrentsourceQ6andQ7generatethebiasvoltageVb=VGS5.DevicesQ12

Page161

Figure4.71
Circuitschematicofopampwithpushpulloutputstage.

Page162

andQ13formacurrentsourcethatsuppliesafixedcurrenttothefoursourcecoupleddevicesQ8toQ11.TheW/LratioofQ8toQ11areequaltherefore,thetailcurrent
isdividedequallyamongthefourdevices,resultinginequalgatetosourcevoltages,so

Sincethegatepotentialsofallfourdevicesareequal,thedifferentialoutputofthepreamplifierstagewillbebiasedtoVb.Theoutputstage,consistingofdevicesQ1to
Q4,issimilartothecircuitshowninFig.4.70,wherethequiescentoutputcurrentisgivenbyEq.(4.121).
TheopenloopgainoftheopampiscalculatedasA=gm14rogm2RL,whereroistheoutputimpedanceofthepreamplifierstageandRListheloadoftheoutputstage.
TheopampcanbecompensatedusingtwoMillercapacitorsC1andC2alongwiththeirzeronullingMOSresistors,QC1andQC2.Assumingwidelyspacedpoles,the
dominantpoleiscalculatedas

whereCM1=(1+gm4/gm3)(C1/2)andCM2=gm2RLC2[14].TheloadcapacitanceCL,alongwiththeotherparasiticcapacitances,generatepolesandzerosthatare
abovetheunitygainfrequency.Thecommonmodefeedbackcircuitcreatesapolezerodoubletwhichisanorderofmagnitudebelowtheunitygainfrequency.
Thesearegivenby

whereCM3=(1+2gm10R2)C2andR2istheresistanceofthezeronullingMOSdeviceQC2.Sincesp1andsz1areclosetoeachother,thepolezerodoubletdoesnot
causeanyinstabilityinthefrequencyresponse.
TheclassABpushpulloutputstagespresentedthusfaruseelaboratetechniquestosolvethelevelshiftingproblembetweenthetwosignalsthatdrivetheoutput
devicesandsettheirquiescentbiascurrents.Asimple,yetverypowerfultechniquethatisbasedonthepushpullstageofFig.4.58isshowninFig.4.72[25].The
circuitconsistsofthepushpulloutputstagemadeofdevicesQ1andQ4.Inthiscircuit,transistorsQ5andQ6formatypicalgainstagewheretheinputsignalaltersthe
relativeconductionlevelsofthecommongatedevices.TheclassABbiascircuitsetsupthetwoloops,Q1,Q3andQ2,Q4,thatfixthevoltagedropbetweenthegatesof
theoutputdevices.
ReferringtoFig.4.72,thequiescentconditionsoftheoutputstageareestablished

Page163

Figure4.72
Railtorailoutputstagewithcommongate
levelshifters.

asfollows.ThecomplementarycurrentsIb1andIb2(Ib1=Ib2=Ib)fromthebiasgeneratorflowintocomplementarystacksofdiodeconnectedtransistorsQ7,Q8and
Q9,Q10whosedrainpotentialsareusedtobiasthegatesofthecommongatetransistorsQ3andQ4.InsteadystatethecurrentI=2IbthroughtransistorQ6isequally
dividedbetweendevicesQ3,andQ4sothateachonecarriesacurrentequaltoIb.Assumingthat

andsinceQ3,Q8andQ4,Q9carrythesamedraincurrentsIb,theywillhaveequalgatetosourcevoltagesandwehaveV2=V3andV1=V4.AsaresultQ2,Q10and
Q1,Q7willalsohaveequalgatetosourcevoltagesandthesteadystateoutputcurrentisgivenby

Whentheoutputstageisdriventosinkalargeloadcurrent,v ingoeslowandpullsv 1andv 2uptohighlevelclosetoVDD.UnderthisconditionQ4iscompletelyshutoff

andQ3carriesthefullcurrentofI=2IbfromQ5.ThesourceofQ3risestoitsmaximumpoint,thuscuttingbackontheconductionofQ1.Thedrainofthecommongate
deviceQ3alsogoeshigh,hencepullingthegateofQ2high,makingitheavilyconductive.Undertheconditionsofstrongsourcing,v ingoeshigh,causingv 1andv 2tobe
pulledlow.InthiscaseQ3iscompletelyshutoffandQ4carriesthefullcurrentofI=2Ib.ThesourceofQ4pullsthegateofQ1low,hencemakingithighlyconductive.

Page164

AcompletedifferentialopampemployingtheoutputstageofFig.4.72isshowninFig.4.73.Afoldedcascodeinputstageisused,providinghighopenloopgain.
ThebiasingcircuitconsistingofresistorRBandtransistorsQ13toQ21isdesignedsuchthatalldevicesarebiasedattheonsetoftheirsaturationregions,hence
maximizingtheoutputvoltageswingwhileprovidinghighgain.Thecommongatelevelshiftercircuitisinsertedintheoutputstageofthefoldedcascodedifferential
stage.TheopampofFig.4.73,withanoutputstagethatusescommongatelevelshiftertobiasthepushpulloutputdevices,isverycompactandpowerefficientand
isverysuitablefordrivingsmallresistiveloads.
4.10
OPAMPswithRailtoRailInputCommonModeRange
InthischaptertwogenerationsofCMOSopampswerepresented.Thefirstgenerationofopampswaslimitedtotransconductanceamplifiers.Theyhadmodest
performanceandwereabletodriveonlycapacitiveloads.Inadditiontohighperformancetransconductanceamplifiers,thesecondgenerationoftheseopampswere
abletodriveresistiveaswellascapacitiveloadswithalevelofperformancewhichiscompatibletothatoftheirbipolarcounterparts.Inadditiontohavingahigh
performanceoutputstage,thirdgenerationCMOSopampshaveawideinputcommonmoderange,whichincludesthepositiveandnegativepowersupplyrails.
Thewideinputcommonmoderangeisimportantforlowvoltageapplicationswheretheopampisconnectedinaunitygainbufferconfiguration.
InanearliersectionitwasshownthatopampswithpchanneldifferentialstageinputdevicessuchastheoneinFig.4.35haveaninputcommonmoderangethat
includesthenegativepowersupply.Thepositivecommonmoderangeis,however,limitedto1.4to1.6Vbelowthepositivesupply.Opampswithnchannelinput
deviceshavetheoppositeproperties.Theyhaveapositiveinputcommonmoderangethatincludesthepositivepowersupply,whereasthenegativerangeis1.4to
1.6Vabovethenegativesupply.Forapplicationswherethecommonmodeinputrangegoesbeyondoratleastincludesbothpowersupplyrails,suchastheunity
gainbuffershowninFig.4.36b,theopamprequiresaninputstagewithanNMOSandPMOSdifferentialpairconnectedinparallel.Severalopampstructureswith
railtorailcommonmodeinputstageareavailable[14,26].OneexampleofsuchaninputstageisshowninFig.4.74.Ithasafoldedcascodedifferentialoutput
structurewithcommonmodefeedback.
TheinputstageoftheopampinFig.4.74isconstructedfromtheparallelconnectionofpandnchanneldifferentialstagesmadeoftransistorsQ6toQ9andQ26to
Q29,respectively.ThedifferentialstagetailcurrentsourcesareformedfromdevicesQ6,Q7andQ28,Q29.Theyuseacascodestructuretoincreasetheoutputimpedance
andhencetheCMRR,assuggestedbyEq.(3.80).Highcommonmoderejectionisimportantwhentheopampisconnectedasaunitygainbuffer.TransistorsQ40to
Q47formasimplebiascircuit.Thetwopchanneltransistors,Q40andQ41,combinedwithresistorRB,generatethereferencecurrent.Thiscurrentismirroredinto
transistorsQ42toQ46,whichgeneratethebiasvoltagesforthehighswingcascodecurrent

Page165

Figure4.73
RailtorailopampusingtheoutputstageofFig.4.72.

Page166

Figure4.74
Railtoraildifferentialinput/differentialoutputstagewithcommonmodefeedback.

Page167

sources.TheinputstageusesafoldedcascodestructuremadeoftransistorsQ10toQ17.Anadditionalcommonmodefeedback(CMF)circuitsetsthedcvoltage
valuesofthetwodifferentialoutputs.TheconfigurationofthecommonmodefeedbackcircuitisbasedontheconceptualblockdiagramshowninFig.4.70.The
operationofthecommonmodefeedbackcircuitwasdescribedinSection4.9.
OnemajorshortcomingofthedifferentialstageofFig.4.74isthefactthatacurrentimbalanceoccursintheloaddevicewhenthecommonmodeinputvoltage
approachesVDDorVSS.ConsiderthecasewhenthecommonmodevoltageapproachesVDD.ThenastheinputdevicesQ8andQ9turnoffthecurrentcomponentsI
thatenterthedrainofthedevices,Q16andQ17becomezero.ThiscurrentimbalancecausesthedrainsofQ16andQ17tosnaptoVSSandtheopampceasesoperatingin
thelinearregion.Toremedythisproblem,thecircuitismodifiedbyaddingtransistorsQ30toQ37(Fig.4.75)totheinputstageanddividingthecurrentsinthedevices
Q10andQ11aswellasQ16andQ17intotwocomponents:onethatisconstantandtheotherthatisinputdependent.Theinputdependentcurrentcomponentbecomes
zerowhentheircorrespondinginputpairdevicesturnoff[14,27].ThecompleteopampisshowninFig.4.75.NowthesumofcurrentsthroughthepairsQ10AQ10B,
Q11AQ11B,Q16AQ16B,andQ17AQ17Barenormallyequalto2I,whilethecurrentsinQ12toQ15areequaltoI.WhentheinputcommonmodevoltageapproachesVDD(or
VSS),devicesQ8,Q9,andQ32(orQ26,Q27,andQ36)cutoffandcausethecurrentsthroughdevicesQ16AandQ17A(orQ10AandQ11A)todroptozero.Asaresult,output
voltagesv o1andv o2remainstableoverthecompletecommonmodeinputvoltagerange.
TheoutputstagefortheopampofFig.4.75isformedfromtransistorsQ1toQ4.ThecommonmodefeedbackcircuitsetsthequiescentcurrentIointheoutput
devicesto

TheclassABpushpulloutputstageisbasedontheconfigurationofFig.4.70itsoperationwasdescribedinSection4.9.
FrequencycompensationfortheopampisachievedusingtwoMillercapacitorsalongwiththeircorrespondingzeronullingMOSresistors.Theopenloopgainis
calculatedtobeA=(gm8+gm26)rogm2RL,whereroistheoutputimpedanceoftheinputstageandRListheloadresistor.
OnemajordrawbackoftherailtorailopampshowninFig.4.75isthatthetransconductance(gm)oftheinputdevicesvariesbyafactorof2overtheinput
commonmoderange.Thislargevariationingmpreventstheopampfromhavinganoptimumfrequencycompensationovertheentireoperatingrange.Tokeepthe
transconductanceconstant,thegmvalueofthelowerandupperpartsoftheinputrangeshouldbeincreasedbyafactorof2.Thisisbecauseinthemiddleofthe
commonmoderangethegmvalueoftheinputstageisthesumofthegmvaluesofthepandnchanneldevices.Inthelowercommonmoderangethenchannel
devicesturnoffandthegmvalueoftheinputstageisreducedtothegmvalueofthe

Page168

Figure4.75
Completerailtorailinputstageopamp.

Page169

pchanneldevices.Clearly,theoppositetakesplaceintheuppercommonmoderange.Thegmvaluesofthepandnchannelinputdevicesaregivenby

Fromtheequationsabove,itcanbeobservedthattomaintainaconstantgmvalue,thefollowingconditionshouldbesatisfiedbetweentheW/Lratiosofthepandn
channelinputdevices:

AssuggestedbyEq.(4.131),thegmvalueoftheMOSdeviceisproportionaltothesquarerootofitsdraincurrent.Therefore,whilethepandnchannelinput
devicesshouldsatisfytheconditionofEq.(4.132),tomaintainaconstantgmvalue,thetailcurrentsoftheinputstagesshouldalsovarybyafactorof4overtheinput
commonmoderange.Inotherwords,inthemiddleofthecommonmoderange,thepandnchannelinputstageswouldhavetailcurrentsthatareequaltoIo.Inthe
upperandlowerpartsoftheinputrange,thetailcurrentsofthepandnchanneldifferentialstagesshouldbeincreasedto4Io,respectively.Thiswillmaintainan
approximatelyconstantgmfortheinputstageovertheentireinputcommonmoderange.
ThisprincipleisappliedtothecircuitshowninFig.4.76[20].Arailtorailinputstageisshown,wherepandnchanneldifferentialpairsareplacedinparallel.

Figure4.76
Railtorailfoldedcascodeconstantg mdifferentialstage.

Page170

SimilartotheopampofFig.4.75,thestageisabletoreachthepositiveandnegativesupplyrailsthroughthenchannel(Q3Q4)andpchannel(Q1Q2)inputpairs.
TheconstantgmpropertyisachievedbytheadditionofthecurrentswitchesQ5andQ8andthetwocurrentmirrorsQ6Q7andQ9Q10,eachwithagainof3.Tobetter
understandtheconstantgmcontrolcircuit,theinputcommonmoderangewillbedividedintothreeregions.
WhentheinputcommonmodegoesbelowVb3=(VGS)Q3+(VDsat)Q20,thenchannelinputdeviceswillstartturningoffandthepchannelinputpairwillbeoperational.
InthiscasethenchannelcurrentswitchQ5willturnonwhilethepchannelcurrentswitchQ8isoff.ThecurrentoftransistorQ5ismultipliedbyafactorof3andis
addedtothetailcurrentofthepchanneldifferentialstage.Thetailcurrentisthereforeincreasedbyafactorof4,whichresultsindoublingtheinputgm.
Inthemiddleoftherange,theinputvoltageisgreaterthanVb3=(VGS)Q3+(VDsat)Q20butlessthanVb2=VDD+|(VGS)Q1|+|(VDsat)Q21|.Nowthepandnchannelcurrent
switches,Q5andQ8arebothoff,withbothinputpairsoperational.Theresultisthatthegmoftheinputstageisequaltothesumofthegmofthepandnchannel
differentialpairs.
Finally,whentheinputcommonmoderangeexceedsVb2=VDD+|(VGS)Q1|+|(VDsat)Q21|,thepchannelinputstagewillstartturningoff,whilethenchannelpairwillstill
beoperational.Thepchannelcurrentswitchwillturnon,andthecurrentoftransistorQ8,afterbeingmultipliedbyafactorof3,willbeaddedtothetailcurrentofthe
nchannelinputpair.Theresultisthatthetailcurrentofthenchannelpairismultipliedbyafactorof4,whichincreasestheeffectiveinputgmbyafactorof2.
ThecascodecurrentmirrorsQ11toQ14andthefoldedcascodedevicesQ15andQ16formthesingleendedoutputstage.ThebiasingschemesshowninFig.4.10can
beusedtomaximizetheoutputvoltagerange.TheopampofFig.4.76canbeusedasastandalonesinglestagetransconductanceamplifierwitharailtorailinput
rangethatcanbeusedtodrivecapacitiveloadsorwiththeadditionofoneofthehighperformanceoutputstagesdescribedinSection4.9,itcanbeusedasa
generalpurposeopampthatisabletodriveresistiveaswellascapacitiveloads.
Problems
4.1.ProveEqs.(4.3)to(4.7)forthecircuitofFig.4.3.Howmuchisthedynamicrangefor(a)theopampaloneand(b)thefeedbackamplifierifVCC=10V,A=
103,

andR2=10R1?

4.2.ShowthattheloadconductancerepresentedbyQ3inFig.4.6isgl=gm3+gd3.
4.3.ShowthatthesmallsignaloutputimpedanceofthedifferentialstageofFig.4.7isgivenbyEq.(4.10).

Page171

4.4.ShowthatthesmallsignaloutputimpedanceofthesinglestagefoldedcascodeopampofFig.4.9isgivenbyEq.(4.12).
4.5.ProveEq.(4.14)forthehighswingfoldedcascodeopampofFig.4.10.
4.6.ProveEq.(4.55)forthepolesofthecircuitofFig.4.23.[Hints:CalculateAv(S)fromEqs.(4.49)and(4.50).Writeitsdenominatoras

Findsp1andsp2use(gm8+gm9)/(gd2+gd4) 1.]
4.7.ProvethatthezerosofAv(s)forthecircuitofFig.4.25areats

,whileitspolesarethesameasforthecircuitofFig.4.23.

4.8.DeriveEqs.(4.57)to(4.59)forthecircuitofFig.4.27.WhyisAv(s)nowathirdorderfunction,whereasforthecircuitofFig.4.23itwasonlysecondorder?
4.9.ProveEq.(4.70)forthethreestageopampofFig.4.30.
4.10.ProveEqs.(4.71)and(4.72)forthesmallsignalequivalentcircuitofFig.4.31.
4.11.ShowthatEq.(4.93)givesthesmallsignaloutputvoltageofthecircuitofFig.4.40aifv in=V1u(t)andtheopamptransferfunctionisgivenbyEq.(4.92).
4.12.UsingthelowfrequencysmallsignalmodelsfordevicesQ1toQ4,showthatthevoltagegainrelationsofEqs.(4.101)and(4.102)holdforthenoisyinputstage
showninFig.4.45.
4.13.ThecircuitofFig.4.77canbeusedtomeasuretheunitygainbandwidth 0ofanopamp.Showthat 0isthefrequencyatwhichVout( )=Vin( )/
thevoltagegainis3dBbelowitsdcvalue.

thatis,

4.14.ForthecircuitofProblem4.13,lettheopenloopgainoftheopamphaveaphasemarginof60attheunitygainbandwidth 0.Howmuchisthephaseshift
betweenVoutandVinat 0?

Figure4.77
Opampinunitygain
configuration(Problem4.13).

Page172

Figure4.78
Opampwithnonzerooutputimpedance(Problem4.15).

4.15.ShowthatinthecircuitofFig.4.78,theeffectiveoutputimpedanceisRout(Ac+1)/A,whereAc |Z1|and|Z2|.
4.16.LettheoutputvoltagesofthedifferentialopampofFig.4.50changebyadifferentialamountsothat
Showthatthesumof
thedraincurrentsofQ3andQ4remainsunchanged.[Hint:AssumethatQ3andQ4areintheirlinearregions,andhenceyoucanuseEq.(2.7).]
4.17.Proverelations(4.107)and(4.108),givingthegainandoutputimpedances,respectively,ofthedifferentialopampofFig.4.50.
4.18.ShowthattheaspectratiosofthebiascircuitofFig.4.51aregivenbyEq.(4.109)ifwechooseI=Io/2inFig.4.50,Ibias=Ioasthebiaschaincurrent,andzero
dccommonmodeoutputvoltage.
4.19.Showthat(ifnecessary)adifferentialoutputopampcanbeconstructedfromtwosingleendedoutputopampsusingthecircuit[15]ofFig.4.79.
4.20.ShowthatfortheoutputstageofFig.4.65themaximumsourcingandsinkingcurrentsaregivenbyEqs.(4.119)and(4.120),respectively.
4.21.FindtheoutputimpedanceofthecircuitofFig.4.68(Hint:Setv in=0andconnecttheoutputterminaltoatestsource.Calculatethecurrentthroughthe
source.)

Figure4.79
Simplifiedequivalentcircuitofa
differentialoutputopamp(Problem4.19).

Page173

4.22.ProveEq.(4.121)fortheoutputstageofFig.4.70.
4.23.ShowthatthedominantpoleofthecompensatedopampofFig.4.71isgivenbyEq.(4.124).
4.24.ProvethatthecommonmodefeedbackcircuitofFig.4.71createsapolezerodoubletgivenbyEqs.(4.125)and(4.126).
4.25.ProveEq.(4.130)fortheopampofFig.4.75.
4.26.Provethatif(1)Av(s)isarationalfunctionwithitspoleshavingnegativerealpartsand(2)Re[kAv(j )]>1forall ,thesvaluessatisfyingkAv(s)=1all
havenegativerealparts.[Hint:Bythemaximummodulustheoremofcomplexfunctions,ifkAv(s)hasnopolesintherighthalfofthesplane,itsrealpartinthesame
regionhasitsminimumvalueonthej axis.]
4.27.ShowthattheinputcommonmodelimitforthedifferentialstageofFig.4.36isgivenbyEq.(4.80).
4.28.ShowthatthemaximumsourcingandsinkingcurrentsfortheFig.4.65aisgivenbyEqs.(4.119)and(4.120).
4.29.ShowthatthedominantpoleoftheopampofFig.4.71isgivenbyEq.(4.124).
4.30.ProvethatthecommonmodefeedbackcircuitintheopampofFig.4.71createsapolezerodoubletgivenbyEqs.(4.125)and(4.126).
References
1.D.J.HamiltonandW.G.Howard,BasicIntegratedCircuitEngineering,McGrawHill,NewYork,1975.
2.P.R.GrayandR.G.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,Wiley,NewYork,1977.
3.K.C.Hsieh,P.R.Gray,D.Senderowicz,andD.G.Messerschmitt,IEEEJ.SolidStateCircuits,SC16(6),708715(1981).
4.P.R.GrayandR.G.Meyer,MOSoperationalamplifierdesignatutorialoverview,IEEEJ.SolidStateCircuits,SC13(3),285294(1978).
5.R.J.Widler,IEEEJ.SolidStateCircuits,SC13(4),184191(1969).
6.R.GregorianandW.E.Nicholson,Jr.,IEEEJ.SolidStateCircuits,SC14(6),970980(1979).
7.P.R.Gray,BasicMOSoperationalamplifierdesignanoverview,inAnalogMOSIntegratedCircuits:PartII,IEEEPress,NewYork,1980.
8.J.H.HuijsingandD.Lineborger,IEEEJ.SolidStateCircuits,SC20(6),11441150(1985).
9.P.R.GrayandR.G.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,Wiley,NewYork,1993.

Page174

10.J.E.Solomon,IEEEJ.SolidStateCircuits,SC9(6),314332(1974).
11.J.C.Bertails,IEEEJ.SolidStateCircuits,SC13(6),791798(1978).
12.M.Banu,J.M.Khoury,andY.Tsividis,IEEEJ.SolidStateCircuits,SC23(6),14101414(1988).
13.D.Senderowicz,S.F.Dreyer,J.H.Huggins,C.F.Rehim,andC.A.Laber,IEEEJ.SolidStateCircuits,SC17(6),10141023(1982).
14.J.N.Babanezhad,IEEEJ.SolidStateCircuits,SC23(6),14141417(1988).
15.P.R.GrayandR.G.Meyer,IEEEJ.SolidStateCircuits,SC17(6),969982(1982).
16.K.C.Hsieh,Proc.Int.Symp.CircuitsSyst.,pp.419422,1982.
17.D.A.JohnsandK.Martin,AnalogIntegratedCircuitDesign,Wiley,NewYork,1997.
18.D.Senderowicz,NMOSoperationalamplifiers,inDesignofMOSVLSICircuitsforTelecommunications,Y.TsividisandP.Antognetti(Eds.),PrenticeHall,
UpperSaddleRiver,N.J.,1985.
19.R.Hogervorst,DesignoflowvoltagelowpowerCMOSoperationalamplifiercells,Ph.D.dissertation,DelftUniversity,1996.
20.R.Hogervorst,J.P.Tero,R.G.H.Eschauzier,andJ.H.Huijsing,IEEEJ.SolidStateCircuits,SC29(12),15051513(1994).
21.E.Seevinch,W.deJager,andP.Buitendijk,IEEEJ.SolidStateCircuits,SC23(3),794801(1988).
22.R.CastelloandP.R.Gray,IEEEJ.SolidStateCircuits,SC20(6),11221132(1985).
23.J.N.BabanezhadandR.Gregorian,IEEEJ.SolidStateCircuits,SC22(6),10801089(1987).
24.B.K.Ahuja,P.R.Gray,W.M.Baxter,andG.T.Uehara,IEEEJ.SolidStateCircuits,SC19(6),892899(1984).
25.D.M.Manticelli,IEEEJ.SolidStateCircuits,SC21(6),10261034(1986).
26.M.D.PardoenandM.G.Degrauwe,IEEEJ.SolidStateCircuits,SC25(2),501504(1990).
27.D.B.RibnerandM.A.Copeland,IEEEJ.SolidStateCircuits,SC19(6),919925(1984).

Page175

Chapter5
Comparators
Comparatorsarethesecondmostwidelyusedcomponentsinelectroniccircuits,afteroperationalamplifiers.Avoltagecomparatorisacircuitthatcomparesthe
instantaneousvalueofaninputsignalv in(t)withareferencevoltageVrefandproducesalogicoutputleveldependingonwhethertheinputislargerorsmallerthanthe
referencelevel.Themostimportantapplicationforahighspeedvoltagecomparatoroccursinananalogtodigitalconvertersystem.Infact,theconversionspeedis
limitedbythedecisionmakingresponsetimeofthecomparator.Othersystemsmayalsorequirevoltagecomparison,suchaszerocrossingdetectors,peakdetectors,
andfullwaverectifiers.Inthischapteranumberofapproachestocomparatordesignarepresented.First,thesingleendedautozeroingcomparatorisexamined,
followedbysimpleandmultistagedifferentialcomparators,regenerativecomparators,andfullydifferentialcomparators.Severaldesignprinciplesareintroducedthat
canbeusedtominimizeinputoffsetvoltageandclockfeedthrougheffects.
5.1
CircuitModelingofaComparator
Oneveryimportantandwidelyusedcomparatorconfigurationisahighgaindifferentialinput,singleendedoutputamplifier[1,2].Figure5.1ashowsthesymbolofa
differentialcomparatorwhichisverysimilartothatofanoperationalamplifier.Usually,thecomparatorstageisfollowedbyalatch,whichisessentiallyabistable
multivibrator.Thelatchprovidesalargeandfastoutputsignalwhoseamplitudeandwaveformareindependentofthoseoftheinputsignalandishencewellsuitedfor
thelogiccircuitsfollowingthelatch.Ifnolatchisused,theoutputv outshouldhavealargeswing,say,0to+5V,astheinputchangesfrom1mVto+1mV.Thus
therequiredgainisaround5V/2mV=2500,or68dB.Ifalatchisused,

Page176

Figure5.1
(a)Differentialinputcomparator
(b)transfercurveofideal
comparator.

v outonlyneedstobehigherthanthecombinedoffsetandthresholdvoltagesofthelatchthisvalueisaround0.2Vorless.Henceagainof200isnowadequate.A
comparatoristhereforeessentiallyahighgainopampdesignedforopenloopoperation.Butunlikeanopampitdoesnotrequirefrequencycompensation.
ThetransfercurveoftheidealdifferentialcomparatorisshowninFig.5.1b.InthisfigurethenegativeinputofthecomparatorinFig.5.1aistiedtoareferencevoltage
Vref.WhenthepositiveinputisgreaterthanVreftheoutputishigh(VOH),andwhenitislessthanVref,theoutputislow(VOL).TheidealtransfercurveofFig.5.1b
correspondstoadifferentialgainofinfinity.InactualitythedifferentialgainhasafinitevalueequaltoAv.ThedctransfercurveofsuchacomparatorisshowninFig.
5.2,whereViLandViHaretheinputexcessvoltagescalledtheoverdrive.Theoverdriveistheinputlevelthatdrivethecomparatorfromsomeinitialsaturatedinput
conditiontoaninputlevelbarelyinexcessofthatrequiredtocausetheoutputtoswitchstate.Anothernonidealeffectofthedifferentialcomparatoristheinput
referreddcoffsetvoltage,Voff.Intheabsenceoftheoffsetvoltage(Voff=0),thecomparatordctransfercurvewillbesymmetricalaroundVref.However,forafinite
valueofVoff,theoutputwillbeginchangingonlyaftertheinputdifferenceexceedsVoff.Thedctransfercurveofapracticaldifferentialcomparatorwithfinite

Figure5.2
Transfercurveofcomparator
withfinitegain.

Page177

Figure5.3
Transfercurveofcomparatorwith
finitegainanddcoffsetvoltage.

gainofAvandadcoffsetvoltageofVoffisshowninFig.5.3.Finally,thespeedorresponsetimeisanotherimportantparameterofacomparator.Inmostapplications
itisrequiredthatfollowinganappropriateinputlevelchange,thecomparatormustswitchbetweentwooutputlevelswithfastriseandfalltimesintheshortestamount
oftime.Theresponsetimeisafunctionoftheinputoverdrivevoltageanditspeedsupastheoverdriveisincreased.
Anotherclassofcomparators,whichcontainacascadeofinverterstages,isshowninFig.5.4.Thesecomparatorshaveasingleendedinput/singleendedoutput
configurationandoperateintwosteps:anautozeroingfunctionfollowedbyacomparisoncycle.Thesecomparators,whichareusedprimarilyinflashanalogto
digitalconverters,arediscussedinthenextsection.
5.2
SingleEndedAutoZeroingComparators[3]
SingleendedautozeroingcomparatorshavebeenusedextensivelyinhighspeedflashA/Dconverters.ConsideringthesystemofFig.5.4,lettheinvertersberealized
inCMOStechnologythenapossibleconfigurationfortheinputinvertersisshowninFig.5.5a,withtheclockwaveformsandnodevoltagev AillustratedinFig.5.5b.
Theoperationisasfollows:Att=0,switchesS2andS3areclosed.S2connectstheleftsideterminaloftheautozeroingcapacitorCtoground,whileS3shortsnodes
AandB.Asaresult,thenodesassumeavoltagethatcanbefoundfromtheintersectionoftheinputoutputdccharacteristicsoftheinverterandthe45line
representingthev A=v Bcondition.Figure5.6illustratesthesituation:Fig.5.6ashowstheinverter,andFig.5.6b(centercurve)illustratesanexampleofinputoutput
characteristics(withS3open)forVDD=VSS=5V,andforthethresholdvoltages,VTn=VTp=1V.Theintersectionofthiscurvewiththev A=v Blineoccursatthe
originthisisinthemiddleofthelinearrange,whereQ1andQ2arebothinsaturationandthegainoftheinverterisatmaximum.Thisfavorablebias

Figure5.4
Singleendedcascadeofinverter
stagecomparator.

Page178

Figure5.5
InputinverterforaCMOScascadecomparator:
(a)circuitdiagram(b)waveforms.

conditionisquiteinsensitivetovariationsofthethresholdvoltages,asillustratedbycurve1(drawnforVTn=0.7V,VTp=1.2V)andcurve2(forVTn=1.2V,VTP=
0.7V)theintersectionpointisinbothcasesnearthemiddleofthelinearrange.(SeeProblem5.1foragraphicalidentificationofthelinearrangeforallthree
curves.)
ReturningtothecircuitofFig.5.5a,clearlyduringthetimeintervalbetweent=0andt=t 1,thecapacitorCchargestovoltagev AB0=v AB,wherev ABisthe
intersection(selfbias)voltageillustratedinFig.5.6b.(There,fornominalthresholdvoltages,v AB 0.)Next,att 1, 3goeslow.ThisresultsinnodesAandBbeing

Page179

Figure5.6
Biasconditionsfortheinputinverter:(a)circuitdiagram(b)input
outputdccharacteristicsforvariousthresholdvoltages(seethetext).

Page180

disconnected.Also,partofthechargeinthechannelofS3entersCinaddition,throughthegatetosourceoverlapcapacitanceofS3,additionalclockfeedthrough
chargesenterC.ThedimensionsofCandS3mustbedeterminedsuchthatevenwiththechangeinv Aduetothesecharges,theQ1Q2invertershouldremainsafelyin
itslinearrange.LettheresultingnodevoltagesatAandBbedenotedby

respectively.

Next(att=t 2),S2opens.NowapartfromthesmallstraycapacitanceCA,nodeAisfloatingandhencev Aandv Bcandrifttoanyvalue.However,sinceCisnearly

opencircuitedatA,therewillbeonlyminimalclockfeedthroughintoCduetothecutoffofS2also,thisclockfeedthroughchargeisstoredinCAandwillbereturned
toCwhenS1closes.Hencethisclockfeedthroughhasnosignificanteffect.
Att=t 3, 1goeshighandC(chargedearlierto

),wecandecidewhetherv in>0orv in<0holds.

AmorecompletediagramofapossiblecircuitisshownschematicallyinFig.5.7a,withtheclocksignalsillustratedinFig.5.7b.Theoperationisasfollows.As
explainedabove,bytheendofthe 3pulse,C1ischargedtoavoltage whichissuitableforbiasingtheQ1Q2inverterinitslinearrange.IfQ3ismatchedtoQ1and
Q4ismatchedtoQ2,thesecondinverterhasthesamebiaspoint,andhenceisalsobiasedinitslinearrange.(Note,however,thattheclockfeedthroughvoltagedue
totheopeningofS3isamplifiedbyQ1andQ2andthenconnectedtothegatesofQ3andQ4hencethesecondstageismorevulnerabletothiseffect).Duringthistime,
theQ5Q6inverterisalsobiasedinitslinearrangebyS4,andC2isprechargedtothecorrespondingbiasvoltage.S4opensonlyafterS3does,sothattheoutput
voltagev CoftheQ5Q6inverterisnotaffectedbytheamplifiedclockfeedthroughtransientduetoS3.Itisaffected,however,bytheopeningofS4.Thistransientcan,
inturn,berenderedineffectivebyC3andS5.WhenS5isclosed,thelatchislockedinaselfbiasedbalancedstate.Thus,whenS3opens,thevoltageacquiredbyC3
wouldkeepaperfectlysymmetricallatchinanunstablebalancedposition.Forthelatchtofunction,however,theenabling(''strobe")signal 6mustalsogohigh.
Byt=t 4,allprechargingoperationsarecomplete.Atthispoint,S2isopenedandtheinputnodeAnowfloats.WhennextS1closes,v Dattheinputofthelatchwillrise
(ifv in<0)orfall(ifv in>0)fromitsearlierbalancedvalue.Hence,when 6rises,thelatchwillswitchtotheappropriateoneofitstwostablestates.
Obviously,thesystemshowninFig.5.7isonlyoneexampleofthemanydifferentpossibilities.(Itis,infact,aCMOSequivalentofthecircuitdescribedinRef.3.)
Othercircuitsmaycontainonlytwoinverterstages,usesourcefollowersasbuffersbetweenthevariousstages,usecapacitivecouplingalsobetweenthefirstand
secondstages,andsoon.Inmostcases,however,biasingandautozeroingisaccomplishedusingtheprechargingoperationsillustratedinFig.5.7.
ThespeedofthecascadedinverterstagesislimitedbytheRCtimeconstantsrepre

Page181

Figure5.7
CMOScascadecomparator:(a)circuitdiagram(b)clocksignals.

Page182

sentedbytheoutputresistanceR0oftheithinverterandtheinputcapacitanceCinofthenext[i.e.,(i+1)st]inverter.Theformeristheparallelcombinationofthedrain
resistanceofthePMOSandNMOSdevicesintheithstagethelattercanbeapproximatedbythesumoftheCgdvaluesinthenextstage,multipliedby(1+|Ai+1|)
duetotheMillereffect.ThedcgainAoftheinverteris,ofcourse,thesumofthetransconductancesdividedbythesumofthedrainconductancesofthetwodevices
inthestage.TypicalvaluesareR0~100k ,Cin~1.5pF,andA~10.
5.3
DifferentialComparators
ThesimplestformofadifferentialcomparatoristheuncompensatedtwostagetransconductanceopampshowninFig.5.8.Althoughremovingthecompensation
capacitorsomewhatspeedsupthecomparator,theresponsetimeisstillslowandnotadequateformanyhighspeedapplications.Asdefinedearlier,theresponse
time,orpropagationdelay,isthedelaybetweenthetimethedifferentialinputpassesthecomparatorthresholdvoltageandthetimetheoutputexceedstheinputlogic
levelofthesubsequentstage.Thepropagationdelayisworstwhentheinputsignalchangesfromalargeoverdriveleveltoanoppositelevelthatbarelyexceedsthe
thresholdvoltage.ThedelaytimeisdeterminedprimarilybythemaximumcurrentavailabletochangetheparasiticcapacitancesshowninFig.5.8.Thecapacitance
CLAconsistsofthejunctioncapacitorsandthegatetosourcecapacitanceCGSoftransistorQ5.ThecapacitorCLBisthecombinationofthejunctioncapacitorsandthe
gatetosourcecapacitancesoftransistorsQ3andQ4.TheresponsetimeisreducedbyminimizingtheparasiticcapacitancesCLAandCLBwhileincreasingthetail
currentofthedifferentialstagesuppliedbytransistorQ0.
OneofthemainapplicationsoftheCMOScomparatoristheswitchedcapacitorcomparator,whichisoneoftheessentialblocksofanA/Dconverter.Figure5.9a
showstheprincipleofoperationofthebasicswitchedcapacitorcomparator.During

Figure5.8
Opampcomparator.

Page183

Figure5.9
(a)Switchedcapacitorcomparator
(b)switchedcapacitorcomparatorwithparasitics.

thesamplemode,switchesS1andS2areclosedwhileS3isopen.Duringtheholdandcomparisonmode,S1andS2areopenandS3isclosed.Intheabsenceofany
nonidealeffects,thevoltagelevelsattheendoftheholdperiodare

whereAvistheopenloopvoltagegainofthecomparator.ThecircuitofFig.5.9ahasseveralnonidealeffects.Oneeffectisthedcoffsetofthecomparator,which
similartotheCMOSopamp,isduetothemismatchbetweentheinputandloaddevicesofthedifferentialstage.Anothersourceoferroristheclockfeedthrough
andchannelchargepumpingeffectoftheresetswitchS1,whichcontributearesidualoffsetchargetotheholdingcapacitor.InFig.5.9bthecomparatorinputoffset
voltageismodeledasthevoltagesourceVoffthatisplacedinseriestooneofitsinputs.Alsoshownisthetotalparasiticcapacitancefromtheinvertinginputtoground,
whichisrepresentedbycapacitorCp.ThusforFig.5.9bthedifferentialvoltageattheinputofthecomparatorattheendoftheholdperiodis

where Qrepresentsthetotalinjectedchargeontheholdingcapacitor.

Page184

Figure5.10
Offsetcanceledswitchedcapacitorcomparator.

AnalternativecircuitconfigurationthatcanprovideoffsetcancellationisshowninFig.5.10.InthisfiguretheresetswitchS1ismovedbetweenthecomparator
invertinginputandoutput.Then,duringthesamplingphasethecapacitorCischargedbetweentheinputvoltageandtheoffsetofthecomparator.Inthesubsequent
holdandcomparisonphase,asbefore,switchesS1andS2areopenandS3isclosed,connectingtheleftsideofcapacitorCtoground.Thevoltageattherightsideof
thecapacitorCbecomes

whichresultsinthedifferentialvoltageattheinputofthecomparatorgivenby

whichisindependentofthecomparatoroffsetvoltage.Althoughthistechniqueworkswellforremovingtheinputoffsetvoltage,theclockfeedthroughandchannel
chargepumpingeffectsoftheresetswitcharenoteliminated.AsEq.(5.4)shows,thesimplestwaytoreducetheerrorsduetothechargeinjectionistoincreasethe
sizeofthesamplingcapacitorandreduce QbyreducingthesizeoftheresetswitchandbyusingCMOStransmissiongateforfirstorderchargecancellation.
Makingthesizeoftheholdingcapacitorlargewhilereducingthesizeoftheresetswitchhastheadverseeffectofincreasingthesettlingtimeconstantofthecircuit.For
highspeedapplicationsacompromiseshouldbearrivedbetweenthesizesoftheholdingcapacitorandtheresetswitch.Analternativestrategytoreducetheclock
feedthrougheffectisdepictedinFig.5.11,wheretheresetswitchisreplacedwithQ1,alargedevice,inparalleltoQ2aminimumsizedevice.Attheendofthesample
phase,firstQ1turnsoffwhileQ2isstillon.ThechargeinjectedbyQ1isthereforeabsorbedbyQ2.Subsequently,Q2turnsoffandinjectssomechargetotheholding
capacitor.Theamountofthechargeisminimizedbecausetheswitchhasthesmallestpossibledimensions.

Page185

Figure5.11
Offsetcanceledswitchedcapacitorcomparator
withreducedclockfeedthrougheffects.

TheoffsetcancelingschemeofFig.5.10canbeusedtosensethedifferenceoftwovoltages.ThisisshowninFig.5.12,whereduringthesamplephaseswitchesS1
andS2areclosedandthecapacitorCischargedbetweentheoffsetofthecomparatorandtheinputvoltagev a.DuringthecomparisonphaseswitchesS1andS2are
openedandS3isclosed,connectingtheleftsideofthecapacitortothevoltagesourcev b.Thus,duringthecomparisonphasethevoltageattherightsideofcapacitor
Cisgivenby

andthedifferentialvoltageattheinputofthecomparatoris

whichis,likebefore,independentofthecomparatoroffsetvoltageandhasadcoffsetvoltage Q/(C+Cp)duetotheresidualfeedthroughcharge.
Inthismethod,sincethecomparatoractsasaunitygainamplifierduringthesamplephase,ithastoremainstable.AtypicalcircuitisshowninFig.5.13.The
comparatorillustratedissimplyatwostageamplifierwithanRCcompensatingbranchQcCc.Thisbranchiseffective,however,onlyduring 1=1halfperiod,
whenCischargingthroughS1andS2,andhencethecomparatorfunctionsasan

Page186

Figure5.12
Offsetcanceleddifferentialswitched
capacitorcomparator.

opampinaunityfeedbackconfiguration.During 2=1interval,theamplifierisinanopenloopconfiguration,andhencecompensation(whichslowsdownits
operation)isnotneeded.
Asmentionedbefore,theoffsetcancelingcomparatorstillsuffersfromthedcoffsetvoltageduetotheresidualfeedthroughcharge.Aneffectivewayforminimizingthe
errorsduetothechargeinjectioneffectsisthefullydifferentialdesignscheme,whichisdiscussedlater.
IntheoffsetcanceledswitchedcapacitorcomparatorofFig.5.10,when 1=1,capacitorCischargedbetweentheinputvoltageandtheoffsetofthecomparator.
Attheinstantthat 1goeslow,theinputsignalv inissampledandheldoncapacitorC.Inthesubsequentcomparisonphase, 2goeshighandtheleftsideofthe
capacitorisconnectedtoground,whiletherightside,intheabsenceofanyoffsetvoltageandclockfeedthrougheffect,becomesv in.Thiscircuithastheimportant
advan

Figure5.13
Opampoffsetcanceledswitchedcapacitorcomparatorwith
compensationcapacitordisconnectedduringthe
comparisonphase.

Page187

Figure5.14
Alternativeformofswitchedcapacitorcomparator.

tagethattheinputsignalissampledandheldduringthecomparisonphase,andthecomparatorhasthefullperiodtodeterminethepolarityoftheinputsignal.One
shortcomingofthiscircuitisthatduringeveryoffsetcancelingphase,whiletherightsideofthecapacitorisheldatvirtualground,theleftsideisfullychargedtothe
magnitudeoftheinputsignal.Asmentionedinanearlierdiscussion,alargesamplingcapacitorshouldbeusedtominimizetheresidualoffsetvoltageduetotheclock
feedthrougheffect.Alargesamplingcapacitoraffectsthesettlingtimeandimposesstringentrequirementsonthechargingcapabilitiesoftheinputsignalsourceandthe
comparatoroutputstage.Alternatively,asshowninFig.5.14,thephasingoftheswitchesconnectedtotheleftsideofcapacitorCcanbeinterchanged.Inthiscase,
duringthephasethat 1ishigh,thecapacitorischargedbetweentheoffsetofthecomparatorandground.Inthenextphase,when 2goeshigh,therightsideofthe
capacitorthatisconnectedtotheinvertinginputofthecomparatorisdisconnectedfromtheoutput,andtheleftsideofthecapacitorisconnectedtotheinputvoltage.
Atthistime,thevoltagev xattheinvertinginputofthecomparatoris

andthevoltageacrossthecapacitoris

If
andv c Voff,thevoltageacrossthecapacitorCduring 1and 2,remainsunchangedatVoff.Thisgreatlyrelaxesthechargingrequirements
fromtheinputvoltagesourceandisspeciallysuitableforhighspeedapplications.Ontheotherhand,thedisadvantageofthisapproachisthatthesampleandhold
situationnolongerexistsattheinputstageandthecomparatorinvertinginputtrackstheinputsignal.Forproperoperation,thecomparatorthereforehastomakea
decisionbasedontheinstantaneousvalueoftheinputsignal.

Page188

Figure5.15
(a)Gainblockbasedonsourcecoupled
differentialpairwithdiodeconnectedloaddevices
(b)gainenhancedsourcecoupleddifferentialpair.

ItwasmentionedearlierthattheresponsetimeoftheopampcomparatorshowninFig.5.8improvesgreatlyastheinputoverdrivevoltageisincreased.Ahigh
resolutionhighspeedcomparatorcanberealizedbyusingamultistageapproach,whereseveralhighspeedlowgaindifferentialamplifiersarecascadedfollowedbya
highgaindifferentialcomparatororlatch.Figure5.15ashowsadifferentialamplifierthatcanbeusedastheinputstageofacomparator.Thedifferentialgainofthe
sourcecoupledpairisgivenby

wherenandparethemobilityoftheNMOSandPMOSdevices.Equation(5.9)showsthedependenceofthedifferentialgainonthesquarerootofthedevice

Page189

Figure5.16
Sourcecoupleddifferentialpair
thatusespositivefeedbackto
provideincreasedgain.

dimensions.HighermobilityNMOStransistorsareusedasinputdevicestoachievehighergain.Toincreasethegainfurther,thecircuitofFig.5.15bcanbeused
wheretheinputtransistortransconductanceisincreasedbyinjectingcurrentsI1andI2(I1=I2)intothemfromthepchannelcurrentsourceQ5andQ6[4,5].Thegainof
themodifiedcircuitisnowgivenby

ApracticalchoiceisI=0.9I0/2,whichincreasesthegainbyafactorof
Anothermethodthatusesacontrolledamountofpositivefeedbacktoeffectivelyincreasethedriverdevicestransconductanceandhencetheoverallgainisshownin
Fig.5.16[1].Thegainofthepositivefeedbackgainstageisgivenby

where =(W/L)5/(W/L)3isthepositivefeedbackfactorthatisresponsibleforincreasingthegain.Areasonablevaluefor is0.75,whichincreasesthegainbya

factorof4.Thevalueof isdeterminedbytheratiooftheloaddevicedimensions,andalthoughitisareasonablywellcontrolledparameter,apracticalmaximum
valuefor is0.9,becausebeyondthatanymismatchesduetoprocessvariationsmaycausethevalueof toapproachunity,andperEq.(5.15),thegainwill
becomeinfinityandthestagewilloperateasacrosscoupledlatch.
TheresponsetimesofthegainstagesofFigs.5.15and5.16arelimitedbytheparasiticcapacitancesoftheloaddevices.Theresponsetimeofthesourcecoupled
differentialstagecanimprovesignificantlyifthediodeconnectedloadsarereplaced

Page190

Figure5.17
Resistiveloadsourcecoupled
differentialpair.

withsimpleresistors,asshowninFig.5.17.Thegainoftheresistiveloaddifferentialstageisgivenby

wheregmiisthetransconductanceoftheNMOSinputdevicesandRListheloadresistance.Onedrawbackofthiscircuitisthatthevoltagedropacrosstheload
resistorscanvarysignificantlyduetovariationsintheresistanceorthemagnitudeofthedifferentialstagetailcurrent.Thevariationsoftheoutputcommonmode
voltagemakesitdifficulttodesignmultistageamplifiersandbiasthecircuittooperateunderallprocessvariations.Onesolutiontothisproblemistouseareplica
biasingscheme.AschematicoftheresistiveloaddifferentialstagewithasimpleVBEbasedbiasgeneratorisshowninFig.5.18.Thebiascurrentisgivenby

Assumingthat(W/L)7=(W/L)6,thevoltagedropacrosstheloadresistorsisgivenby

ThisgeneratesaveryreproduciblefractionofVBEsinceitisdeterminedbyresistorandtransistorratios.Inadditiontoprovidingknownbiasvoltage,themaximum
positiveoutputswingofthedifferentialstageiswellcontrolledatavalueof

Page191

Figure5.18
Resistiveloadsourcecoupleddifferentialstage
withreplicabiasing.

NotethattofirstorderthestageoutputvoltageswingisindependentofVDD.Asanexample,ifweassumethatthebiasresistanceisRB=3500 ,thebiascurrentis
givenby

Usingavalueof =55A/V2fortheNMOStransconductancefactorandathresholdvoltageofVTn=0.8V,thenfor(W/L)10/(W/L)9=2and(W/L)11/(W/L)12=
100,thetransconductanceoftheinputdeviceswillbe

ForRL=5000 thedifferentialgainisgivenby
Ad=gmiRL=2.11035000=9.8
andthemaximumoutputvoltageswingis,fromEq.(5.15),

Athreestagedirectcoupledcomparatorcircuitcomprisedoftwocascadedresistiveloadandsourcecoupleddifferentialstagesfollowedbyanopampcomparator
is

Page192

Figure5.19
Directcoupledthreestagecomparatorcircuit.

showninFig.5.19.Theoverallgainofthefirsttwostagesforidenticalsectionsisgivenby

Soifeachstagehasagainof10,theoverallgainisAd=100,andadifferentialinputof100Vappearsasa10mVsignalattheinputofthefinalstage.Thisvoltage
islargeenoughtoresultinafastresponsetimeinthelaststageofthecomparator.Sincethestagesaredirectcoupled,theoffsetisnotcanceled.IfVoff1,Voff2,andVoff3
representtheoffsetvoltagesofthefirst,second,andthirdstages,theinputreferreddcoffsetvoltageisgivenby

Offsetcancellationtechniquesforthemultistagecomparatorswillbeintroducedlater.
5.4
RegenerativeComparators(SchmittTriggers)
Often,comparatorsareusedtoconvertaveryslowlyvaryinginputsignalintoanoutputwithabruptedges,ortheyareusedinanoisyenvironmenttodetectaninput
signalcrossingathresholdlevel.Iftheresponsetimeofthecomparatorismuchfasterthanthevariationoftheinputsignalaroundthethresholdlevel,theoutputwill
chatteraroundthetwostablelevelsastheinputcrossesthecomparisonvoltage.Figure5.20ashowstheinputsignalandtheresultingcomparatoroutput.Inthis
situation,byemployingpositive(regenerative)feedbackinthecircuit,itwillexhibitaphenomenoncalledhysteresis,whichwilleliminatethechatteringeffects.The

Page193

Figure5.20
Responseofafastcomparatortoaslowlyvarying
signalinanoisyenvironment:(a)withouthysteresis
(b)withhysteresis.

regenerativecomparatoriscommonlyreferredtoasaSchmitttrigger.TheresponseofthecomparatorwithhysteresistotheinputsignalisshowninFig.5.20b.
ASchmitttriggercanbeimplementedbyusingpositivefeedbackinadifferentialcomparator,asshowninFig.5.21a.Assumethatv i<v 1,sothatv o=Vothenv 1is
givenby

Ifv iisnowincreased,v oremainsconstantatVountilv i=v 1.Atthistriggeringvoltage,theoutputregenerativelyswitchestov o=Voandremainsatthisvalueaslong

asv i>v 1.Thevoltageatthenoninvertingterminalofthecomparatorforv i>v 1isnowgivenby

Ifwenowdecreasev i,theoutputremainsatv o=Vountilv i=v 1.AtthisvoltagearegenerativetransitiontakesplaceandtheoutputreturnstoVoalmost

instantaneously.ThecompletetransferfunctionisindicatedinFig.5.21b.Notethatbecauseofthehysteresis,thecircuittriggersatahighervoltageforincreasingthan
fordecreasingsignals.NotethatVn<Vp,andthedifferencebetweenthesetwovaluesisthehysteresisVHgivenby

AnothermethodtoeliminatethechatteringeffectaroundthezerocrossingoftheinputsignalistousethecomparatorwithdynamichysteresisshowninFig.5.22.

Page194

Figure5.21
(a)Schmitttrigger(b)composite
inputoutputcurve.

Assumethatv in<v 1,sothatv o=+Voandv 1=0.Ifv inisnowincreaseduntilv in>0,theoutputswitchestov o=Vo.Thenegativetransitionoftheoutputwill

capacitivelybecoupledtothepositiveinputofthecomparator,whichalsomakesanegativetransition.Thiswillcausethedifferentialinputvoltagebetweenthe
negativeandpositiveinputsofthecomparatortobecomelargerandspeeduptheoutputtransition.Sincethefirsttransitionattheoutputofthecomparator
regenerativelyincreasesthemagnitudeofthedifferentialinputsignal,thecomparatorrespondstothefirsttimetheinputcrosseszeroandignoresanysubsequentzero
crossingsduetonoise.TheRCtimeconstantdeterminesthelengthofthetimethattheinputsignalwillbeignoredafteritsfirstzerocrossing.Ifthetimeconstantis
madetoolarge,itwilllimitthemaximumfrequencythatthecircuitcanoperate.
Manyotherwaysareavailabletoaccomplishhysteresisinacomparator.Allofthemusesomeformofpositivefeedback.Earlierthesourcecoupleddifferentialpair
ofFig.5.16wasintroducedwherepositivefeedbackwasemployedtoincreasethegain[1].ThegainofthestageisgivenbyEq.(5.11),where =(W/L)5/(W/L)3is
thepositivefeedbackfactor.For <1[(W/L)5<(W/L)3],thecircuitbehavesasagainstage.For =1thestagebecomesapositivefeedbacklatch.For >1the
stagebecomesaSchmitttriggercircuitwiththeamountofhysteresisdeterminedbythevalueof .Next,thetriggerpointsandamountofhysteresiswillbecalculated
forthecasewhen >1.

Page195

Figure5.22
(a)Comparatorwithdynamichysteresis
(b)inputandoutputwaveforms.

ConsiderthecircuitofFig.5.23,where isgraduallyincreasedsothattransistorQ2beginsconductingandpartofthetailcurrentIostartsflowingthroughit.This
processcontinuesuntilthecurrentintransistorQ2equalsthecurrentinQ5.Anyincreaseoftheinputvoltagebeyondthispointwillcausethecomparatortoswitchstate
sothatQ1turnsoffandallthetailcurrentflowsthroughQ2.Attheswitching

Page196

Figure5.23
Sourcecoupleddifferentialpairwith
positivefeedbackfactor >1
forhysteresis.

pointassumethatthecurrentthroughtransistorsQ1andQ2arei1andi2,respectively.Thenwehave

or

Nowthegatetosource(v GS)voltagesofQ1andQ2canbecalculatedfromtheirrespectivedraincurrentsandaregivenby

Intheequationsabove,i2>i1,sov GS2>v GS1andsincethegateofQ1istiedtoground,thedifferencebetweenv GS2andv GS1isthepositivetriggerlevel,equalto

Page197

UsingEqs.(5.23)and(5.24)andsince(W/L)1=(W/L)2,Eq.(5.27)willbesimplifiedto

WhentheinputvoltageisincreasedbeyondVtrig+,thecomparatorswitchesandv o1turnslowandv o2goeshigh.NowtransistorQ2isonandQ1isoff,andallthetail

currentIoflowsthroughQ2andQ4.ThecurrentsintransistorsQ1,Q3,Q5,andQ6arezero.
Nextconsiderreducingtheinputvoltage

isgivenby

Thehysteresiscanbecalculatedas

where =[(W/L)5/(W/L)3]=[(W/L)6/(W/L)4].
Thecompleteschematicofacomparatorwithhysteresis,whichconsistsofasourcecoupleddifferentialpairwithpositivefeedback,andadifferentialtosingleended
converterisshowninFig.5.24.Forthiscircuitthevalueof =[(W/L)5/(W/L)3]=[(W/L)6/(W/L)4]isgreaterthan1andthehysteresisisgivenbyEq.5.30.

Figure5.24
Completeschematicofacomparatorwithhysteresis.

Page198

Figure5.25
Fullydifferentialinputoffsetstorage(IOS)comparator.

5.5
FullyDifferentialComparators
Forhighaccuracyapplicationsaneffectivewayforreducingthedcoffsetvoltageduetothefeedthroughchargeistouseafullydifferentialschemeforthe
comparators.Insuchcircuits,notonlyareclockfeedthrougheffectsreduced,butpowersupplynoiseand1/fnoisealsotendtocancel.Anoffsetcancelingfully
differentialcomparatorisshowninFig.5.25.Inthisscheme,duringtheoffsetcancellationmode,switchesS0toS3areonwhileswitchesS4andS5areoff.Thiswill
causeaunitygainfeedbacklooptobeestablishedaroundthecomparatorandthetwosamplingcapacitorstobechargedbetweengroundandtheoffsetvoltageof
thecomparator.Duringthetrackingmode,switchesS0toS3turnoff,breakingthefeedbackloopofthecomparatorS4andS5turnonandconnectthecapacitorsto
theinputsignal.Theinputdifferentialvoltageisamplifiedbythecomparatorandissensedbythelatch,whichprovidesalogiclevelatitsoutput,representingthe
polarityoftheinputdifferentialvoltage.IfVoffAandVoffLrepresenttheinputoffsetvoltagesofthecomparatorandthelatch,Q0andQ1,representthefeedthrough
chargesofswitchesS0andS1,theresidualinputreferredoffsetvoltageisgivenby

FromEq.(5.31),ifthechargesinjectedbyswitchesS0andS1matchwhilethecommonmodevoltagewillbeslightlyaffectedbyanamountequalto(Q0+Q1)/2C,the
differentialinputvoltage, Q/C=(Q0Q1)/Cwillbezero.Inpractice,thechargeinjectedbythetwoswitcheswillnevermatch,buttheresidualoffsetvoltagedueto
themismatchesintheclockfeedthroughwillbeanorderofmagnitudelessthaninthesingleendedcase.Forthisreasonmostadvancedintegratedcomparatorsuse
fullydifferentialdesigntechnique.
TheoffsetcompensationtechniqueshowninFig.5.25isknownastheinputoffsetstorage(IOS)topology[4,5].Itischaracterizedbyclosingaunitygainfeed

Page199

Figure5.26
Fullydifferentialoffsetcancelingcomparator.

backlooparoundthecomparatorandstoringtheresultingoffsetvoltageontheinputcapacitors.Inthisconfiguration,sincetheinputsignaliscapacitivelycoupled,it
hasawideinputdynamicrange.Also,sinceduringthecancellationphase,thecomparatorisconnectedasaunitygainamplifier,itrecoversfromtheinputoverdriveas
wellasstartingthetrackingphaseinitsactiveregion,therebyimprovingitsresponsetime.ThedisadvantageofthistopologyisevidentfromEq.(5.31),whereitcan
beseenthattoreducetheresidualinputoffsetvoltage,thecomparatorshouldhaveahighgainandalargevalueinputcapacitorshouldbeused.Acomparatorwith
highgainconsumesmorepowerandishardertocompensateforstableoperationduringtheoffsetcancellationphase.Alargesamplingcapacitorincreasesthesettling
timeandhencedegradestheresponsetimeofthecomparator.Italsoloadstheprecedingcircuitandcausesalargeamountoftransientnoise.
Figure5.26showsasimplefullydifferentialstageemployingtheinputoffsetstoragetopology[6,pp.99102].InthiscircuitthetwoautozeroingcapacitorsC1and
C2areprechargedduringthe 1intervalbetweengroundandv s,wherev sistheselfbiasedinputvoltageoftheamplifier.When 2goeshigh,theinputvoltagev inis
sensedbythecomparatorandanamplifieddifferentialvoltage
appearsattheoutput.Thereisalsoaclockfeedthroughsignalateachinputnode,which
appearsasacommonmodesignalandishencesuppressed.Ahighgain(>80dB)comparator,usingafoldedcascodefirststagefollowedbyacascodesecond
stagewithaswitchedcompensationcapacitorisdescribedinRef.7.
InhighresolutionapplicationsasinglestagehighgainoffsetcancelingcomparatorsuchastheoneshowninFig.5.26willhavealongresponsetime.Therefore,high
resolutioncomparatorsuseamultistagedesign.EachstageofthemultistagedesignusesoneofthelowgainamplifierstagesshowninFigs.5.15to5.17.Athree
stagefullydifferentialinputoffsetstorage(IOS)multistagecomparatorand

Page200

theindividualgainstageareshowninFig.5.27aandb,respectively[8].Thegainstageissimilartothegainenhancedamplifierstagedescribedearlierandshownin
Fig.5.15b.ThetwocascodetransistorsQ7andQ8havebeenaddedtoreducetheMillercapacitanceattheinput.Torecoverfromoverdrivevoltageandspeedup
thesettlingtime,theresetswitchQ9isusedtoequalizethedifferentialoutputofthegainstageforashortperiodduringtheoffsetstoragecycle.Eachstageis
capacitivelycoupledtothenextone,andbyclosingthefeedbacklooparoundeachstageindependently,thepossibleinstabilityproblemofathreestageamplifierwith
onefeedbacklooparoundallthreestagesiseliminated.Thecircuitoperatesasfollows.Duringtheoffsetstoragemode,thefeedbackswitchesareclosed,aunitygain
feedbackloopisestablishedaroundeachgainstage,andtheoffsetofthecomparatorsisstoredontheinputcapacitors.Inthetrackingmodethefeedbackaroundthe
comparatorsisopenedandtheinputdifferentialvoltageissensedandamplifiedbyA3,whereAisthevoltagegainofeachamplifierstage.Theoutputofthe
comparatorisstrobedbyalatchthatproducesalogiclevelatitsoutput.Themismatchbetweenthechannelchargeinjectedfromthefeedbackswitchesintroducesan
uncanceledoffsetattheinputofeachgainstage.Thetotalinputreferreddcoffsetvoltageisdominatedbytheoffsetofthefirststage.Itispossibletoreducethistype
oferrorbyimplementingthesequentialclockingschemeshowninFig.5.27c,wherethegainstagesarebroughtoutoftheoffsetcancellationmodesequentially,A0first
andA2last[1,8].WhenswitchesS1andS2areopened,A0leavestheoffsetcancellationmodewhileA1andA2remaininthatmode.Theoffsetvoltagesduetothe
chargeinjectionmismatchesofS1andS2oncapacitorsC1andC2areamplifiedbythefirststageandstoredoncapacitorsC3andC4beforetheotherfeedback
switchesareopened.ThiscanberepeatedwithswitchesS3andS4openingbeforeS5andS6switchestocancelitschargeinjectionerror.Toensureproperoperation,
thedelaybetweentheclockedgesshowninFig.5.27cshouldbelongenoughtoallowtheinputcapacitorsofthenextstagetofullyabsorbtheoffsetvoltageofthe
previousstage.
AnalternativeoffsetcancellationtechniqueisshowninFig.5.28[4].Inthismethodtheoffsetiscanceledbyshortingthepreamplifierinputsandstoringtheamplifier
offsetontheoutputcouplingcapacitors.Thistopology,knownasoutputoffsetstorage(OOS),operatesasfollows.Duringoffsetcancellation,switchesS0toS3are
on,switchesS4andS5areoff,andtheoutputofthegainstageisAVoffa,whereAisthegainoftheamplifier.Inthisphasetheamplifiedoffsetofthegainstageisstored
onC1andC2.Duringthetrackingmode,S1toS4areoff,S5andS6areon,andtheamplifiersensesandamplifiestheanalogdifferentialvoltage.Thisvoltageis
subsequentlysensedandamplifiedbyalatchwhichprovidesalogiclevelatitsoutput.InthiscomparatoremployingOOS,theresidualoffsetis

whereVOFFListhelatchoffsetand Q=Q0Q1ismismatchinchargeinjectionfromswitchesS0andS1ontocapacitorsC1andC2.AssuggestedbyEq.(5.32),the
offsetoftheamplifieriscanceledcompletely.ThisisevidentfromFig.5.28,where

Page201

Figure5.27
(a)ThreestageIOScomparator(b)gainenhancedamplifierstage
(c)sequentialclockingscheme.

Page202

Figure5.28
Fullydifferentialoutputstorage(OOS)comparator.

duringthecancellationmodetheinputsoftheamplifierandthelatcharebothzerohenceazerodifferenceofthecomparatorinputgivesazerodifferenceatthelatch
input.Also,asshowninEq.(5.32),theoffsetduetothechargeinjectionoftheswitchesisdividedbythegainoftheamplifier,resultinginasmalleroverallinput
referredoffsetvoltagecomparedtothatofIOS,asevidentfromEq.(5.31).
Inadditiontohavingalowerresidualdcoffsetvoltage,theOOStopologygenerallyhasasmallerinputcapacitance,whichislimitedtotheinputcapacitanceofthe
amplifier,whichcanbemaintainedwellbelow100fF.TheOOStopologyisthereforethepreferredchoiceinapplicationswherealowinputcapacitanceisrequired,
suchasaflashA/Dconverter,wheremanycomparatorsareconnectedinparallel.OnedrawbackoftheOOStopologyisitslimitedinputcommonmoderange,
whichisduetothedccouplingatitsinput.Anotherdrawbackisthatduringoffsetcancellationmode,theamplifierinanOOSoperatesinopenloopmodeandthe
inputoffsetisamplifiedbyitsgain.Therefore,alowgainamplifiershouldbeusedtoensureoperationsintheactiveregionundermaximuminputdcoffsetvoltage.
Typically,thecomparatorisfollowedbyastandardCMOSlatchwithapotentiallylargedcoffsetvoltage.Therefore,toachievealowinputreferredoffsetvoltage,as
suggestedbyEq.(5.32),ahighgainamplifiershouldbeused.Consequently,inhighresolutionapplications,theuseofasinglestagecomparatorisnotfeasible,and
similartotheIOStopology,amultistagecalibrationtechniquewillberequired.Figure5.29aillustratesathreestageOOScomparatorwhereeachstagecanbe
constructedfromoneofthelowgainamplifierstagesshowninFigs.5.15to5.17.AsequentialclockingschemesuchastheoneshowninFig.5.29bwillthenreduce
thedcoffsetduetotheclockfeedthrough.IfVOFFLrepresentstheoffsetofthelatch,thenumberofamplifierstagesn,andthecorrespondinggainA,shouldbeselected
suchthattheinputreferredoffsetvoltageislessthan0.5LSB,or

Afterthevalueoftherequiredgain(A)nisdetermined,thenumberofthestagesisselectedtoprovidethesmallestdelay[8].

Page203

Figure5.29
(a)ThreestageOOScomparator(b)sequentialclockingscheme.

Themultistagecalibrationtechniqueisaneffectivemethodtoreducethecontributionofthelatchoffsettotheoverallresidualinputreferreddcoffsetvoltage.An
alternativemethodtoimprovetheperformanceofafullydifferentialcomparatoristoapplytheoffsetcancellationtoboththegainstageandthelatch[4].Bycanceling
theoffsetofthelatch,itwillnotbenecessarytousemultistagelowgainamplifiers,andhighperformancecanbeachievedbyusingasinglelowgainamplifierthatis
optimizedforbothspeedandpowerdissipation.
ThesimplifiedblockdiagramofaCMOScomparatorthatappliesoffsetcancellationtoboththeamplifierandthelatchisshowninFig.5.30.Itconsistsoftwo
transconductanceamplifiers,Gm1andGm2,thatsharethesameoutputnodes,loadresistors,andoffsetstoragecapacitors.InthiscircuitB1andB2arebuffersthat
isolatethecommonoutputnodesfromthefeedbackcapacitors.Theoperationofthecircuitisasfollows.Duringtheoffsetcancellationmode,S1toS6areon,S7toS10
areoff,theinputsofGm1andGm2aregrounded,andtheiroffsetsareamplifiedandstoredoncapacitorsC1andC2.Duringthecomparisonmode,S1toS6turnoff,S7
toS10turnon,thecapacitorsareconnectedinthefeedbackloopofGm2,the

Page204

Figure5.30
CMOScomparatorblockdiagramandtiming.

inputsofGm1arereleasedfromground,andtheinputvoltageissensed.TheinputvoltageisamplifiedbyGm1toestablishanimbalanceinoutputnodesAandBwhich
iscoupledtotheinputsofGm2throughC1andC2,initiatingregenerationaroundGm2.Thiscalibrationmethodcanbeviewedasanoutputoffsetstorageappliedtoboth
theamplifierGm1andthelatchGm2,resultingincompletecancellationoftheiroffsets.
ACMOScomparatorbasedonthetopologyofFig.5.30isshowninFig.5.31.InthiscircuitthesourcecoupledpairsQ1Q2andQ3Q4constituteamplifiersGm1and
Gm2,respectively.TheloadsareformedfromthediodeconnectedtransistorsQ5andQ6andgainenhancementdevicesQ7andQ8.Theoutputcommonmodevoltage
issetbytransistorsQ5andQ6.ThesourcefollowersQ9andQ10serveasbuffersB1andB2inFig.5.30.AsdescribedearlierandshowninFig.5.15a,theadditional
currentsources,Q7andQ8,increasethegainanddecreasethevoltagedropacrossQ5andQ6.Normally,thegatesofQ7andQ8wouldbeconnectedtoafixedbias
voltage.However,byconnectingthegatestotheinputsofthedifferentialstage,thepushpulloperationofQ3withQ7andQ4withQ8improvesthechargeand
dischargeresponsetimesofnodesAandBinthefollowingway:When,forexample,nodeFgoeslowandnodeEgoeshigh,thecurrentinQ8isincreased,thereby
pullingnodeBmorequicklytoahighervoltage.ThecurrentinQ7isreduced,thusallowingQ3todischargenodeAtoalowervoltagemuchfaster.
Inthiscircuit,duringthecalibrationmode,S1toS6areon,S7toS10areoff,andthecombinedoffsetvoltagesofGm1andGm2arestoredoncapacitorsC1andC2.
DuringthecomparisonmodethecomparatorsareconnectedinthefeedbackloopsofGm2andtheinputvoltageissensedbyGm1.Anydifferentialinputvoltagewill

Page205

Figure5.31
CMOScomparatorcircuitdiagram.

offbalancethecurrentsofthedifferentialpairQ1Q2,whichreflectsintoadifferentialvoltageatnodesAandB.Thisvoltageisregenerativelycoupledtotheinputsof
Gm2throughcapacitorsC1andC2,causingtheoutputstoswitch.SincethecomparatorofFig.5.31includescalibrationofboththeamplifierandthelatch,itsresidual
offsetisdueprimarilytomismatchesinthechargeinjectionofswitchesS3toS6,S9,andS10.
Thedifferentialoutputvoltageswingofthecomparatorisnormallyontheorderof1to2V.Thecomparatorcanbefollowedbyalatchoranonregenerativeamplifier
suchastheoneshowninFig.5.32todevelopfullCMOSlevelsfromthedifferentialoutput.ThebiascircuitconsistingoftransistorQ15Q17andcurrentsourceI1
replicatestheXandYcommonmodevoltageatthesourceofQ17andgeneratepullupcurrentsinQ13andQ14that,duringreset,areequaltopulldowncurrentsin
Q11andQ12iftheirgatesaredrivenfromXandY.
5.6
Latches
Asmentionedearlier,toprovidethegainneededtogeneratelogiclevelsattheoutput,aswellassynchronizetheoperationofthecomparatorwithotherpartsofa
system,theamplifierofthecomparatorisusuallyfollowedbyalatch.Thelattercansimplybeacrosscoupledbistablemultivibrator.Somepossiblelatchcircuitsare
showninFigs.5.33to5.35.ThecircuitofFig.5.33isadynamicCMOSlatch[9]usedtoamplifysmalldifferencestoCMOSlevels.Inthiscircuit,when is

Page206

Figure5.32
CMOScomparatoroutputstage.

low,Q5isoff,S1andS2areon,andtheinputcapacitancesareprechargedtov in1andv in2.Subsequently,when goeshighitturnsoffS1andS2toisolatenodesXand

YfromtheinputterminalsandturnsonQ5toinitiateregeneration,andthelatchassumesoneofitsstablestates,dependingonthesignofv in1v in2.
ThelatchofFig.5.34alsoincludesselfbiasingandautozeroingcircuitry[6,pp.99102].Theoperationisasfollows.When 2goeshigh,S4andS5shortcircuitthe
gatesanddrainsofQ2andQ3,respectively.ThisactionbiasesthetwoinvertersQ2Q5andQ3Q6(whichformthemultivibrator)intheirlinearregions.Italso
prechargesthecapacitorsC3andC4suchthatanyasymmetrybetweenthetwoinvertersiscompensatedforbytheslightlydifferentbiasvoltagesprovidedbyC3

Figure5.33
DynamicCMOSlatch.

Page207

Figure5.34
Capacitivelycoupledlatchwithautozeroinginputcircuitry:(a)circuitdiagram(b)clocksignals.

Page208

andC4.Duringthistimethemultivibratorhasaloopgainlessthan1,andhenceitdoesnotswitchintoeitheroneofitsstablestates.Next,when 1and 3gohigh,S2

andS3prechargeC1to

isvalid.

Thesequenceinwhichthevariousclockphasesriseandfallisimportantforproperoperationofthislatchcircuit(asitisforalmostanyother).Thereaderisurgedto
analyzetheoperationif(say) 2goeslowbefore 3goeshigh,andsoon,toconvincehimselforherselfofthevalidityofthisstatement.
Yetanotherlatch[10]isshowninFig.5.35.Inthiscircuit,transistorsQ1,Q2,Q3,Q4,andQ7actasadifferentialpreamplifierwhenS5isclosed.Ontheotherhand,
whenS6isclosed,Q3,Q4,Q5,Q6,andQ7formabistablemultivibrator.When 1, 2,and 3arehigh,thepreamplifierisselfbiasedandC1andC2areprechargedto
,respectivelythiscausesan

Page209

Figure5.35
Preamplifierlatchcombination:(a)circuitdiagram(b)clocksignals.

Page210

Figure5.36
Directcoupledmultivibrator:(a)circuitdiagram(b)smallsignalequivalentcircuit.

amplifiedvoltagedifferencebetweennodesCandD.Atthispoint,S5slowlyopensandS6slowlycloses.Thiscausesthemultivibratortocometolifeandtoassume
oneofitsstablestates.Thestatechosenisdeterminedbythesignofv Cv D.
Eveniftheamplifierandthelatcharebuiltfromthesametypesofinverters,theriseandfalltimesoftheamplifierwillbemuchlongerthanthoseofthelatch.To
understandthisphenomenon,considerthesimplemultivibratorofFig.5.36a.ItssmallsignalequivalentcircuitwithalldevicesinthesaturationregionisshowninFig.
5.36b,wheregm=gm1+gm3=gm2+gm4andgd=gd1+gd3=gd2+gd4also,CisthecapacitanceloadingnodesAandB.Itcaneasilybeshown(Problem5.12)that
thenaturalmodes(poles)ofthecircuitofFig.5.36ares1.2=gm/C.Henceitstransientsareexponentialfunctionswithatimeconstant =C/gm.Intheabsenceof
positivefeedback,iftheinvertersQ1Q3andQ2Q4aresimplycascadedasinanamplifier,thetimeconstantis =C/gd.Theratioofthetimeconstantsis / =gd/gm
=1/A,whereAisthegainoftheinverter[11].Sincetypically,A=10,thelatchcanbeaboutanorderofmagnitudefasterthantheamplifierdrivingit.Itispossibleto
takeadvantageofthespeedofthelatchbyusingtwoamplifierstofeedasinglelatch(Fig.5.37a).Inthissystem[12],thetwoamplifiershavethesameconfiguration
asthetwoinputstagesinthecircuitofFig.5.7a.Theyalternateinautozeroingandamplifying,buttheamplifyingperiodshaveadutycyclelongerthan50%(Fig.
5.37b),sothattheinputofthelatchcanreceiveacontinuoustimeinputsignal.Toassurethis,theintervalsduringwhichtheswitchesSAandSBconnecttheamplifiers
tothelatchoverlap.Thusthelatchclockfrequency(whichistheeffectiveoverallclockfrequencyofthecomparator)canbedifferentfromtheamplifierclockrates.
Thissystemcanthusoperateabout10timesfasterthantheusualsingleamplifierversion,sincethelimitingfactorisnowthespeedofthelatch,notthatoftheamplifier.

Page211

Figure5.37
Fastcomparatorsystemwithtwoamplifiersandasinglelatch:
(a)circuitdiagram(b)clocksignals.

Page212

Figure5.38
Reductionofinputoffsetvoltagebycapacitivestorage
foramultistagecomparator(forProblem5.5).

Problems
5.1.FortheinverterofFig.5.6awiththeinputoutputcharacteristicsshowninFig.5.6b,provethatthelimitsofthelinearrange(whereQ1andQ2arebothin
saturation)aretheintersectionsofthecharacteristicswiththe45linesv B=v A+|VTp|andv B=v AVTn.DrawtheselinesforthecurvesofFig.5.6b,andidentifythe
linearranges.
5.2.ThecircuitofFig.5.7aistobefabricatedusingaCMOSprocesswiththefollowingparameters:VTn=VTp=1V,n=3p=670cm2/Vs,t ox=800, n=
0.012V1,and p=0.02V1.Designtheinputinvertersuchthatforv A=0V,v B=0VandiD1=iD2=50A.Howmuchisthegainofthestage?(Hint:Usethe
formulasofTables2.2and2.3.)
5.3.InthecircuitofFig.5.7a,theclockfeedthroughcapacitancebetweenthegateofS3andnodeAis15fF.Theclockvoltageis10Vpeaktopeak.Howlarge
mustC1beifthefirsttwoinverters(Q1Q2andQ3Q4)aretooperatewithalldevicesinsaturation,despitetheclockfeedthroughvoltageatnodeA?AssumetheW
andLvaluesobtainedinProblem5.2forthetwoinputinverters.
5.4.ShowthatthedifferentialvoltageattheinputofthecomparatorofFig.5.9battheendoftheholdperiodisgivenbyEq.(5.2).
5.5.CalculatetheeffectiveinputoffsetvoltageoftheautozeroedcomparatorofFig.5.38fromtheindividualgainsandoffsetvoltagesofitstwostagesA1andA2.
Assumethattheclockfeedthroughchargeis QandtheinputcapacitanceofthefirststageisCp.
5.6.ProveEq.(5.10)forthecomparatorofFig.5.15b.
5.7.ForthesourcecoupleddifferentialstageofFig.5.18,determinethevaluesofRBandRL,theaspectratiosofQ6Q7andQ9Q10andthedimensionsofQ11andQ12
suchthatthedifferentialgainbecomes16.(Assumethatk n=55mA/V2andVTn=0.8V.)
5.8.ProveEq.(5.17)forthethreestagecomparatorcircuitofFig.5.19.

Page213

5.9.SelectvaluesforR1andR2sothatthecomparatorofFig.5.21ahas30mVhysteresis.(AssumethatVDD=5VandVSS=5V.)
5.10.ForthecircuitofFig.5.24,ifW1=W2=50m,L1=L2=2m,andthetailcurrentI0=100A,calculate fromEqs.(5.28)and(5.29)suchthat
5.11.ProveEq.(5.31)forthecircuitofFig.5.25.
5.12.ForthemultivibratorofFig.5.36a:(a)derivethesmallsignalequivalentcircuitofFig.5.36b(b)usingLaplacetransformanalysis,findthenaturalmodesofthe
circuitand(c)findthenaturalmodesforthecasewhenthetwoinverters(Q1Q3andQ2Q4)arecascadedwithoutclosedloopfeedback.(d)Whatconclusionscan
bedrawnfromtherelativemagnitudesofthenaturalmodesofthetwocircuits?
References
1.D.J.Allstot,IEEEJ.SolidStateCircuits,SC17(6),10801087(1982).
2.R.GregorianandJ.G.Gord,IEEEJ.SolidStateCircuits,SC17(6),698700(1983).
3.Y.S.Lee,L.M.Terman,andL.G.Heller,IEEEJ.SolidStateCircuits,SC13(2),294297(1978).
4.B.RazaviandB.A.Wooley,IEEEJ.SolidStateCircuits,SC27(6),19161926(1992).
5.B.Razavi,PrinciplesofDataConversionSystemDesign,IEEEPress,NewYork,1995.
6.K.W.Martin,ProjectReports,MicroelectronicsInnovationandComputerResearchOpportunities(MICRO)Program,UniversityofCalifornia,Berkeley,Calif.,
1983.
7.H.S.Lee,D.A.Hodges,andP.R.Gray,IEEEInt.SolidStateCircuitsConf.,pp.6465,1984.
8.J.Doernberg,P.R.Gray,andD.A.Hodges,IEEEJ.SolidStateCircuits,SC24(2),241249(1989).
9.S.Chin,M.K.Mayes,andR.Filippi,ISSCCDig.Tech.Pap.,pp.1617,Feb.1989.
10.K.Martin,personalcommunication.
11.W.C.Black,Jr.,personalcommunication.
12.Y.Fujita,E.Masuda,S.Sakamoto,T.Sakane,andY.Sato,IEEEInt.SolidStateCircuitsConf.,pp.5657,Feb.1984.

Page214

Chapter6
DigitaltoAnalogConverters
Theanalogtodigital(A/D)anddigitaltoanalog(D/A)convertersarethemainlinkbetweentheanalogsignalsandthedigitalworldofsignalprocessing.Data
convertersaregenerallydividedintothetwobroadcategoriesofNyquistrateandoversamplingconverters.Nyquistrateconvertersareconvertersthatoperateat
1.5to5timestheNyquistrate(i.e.,asamplerateof3to10timesthesignal'sbandwidth),andeachinputsignalisuniquelyrepresentedbyanoutputsignal.
Conversely,oversamplingordeltasigmaconvertersoperateatsamplingratesthataremuchhigherthantheinputsignal'sNyquistrateandincreasetheoutput
signaltonoiseratiobysubsequentfilteringthatremovestheoutofbandquantizationnoise.TheratioofthesamplingratetotheNyquistrateiscalledthe
oversamplingratio.Formostpracticaldeltasigmaconverters,theoversamplingratioistypicallybetween16and256.
ANyquistratedigitaltoanalogconverter(DAC)isadevicethatconvertsadigitalinputsignal(orcode)toananalogoutputvoltage(orcurrent)thatisproportional
tothedigitalsignal.InthisandthefollowingchaptersavarietyofmethodsarepresentedforrealizingNyquistrateconverters.Oversamplingconvertersarenot
discussedinthisbooktheinterestedreaderisreferredtoRef.20foranindepthcoverageofthissubject.Thechapterbeginswithageneralintroductionand
characterizationoftheconverters,followedbyadiscussionofvoltage,charge,current,andhybridmodeD/Aconverters.
6.1
DigitaltoAnalogConversion:
BasicPrinciples
TheblockdiagramofaD/AconverterisshowninFig.6.1.TheinputsareareferencevoltageVrefandanNbitdigitalwordb1b2b3bN.Underidealconditions,in
the

Page215

Figure6.1
Blockdiagramofadigitaltoanalogconverter.

absenceofnoiseandanyimperfections,theD/Aconvertervoltageoutputcanbeexpressedas

whereNisthenumberofthebitsoftheinputdigitalword.ForanNbitD/Aconvertertheresolutionis2Nandisequaltothenumberofdiscreteanalogoutputlevels
correspondingtothevariousinputdigitalcodes.IfVrefrepresentstheinputreferencevoltage,thesmallestanalogoutputcorrespondingtooneleastsignificantbit
(LSB)is

Forbipolaranalogoutputs,thedigitalinputcoderetainsthesigninformationinoneextrabitthesignbitinthemostsignificantbit(MSB)position.Themost
commonlyusedbinarycodesinbipolarconversionaresignmagnitude,one'scomplement,offsetbinary,andtwo'scomplement.Table6.1showseachofthebipolar
codesfora4bit(3bitplussign)digitalword.ThewordlengthNdeterminestherangeofthenumbersassociatedwitheachofthefourbinaryrepresentationsystems.
Inallfournotations,thelargestpositivenumberisgivenby12(N1)indecimal.Forsignmagnitudeandone'scomplementnumbers,thelowerboundis[12(N
1)],whileintwo'scomplementandoffsetbinarythemostnegativenumberis1.Allfournumbersystemshaveuniquerepresentationsforallnumbersexceptforthe
zeroinsignmagnitudeorone'scomplementnotations.Positiveandnegativezeroshavedifferentrepresentationsinthesetwonumbersystems.Fortwo'scomplement
andoffsetbinarynotationsthereisauniquezerorepresentation.
Themostusefulwayofindicatingtherelationshipbetweenanaloganddigitalquantitiesinvolvedinaconversionistheinputoutputtransfercharacteristic.Figure6.2
showsthetransfercharacteristicforanideal3bitunipolarD/Aconverterthatismadeupof23distinctoutputlevels.InpracticalD/Aconverterstheidealtransfer
characteristicofFig.6.2cannotbeachieved.ThetypesoferrorsordeviationsfromthisidealconditionaregraphicallyillustratedinFig.6.3.Theoffseterroris
illustratedinFig.6.3aandisdefinedasthedeviationoftheactualoutputfromtheidealoutputwhenthe

Page216
TABLE6.1.CommonlyUsedBipolarCodes
Decimal
Fraction

Sign
Magnitude

One's
Complement

Offset
Binary

Two's
Complement

+7

7/8

0111

0111

1111

0111

+6

6/8

0110

0110

1110

0110

+5

5/8

0101

0101

1101

0101

+4

4/8

0100

0100

1100

0100

+3

3/8

0011

0011

1011

0011

+2

2/8

0010

0010

1010

0010

+1

1/8

0001

0001

1001

0001

0+

0000

0000

1000

0000

1000

1111

1000

0000

1/8

1001

1110

0111

1111

2/8

1010

1101

0110

1110

3/8

1011

1100

0101

1101

4/8

1100

1011

0100

1100

5/8

1101

1010

0011

1011

6/8

1110

1001

0010

1010

7/8

1111

1000

0001

1001

8/8

0000

1000

Number

Figure6.2
Idealconversionrelationshipina3bitD/Aconverter.

Page217

Figure6.3
GraphicillustrationofvariouserrorspresentinaD/A
converter:(a)offseterror(b)gainerror.
(c)differentialnonlinearity,integralnonlinearity,
andnonmonotonicresponse.

Page218

idealoutputshouldbezero.ThegainerroristhechangeintheslopeofthetransfercharacteristicandisshowninFig.6.3b.Thegainerrorisduetotheinaccuracyof
thescalefactororthereferencevoltage.Thelinearityisameasureofthenonlinearityerrorattheoutput,aftertheoffsetandgainerrorshavebeenremoved.There
aretwotypesofnonlinearityerrors.Integralnonlinearity(INL)isdefinedastheworstcasedeviationofthetransfercharacteristicfromanidealstraightlinebetween
zeroandfullscale(i.e.,theendpointsofthetransfercharacteristic).Thedifferentialnonlinearity(DNL)isthemaximumdeviationofeachoutputstepsizeof1LSB.
ItisameasureofthenonuniformstepsizesbetweenadjacenttransitionsandisnormallyspecifiedasafractionofLSB.Theintegralanddifferentialnonlinearitiesare
showninFig.6.3c.Unliketheoffsetandgainerrors,thenonlinearityerrorscannotbecorrectedbysimpletrimmingandtheycanonlybeminimizedbyimprovingthe
matchingoftheprecisioncomponentsoftheD/Aconverters(i.e.,resistorsorcapacitors).Finally,monotonicityinaD/Aconverterimpliesthattheanalogoutput
alwaysincreasesasthedigitalinputcodeincreases.Nonmonotonicityisduetoexcessivedifferentialnonlinearity.Guaranteedmonotonicityimpliesthatthemaximum
differentialnonlinearityislessthanoneLSB.NonmonotonicityisillustratedinFig.6.3c,wheretheanalogoutputdecreasesatsomepointsinitsdynamicrangewhile
theinputcodeisincreasing.
6.2
VoltageModeD/AConverterStages
Animportant,yetsimpleclassofD/AconvertersisbasedontheaccuratescalingofareferencevoltageVref.Voltagescalingcanbeachievedbyconnectingaseriesof
NequalsegmentsofresistorsbetweenVrefandground.ForanNbitconverter

Page219
N

theresistorstringconsistsof2 segments.ThestringofresistorsbehaveasavoltagedividerandthevoltageacrosseachsegmentisoneLSB,givenby

AnNbitD/Aconvertercanberealizedbyusingastringof2NresistorsandaswitchingmatriximplementwithMOSswitches[1].TheD/Aconversiontechniqueis
illustratedwithaconceptual3bitversionoftheunipolarconvertershowninFig.6.4.Heretheswitchmatrixisconnectedinatreelikemanner,whicheliminatesthe
needforadigitaldecoder.ForanNbitconverter,2N+12switchesareneeded.AsillustratedinFig.6.4,thevoltageselectedpropagatesthroughNlevelsof
switchesbeforegetting

Figure6.4
ThreebitunipolarresistiveDACwith23resistors
andtransmissiongatetreedecoder.

Page220

Figure6.5
ThreebitunipolarresistiveDACwith23resistors
anddigitaldecoder.

tothebufferamplifier.Thebufferisnecessarytoprovidealowimpedanceoutputtotheexternalload.Assumingthatthebuffer'sdcoffsetvoltagedoesnotvarywith
itsinputcommonmodevoltage,theD/Atechniquehasguaranteedmonotonicityandcanbeusedforconvertersupto10bitresolution.Asthenumberofthebits
increases,thedelaythroughtheswitchnetworkimposesamajorlimitationonthespeed.Theoutputimpedanceoftheresistorstringalsovaries,asafunctionofthe
closedswitchpositioninthenetwork.Also,thedelaythroughtheresistorstringmaybecomeamajorsourceofdelay.
Forhighspeedapplicationsthetreedecoderisreplacedwithadigitaldecoder.Onesuch3bitDACisshowninFig.6.5.ThelogiccircuitisanNto2Ndecoder

Page221
N

thatcantakealargearea.Thecommonnodeofallswitchesisdirectlyconnectedtothebufferamplifier.The2 junctionsofthetransistorshavealargeareaandresult
inalargecapacitiveload.Thevoltageselectedpropagatesthroughoneswitchhence,despitethelargercapacitiveload,theDACoutputcanachievehigherspeed
operation.
Amoreefficientimplementationofa5bitresistorDACisshowninFig.6.6.Thismethod,knownastheintermeshedladderarchitecture,usesatwolevelrow
columndecodingschemesimilartooneusedindigitalmemory[24].TheNto2NdecodingisachievedbysplittingNtoN1+N2=Nandrealizingitasthe
combinationof

Figure6.6
FivebitintermeshedladderarchitectureresistiveDAC.

Page222
N1

N2

N2

anN1to2 rowandN2to2 columndecoders.Foragivendigitalcode,oneofthe2 columnsisselected,alltransistorswitchesinthatcolumnareturnedon,and

the2N1resistornodesareconnectedto2N1rows.Therowdecoderselectsoneofthe2N1rowsandconnectsittotheinputofthebufferamplifier.
Thisapproachuses2N1subsegments,eachconsistingof2N2resistorsegments.ForlargeNthenumberoftheresistors,2N,growsexponentiallyandtheimpedanceof
theresistorarraybecomesverylarge.Theoutputimpedancealsovariesasafunctionofthepositionoftheclosedswitchinthenetwork.Toreducetheimpedanceof
thearrayandhenceitssettlingtime,acoarsearrayisplacedinparalleltothefineone.Thecoarsearrayconsistsof2N1(N1isthenumberoftherows)resistorsandis
denotedbyRcinFig.6.6.Thecoarsearrayinthiswaydetermines2N1accuratevoltagesanddeterminesthevaluecorrespondingtotheN1MSBs.Inthisarrangement
the2N1resistorsubsegmentseachconsistof2N2segments,andtheendpointsofthesubsegmentsareconnectedtothe2N1coarseresistors.Ifthecoarseresistorsare
representedbyRcandtheresistorsinthesubsegmentbyRf,thetotalresistanceofthearrayisgivenby

Asaresultofthismodification,theworstcaseoutputresistanceofthearrayseenbythebufferisreducedtoRarray/4.
ForhighresolutionapplicationstheresistorstringDACsuffersfromseveraldrawbacks:Thenumberoftheresistorsandswitchesgrowsexponentiallyanditexhibitsa
longdelayattheoutput.HencetheresistiveDACsofFigs.6.4to6.6arenotpracticalwhenthenumberofthebitsgrowsbeyond10.Totakeadvantageofthe
inherentmonotonicityofthevoltagedivisionDACwhilekeepingthenumberofresistorstoamanageablelevel,itispossibletouseatwostageDACsuchastheone
showninFig.6.7[5].Asthefigureshows,the6bitDACconsistsoftworesistorstringseachhavingeightsegments.Thecoarseresistorstringisconnectedbetween
Vrefandground.TwooperationalamplifiersconnectedasvoltagefollowersbufferconsecutivevoltagesofthecoarseDAC.Thefineresistorstringisconnected
betweenthetwooutputsofthefollowers.ThemonotonocityofthetwostageDACcannotbeguaranteed,duetotheoffsetvoltageoftheunitygainbuffers.Aspecial
sequencecanbeusedtooperatethecoarsearrayswitchestomaketheoperationoftheDACindependentofthebufferoffsetvoltages.Tounderstandthis,considera
portionofthecoarsearrayshowninFig.6.8.Thisfigurecorrespondstotheithcodeofthecoarsebits,wherebuffer1isconnectedtosegmentvoltageViandbuffer
2tosegmentvoltageVi1.Theoutputofthebufferswillbe(V1)i=ViVoff1,and(V2)i=Vi1Voff2,whereVoff1andVoff2arethecorrespondingoffsetvoltagesofthe
firstandsecondopamps.Forthenextsequentialcode,ifnodeAmovestoVi+1andnodeBtoVi,thebufferoutputswillbe(V1)i+1=Vi+1Voff1and(V2)i+1=ViVoff2.
Formonotonicoperationitisnecessaryfor(V2)i+1=(V1)iotherwise,theconsecutivecoarseoutputvoltageswillnotbecontinuous.ThisispossibleonlyifVoff1=Voff2
orVoff1=Voff2=0,whichcannotbeguaranteedinpractice.Alternatively,forthesequentialcode,nodeAcanbekeptatViandnodeBswitched

Page223

Figure6.7
Twostage6bitresistordividerDAC.

Page224

Figure6.8
Portionofthecoarseresistorsegment.

toVi+1.ThischoiceguaranteesacontinuousoutputfromthecoarsearrayandhencemonotonicoperationfortheDAC.However,sincethetopandbottomofthefine
resistorstringswitchesforconsecutivecodes,thedecodingandswitchingofthefineDACshouldbemodifiedaccordingly.Figure6.9showsthecompletecircuit
diagramofthe6bitDAC,whichincludestheswitchingdetailsofthecoarseandfineDACs.Asthefigureshows,foranNbitDAC,theconverterfunctionsby
applyingvoltageVreftothetopofthecoarseresistorarrayanddividingitto2N/2nominallyequalvoltagesegments.Foragivencode,bufferA1transfersthevoltageat
theithtaptothetopofthefinestring,whileA2appliesthevoltageattapi1tothebottomoffinestring.TheA3outputresultsfromlinearlyinterpolatingthevoltage
dropbetweentapsiandi1,weightedbytheN/2lowerbitsoftheNbitinputdigitalword.Forthenextcoarsedigitalcode,thepolarityofthevoltageacrossthe
fineresistorstringisreversed.Thisreversaloccursateveryotheradjacentresistorsegmentandiscorrectedinthesecondstagebyalternatingbetweentwoswitch
arrays.TheleastsignificantbitofthedigitalinputcodeofthecoarseDACmakesthisselection.Thisbitselectsbetweentheoddandevensegments,whichallowsthe
analogoutputofthecoarsedividertohaveacontinuousoutputvoltageindependentoftheoffsetofthetwovoltagefollowers.Byusingthismethoditispossibleto
obtaina16bitDACwhichhasaguaranteedmonotonicitywithouttheneedforastraight216segmentresistordivider.
ForanNbitDAC,thecircuitofFig.6.9usestwo2N/2segmentresistorstrings,twoN/2to2N/2decoders,andfoursetsofswitchingelements.Alternatively,thetwo
stageDACcanbeimplementedusingasingle2N/2segmentresistorstring,twosetsofswitchingelements,andtwoN/2to2N/2decoders.A6bitversionofsucha
DACisshowninFig.6.10.HerethetwoinputsoftheA1andA2buffersareindependentlyswitchedtothetapsoftheeightsegmentresistorstring.ThethreeMSBs
oftheinputdigitalwordaredecodedtoeightlinesthatcontroltheconnectionofA1tothetapsoftheresistorstring.ThenextthreeLSBscontroltheconnectionofA2
totheresistorstringinasimilarfashion.AninesegmentresistorstringisplacedbetweentheoutputsofA1andA2.Tap8,fromthebottomofthestring,isbufferedby
A3andbroughtoutastheoutputoftheDAC.FromFig.6.10,V1and

Page225

Figure6.9
Detailedcircuitdiagramoftwostagemonotonic
voltagedividerDAC.

Page226

Figure6.10
Alternativeformof6bitunipolartwostageresistivedividerDAC.

Page227

V2aretheoutputsoftwoindependentlycontrolled3bitDACs.OneconvertsthethreeMSBsandtheotherthethreeLSBsoftheinputdigitalwordtoanalog
voltages.Ignoringthedcoffsetvoltagesofthethreeopamps,v outcanbecalculatedas

sothat

Ignoringthefactor8/9,therelationshipinsidetheparenthesesrepresentstheoutputofa6bitsegmentedDAC.Iftheeffectoftheopampoffsetsisincludedinthe
calculations,Eq.(6.5)willbemodifiedinthefollowingway:

AsEq.(6.6)shows,thedcoffsetoftheopampsappearsasaconstantdcvoltageattheoutputwithoutinterferingwiththeDACoperation.Therefore,iftheopamp
offsetvoltagesdonotchangewiththecommonmodevoltage,thisstructureisinherentlymonotonicandthecomplexswitchingschemeoftheDACshowninFig.6.9
willnotbenecessary.Theonlydisadvantageofthisschemeisthe8/9attenuationfactorforthe6bitDAC.ForanNbitDAC,ifwesplittheinputcodeintotwoN/2
bits(Niseven)segments,theoutputrelationshipwillbegivenby

Asanexamplefora16bitDAC,N=16andwehave

Thefirststagewillbean8bitDACfollowedbytwobufferamplifierswitha257segmentresistorstringconnectedbetweentheiroutputs.Thefinal16bitDAC
outputwillbetakenfromtap256ofthesecondstageresistorstring.The256/257attenuationcanbeignoredorcompensatedbymodifyingthereferencevoltage,
Vref,whichisconnectedtothetopofthefirststageresistorstring.

Page228

Figure6.11
Offsetcompensatedswitchedcapacitor
sampleandholdcircuit.

TheDACsdescribedsofarinthissectionalluseunitygainbufferstoisolatetheresistorstringfromtheexternalload.Theunitygainbufferhasseveraldisadvantages.
ForhighresolutionDACs,theopampshouldhavealargecommonmoderejectionratio(CMRR)tomaintaintheaccuracyovertheentireinputcommonmode
range.Also,forlowvoltageoperation,complexopampswithrailtorailinputstageshouldbeusedtofacilitateoperationoverthewideinputrange.Forbipolar
outputs,thebottomoftheresistorstringwillbeconnectedtoanegativereference.Theabsolutevaluesofthepositiveandnegativereferencevoltagesshouldmatch
closely.Anymismatchwillintroduceanoffsetandlinearityerror.
AnalternativetotheunitygainbufferistheoffsetcompensatedswitchedcapacitorsampleandholdstageshowninFig.6.11,where 1and 2arenonoverlapping
twophaseclocks[6].When 1ishigh,capacitorCwillbechargedbetweentheoutputoftheDACandtheopampoffsetvoltageandacquiresthevoltagev inVoff,
wherev in=Vdac.When 2goeshigh,theoutputbecomesVDACVoff+Voff=VDAC,whichisindependentoftheopampoffsetvoltage.
ItisalsopossibletousetheswitchedcapacitorgainstageshowninFig.6.12aasabuffer[7,8].Inthiscircuit,when 1=''1,"theopamphasitsinvertinginput
terminalshortedtoitsoutputnodeandhenceperformsasaunitygainvoltagefollowerwithoutputvoltageVoff.Hencecapacitor CchargestoVoffv tnwhileC
changestoVoff.Whennext 2goeshigh, CrechargestoVoffandCtoVoffv out.Ifthetimewhenthishappensist=NT,bychargeconservationatnodeA,

Inthisequation,Vofftermscanceloutandv out(nT)= v in(nTT/2)results.Thusapositivegainof andadelayT/2areprovidedbythestage,andtheoutputoffset

voltageisVos=0.NotealsothatthecircuitsofFigs.6.11and6.12arefullystrayinsensitive.
Byinterchangingtheclockphasesattheinputterminals,aninvertingvoltageamplifiercanalsobeobtained(Fig.6.13).Byananalysissimilartothatperformed

Page229

Figure6.12
Offsetcompensatednoninvertingvoltage
amplifier:(a)circuit(b)outputwaveform.

Figure6.13
Offsetcompensatedinvertingvoltageamplifier.

Page230

forthecircuitofFig.6.12,itcanbeshown(Problem6.3)thatthiscircuitisadelayfreeinvertingamplifierwithgain .Asbefore,Voffiscanceledbytheswitching
arrangementanddoesnotenterv outiftheopampgainisinfinite.(SeeProblem6.3forthefinitegaincase.)
Asmentionedearlier,inthecircuitsofFigs.6.11,6.12,and6.13,theoutputvoltageisVoffwhenever 1ishigh,hencetheoutputisvalidonlywhen 2ishigh.Asan
example,forthecircuitofFig.6.12a,theoutputwaveformisasillustratedschematicallyinFig.6.12b.Clearly,theopampmusthaveahighslewrateandfastsettling
time,especiallyiftheclockrateishigh.Atthecostofafewadditionalcomponents[9],thisdisadvantageofoffsetcompensationcanbeeliminated(Problem6.4).
Lowfrequencynoisesignals,whichdonotchangesubstantiallyduringclockperiodT,aresimilarlycanceledbyoffsetcompensation.Thusthetroublesome1/fnoise
discussedinSection2.7isgreatlyreduced.Figure6.14aandbillustratetheoutputnoisespectrawithandwithoutoffsetcompensation,respectively.Notethat
cancellationalsooccursat2f c,4f c,...,whichareequivalenttodcforthesamplednoise.
Ifthedigitalinputsignalisbipolar,thatis,ifithaseitherapositiveoranegativesignasindicatedbyasignbitb0,thegainstagewithpolaritycontrolshowninFig.6.15
canbeused.Whenb0=0,indicatingthatthedigitalsignalispositive,thecircuitfunctionslikethenoninvertingunitygainsampleandholdstageofFig.6.12.Ifb0=1,
thedigitalsignalisnegativethentherolesof 1and 2interchangein

Figure6.14
Noisepowerforaswitchedcapacitorvoltageamplifier:
(a)withoutoffsetcompensation
(b)withoffsetcompensation.

Page231

Figure6.15
Offsetcompensatedswitchedcapacitorgain
stagewithpolaritycontrol.

theinputbranchandthecircuitfunctionsliketheinvertingunitygainstageofFig.6.13.TheadvantagesofusingtheswitchedcapacitorstagesofFigs.6.11to6.15
arethattheopamphasnocommonmodeinputsignal,andbipolaroutputscanbegeneratedfromaunipolarDACwithasinglepositive(ornegative)reference
voltage.
6.3
ChargeModeD/AConverterStages
Animportantadvantageofswitchedcapacitorcircuitsisthattheycanbemadedigitallyvariableandthusalsoprogrammable.Thisisaccomplishedbyreplacingsome
capacitorsinthecircuitbyprogrammablecapacitorarrays(PCAs).Suchabinaryprogrammedarray[10]isshowninFig.6.16.Inthefigurethetriangularsymbols
denoteinverters,andb0,b1,...,b7,arebinarycoded(highorlow,1or0)digitalsignals.Thusif(say)b7ishigh,theleftsideswitchingtransistorassociatedwith
capacitorCisonandtherightsidetransistorisoff.HenceCisconnectedbetweennodesXandX .Ifb7islow,therightsidetransistorison,anditconnectsthe
rightsideterminalofCtogroundratherthantoX .Therefore,Cneverfloats,andthetotalcapacitanceloadingatnodeXisconstant.Thevalueofthecapacitance
betweenXandX inthe8bitPCAofFig.6.16isthusclearly

whilethetotalcapacitanceloadingnodeXis2C(128)(Problem6.5).
CaremustbetakeninthedesignofthePCAtominimizenoiseinjectionfromthesubstrateintothecircuit.Thusthebottomplateofthecapacitor(whichisinthe
substrateorrightaboveit)shouldneverbeconnectedtotheinvertinginputterminalofanopampotherwise,thenoisefromthepowersupplywhichbiasesthe
substratewillbecoupledtotheopamp'sinputandamplifiedbytheopamp.
AnobviousapplicationofPCAsistherealizationofchargemodeD/Aconverters.

Page232

Itcanbeobtainedbyreplacingtheinputcapacitance CintheoffsetfreevoltageamplifierofFig.6.12abyaPCA.AnexampleofanNbitchargemodeDACis
showninFig.6.17,whereVrefisatemperaturestabilizedconstantreferencevoltage.Ifb1representsthemostsignificantbit(MSB)andbNtheleastsignificantbit
(LSB),theoutputvoltageattheendofclockperiod 2isgivenby

ThustheoutputistheproductofthereferencevoltageVrefandthebinarycodeddigitalsignal(b1,b2,b3,...,bN).
Notethattheorientationofallcapacitorsissuchthattheirtopplates(indicatedbylightlines)areconnectedtotheopampinputterminal.Thisreducessubstratenoise
voltageinjection.Also,duetothepresenceoftheswitchingdevicesdrivenby
andsoon,thetotalcapacitanceconnectedtotheopampinputisconstant,
whichmakesitscompensationaneasiertask.

Figure6.16
Binaryprogrammablecapacitor
array(PCA).

Page233

Figure6.17
Annbitchargemodedigitaltoanalogconverter.

Ifthedigitalinputsignalisbipolar,thatis,ifithaseitherapositiveoranegativesignasindicatedbyasignbitb0,theDACshowninFig.6.18canbeused.Ifb0=0,
indicatingthatthedigitalsignalispositive,thecircuitfunctionsinexactlythesamewayastheDACofFig.6.17.If,however,b0=1,sothatthedigitalsignalisnegative
(ascaneasilybededuced),intheinputbranch 1and 2exchangeroles.NowthecircuitfunctionsastheinvertingvoltageamplifierofFig.6.13.Thustheinputoutput
relationis

asrequiredbythenegativedigitalsignal.
ForanNbitDAC,thecapacitorratiois2NandthetotalcapacitanceCtotal=(2N+11)C.ForN=8,28=256andCtotal=511C.Theratioandthetotalcapacitance
increaserapidlywithincreasingNandthematchingaccuracydeteriorates.TheoffsetfreeschemeofFig.6.18canbeusedinacascadedesigntoreducethe
capacitorratio[11].Thecircuitdiagramforabipolar8bitD/AconverterisshowninFig.6.19.Theoutputofthefirststageisfedtothesecondstagewiththesame
weightingastheleastsignificantbit.Theoutputvoltageattheendofclockperiod 2isgivenby

Page234

Figure6.18
DACwithbipolaroutput.

whichreducesto

wherekisdeterminedbythesignofb1.Thecapacitorratioisreducedto24=16andthetotalcapacitanceisCtotal=63C.AsFig.6.19shows,thecapacitorratiois
reducedwithoutincreasingtheconversioncycles.ForanNbit(Neven)bipolarD/Aconverter,thecapacitorratiois2N/2andthetotalcapacitanceCtotal=[2(N/2+2)
1]C,whichcorrespondstoanimprovementof2N/21overthedirectmethod.Thecircuitiscompatiblewithmostprocesstechnologiesandusesasinglereference
voltageforbipolaroutputs.
6.4
HybridD/AConverterStages
InthecascadedD/AconvertershowninFig.6.19,thevoltagecorrespondingtotheLSBspropagatesthroughtwoopampsbeforereachingtheoutput.Thesettling
timeofthetwocascadedopampstagessetsanupperlimitonthemaximumconversionspeed.Amoreeffectivewaytoreducecomponentspreadandachievehigh
precisionistocombinethechargemodeandresistordividermodeDACsdescribedearlierinthechapter.Themoststraightforwardcombinationistoreplacethe
LSBstage(firststage)ofthecascadedD/AconverterofFig.6.19withoneoftheresistor

Page235

Figure6.19
Circuitdiagramofabipolaroutput8bitcascadedD/Aconverter.

Page236

Figure6.20
SevenbithybridDACstagewithchargeMSBandvoltagedividerLSBDACs.

dividerDACsofFig.6.5or6.6.OneexampleofthisapproachisshowninFig.6.20,wherea7bitbipolaroutputDACisrealizedasthecascadeofa3bit
chargemodeDACanda3bitresistordividermodeDAC.TheMSBinthiscaseisthesignbitandcontrolsthepolarityoftheoutput.Fora16bitunipolarDACan
8bitchargemodeDACandan8bitresistordividermodeDACcanbeused.InthisapproachtheLSBsareusedtoprogramtheoutputoftheresistorDACwhile
theMSBscontrolthecapacitorarray.Theoverallaccuracyisdeterminedlargelybythe

Page237

Figure6.21
SixbithybridunipolarDACstagewithresistordivider
MSBandchargeLSBDACs.

MSBDAC.MonotonicitycannotbeguaranteedbecausethechargemodeDACisnotaccuratewithinoneLSBoftheoverallDAC.
Forinherentlymonotonicdesign,atwostageapproachcanbeusedwheretheMSBsareusedtoprogramaresistordividerDACandtheLSBscontrolabinary
weightedprogrammablecapacitorarray(PCA)[12].ThisapproachissimilartotheoneusedinaninherentlymonotonicsuccessiveapproximationA/Dconverter
[13].A6bittwostageunipolarD/AconverterisshowninFig.6.21.Fora7bitbipolarDAC,asignbitcanbeaddedtocontroltheclockphasesoftheswitched
capacitorgainstage.TheoverallDACconsistsofa3bitresistordividerDACanda3bitchargemodeDAC.ThethreeMSBconnectadjacentnodesofthe
resistorstringtothetwohigh(busH)andlow(busL)buses.ThethreeLSBsconnectthebinaryweightedcapacitorarraytothehighandlowbusesthroughthetwo
switchescontrolledby 1and 2.IfanLSBisa"1,"thecorrespondingcapacitorisconnected

Page238

tothehighbus(busH)ifthebitis''0"itisconnectedtothelowbus(busL).Forapositiveoutput,when 1ishigh,thebottomplatesofthebinaryweighted
capacitorareconnectedtobusHorbusL.When 1goeslowand 2goeshigh,thebottomplatesofthecapacitorsswitchtogroundandavoltagecorrespondingto
thedigitalcodeappearsattheoutputofthegainstage.Ifasignbitisusedtocontrolthesequenceoftheclockphases,apositiveornegativeoutputwillbegenerated
attheoutputoftheDAC.TheabsoluteaccuracyandlinearityoftheentireDACarelimitedbytheaccuracyofthevoltagedivisionoftheresistorstring.The
monotonicityoftheentireDACisguaranteedaslongasthecapacitorarrayismonotonic.Fora16bitbipolaroutputDAC,an8bitresistorDACanda7bit
capacitorDACcanbeused.Thesignbitwillcontrolthepolarityoftheoutput.
6.5
CurrentModeD/AConverterStages
AllcurrentmodeDACsaremadeofthreebasicblocks:acurrentreferencegenerator,acontrolledcurrentswitchingmatrix,andacurrenttovoltageconverter.The
currentreferencegeneratorissimplyavoltagetocurrentconverter.OnesuchcircuitisshowninFig.6.22,whereareferencevoltageandresistorisusedtogenerate
thereferencecurrent.ForthecircuitofFig.6.22,theopampforcesthevoltageacrossthereferenceresistortoVref.Sothereferencecurrentisgivenby

ThediodeconnectedpchanneldeviceQ1generatesagatetosourcevoltagethatcanbeusedasbiasvoltagetomirrorthereferencecurrentintothecurrent
switching

Figure6.22
Currentreferencegeneratorfor
thecurrentDAC.

Page239

Figure6.23
SimplifiedblockdiagramofacurrentmodeDAC.

matrix.ThecurrentswitchingmatrixunderthecontroloftheNbitdigitalinputcodeproducesanoutputgivenby

whereb1istheMSBandbNtheLSB.
Theoutputcurrent,Iout,flowsintothecurrenttovoltageconverter,whichinitssimplestformisaresistor.Toprovidealowimpedanceoutput,anopampshouldbe
used.Inthiscasethecurrenttovoltageconverterisanopampwithafeedbackresistor.ThesimplifiedblockdiagramofacurrentmodeDACisshowninFig.6.23,
wheretheoutputv outisgivenby

OneofthemainapplicationsofhighspeedcurrentmodeD/Aconvertersisinrasterscangraphicsmonitors,whichareusedinmostcomputersystems.Highspeed
DACsarealsousedindigitalandhighdefinitiontelevision.Thesesystemsnormallyincludethree8bithighspeedDACsforred,green,andbluecolors.Intoday's
highresolutioncolormonitors,eachDACoperatesatspeedsinexcessof200MHzandisdesignedtohaveacurrentoutputthatdrivesa75 doublyterminated
line[14,15].
Thebasicarchitectureofa3bitcurrentDACisshowninFig.6.24.TheDACconsistsof231=7identicalcurrentsources,whereeachcurrentsource,underthe
controloftheinputcode,canswitchbetweentheoutputloadandground.ForaninherentlymonotonicDACwithgooddifferentialnonlinearity(DNL),a
thermometertypedecodermustbeused.A3bitthermometerdecoderconvertstheinput3

Page240

Figure6.24
ThreebitcurrentDACusinga
thermometerdecoder.

bitsto231=7outputbits,wherethenumberof1'sintheoutputcodeisequaltothedecimalvalueofthebinarycode.Table6.2presentsthetruthtableofa3bit
thermometercodedecoder.Ifd0tod6areusedtocontrolthecurrentsourcesofFig.6.24,thenmovingfromonecodetothenext,oneadditionalcurrentsourceis
turnedon,whichincreasesthetotaloutputcurrent,henceguaranteeingmonotonicity.
TABLE6.2.TruthTablefor3BitThermometerDecoder

b1

b2

b3

d6

d5

d4

d3

d2

d1

d0

Page241

Thethermometerdecodingschemealsoimprovestheglitchperformance.Aglitchoccurswhen,say,goingfrom3I0to4I0,fortheoutputcurrent,onesetofthree
currentsourcesturnoffandanothersetoffourcurrentsourcesturnon.Anydelaybetweenturningthetwogroupsonandoffwillresultinapositiveornegativeglitch.
ThisphenomenoniscommoninabinaryweightedcurrentsourceDAC.InathermometerdecoderDAC,goingfrom3I0to4I0,thethreecurrentsourcesthatsupply
3I0remainonandafourthturnsontosupply4I0,eliminatinganyglitches.
Asthenumberofbitsincrease,straightthermometerdecodingbecomesimpractical.Formoreefficientimplementation,atwodimensionalrowcolumndecoding
schemecanbeused.Forexample,fora6bitDAC,a3bitrowand3bitcolumndecodercanbeused.TheDACwillconsistof261=63identicalcurrent
sourcesarrangedasamatrix.Figure6.25showsthebasicarchitectureofthe6bitDAC.Forexample,ifthedigitalvalueforthe6bitinputcodecorrespondstoa
decimalnumberof30,thirtycurrentsourcesinthematrixareturnedonandtheseoutputsaresummedtoformtheoutputcurrent.InFig.6.25thematrixconsistsof
threetypesofrows:(1)rowsinwhichallcurrentcellsareturnedon,(2)rowsinwhichallthecurrentcellsareturnedoff,and(3)arowinwhichthecellsarepartially
turnedon.Basedonthethreetypesofrowsandtheoutputsoftherowandcolumndecoders,alogicisdesignedtocontroltheindividualcurrentcells[14].
ThearchitectureofFig.6.25issuchthatintheactualphysicallayoutofthe

Figure6.25
SixbitcurrentDACarchitecture.

Page242

Figure6.26
Simplified6bitcurrentDACarchitecture.

DAC,thecontrollogicforeachcellshouldbeplacednexttothecurrentsource.Thisrequirementputsalimitationonthematchingaccuracyofthecurrentcellsand
hencethelinearityoftheDAC.ThearchitectureoftheDACcanbegreatlysimplifiedifaslightlydifferentdecodingschemeisused.Theblockdiagramofthe
simplified6bitDACisshowninFig.6.26.Itconsistsofonerowofsevencurrentcellsandsevenrowsofeightcurrentcells.Theoutputofthecolumndecoder
controlstheindividualcellsinthefirstrow,andthesevenoutputsoftherowdecodereachcontrolanentirerow.Inthisarrangement,foradigitalcodecorresponding
toadecimalvalueof30,threeentirerowsandsixcellsinthefirstrowwillturnon.Asweincrementtheinputdigitalcode,thecurrentcellsofthefirstrowturnon
sequentially.Whenallsevencurrentcellsareturnedon,onemoreincrementwillturnoffallsevencellsinthefirstrowandturnononeentirerowofeightcurrentcells.
Turningoffonesetofsevendevicesandturningonanothersetofeightdevicesmaycauseaslightglitch.Also,thearchitectureinnotinherentlymonotonic.However,
fora6bitDAC,monotonicitycanbeguaranteedaslongastheDACis3bitaccurate.ThephysicallayoutoftheDACisverystraightforward,however.Sincethe
outputsofthethermometerdecoderscontrolthecurrentcellsdirectly,noadditionallogicisnecessaryandallcurrentcellscanbeplacednexttoeachother,improving
thematchingandhencetheaccuracyoftheDAC.

Page243

Figure6.27
Configurationofcurrentsource:(a)singletransistor
configuration(b)cascodeconfiguration.

TheindividualcurrentswitchisshowninFig.6.27a.ThegateofQ0istiedtoabiasvoltagesuchastheoneshowninFig.6.22andestablishesthebiascurrent.When
theClksignalishighQ2isoff,Q3ison,andIbiasflowsintotheoutputload.WhenClkgoeslow,Q3turnsoff,Q2turnson,andIbiasflowsintoground.AsshowninFig.
6.27a,whenthecurrentflowsintotheload,theoutputvoltage,v out,modifiesthevoltageofnodeA,hencechangingthedraintosourcevoltageofQ0and
consequently,thebiascurrent.Toincreasetheoutputimpedanceofthecurrentsource,thecascodeconnectedcurrentmirrorshowninFig.6.27bcanbeused.The
outputvoltageswingofthecurrentsourcecanbeimprovedbyusingthemodifiedbiasingschemesdiscussedinChapter3.
AnalternativecurrentswitchwithimprovedcurrentregulationisshowninFig.6.28[16].InthiscircuitthegateoftransistorQ3isnotswitchedbutistiedtoa

Figure6.28
Configurationofimproved
currentswitch.

Page244

Figure6.29
Currentswitchwithavoltagetocurrentconverter.

constantvoltageVdc.Thisstageisessentiallyafullyswitcheddifferentialpair.ThecurrentIbiasissteeredeithertogroundortotheoutputload,dependingonthe
polarityofthedigitalinputsignalthatisappliedtothegateofQ2.InthiscircuitthepotentialofnodeAisindependentofthepotentialofv outandisdeterminedbythe
biasvoltageVdc,thebiascurrent,andtheVGSdropofQ3.SincethedraintosourcevoltageofQ0remainsconstantandindependentoftheoutputvoltage,itsdrain
currentalsoremainsunchanged.ThesimplifiedschematicofthevoltagetocurrentconverterandthecurrentswitchisshowninFig.6.29[17].ThetransistorQb1is
insertedinthefeedbackofthevoltagetocurrentconvertertobalancethedraintosourcevoltageofallthecurrentmirrortransistors,henceequalizingtheircurrents.
CurrentoutputD/Aconvertersusingthesetypesofswitchesexhibitveryrapidsettlingtimes,typicallyontheorderof5to10ns.
6.6
SegmentedCurrentModeD/AConverterStages
ForhighresolutioncurrentmodeDACs,themethodsdescribedinSection6.5arenotpracticalbecausethenumberofcurrentelementsrisesexponentiallyandthe
siliconareanecessarytoimplementtheDACbecomesexcessivelylarge.AmoreefficientmethodofimplementinghighresolutioncurrentDACs,similartothevoltage
mode,isthesegmentedapproach[18].Figure6.30showsthebasicblockdiagramofanNbitsegmentedD/Aconverter.AnarrayofMequalcoarsecurrentsources
(Iu)isshown.Oneofthecoarsecurrentsourcescanbedividedintomorefinecurrentlevelsbyapassivecurrentdivider.Controlledbythevalueoftheinputdigital
code,anumberofthecoarseandfinecurrentsareswitchedtotheoutputterminal,andtheremainingcurrentsaredumpedtosignalground.InthecircuitofFig.6.30,
athermometerdecoderthatdecodestheN1MSBsoftheinputcodecontrolsthecoarsecurrentsources.Thefinecurrentsourceswillbecontrolledbytheremaining
N

Page245

N1LSBs.Inthisapproach,useofthethermometerdecoderguaranteesmonotonicityforthecoarsecurrentsources.TheentireDACisnotinherentlymonotonic,
however,becausethelastcurrentsource,whichisdividedintothefinecurrents,shouldmatchtheothercoarsecurrentsourceswithinoneLSBofaccuracy.To
guaranteemonotonicity,athreewayswitchcanbeaddedtoeachcoarsecurrentsource.Foreachcode,thefirstm1coarsecurrentunitsareswitchedtothe
output,andcoarsecurrentunitnumbermisswitchedtothefinecurrentdivider.Thismethodguaranteesmonotonicoperationbecausethesegmentcurrentselected,
whichisappliedtothefinecurrentdivider,dependsonthedatainput.Figure6.31showsthebasicblockdiagramofanNbitD/Aconverter.TheNbitinputdigital
codeisdividedintoCbitcoarse(MSBs)andFbitfine(LSBs)codes.TheCbitMSBsaredecodedbyabinarytothermometerdecoderthatcontrolsthecoarse
currentsources.TheremainingFbitsdirectlycontrolabinaryweightedcurrentdivider.TheCcoarsebitsrepresentvaluesfromzeroto2C1.Therefore,2Cunit
coarsecurrentsourcesarerequired,includingoneforthesegmentationcurrent.Figure6.32showstheoutputcurrentoftheconverterasafunctionoftheinputcode.
AssumethatpointAonthegraphrepresentstheanalogvaluecorrespondingtotheinputdigitalword.Theunitcoarsecurrentsources1throughm1(of2Cavailable
unitcurrentsources)areswitchedtotheoutputline(I0,coarse)controlledbytheMSBs,whiletheunitcurrentsourcemdenotedbyIseg,isdividedintothefinecurrent
levelsbyabinaryweightedcurrentdividerandisswitchedtotheoutputcurrentlinecontrolledbytheLSBs.Theoutputcurrentsofthecoarsenetworkandfine
currentdividerareaddedtoformthetotaloutputcurrent,expressedas

whereDfrepresentsthedecimalvaluecorrespondingtotheFLSBsandIuistheunitcoarsecurrentsource.Anexampleofa7bitsegmentedDACisshowninFig.
6.33whereC=3andF=4.Thereareatotalof23=8unitcoarsecurrentsanda4bitbinaryweighteddivider.ThereferencevoltageVref1isusedtobiastheunit

Figure6.30
BasicblockdiagramofasegmentedD/Aconverter.

Page246

Figure6.31
BasicblockdiagramofasegmentedNbitinherently
monotoniccurrentDAC.

Figure6.32
SegmentedD/Aoutputcurrentasafunctionofinputcode.

Page247

Figure6.33
SevenbitsegmentedcurrentDAC.

Page248

coarsecurrenttransistorsQ1toQ8.ThebinarytothermometerdecoderoutputscontrolthegatesofthethreewayptypeMOSswitchesQ9toQ32thatoperateinthe
linearregion.CascodedevicesQ33toQ48areaddedtoimprovetheaccuracyofthecoarsecurrents.Thisisachievedbyequalizingthepotentialsoftheswitchesand
thesegmentcurrentline,Iseg,whichisconnectedtothe4bitbinaryweightedcurrentdivider.Thebasiccurrentdividerconsistsof16equalsizedcommongateand
commonsourcetransistorsQf1toQf16.Theindividualdrainsarecombinedinbinaryweightednumbers,1,2,4,and8.Theoutputcurrentiscontrolledbyatwoway
switch,whichconsistsofptypeMOStransistorsQf17toQf24.ThefourLSBsdirectlycontrolthegatesofthesetransistors.
TheaccuracyofthesegmentedDACisdeterminedlargelybythematchingofthecoarseunitcurrentelements.SymmetricallayouttechniquesfortheMOStransistors
ofthecoarsecurrentsourcescanimprovetheaccuracy.However,theachievableprecisionbaseduponmatchingofcomponentsinastandardprocessisnot
sufficient.Therefore,additionalcalibrationtechniquesareusedtoachievehighresolutionconverters.Useofdynamicallymatchedcurrentsourcesisoneoftheself
calibrationtechniquesthatcanbeappliedtothesegmentedcurrentDACofFig.6.30toachievewellmatchedcurrentsourcesandhenceahighprecisionD/A
converter[19].Toaccomplishthis,eachunitcoarsecurrentsourceinFig.6.30iscontinuouslycalibratedbyareferencecurrentIrefinsuchawaythatallcoarse
elementsarematchedprecisely.Beforedescribingthecompleteprocess,thecalibrationprincipleforonesinglecurrentsourcewillbeexplained.
ThebasiccalibratedcurrentcellisshowninFig.6.34.Duringthecalibrationcycle,thesignalCALgoestoahighstate,transistorsQ3andQ2turnon,andQ4turnsoff.
Consequently,thereferencecurrentIrefisforcedtoflowthroughthediodeconnectedNMOSdeviceQ1andestablishesavoltageVgsacrossitsgatetosource
capacitanceCgs.Thedimensionsandparametersofthetransistordeterminethemagnitudeofthisvoltage.WhenCALturnslow,thecalibrationprocessiscomplete.
TransistorsQ2andQ3turnoffandQ4turnsonandthegatetosourcevoltageVgsofQ1remainsstoredonCgs.ProvidedthatthedrainvoltageofQ1alsoremains

Figure6.34
Calibrationcircuitfor
asinglecurrentcell.

Page249

Figure6.35
Improvedcalibrationcircuit
forasinglecurrentcell.

unchanged,itsdraincurrentwillstillbeequaltoIref.ThiscurrentisnowavailableattheioutterminalandIrefisnolongerneededforthiscurrentsource.
Twononidealeffectsdegradethecalibrationaccuracyofthecurrentcell.Theseeffects,showninFig.6.34,arethechannelchargeofQ2whichwhenturnedoffis
partiallydumpedonthegateofQ1,andtheleakagecurrentofthereversebiasedsourcetosubstratediodeofQ2.Botheffectsalterthechargethatisstoredonthe
gatetosourcecapacitorCgsandhencemodifythedraincurrent.Itcanbeshownthatdecreasingthetransconductance(gm)ofQ1canreducetheimpactofboth
nonidealeffectsontheoutput(drain)current[19].
ThecalibrationcircuitofFig.6.34canbemodifiedbyaddingafixedcurrentsourceinparalleltothecurrentsourcetransistorQ1.ThemodifiedcircuitisshowninFig.
6.35,andtheadditionalcurrentsourceisrepresentedbytransistorQ5,withitsgatetiedtoafixedbiasvoltage,Vbias.Theaddedcurrentsourcehasavalueofabout
90%ofthereferencecurrentIref.ThisreducesthevalueofQ1'scurrenttoabout10%ofitsoriginalvalueanddecreasesitstransconductancebyafactorof

Furthermore,sincethecurrentofQ1islower,itsW/LratiocannowbereducedbyincreasingthelengthL.Inthiswayitispossibletoreducethetransconductanceof
Q1furtherbyafactorof8to10whileincreasingitsCgs.
ForthecalibrationtechniquetobesuitablefortheDACofFig.6.30,theprinciplemustbeextendedtoanarrayofcurrentsources.Asystemthatusesthecontinuous
calibrationtechniqueforanarrayofcurrentcellsisshowninFig.6.36.TheprincipleischaracterizedbyusingN+1currentcellstogenerateNequalcurrentsources.
ThecurrentcellnumberN+1isthesparecell.An(N+1)bitshiftregistercontrolstheselectionofthecelltobecalibrated.Oneoutputofthe(N+1)bitshift
registerisalogic1,whiletheotheroutputsareallzero.Thecellcorrespondingtotheregisterwiththelogiclevel1isselectedforcalibrationandisconnectedtothe
referencecurrent.Becausethiscellisnownotdeliveringanycurrenttoitsoutputterminal,theoutputcurrentofthesparecellisswitchedtothisterminal.After
completionofacalibrationcycle,thecontentsoftheshiftregisterisshiftedbyoneplace,andthenextcellinthearrayisselectedforcalibration.Thisway,every

Page250

currentcellissequentiallycalibratedandinsertedbackintothearray.Theswitchingnetworkisresponsiblefortakingthecurrentsourceselectedoutofthearrayfor
calibrationandreplacingitwiththesparecell.Sincetheoutputoftheshiftregisterisconnectedtoitsinput,afterallcellsarecalibratedsequentially,thefirstcellis
calibratedagain.Byusingonesparecell,notimeislostduringthecalibrationperiodandtherearealwaysNequalcurrentsourcesavailableattheoutputterminals.At
thispointitisworthmentioningthatthepurposeofcalibrationisnottomakethevalueofthecurrentsourcespreciselyequaltoIrefbuttomakethecurrentsources
matchaccurately.
ThecoarsecurrentarrayintheDACofFig.6.31canbereplacedwiththecalibratedcurrentarrayofFig.6.36.Thebasicblockdiagramofa16bitDACisshownin
Fig.6.37.TheDACissegmentedinto6bitcoarseand10bitfineDACs.Thecoarsecurrentarraynowconsistsof65calibratedcurrentcellsshowninFig.6.35.
Thecurrentoutputsof63normallyfunctioningcellsareconnectedto63twowaycurrentswitches,andonecellisconnecteddirectlytothe10bitbinaryweighted
currentdivider.Thenonfunctioningcurrentcellisconnectedtothereferencecurrentforcalibration.Inthisarrangementsinceallcurrentcellsarecalibrated,aunique
currentcellisdedicatedtothefinecurrentdivider,unliketheDACofFig.6.33.AsimplifiedversionofthecalibrationcircuitryandthecurrentcellisshowninFig.
6.38.Ofthe65currentcells,63supplycurrentstothecoarseDAC,onesuppliescurrenttothefinecurrentdivider,andonecellisbeingcalibrated.Foranormally
functioningcell,transistorsQ2,Q5,andQ7areoffandthecurrentsourcecomprisedoftransistorsQ1andQ4suppliesthecurrenttotheoutputterminalthroughthe''on"
deviceQ6.Forthecellthatisbeingcalibrated,devicesQ2,Q5,andQ7areonandQ6isoff.Sincethecellisnotoperational,thesparecellisswitchedtothe
correspondingoutputterminalthroughdeviceQ7.NoticethatterminalsAnandBnofall65currentcellsareconnectedtonodesAandBofthecalibrationcircuitry.For
thecellselected,thereferencecurrentIrefflowsintoQ1throughQ5,andtheloopbetweenthedrainandgateofQ1isclosedbythethreetransistorsQ5,Q8,andQ2.
ThisprocesschargesthegateofQ1toanappropriatevoltagerequiredformaintaininga

Figure6.36
BlockdiagramofacontinuouslycalibratedarrayofNcurrentsources.

Page251

Figure6.37
Blockdiagramofa16bitcontinuouslycalibratedDAC.

Figure6.38
(a)Calibrationcircuitry(b)currentcell.

Page252

draincurrentofIref.Attheendofthecalibrationperiodthecellreturnstoitsnormaloperationandthenextcellinthearraybecomescalibrated.InFig.6.38,transistor
Q3hasbeenaddedforchannelchargecancellation.ThegatesofQ2andQ3areconnectedtothetwooppositephasesofthecontrolclock.Thetransistorsareidentical
exceptthatQ3hashalfthechannelwidthofQ2.ThechargetransferredfromthecontrolsignaltoCfromQ2duringthefallingedgeoftheclockiscanceledbythe
chargetransferredtoCbyQ3duringtherisingedgeoftheoppositeclock.
SixteenbitDACsusingthecontinuouscalibrationtechniquedescribedinthissectionhaveachieved0.0025%linearityatapowerdissipationof20mWanda
minimumpowersupplyof3V[19].
Problems
6.1.Whatisthenecessaryrelativeaccuracyoftheresistorratiosinthe8bitversionoftheresistiveDACofFig.6.4toachieve8bitlinearity?
6.2.ProveEq.(6.4)forthefoldedresistordividerDACofFig.6.6.
6.3.AnalyzethecircuitofFig.6.13.Describev 0(nT)intermsofv in(nT).Assumefirstinfinite,thenfiniteopampgain.
6.4.Figure6.39showsanoffsetcompensatedvoltageamplifierthatdoesnotrequireahighslewrateopamp[9].Analyzethecircuitforbothchoices(shownin
parenthesesandwithoutparentheses)oftheinputbranchclockphases.Howmuchdoesv outvarybetweenthetwointervals 1="1"and 2="1"?Plottheoutput
voltagev outforbothchoices.
6.5.CalculatethetotalcapacitanceloadingnodeXinannbitPCAasshowninFig.6.16.
6.6.WhatisthenecessaryrelativeaccuracyofthecapacitorratiosinthechargemodeD/AconverterofFig.6.17toachieve11bitlinearity?
6.7.DesignthetwostagecascadedD/AconverterofFig.6.19for12bitresolution.Determinethenumberofthebitsinthefirstandsecondstagessothatthetotal
capacitanceisminimized.
6.8.Designa10bithybridD/AconverterusingachargemodeMSBandresistormodeLSBstructure(Fig.6.20).Determinetherelativeaccuracyofthecapacitor
andresistorratiostoachieve10bitlinearity.
6.9.Deriveanexpressionforthenumberofunitcapacitors,resistors,andswitchesfortheNbitDACofFig.6.21.AssumethatN=N1+N2,whereN1isthenumber
ofLSBsassignedtotheresistiveDACandN2isthenumberofMSBsassignedtothecapacitiveDAC.
6.10.Designan8bitcurrentDACaccordingtothearchitectureofFig.6.25.Use

Page253

Figure6.39
Offsetcompensatedvoltageamplifier(forProblem6.4).

anequalnumberofbitsforthecolumnsandrows.Designthecolumnandrowdecodersandthecurrentcelllogic.
6.11.RepeatProblem6.10forthearchitectureofFig.6.26.Designthecurrentreferenceandtheunitcurrentsinsuchawaythatthefullscaleoutputcurrent
generates1Vofpeakvoltageacrossa75 loadresistor.
6.12.ForthecircuitofFig.6.29,plotthewaveformatnodeAwhenClkgoesfromlowtohighandhightolow.Assumethatthelowlevelis0V,thehighlevelisVDD
(thepositivesupplyvoltage),andthepchannelthresholdvoltageisVDD/5.
6.13.Designthe10bitversionofthesegmentedDACofFig.6.31.Use4bitsforthecoarsecurrentand6bitsforthefinecurrentDACs.Ifthefeedbackresistorof
thecurrenttovoltageconverteris1k ,findthevalueofthefullscalecurrentifthemaximumoutputvoltageis2V.Whatisthevalueofeachcoarsecurrentsource
andthecurrentcorrespondingtooneLSB?
6.14.Figure6.31showsaunipolarsegmentedcurrentDACwheretheoutputvoltagevariesbetween0VandVFS=RIFSandIFSisthefullscaleoutputcurrent.

Page254

Inasinglesupplyapplication,assumethatthepositiveinputoftheopampisconnectedtoVDD/2(VDDisthepositivesupplyvoltage).ModifythecircuitofFig.6.31so
thatthevoltageoutputvariesbetweenVDD(zeroinputcode)andVDD(fullscaleinputcode).AssumethattheDACis8bits,VDD=5V,andR=1k .(Hint:
Connectafixedcurrentsourcetotheinvertinginputoftheopamp.)
References
1.A.R.Hamad,IEEEJ.SolidStateCircuits,SC13(6),785791(1978).
2.A.DingwallandV.Zazzu,IEEEJ.SolidStateCircuits,SC20(6),11381143(1983).
3.M.J.M.Pelgrom,IEEEJ.SolidStateCircuits,SC25(6),13471352(1990).
4.A.Abrialetal.,IEEEJ.SolidStateCircuits,SC23,13581369(1988).
5.P.Holloway,ISSCCDig.Tech.Pap.,pp.6667,Feb.1984.
6.Y.A.Hague,R.Gregorian,R.W.Blasco,R.A.Mao,andW.E.Nicholson,IEEEJ.SolidStateCircuits,SC14(6),961969(1979).
7.R.Gregorian,Microelectron.J.,12,1013(1981).
8.R.Gregorian,K.Martin,andG.C.Temes,Proc.IEEE,71,941966(1983).
9.K.Huang,G.C.Temes,andK.Martin,Proc.Int.Symp.CircuitsSyst.,pp.10541057,1984.
10.J.L.McCrearyandP.R.Gray,IEEEJ.SolidStateCircuits,SC10(6),371379(1975).
11.R.GregorianandG.Amir,Proc.Int.Symp.CircuitsSyst.,pp.733736,1981.
12.K.W.Martin,L.Ozcolak,Y.S.Lee,andG.C.Temes,IEEEJ.SolidStateCircuits,SC22(1),104106(1987).
13.B.FotouhiandD.A.Hodges,IEEEJ.SolidStateCircuits,SC14(6),920926(1979).
14.T.Miki,Y.Nakamura,M.Nakaya,S.Asai,Y.Akasaka,andY.Horiba,IEEEJ.SolidStateCircuits,SC21(6),983988(1986).
15.L.Letham,B.K.Ahuja,K.N.Quader,R.J.Mayer,R.E.Larson,andG.R.Canepa,IEEEJ.SolidStateCircuits,SC22(6),10411047(1987).
16.A.B.Grebene,BipolarandMOSAnalogIntegratedCircuitDesign,Wiley,NewYork,1984.
17.D.A.JohnsandK.Martin,AnalogIntegratedCircuitDesign,Wiley,NewYork,1997.
18.H.J.Schouwenaers,D.W.J.Greeneveld,andH.A.H.Tremeer,IEEEJ.SolidStateCircuits,23(6),12901297(1988).
19.C.A.A.Bastiaansen,IEEEJ.SolidStateCircuits,24(6),15171522(1989).
20.S.R.Norsworthy,R.Schreier,andG.C.Temes,DeltaSigmaDataConvertersTheory,Design,andSimulation,IEEEPress,Piscataway,NJ,1997.

Page255

Chapter7
AnalogtoDigitalConverters
Theanalogtodigitalconverter(usuallyabbreviatedADCorA/Dconverter)isanessentialbuildingblockinmanydigitalsignalprocessingsystems.Itprovidesalink
betweenthedigitalsignalprocessorandtheanalogsignalsofatransducer.TheA/Dconverterisconsideredtobeanencodingdevice,whereitconvertsananalog
sampleintoadigitalquantitywithaprescribednumberofbits.NumeroustypesofA/Dconvertershavebeendesignedforawidevarietyofapplications.Thetypeof
theapplicationlargelydeterminesthechoiceoftheA/Dconversiontechnique.Fromtheviewpointoftheimplementation,analogtodigitalconverterstypicallycontain
oneormorecomparators,switches,passiveprecisioncomponents,aprecisevoltagereferenceanddigitalcontrollogic.
InthischapterthebasicprinciplesandperformancemetricsoftheA/Dconvertersarepresentedfirst.Followingthat,severaltypesofNyquistrateA/Dconversion
techniquesareexamined,andtheirimplementationintheCMOStechnologyisdiscussed.
7.1
AnalogtoDigitalConversion:
BasicPrinciples
AswasthecasewithNyquistratedigitaltoanalogconverters,thereareavarietyofalgorithmsandrealizationsavailableforanalogtodigitalconvertersoffering
differentadvantagesanddisadvantages.Thetradeoffsbetweentheconversionaccuracy,speed,andeconomy(thelattermeasuredbycircuitcomplexity,chiparea,
powerdissipation,etc.)offeredbytheseoptionsvarywidely.Aswillbeseen,practicalconvertersexistforsignalbandwidthsrangingfrom1Hzto5GHz,with
resolutionsanywherebetweenafewbitsto24bits.DifferentapplicationsobviouslyrequiredifferentparametersFig.7.1illustratestheapproximaterangeof
requirementsfor

Page256

Figure7.1
SpeedandresolutionrequirementsonADCsinvariousapplications.

Page257

somecommonsystemscontainingADCs.AswedidforDACs,weclassifyNyquistrateADCsaccordingtotheirconversionspeedintothreecategories:
1.HighSpeedADCs.Inthesedevicestheanalogsamplestobeconvertedcanbeenteredatarateequaltotheclockrate,orhalftheclockrate.Thusthethroughput
rateofdataequalstheclockrate,orhalfofit.Theremay,however,bealongconstantdelay(latency)betweenthetimethattheanalogsampleenterstheconverter
andwhenitsdigitalreplicaappearsattheoutput.TypicalexamplesofsuchhighspeedADCsaretheflash,interpolating,twostep(orhalfflash),pipeline,andtime
interleavedconverters.Suchconverterscanachieveconversionratesintherangeof0.5megasamples/second(MS/s)to10GS/s.Theiraccuracyrangesfrom8to12
bits.Typicalapplicationsincludevideo,imaging,andradarsystems.
2.MediumSpeedADCs.ForanNbitADC,suchconvertersrequireNclockperiodsforeachanalogsample.ThustheirthroughputisNtimesslowerthantheclock
rate.Typicalrealizationsincludethevariousserial(successiveapproximation)converters.Theseconvertersusuallyachievea10to14bitresolutiontheirconversion
speedmaybeintherange0.1to5MS/s.Theirapplicationsincludetelecommunication,control,andlowtomediumspeedmeasurementsystems.
3.LowSpeedConverters.ForaresolutionofNbits,thesedevicesrequireapproximately2Nclockperiodstoconvertananaloginputsample.Thiscanleadtovery
slowoperationforexample,ifN=16,65,536clockperiodsareneededforeachconversion.Clearly,theseconverterscanonlybeusedforconstant,orveryslowly
varyingsignals.Convertersinthiscategoriesincludethevariousintegratingandcountingcircuits,suchassingleanddualrampconverters.Typicalaccuraciesrange
from15to24bitstypicalapplicationsincludedigitalpanelinstruments,suchasdigitalvoltmetersandbiomedicalmeasurementinstruments.
WediscussthemostcommonA/Dconvertertypesandtheirkeypropertieslaterinthechapter.
Next,thekeyparametersthatcharacterizeanA/Dconverterarediscussed.TheblockdiagramofanADCisshowninFig.7.2.Theanaloginput(typically,avoltage
v in),isnormalizedtoa(voltage)referenceVrefandtheirratioisconvertedintoanNbitdigitaloutputwordBoutcontainingb1,b2,...,bN.Underidealconditions,
ignoringnoiseandanyimperfectionsofthecomponents,therelationbetweenthethreequantitiesis

Herev qisthequantizationerrorduetothefinitenumberNofbitsusedintheconversion.Thiserrorisinherentintheprocessandcanonlybereducedbyincreas

Page258

Figure7.2
Blockdiagramofananalogtodigitalconverter.

ingNorbyreducingVref.TheoutputinputcharacteristicoftheconversionisillustratedinFig.7.3forN=2thequantizationerrorv qisthedifferencebetweenthe
solidstaircasecurve(theactualcharacteristic)andthedashedline(whichrepresentstheidealcurveforinfiniteN).Weshalldefinetheleastsignificantbit(LSB)
voltageVlsb=Vref/2N.HereVlsb=Vref/4forN=2.Then,asFig.7.3shows,themagnitudeofv qcannotexceedVlsb/2aslongasv inremainsintherange0toVref
Vlsb/2.ThisiscalledthelinearconversionrangeoftheADCforv invaluesoutsidethisrange,theconverteroverloadsandtheabsolutevalueofv qisnotbounded

Figure7.3
Inputoutputcharacteristics(transfercurve)fora2bitADC.

Page259

byVlsb/2.ForreasonablylargevaluesofN,Vrefcanapproximatetheupperboundaryofthelinearrange.Thefigurealsoshowsthetransition(orthreshold)voltages.
ThesearetheinputvoltagevalueswhereBoutchangesitsvalueforourexample,theyareatVref/8,3Vref/8,and5Vref/8.Also,thecodecenterpoints,locatedhalfway
betweenthetransitionvoltages,canbeobserved.Thesearelocatedontheideal(infiniteN)linecharacteristic.
Forarandomlyvaryinginputsignalv in(t)thatstayswithinthelinearrange,wemayoftenassumethatthequantizationerrorv qisarandomnoisewithazeromeanvalue
andthattheinstantaneousvalueofv qisarandomvariablewithauniformdistributionprobabilitybetweenVlsb/2and+Vlsb/2.Thenitsrmsvaluecanreadilybefound
(Problem7.1)tobe

Thepowerofthequantizationnoisev qistherefore

Toillustratethevalidityofthisapproach,Fig.7.4showsthespectrumofasinewavesignalafteran8bitquantization.Thetalllineat / c=0.24represents

Figure7.4
Spectrumofasinewavesignalafter8bitquantization.

Page260

thespectrumoftheoriginalsinusoid,andtherandomwhitenoiselikespectrumeverywhereelsebelongstov q.Clearly,inthiscasetheapproximationofv qbya

whitenoiseisreasonablyaccurate.
Next,lettheinputsignalv inbeasinewavewithapeaktopeakamplitudeVref.ThisisthemaximuminputamplitudethattheADCcanhandlewithoutoverloading.
Thepowerofthesignalv inis,then,
Hereweignoredtheunimportantdcpowerduetothedcbiasneededtocentertheinputsignalinthelinearrangeof
theADC.Therefore,usingthenoisemodelofv q,thesignaltoquantizationnoiseratiooftheNbitADCis

AsimilarcalculationperformedforasawtoothinputsignalgivesanSNRof6.02NdB(Problem7.2).ThustheSNRofanNbitA/Dconverterwithagiven
referencevoltageVrefislimitedbyquantizationnoisetoabout6NdBtheSNRisincreasedby6dBforeveryaddedbit,sinceeachextrabitreducestheamplitudeof
v qbyafactorof2.
Inpractice,theidealconversioncurveofFig.7.3cannotbeachievedthethresholdvoltagesthatarenominallyatoddmultiplesofVlsb/2willinfactoccuratdifferent
v invalues,andhencevariouserrorswillappear.SomeofthecommonlyusederrordefinitionsareillustratedinFigs.7.5to7.8.Figure7.5showsatransfer
characteristicwithoffseterror:theidealconvertercurveishorizontallyshifted.Theoffseterror

Figure7.5
Transfercharacteristicsfora2bitADCwithandwithoutoffseterror.

Page261

Figure7.6
Transfercharacteristicsfora2bitADCwithandwithoutgainerror.

issimplytheamountofshift.ThegainerrorisillustratedinFig.7.6thethresholdvoltagesremainequallyspaced,butthespacingisnolongerthecorrectVlsb.Both
offsetandgainerrorsarelinearerrorstheydonotdistorttheinputsignal,onlyshiftorscaleit.Thusforasinewaveinputthequantizationerrorremainsarandom
noiselikesignal,andnoharmonicsoftheinputsignalaregenerated.Hencesucherrorscanusuallybeacceptedand/orcompensatedelsewhereinthesystem.Amore
seriousdistortionresultsfromtheunavoidableunequalspacingofthethresholdvoltages,whichcausesnonlinearityerrors.Twosuchnonlinearcharacteristicsare
showninFigs.7.7and7.8.Intheformer,thenonlinearityerrorisrelativelysmall,andoverthecompleterangeofv intheADCgenerateseveryoutputcode.Inthe
latter,thedistortionduetononuniformvariationofthethresholdvoltagesisexcessive,andoneoutputcode(010)cannotbegeneratedatall.Thiseffect,called
missingcodeerror,isnormallyunacceptableinapracticalADC.AswasthecaseforDACs,thenonlinearityerrorsofADCsareusuallyquantifiedbythevaluesof
theirintegralnonlinearityerror(INL)anddifferentialnonlinearity(DNL).InADCs,theINLisdefinedasthelargestverticaldifference(expressedinLSBs)
betweenthecodecenterpointsoftheactualcharacteristiccurveandthelineconnectingtheendpointsonthecurve(Fig.7.9).TheDNLisdefinedasthelargest
deviationbetweentheactualdifferencesoftwoadjacentthresholdvoltagesandtheidealdifferencevalue(Vlsb),asshownintheADCcharacteristicsofFig.7.9.Here
thelargesterroroccurswhenthetransitionleveldifferenceequalsd,andhencetheINLexpressedinLSBsis(dVlsb)/Vlsb.

Page262

Figure7.7
Transfercharacteristicsfora2bitADCwithand
withoutnonlinearity.

Figure7.8
Transfercurveofa2bitADCwithandwithout
missingcodeerror.

Page263

Figure7.9
NonlineartransfercurveshowingtheINLandtheworstcase
transitiondifference.TheDNLis|dVlsb|.

7.2
FlashA/DConverters
FlashanalogtodigitalconvertersarethefastestandconceptuallythesimplestA/Dconverters.InanNbitflashA/Dconverter,2N1separateanalogcomparators
andreferencevoltagesareusedtoconverttheanalogvoltagetoadigitalword.Eachoneofthe2N1referencevoltagescorrespondstoonequantizationlevelinthe
digitalword.Figure7.10showstheconceptualdiagramofanNbitflashA/Dconverter.Here2N1comparatorsareusedandthe2N1quantizationlevelsare
generatedbyanNsegmentresistivevoltagedivider.Theoutputsofthecomparatorsareprocessedbytheencoder/decoderlogictoproduceanNbitdigitalword.
Figure7.11showsthestructureofa3bitflashA/Dconverterinsomewhatmoredetail.Thepositiveinputofthe231=7latchingcomparatorsisconnectedtoa
commonanalogbus,whichisdrivenbytheanaloginputvoltage.Theotherinputofeachcomparatorisconnectedtoadistinctanalogdecisionlevel.Foragiven
analoginputlevelv in,thecomparatorswhoseinputreferencelevelsarebelowv inwillhaveanoutputstateof1,andthosewithreferencelevelsabovev inwillhavean
outputstateof0.Thusthereferencevoltagesandcomparatorstagesareusedtoconverttheanaloginputtoadigitalthermometeroutputcode.Table7.1showsthe
thermometercodeandthecorrespondingdigitalbinarycode.Withincreasinganalog

Page264

Figure7.10
ConceptualdiagramofanNbitflashA/Dconverter.

voltagev in,thenumberofthe1'sinthethermometeroutputcodewillincrease.ExaminingTable7.1revealsthattheparticularresistorsegmentinwhichtheanalog
inputliescanbedeterminedbyanencoderlogicthatcomparestheoutputlogiclevelsofeachcomparatorwiththeoutputsimmediatelybelowit.AsshowninFig.
7.11forthe3bitflashA/Dconverter,theencoderlogicconsistsof231=7twoinputANDgates.Forexample,forananaloginputlevelcorrespondingtothe
binarydigitalword100,theoutputoftheANDgatewiththeinput willbetrue.Theoutputoftheencoderisappliedtoadecoderlogictoforma3bitword.As
showninFig.7.11,anadditionalcomparatorcanbeaddedwhichdetectsoverflowconditionscorrespondingtoinputlevelsthatexceedVref.
Asmentionedearlier,thecomparatorsinaflashconvertergenerateathermometercode.Wheneverythingisworkingideally,thepatternofcomparatoroutputsshould
resemblethatofathermometer,all0'sabovetheinputlevel,all1'sbelow.Thezerotoonetransitionpointrisesandfallswiththeinputlevel.However,under

Page265

Figure7.11
Basicstructureofa3bitflashA/Dconverter.

extremelyhighinputslewrateconditions,timingdifferencesbetweenvarioussignalpathsorevenslightdifferencesbetweencomparatorresponsetimescancausethe
effectivestrobepointofonecomparatortobequitedifferentfromanother.Consequently,a1maybefoundabovea0inthethermometercodeeventhoughthis
cannothappenatdc.Errorsofthetypearesometimesreferredtoasbubblesbecausetheyresemblebubblesinthemercuryofathermometer.Table7.2showsa
normalthermometercodeandthecorrespondingencoderoutput,andathermometercodethatiscontaminatedbyabubbleerror,inthiscasea0surroundedby1's.
TheencoderoutputsofFig.7.11wouldnowgeneratetwotrueoutputs,which(dependingonthedesignofthedecoder)mayproducegrosslyerroneouscodes.
AcommonmethodofsuppressingbubblesistouseathreeinputANDgatethatcomparesthelogicoutputofeachcomparatorwiththoseimmediatelyaboveand
below.Thiswouldthenrequiretwo1'sanda0tocausetheencoderoutputtobetrue,andthebubbleerrorsshowninTable7.2wouldbeavoided.Figure7.12
shows

Page266
TABLE7.1.BinaryThermometerCodeRelationship
Decimal
Number

BinaryCode

ThermometerCode

b2

b1

b0

the3bitflashA/Dconverterwithamodifiedencodertoremovethebubbleerrors.However,thiscircuitwillnotremovebubbleerrorswheretwoormorestringof
0'saresurroundedby1's.Moresophisticatedencoderscanbeusedtoeliminatetheseandotherpossiblebubbleerrors[1,2].
Inbipolartechnology,flashA/Dconvertersoperateinacontinuoustimemode.Sampleandholdcircuitscannotbeusedbecauseofthedroopcausedbythecurrent
ofbipolarcomparatorinputdevices.Furthermore,analogswitchesarenoteasilyimplementedinbipolartechnology.CMOSflashA/Dconverters,ontheotherhand,
canoperateineithercontinuousordiscretetimemode.Inthediscretetimemodeofoperation,asampleandholdcircuitcanbecombinedwiththecomparatorinput
stage.ThecomparatorisnormallyimplementedwithoneormoreoffsetcancelingCMOSinverterstage.InanNbitflashA/Dconverter,2N1offsetcanceled
TABLE7.2.EncoderOutputsforThermometerCodesWithandWithoutBubbleError

Normal
Thermometer
Code

Encoder
Output

Thermometer
Codewith
BubbleError

Encoder
Output

Bubble

Page267

Figure7.12
Structureofa3bitflashA/Dconverterwithanencoderthat
eliminatessimplebubbleerrors.

CMOSamplifiercomparatorstageswithsampleandholdinputcapacitorswillbeusedtoperformtheconversion.
Figure7.13showsthedetailsofanautozeroedsequentiallysampleddifferentialinputcomparatorstage[3].ItusesaCMOSinverterstagewiththreeCMOS
switchesS1,S2,andS3andcapacitorC,whichsamplestheinputsignal,aswellastheinputoffsetvoltageoftheinverter.TheCMOSswitchesarecontrolledby
thetwocomplementaryclockphases and .Duringthefirsthalfclockcycle,when ishigh,switchesS1andS2arebothonandswitchS3isoff.SwitchS1shorts
theinputandoutputoftheinverterstageandchargesonesideofthecapacitorCtoabiasvoltagedeterminedbytheW/Lratiosofthedevicesintheinverterstage.
ThePMOSandNMOSdevices,withtheirgateanddraintiedtoeachother,formavoltagedividerbetweenthepositivesupplyandgroundandarenormallysizedso
thatthebiasvoltageatthecenternodeisapproximatelyonehalfofthepositive

Page268

Figure7.13
AutozeroedCMOScomparatorwithsampleandholdinputbranch.

supplyvoltage.TheothersideofcapacitorCisconnectedtotheinputvoltagev inviaswitchS2.Duringthisphasethecomparatorinverterisautozeroedtoitstoggle
pointbyS1,andtheinputvoltageisconnectedtocapacitorCthroughswitchS2.Assoonas goeslow,bothS1andS2turnoff,andtheinputvoltageremainsstored
oncapacitorC.WithS1open,theinverterbecomesagainstageanditsgatefloatsarounditstogglepoint.Duringthesecondhalfclockcycle, clocksignal.
AsmentionedbrieflyinChapter5,thecomparatorofFig.7.13hastwopotentialproblems.Oneproblemisthatthevoltagegainofthesingleinverterstageisrather
low,typicallyaround50.Thisputsalowerlimitontheminimumvoltagethatthecomparatorcanresolve.Theotherproblemisthatthechannelchargeinjectionand
clockfeedthroughoftheswitchesmodifythevoltagestoredoncapacitorC,resultinginanoffsetvoltagethatisafunctionoftheclocksignal.Toinvestigatetheclock
feedthrougheffect,considertheparasiticcapacitorsCp1andCp2showninFig.7.13.WhenswitchesS1andS2turnoff,aportionoftheirchannelchargesandthe
capacitivelycoupledclockfeedthroughchargearetransferredtoCp1andCp2.TheparasiticchargetransfertoCp1hasnoadverseeffectsbecausewhenS3turnson,
capacitor

Page269

Cp1willbeconnectedtoVref.SoCp1isalwaysswitchedfromonevoltagesourcetoanother,andtheintermediatevoltageofCp1whenbothS2andS3areoffis
unimportant.ThechargecouplingtoCp2,however,cannotbeignored,becausetheresultingchangeofvoltageacrossCp2modifiesthebiasvoltageofthecomparator
thatisstoredonC.UsingminimumsizedcomplementaryswitcheswithCMOSdevices,sothatthepandnchannelcontrolvoltagesareequalandoppositewill
resultinsomeerrorcancellation.AmoreeffectivesolutionistousethetwostagecomparatorshowninFig.7.14a.Thiscircuitconsistsoftwocascadedautozeroed
comparatorstagescontainingtwocapacitors,C1andC2andfourswitches,S1,S2,S3,andS4[4].Duringthefirstautozeroinghalfcycle,when 1and 2arehigh,
switchesS1,S2,andS4areonandS3isoff.Next,switchesS1andS2turnoffwhileS4remainsonandC2storesthevoltagechangeduetothechargeinjectionofS1.
Subsequently,S4turnsoffandS3turnson,andthecomparatorentersthehighgainregion.Itamplifiesthevoltagedifferencebetweenthesampledinputsignaland

Figure7.14
(a)Twostageautozeroedcomparator(b)comparatortiming.

Page270

thereferencevoltage.Figure7.14bshowsthetimingoftheclockwaveforms.Thecomparatorhasamuchhighergainandcanrespondaccuratelytomuchsmaller
inputvoltages.Asbefore,amatchinginverterandaclockedlatchthatcapturesthefinaldigitaloutputfollowthecomparator.Themaximumsamplingfrequencyofthe
flashA/Dconverterthatusestheautozeroingcomparatorisdeterminedbythespeedofthecomparatorandthequantizationvoltage(absolutevoltageofoneLSB),
whichisafunctionofthemagnitudeofthereferencevoltageandthenumberofbitsinthedigitaloutput.
7.3
InterpolatingFlashA/DConverters
TheconceptoftheflashA/DconverteraspresentedinSection7.2isstraightforward,anditcanveryeasilybeextendedtohigherresolutionsystems.Thecomplexity,
however,increasesveryrapidlywiththeresolution(Nbits).ForanNbitsystem,thearchitecturerequiresaminimumof2N1comparatorsand2Nresistors.For
example,an8bitA/Dconverterwillrequire255comparatorsand256resistors.ItisthereforedifficulttorealizehighresolutionhighspeedflashA/Dconvertersand
maintainlowpowerdissipationandsmalldiearea.Thephysicallayoutoftheflashconverterposesanotherchallenge.Thecomparatorsandlongresistorstringsshould
belocatedinasymmetricalfashiontoavoidunequalpropagationdelaysfortheclockandinputsignalsandtopreventunevensamplinginstancesoftheinputsignal
acrossthecomparatorarray.Asthenumberofbitsincreases,theinputcapacitanceofthesystemincreaseslinearlywiththenumberoftheautozeroedcomparators.
Thislargeinputcapacitancecauseshighspeedcurrentspikesinboththeanaloginputandthereferencetaps.Toovercometheeffectsofthesedynamictransient
signals,theuserisrequiredtoprovideahighpowersignalbufferfordrivingtheanaloginputterminal.Onemethodforachievinglowerinputcapacitanceistouse
interpolationtechnique[4].Figure7.15showsasimpleinterpolationcircuitthatcanreducethenumberoftheinputcomparatorsandconsequently,theinput
capacitancebyafactorof2.ForanNbitflashA/Dconverter,thereferenceresistordividerisdesignedwith2N1taps,whichisalsoafactorof2reduction.
Interpolatingresistorsareconnectedbetweentheoutputsofadjacentcomparators,andthevoltageatthecommonterminalofthetworesistorsistheaverageofthe
twocomparatoroutputsignals:

Tounderstandtheoperationofthecircuit,assumethatallinverterstagesintheautozeroinginputcomparatorsandthosethatfollowthemaremadeofmatchingp
andnchanneltransistors,sothattheyallhaveidenticaltogglevoltageequaltoVblas.Assumealsothattheanaloginputvoltage(oncecapturedonthesampleandhold
capacitors)causestheoutputofinverteri1andallthosebelowittobein

Page271

Figure7.15
InterpolatingflashA/Dconverter.

saturation,indicatingalogic1andcausestheoutputsofinverteri+1andallthoseaboveittobeinsaturation,indicatinga0.Comparatorsi+1andiwill,however,
beoperatingintheirhighgain(linear)regions.Theywillhencebeamplifyingthedifferencebetweentheanaloginputvoltageandtheirrespectivetapvoltagesonthe
referencedivider.Inthiscase,thevoltagethatwillappearattapAontheseconddividerwillbehalfwaybetweenthevoltagesattheoutputsofcomparatoriandi+1
andwillhavethevaluegivenbyEq.(7.5).IfthisvoltageisgreaterthanVblas(thetogglevoltageoftheinverter),theoutputofinverteri+connectedtonodeAwill
be0otherwise,itwillbea1.The2N1outputsfromthecomparatorsandtheaveraginginvertersarecapturedbyanarrayoflatches.Justasinallflash

Page272
N

converters,the2 1thermometercodeoutputdatafromthelatchesfeedadecoderthatconvertsthemtoanNbitbinaryword.
Alternatively,activeanalogcomponentscanbeusedinanaveragingcircuit[5].Figure7.16illustratesananalogaveragingcircuitemployingCMOSinverters.Thetwo
invertershavetheirinputstiedtoV1andV2(thevoltagestobeaveraged),withtheoutputsconnectedtoprovideanamplifiedaverageofthetwoinputsignals.
AssumingthatthetwoinverterstagesareidenticalandhaveequalgainsgivenbyA,theoutputwillbetheamplifiedaverageofthetwoinputvoltagesV1andV2:

Theimplementationoftheaveragingfunctionusingactivecomponentshasseveraladvantagesovertheaveragingcircuitsusingpassivecomponents.Firstthecircuit
amplifiestheaveragedsignalwhichimprovesresolutionandthenoiseperformance.Second,thecircuitprovidesanactivedrive,whichincreasesthespeedofthe
circuit.
Figure7.17isaschematicofaflashA/DconverterthatusestheactiveanalogaveragingcircuitshowninFig.7.16.Inthiscircuit,asbefore,onlyhalfthenumberof
requiredcomparatorsisusedintheinputstage.Theothersareimplementedbyusingtheactiveaveragingcircuitplacedbetweenadjacentcomparatoroutputs.
InterpolatingflashA/Dconvertershaveanumberofadvantagesoverconventional

Figure7.16
Activeinterpolatingcircuit.

Page273

Figure7.17
InterpolatingflashA/Dconverteremployingactiveaveragingcircuits.

fullflashconverters.Fewerautozeroingcomparatorsarerequired,whichsignificantlyreducesthesiliconarea,powerdissipation,andinputcapacitance.Hencethe
transientsignalsattheanaloginputandthereferencevoltagetapsarealsoreduced.Thisalsoreducestherequirednumberoftheprecisionvoltagetaps,whichleadsto
asignificantreductioninsiliconareaandinimprovedaccuracy.Activeinterpolationtechniques,(Fig.7.17)usesimpleinverterstagestoamplifyandaveragethe
effectiveresidualsignals.Thisincreasesthespeedandaccuracyoftheconvertersignificantly.
7.4
TwoStepA/DConverters[69]
TheflashA/DconvertersdescribedinSection7.3require2N1comparatorstoachieveanNbitresolution.Thustheoverallcircuitcomplexityincreasesveryrapidly
withincreasingN.Theinterpolatingarchitecturesreducethetotalinputcapacitancebyreducingthenumberofautozeroingcomparatorsconnectedtotheinputline.
Thiswillincreasetheconversionspeedbutdoesnotintrinsicallyreducethetotalnumberofcomparatorsandclockedlatches.Analternativetoaflasharchitectureis

Page274

Figure7.18
BlockdiagramofatwostepflashA/Dconverter.

themultistepA/Dconversiontechnique,withthetwostepflashbeingthemostpopular,duetoitshighspeedandeaseofimplementation.Thetwosteparchitecture
usesacoarseandafinequantizationtoincreasetheresolutionoftheconverter.SeveraltwostepA/Dconversiontechniquesareavailable.Figure7.18showsthe
blockdiagramofan(N+M)bittwostepA/Darchitecture.Thecircuitoperatesontheinputsignalintwoserialsteps.FirstanNbit"coarse"flashA/Dconverter
determinestheNmostsignificantbits.Afterthecoarsequantizationhasbeenperformed,theNbitdigitaldataarereconvertedintoananalogvalueusinganNbitD/A
converter.Thisanalogvalueisthensubtractedfromtheoriginalanaloginput.ThedifferenceissubsequentlyappliedtoanMbit"fine"flashA/Dconverterthat
generatestheMleastsignificantbits.Inmostcases,MandNarechosentobeequaltokeepthecircuitsymmetricalandthecomplexitylow.Forexample,inan8bit
twostepflash,onewouldusetwo4bitflashA/Dconvertersanda4bitD/Aconverter.
ThetwostepflashADC(alsoknownassubrangingADC)providesapowerfullowcostalternativetotheflashA/Dconverterwhenmaximumspeedisnot
necessary.Foran8bitA/Dconverter,thetwostepflashapproachreducesthecomparatorcountfrom28=256to31.Thisrequiresarelativelysmalldiesize,with
theinputloadingandpowerdissipationalsogreatlyreduced.Themajordisadvantageofthetwostepflashapproachisthereductioninthethroughputrate(onehalf
ofthatofflash):Twoclockcyclesarerequiredforeachconversioncycle,sincethefineconversioncannotstartuntilthecoarseconversioniscompleted.
Theblockdiagramofa6bittwostepflashA/Dconverter,whichwillbeusedtoexplainhowtheconceptcanbeimplemented,isshowninFig.7.19.Thesystem
containstwo3bitflashA/Dconverters.Eachflashsubsectionismadeupofsevencomparators,whichcomparetheunknowninputwiththetapvoltagesofastringof
referenceresistorstogeta3bitdigitaloutput.Thereferencestringconsistsofeight

Page275

Figure7.19
SixbittwostepflashA/Dconverter.

Page276

"coarse"resistors,eachofwhichhasavalueR.Eachcoarseresistorismadeupofeight"fine"resistors,eachwithavalueR/8.Thetotalresistanceoftheentirestringis
thus64R/8=8R.Thecoarseresistorsprovideseventapsforthe"coarse''comparatorsCM1toCM7,withvoltagesrangingfromVref/8to7Vref/8inincrementsof
Vref/8.Thesmallerresistorsformadivider,withoutputvoltagesrangingfromVref/64toVref/8inincrementsofVref/64.Onlythetapsofthelowerresistorstringare
connectedtothe"fine"comparators.TheA/DconverterofFig.7.19isapipelinedsubrangingarchitecture.Itconvertsintwosteps.Thefirst3bitconversion
subdividestheinputrangeintoeightsegments.Thenthesubrangechosenisfurtherquantizedintoeightsegments(3bits).Thetwo3bitwordsarethenmergedto
forma6bitoutputword.
ThecoarseandfineA/Dconverterseachusesevenautozeroingcomparators,CM1toCM7andCL1toCL7,respectively.AnadditionalcomparatorCM8isusedin
thecoarseA/Dconvertertodetectoverflow.ThedetailsofthecoarseandfineautozeroingcomparatorsareshowninFig.7.20aandb,respectively,andthetiming
diagramisillustratedinFig.7.20c.
Next,wediscusstheoperationsofthevariousstagesintheconverter.ThecoarseA/Dconvertercomparators(Fig.7.20a)areautozeroedduringthe 1=1period:
SM1,andSM2areclosed,andhenceC1incomparatorCMichargestoVMiVBM.HereVMi=(i/8)VrefistheithtapvoltageinthecoarseRstring,whileVBMistheself
bias(toggle)voltageofthecoarsecomparators.Whennext 1 0and 2 1,theinputvoltageofcomparatorichangesfromVBMto

HereCpistheparasiticinputcapacitanceofCMiandCLi(Fig.7.20a).ThustheoutputofCMiisdeterminedbythesignofv inVMiatthetimewhen 2 1.The

coarsecomparatoroutputsarethencapturedbyanarrayofclockedlatchesandencoded/decodedintothethreeMSBsoftheoutputwordusingtheprocess
illustratedinFig.7.12.TheoutputoftheencoderisalsousedtoselectasVDACthetapvoltageVMiinthecoarseresistorstring,whichisthelargestVMi<v in,byclosing
theappropriateswitchSi.Thisperformsthe3bitDACoperation(Fig.7.18).
ThefineA/Dconverteroperatesinapushpulltimingmodewiththecoarseconverter.Theithcomparatorisautozeroedduring 2=1.Inthefollowingphase,SL1,
SL2,andSL3areopenedandSL3andSL4closed.ThiscausesthecomparatorinputvoltagetochangefromVBLto

SinceC1=C2=Cisused,theoutputofCLiisdeterminedbythesignofVLi(v inVDAC).Therefore,VBLi<VBLwilloccurifv inVDAC>VLiandVBLi>VBLifv inVDAC

<VLi.ThustheCLicomparatoroutputsgiveathermometer

Page277

Figure7.20
(a)Mostsignificantautozeroingcomparator(b)leastsignificant
autozeroingcomparator(c)A/Dtimingdiagram.

Page278

coderepresentationofv inVDAC,asrequired(Fig.7.18).Byrecordingtheseoutputs,thethreeLSBsoftheoutputwordareobtained.Thesecanthenbecombined
withthethreeMSBsstoredintheclockedlatchestoobtainthedigitaloutputoftheADC.Itshouldbenotedthatv inisacquiredbytheinputcapacitorsC1ofall
comparatorsatthesametime,when 2=1.Thisgenerallymakesuseofaninputsampleandholdstageunnecessary.
SeveralalternativevariationsofthetwostepflashA/Dconvertersareavailable[10,11].OnearchitecturethatavoidsanalogsubtractionsorDACsistheintermeshed
laddersubrangingarchitecture.ThecentralfeatureofthisapproachisshowninFig.7.21.Itisanintermeshed"coarsefine"resistornetworkthatprovidestheMSB
andLSBreferencelevelsagainstwhichtheinputistested.Asintheconventionalarchitectureforan(N+M)bitA/Dconverter,thecoarseMSBstringhas2Nlow
resistancesections.Ahigherresistance"fine"resistorstringisintermeshed(paral

Figure7.21
Intermeshedresistorsegmentnetwork.

Page279

Figure7.22
BlockdiagramofCMOSsubrangingADCusingintermeshed
resistorstringnetwork.

leledacross)eachcoarseresistorRCeachofthe2Nfinesectionsistappedat2M1nodes.Asbefore,thesystemneeds2Ncoarsecomparators(oneextrafor
overflow)and2M1fineones.
Implementationofa4bitADCexamplewherethesystemissplitintotwo2bitquantizersisshowninFig.7.22.Fourcomparatorsareconnectedtothetapsofthe
"coarse"segment,whilethethree"fine"comparatorsareaddressedbyablockselectionlogicthatobtainsitsinformationfromthecoarsequantizer.Atwophase
clockwiththetimingshowninFig.7.20canbeusedfortheconversion.Asbefore,during 1=1thecoarsecomparatorsareautozeroedanditsinputcapacitorsare

Page280

chargedtothecoarsereferencevoltages.During 2=1,thefinecomparatorsareautozeroedandtheinputcapacitorsofbothfineandcoarsecomparatorsare
connectedtotheinputvoltage.Attheendofphase2,theoutputsofthecoarsecomparatorsarelatched,andtheinputvoltageissampledontheinputcapacitorsof
thefinecomparators.Thecoarsequantizationdeterminesthetwolevelsbetweenwhichthefinequantizationmusttakeplace.Afterdecodingthethermometercode
fromtheoutputsofthecoarsecomparators,ablockselectionisperformedandthefinereferencelevelsbetweenthepreviouslydeterminedcoarselevelsareapplied
totheinputcapacitorsofthefinecomparators.Thenthefineconversionisperformed.Noticethatduringphase1,whilethefinecomparatorsareperformingthefine
conversion,thecoarsecomparatorsareautozeroedandtheirinputcapacitorsarerechargedtothecoarsereferencevoltages.

Figure7.23
(a)Threestageautozeroingcomparatorstage
(b)timingdiagramoftheconversionprocess.

Page281

Figure7.24
Fourbittwostepflashconverter.

Ifthreeclockcyclesareavailableduringaconversionperiod,thethreeinputautozeroingcomparatorshowninFig.7.23acanbeused.Thisallowssharingofthe
coarseandfinecomparators.Atwostep4bitflashA/DconverterthatusesfoursuchcomparatorsisshowninFig.7.24.Thetimingdiagramoftheconversion
processisshowninFig.7.23b.Duringthefirstclockperiod( 1=1)thecomparatorsareautozeroedandtheinputsignalissampledandstoredontheinput
capacitors.Aftercompletionofthissamplingcycle,duringthe 2=1periodacoarsecomparisonisperformedwiththefourreferencevoltagesequallyspaced
betweenVrefandground.Thecomparatorsproduceacoarsethermometercode,whichisdecodedtoproducethetwooutputMSBs.Theoutputoftheencoderis
alsousedtoselecttheproperfineresistornetwork.Next,while 3=1thethreefinevoltagetapsbetweenthepreviouslydeterminedcoarselevelsareappliedtothe
samecomparatorsandfineconversionisperformed.Finally,thetwonewlyobtainedLSBsandthestoredMSBdataarecombinedtoobtainthe4bitoutputdata.
Oneofthemajoradvantagesofthisarchitectureandtheprecedingoneistheassuredmonotonicity,sincethesamecircuitrealizesthefineandcoarseresistorstrings.

Page282

7.5
SuccessiveApproximationA/DConverters
SuccessiveapproximationisoneofthemostpopularA/Dconversiontechniques,becauseitoffersthecombinationofhighaccuracyandmoderateconversionspeed.
Itisafeedbackschemethatusesatrialanderrortechniquetoapproximateeachanalogsamplewithacorrespondingdigitalword.InFig.7.25,thebasicblock
diagramofsuchasystemisshown.ItcontainsasampleandholdstageaswellasaD/Aconverter,asuccessiveapproximationregister(SAR),andavoltage
comparator.ThesuccessiveapproximationregisterforanNbitA/DconvertercontainsanNbitpresentableregisterthatisclearedpriortothestartoftheconversion
process.Theregisterbitsaresetoneatatimetoahighstate1andproduceaninputtotheNbitdigitaltoanalogconverter.TheoutputoftheDACiscomparedto
theanaloginputvoltage,andadecisionismadetokeepthelastbithighorreturnittozero.Inthefirststepoftheconversion,theMSBoftheSARissettoahigh
state(b1=1).TheMSBDACvoltageVDAC=VFS/2(whereVFSisthefullscalevoltage)issubstractedfromtheanaloginputvoltage.Iftheremainder ispositive,the
MSBremainshigh(b1=1)fortherestoftheconversionperiod.Iftheerrorsignalisnegative,theMSBisreturnedtozero(b1=0)andremainszerofortherestofthe
conversionprocess.Inthenextclockcyclethenextmostsignificantbitoftheregisterissethigh(b2=1)andtheDACoutputvoltageVDAC=(b1VFS/2+b2VFS/4)is
subtractedfromtheinputvoltage.Again,iftheremaindersignalispositive,b2remainsset(b2=1)otherwise,itreturnstozero(b2=0).Thisprocesscontinuesfor
eachsuccessivebitoftheSARforNclockcyclestocompletetheconversionprocessforoneanalogsample.Ineachcycle,iftheerrorsignalispositive,thebit

Figure7.25
BlockdiagramofanNbitsuccessiveapproximationA/Dconverter.

Page283

Figure7.26
Decisionsequencefora3bitsuccessiveapproximationA/Dconverter.

stayshighotherwise,itisreturnedtozero.Thedigitaloutput,whichcorrespondstothedataintheSAR,isnotvaliduntiltheentireconversioncycleiscompletedand
allbits(MSBthroughLSB)havebeenevaluated.Thedecisionsequencefora3bitsuccessiveapproximationA/DconverterisshowninFig.7.26.The
correspondinginputvoltage,thesequentialoutputoftheDAC,andtheremaindersignalareshowninFig.7.27.
SuccessiveapproximationA/Dconversiontechniquesrequireanalogcomparators,digitallogic,andprecisionanalogcomponents.Anumberofuniquearchitec

Page284

Figure7.27
RemainderandDACvoltagetimingdiagramofa4bit
successiveapproximationA/Dconverter.

tureshavebeendevelopedforsuccessiveapproximationA/DconvertersinCMOStechnologies.Themostpopularamongthesearethechargeredistribution
capacitorcircuit,theresisterstringcircuit,andresistorcapacitor(hybrid)circuit.
IfcapacitorsareusedastheprecisioncomponentsandMOSdevicesasswitches,onecanusechargeratherthancurrentorvoltagetorepresentanalogsignalsinside
theconverter.Thistechnique,referredtoaschargeredistribution,hasbeenusedtoimplementmonolithicA/Dconvertersformanyyears[12].Aconceptual5bit
versionofachargeredistributionA/DconverterisshowninFig.7.28a.Itconsistsofacomparator,a5bitbinaryweightedcapacitorarray(plusoneadditional
capacitorofaweightcorrespondingtotheleastsignificantbit),andMOSswitchesthatconnectthebottomplatesofthecapacitorstodifferentvoltages.The
comparatorisbasicallyaninvertinghighgaindifferentialamplifierwithoutfeedback.Itsoutputisthusnormallylatchedtopositiveornegativesupply,dependingon
whetheritsinputvoltageisnegativeorpositive.TheoperationoftheADCisperformedinthreephases.Inthefirst,S0isclosedandthebottomplatesofallcapacitors
areconnectedtov in.Thisresultsinachargeproportionaltov instoredinallcapacitors.Inthesecondphase,S0isopenedandallbottomplatesarethengrounded(Fig.
7.28b).Thiscausesthetopplatepotentialtobecomev in.Inthefinalphase,thebitsofthedigitaloutputarefoundonebyone.Tofindthemostsignificantbit(MSB)
b1,S7andS1switchthebottomplateofthelargestcapacitor(C)toVref(Fig.7.28c).ThetopplatepotentialVxisnowraisedtov in+Vref/2.Ifv in>Vref/2,thisvalue
willbelessthan0.Therefore,thecomparatoroutputwillbepositive,correspondingtoalogic1,andthiswillbethevalueassignedtob1otherwise,b1=0.Next,S1

Page285

Figure7.28
Successiveapproximationanalogtodigitalconverter:(a)conceptualcircuit
diagram,showninthefirst(sample)stageofoperation(b)circuitinthesecond
(hold)stage(c)approximationstage(d)finalconfigurationforthe
output01001.(FromRef.12,1975IEEE.)

willreturntogroundifb1=0(orstayatVrefifb1=1),andS2willbeswitchedtoVref.Thevalueofv xthenbecomes

ascaneasilybeshown(Problem7.5).Ifv x>0,b2willbeassignedthevalueof0,andS2willreturntoground:otherwise,b2=1andS2willstayatVref.Next,b3,b4,
andb5arefoundinasimilarmanner.Figure7.28dshowsthefinalpositionsofS1toS5afterobtainingthedigitaloutput01001.
ThecircuitdescribedrepresentsthebasicconceptoftheADC.Oneofthefactors

Page286

ignoredistheoffsetvoltageofthecomparator.Thiscanbegreatlyreducedbyusingoffsetcompensation(autozeroing)circuits.Figure7.29illustratesthebasic
concept.WhenS1isclosedandS2grounded,thecapacitorCischargeduptotheoffsetvoltageVoff.Theoutputv outofthecomparatorwillbehighifv x<Voffandlow
ifv x>Vofftheseconditionscorrespondtov outbeinghighifv in<0andlowifv in>0,asinanoffsetfreecomparator.Anothercompensationmethodisdescribedin
Problem7.7.
Comparatorsareoftenbuiltbycascadingseveralstages.Ifthegainofeachstageislow,severalstagesmayberequiredandthefeedbackpathprovidedbyS1may
leadtoinstability.ThenitismoreexpedienttoconnectS1toanintermediatestage(Fig.7.30).TheoffsetofA1iseliminatedbytheautozerocircuittheinputoffsetof
A2isnot,butwhenitisreferredbacktotheinputofA1,itgetsdividedbythegainofA1andhencegreatlyreduced(Problem7.7).Itisalsopossibletouseseparate
autozeroingcircuitsforthetwocircuits.
ThechargeredistributionA/DconverterofFig.7.28isapplicableforunipolar(e.g.,onlypositive)inputsignals.Aslightlymodifiedversionofthisstructure,shown

Page287

Figure7.29
Comparatoroffsetcancellationbyautozeroing.

inFig.7.31,canbeusedforbipolar(positiveornegative)inputs.Theswitchingsequencehasbeenalteredtoincorporateasignbitdetectioncycle.Thisarchitecture
needs+VrefforpositiveinputsandVreffornegativeinputs.
Thesignbitisdetectedduringthesecondphase,whenthetopplategroundingswitchS0isopenedandthebottomplatesofthecapacitorsareconnectedtoground
byS1toS8.Theoutputofthecomparatorcorrespondstothepolarityofv in,thetopplatevoltageofthecapacitorarray.Attheendofthesecondphase,the
comparatoroutputisstoredinaclockedlatch.Itrepresentsthesignoftheanalogsample.Next,thissignbitisusedtoswitchtheVref,withtheappropriatepolarityto
thebottomplatesofthecapacitorarrayusingS7andS9.Thereferencevoltageisusedsubsequentlyduringtheredistributioncycletodeterminethebitsofthedigital
wordcorrespondingtothemagnitudeoftheinput.
The5bitchargeredistributionA/DconverterofFig.7.31alsocontainsacapacitorC/32thathasaweightofLSB.Withoutthiscapacitor,theA/Dtransfercurve
aroundzerowouldhaveadiscontinuitysimilartothatshowninFig.7.32a.ThisproblemisremediedbyswitchingthecapacitorC/32fromgroundtothereference
voltageafterthesignbitisdetermined.Thisactionwillcausethetopplatevoltageofthecapacitorarraytochangefromk vinto(v in+Vref/64)k,wherek=1/(1+
1/64+Cp/2C)andCpistheparasiticcapacitancefromthecomparatorinput

Figure7.30
Reductionininputoffsetvoltagebycapacitive
storageforamultistagecomparator.

Page288

Figure7.31
FivebitsignedchargeredistributionA/Dconverter.

toground.ThisisequivalenttoshiftingtheinputvoltagebyLSB,and(asshowninFig.7.32b),iteliminatesthediscontinuityoftheA/Dtransfercurvearoundzero.
Highperformancedataacquisitioncircuitsmakeuseofafullydifferentialarchitecture.Themainmotivationistorejectthenoisefromthesubstrateaswellasfromthe
powersupplylines.FullydifferentialchargeredistributionA/Dconvertersuseafullydifferentialcomparator,twobinaryweightedcapacitorarrays,andapositiveand
negativevoltagereference.Afullydifferential5bitplussignchargeredistributionA/DconverterisshowninFig.7.33[13].Therearetwo5bitbinaryweighted
capacitorarrays.Theconversionprocessissimilartothesingleendedcaseitisperformedinthreephases:thesamplingphase,theholdandsignbitdetermination
phase,andtheconversionphase.Asbefore,twoadditionalcapacitorswithweightingsequaltoLSBmustbeaddedtothetwocapacitorarraystoeliminatethe
conversiondiscontinuityaroundzero.
TheresistorstringbasedA/DconverterstructureconsistsofavoltageoutputDAC,acomparator,andasuccessiveapproximationregister.ForanNbitsystem,the
DACcontainsastringof2Nresistorsconnectedinseriesandaswitchingmatrix.A3bitversionofaunipolarresistorstringA/DconverterisshowninFig.7.34[14].
Thestringofeightresistorsactsasavoltagedivider,andthevoltageatanytapinthestringisoneLSBvoltagehigherthanthevoltageatthetapbelowit.Thevoltage
ateachtapdefinesatransitionleveloftheA/Dconverter.ThebottomresistorischosentobeR/2andthetopresistoras3R/2,sothatthedecisionlevelsareshiftedto
themidpointoftwoadjacenttransitionlevels.ThecomparatorusesanoffsetcancelingcapacitorC,whichalsoactsasasampleandholdstage.
Theconversionisagainaccomplishedinthreesteps.Inthefirst(sampling)step, 1goeshigh,andthecomparatorenterstheoffsetcancellationmodebyclosingthe

Page289

Figure7.32
A/Dtransfercurve:(a)withoutcapacitor
(b)withcapacitorC/32.

MOSswitchS0betweenthecomparatoroutputanditsinvertinginput.DuringthisphasetheMOSswitchS1isalsoturnedon,andthesamplingcapacitorCishence
chargedbetweentheoffsetvoltageVoffofthecomparatorandtheinputsignal.When 1goeslow,bothswitchesS0andS1turnoffandtheinputsignalisheldacross
capacitorC.Also,thefeedbackpathacrossthecomparatorisopened.Duringthe

Page290

Figure7.33
FivebitchargeredistributionfullydifferentialA/Dconverter.

subsequentholdcycle, 2goeshighandthecapacitorisconnectedtotheoutputoftheDAC.Thevoltageattheinputofthecomparatorthusbecomes

HereVbrepresentsanappropriatebiasvoltage,normallymidwaybetweenthepositivesupplyandground,connectedtothepositiveinputofthecomparator.During
thethirdphase,theusualsuccessiveapproximationsearchisperformedbyplacingatrialvalue1intheMSBpositionandmakingadecisionbyexaminingthestate

Page291

Figure7.34
Conceptualdiagramofaunipolar3bitsuccessiveapproximation
resistorstringA/Dconverter.

ofthecomparatoroutput.Forexample,inthefirststepwhenb1=1andb2=b3=0,switchesS3,S6,andS12closeandthevoltageatnodeAoftheresistorstringis
appliedtothecapacitorC.FromEq.(7.10),voltagev xisnowgivenby

v xisnextcomparedtothevoltageonthepositiveinputofthecomparatorgivenbyVoff+Vb.Ifv inisgreaterthan7/16Vreftheoutputofthecomparatorgoeshighand
thebitb1remains1.However,ifv inislessthan7/16Vreftheoutputofthecomparatorgoeslowandthebitb1ischangedto0.Thisprocessisthenrepeatedin
descendingsequenceforeachofthelessersignificantbits.
Sincethevoltageatanygivennodeoftheresisterstringisalwaysgreaterthanthevoltageatthenodebelowit,theD/Aconverterisinherentlymonotonic,andtheA/D
converterwillhavenomissingcodes.ForhigherresolutionA/Dconverters,thefoldedresisterladderstringDACdescribedinChapter6canbeusedtosimplifyand
improvetheperformanceofthecircuit.
AsthebitcountNoftheA/Dconverterisincreased,thecomplexityofthesimpleresistorstringorchargeredistributionA/Dconvertersincreasesrapidly.For

Page292

Figure7.35
Successiveapproximationhybrid8bitA/Dconverterwithsign.

example,foranNbitconverter,2Nresistorsorcapacitorswillbeneeded.Majorsimplificationsbecomepossibleifoneuseshybridarchitecturesbycombiningthe
resisterstringtechniqueswiththechargeredistributionmethods[15,16].Anexampleofan8bit(7bitplussign)hybridsuccessiveapproximationbipolarA/D
converterisshowninFig.7.35.Itcontainsa4bitbinaryweightedcapacitorarrayfortheMSBsanda3bitresistorstringforthesteps.Theconversionisagain
performedinthreephases.Inthefirst(sampleandautozero)phase,switchS0inthefeedbackofthecomparatorisclosedandswitchesS2toS6connectthebottom
platesofthecapacitorstotheinputvoltagethroughswitchS1.Thusthecapacitorsarechargedtov inVoffwhereVoffistheoffsetvoltageofthecomparator.Inthe
second(holdandsigndetermination)phase,S0isopenedandthebottomplatesofallcapacitorsandconnectedtoground.Thiswillcausev x,thevoltageonthetop
plateofthecapacitors,tochargetov in+Voff.Theoutputstateofthecapacitornowrepresents

Page293

thepolarityoftheinputsample.AttheendofthesecondstepthestateofthecomparatoroutputislatchedanditisusedtocontrolswitchS7,whichsuppliesthe
referencevoltagewiththecorrectpolaritytothecapacitorarrayandtotheresisterstring.Inthethirdstepasuccessiveapproximationsearchisperformedtofindthe
7bits.First,thebottomplateofcapacitorC/8isswitchedtothepointontheresistorstringthatcorrespondstoVref/16.Thisineffectshiftsthetopplatevoltageby
LSBtov in+Voff+Vref/512,whichisnecessarytomaintaincontinuityaroundzero.Next,thefourMSBsaredeterminedinthecapacitiveDAC,oneatatime,by
settingthebitstoabinary1stateandexaminingthestateofthecomparatoroutput.Finally,thethreeLSBsaredeterminedbyswitchingthebottomplateofcapacitor
C/8totheoutputoftheresistiveD/Aconverterandperformingasuccessiveapproximationsearchtofindthecorrecttapvoltageontheresistorstring,whichresets
thetopplatevoltagetozero(withinLSB).Duringthiscycle,thetopplatevoltageisgivenby

Thetotalconversiontakesninecycles:onecycletosampletheinputandautozerothecomparator,onecycletodeterminethesignbit,andsevencyclestodetermine
the7bits.
TheaccuracyoftheA/DconverterofFig.7.35isdeterminedlargelybythematchingaccuracyofthecapacitors.Sincemonotonicitycannotbeguaranteedforbinary
weightedcapacitorarrays,theA/Dstructureisnotinherentlymonotonic.AnalternativearchitectureforahybridA/DconverterthatusesaresistorDACforthe
MSBsandacapacitorarrayfortheLSBsisshowninFig.7.36[16].Operationofthecircuitisagainperformedinthreephases.Inthefirstphase,SFisclosedandthe
bottomplatesofallcapacitorsareconnectedtov in.Thusallcapacitorsarechargedtov inVoff,whereVoffistheoffset(threshold)voltageofthecomparator.Next,SF
isopenedandasearchisperformedamongtheresistorstringtapstofindthesegmentwithinwhichthisstoredvoltagesamplelies.NodesAandBarethenswitched
totheterminalsoftheresistorRithatdefinesthissegment.Inthefinalstage,thebottomplatesofCk+1,Ck,...,C1areswitchedsuccessivelybackandforthbetween
AandBuntiltheinputvoltageofthecomparatorconvergestoVoff.Thesequenceofcomparatoroutputsduringthesuccessiveapproximationsgivesthebinarycode
forv in.DuetothefirststepinwhichVoffwassubtractedfromv in,theoffsetvoltageofthecomparatordoesnotaffectitsoutput.SincetheresistorstringDACis
inherentlymonotonic,aslongasthecapacitorarrayismonotonic,theA/Dconverterwillalsobemonotonicandtherewillbenomissingcodes.
ThesuccessiveapproximationA/Dconversiontechniquesusingsinglearraysofcapacitorsorresistorsaresuitableforupto10bitsofresolution.Thecapacitive
chargeredistributiontechniqueexhibitsexcellenttemperaturestabilityduetotheverylowtemperaturecoefficientofMOScapacitors.Typicalconversiontimesfor8
to10bitresolutionareintherange10to40s.Thehybridtechniqueusingacombinationofresistorsandcapacitorscaneasilybeextendedtoresolutionsgreater

Page294

Figure7.36
SuccessiveapproximationhybridADC.
(FromRef.16,1979IEEE.)

than16bits.Unlessselfcalibrationisusedforhighaccuracy[17],typicalcapacitorandresistormatchingcanguaranteeupto10bitlinearitybyfollowingcareful
layouttechniques.
7.6
CountingandTrackingA/DConverters
CountingandtrackingA/Dconvertersarethetwomainclassesofdigitalrampconverters.TheycontainabinarydigitalcounterandaD/Aconverterinafeedback
looparoundavoltagecomparator.Figure7.37showstheblockdiagramofacountingA/Dconverter.Inthissystem,adigitalrampinputisappliedtoaD/A
converter.TheanalogoutputoftheDACisthencomparedwiththeanaloginput.Ineachconversionstep,firstthecounterisclearedandthenitstartscountingthe
inputpulses.TheoutputofthedigitalcounterisappliedtotheD/Aconverter,whichcreatesastaircaseanalogoutputsignal.ThecountingcontinuesuntiltheD/A
outputexceedstheinputvalue.Atthispoint,theoutputofthedigitalcounteristherequiredoutputwordandisdumpedintoastorageregister.Thecounteris
subsequentlycleared,andthecircuitisreadytoperformthenextconversion.Althoughquitesimpleinconcept,thisconverter,hasthedisadvantageofbeingverylow
speedforagivenresolution.Also,theconversiontimeisfunctionoftheanaloginputsignallevel.ForanNbitconverterandaclockperiodofT,theconversiontime
forafullscaleinputisequaltoTc=2NT.Forexample,forN=12and1/T=10MHz,themaximuminputsamplerateisFc=2441Hz,verylow.

Page295

Figure7.37
FunctionalblockdiagramofacountingA/Dconverter.

AnalternativeformofthecountingA/Dconverteristhetrackingorservoconverter,whichisrealizedbyreplacingthesimpleunipolardigitalcounterofthesystem
showninFig.7.37withanupdowncounter.Inthisconverter,iftheinputvoltageishigherthantheoutputoftheD/Aconverter,thecountercountsup.Conversely,if
theinputvoltageislowerthantheD/Aoutput,thecountercountsdown.TheanalogoutputoftheD/Aconverteriscomparedcontinuouslywiththeanaloginput.The
endoftheconversionoccursattheclockperiodimmediatelyfollowingachangeinthestateofthecomparator,atwhichpointthecounterstopscountinganditsstate
isdumpedintoanoutputregister.UnlikethecountingA/Dconverterdiscussedpreviously,thecounterdoesnotgetclearedatthebeginningofaconversioncycle.
Instead,itretainsthepreviouscountanditcountsupordownfromtherebasedonthepolarityoftheerrorsignalandtheoutputofthecomparator.Theconversionis
againcompletewhentheoutputoftheD/Areachestheinputsignallevelandthecomparatorchangesstate.
Ifthedifferencebetweentwoconsecutiveinputsamplesislarge,closetofullscale,theconversiontimeforthetrackingA/Dconverterisquiteslow,similartothe
countingconverter,whichisontheorderof2Nclockcycles.However,forslowlyvaryinginputsignals(i.e.,forhighlyoversampledsignals),theconversiontimecan
bequitefastandthedigitaloutputcantracktheanaloginputsignalwithinafewclockcycles.ItisthispropertyoftheseA/Dconvertersthatgaverisetotheadjectives
trackingorservo.
7.7
IntegratingA/DConverters[18,20]
IntegratingA/Dconvertersareusedwhenhighaccuracyisneededandlowconversionspeedisacceptable.InintegratingtypehighresolutionA/Dconverters,an
indi

Page296

rectconversionisperformedbyfirstconvertingtheanaloginputsignaltoatimeintervalwhosedurationisproportionaltotheinputsignalandthenconvertingthetime
durationintoadigitalnumberusinganaccurateclockandadigitalcounter.Theconversiontimeisslowbecauseofthelengthycountingoperationduringthetimeto
digitalconversioncycle.SingleanddualrampADCsareexamplesofintegratingA/Dconverters.ThedualrampADCisspeciallysuitablefordigitalvoltmeter
applications,wheretherelativelylongconversiontimeprovidesthebenefitofreducednoiseduetosignalaveraging.
AsingleslopeintegratingA/DconverterisshowninFig.7.38a.Thecircuitconsistsofanintegratorwitharesetablefeedbackcapacitor,acomparator,adigital
counter,andcontrollogic.Theintegratorgeneratestheaccuratereferencerampsignal.Figure7.38bshowsthetimingwaveformsassociatedtoaconversioncycle.
Priortostartingtheconversioncycle,thedigitalcounterisresettozeroandthefeedbackcapacitoroftheintegratorisdischargedbyclosingtheswitchSF.Atthe
momenttheconversionstarts,theswitchSFisopened,theinputsignalv inisappliedtothenoninvertinginputofthecomparator,andtheintegratorstartsgeneratingthe
rampfunctionappliedtotheinvertinginput.Inthemeantime,thecontrollogicenablesthedigitalcounter,whichstartscountingtheclockpulses.Thecountercontinues
countingtheclockpulses,andthecountaccumulatesuntiltherampvoltagereachestheanaloginputlevelv in.Atthistimethe

Figure7.38
(a)BasicstructureofasingleslopeA/Dconverter(b)timingwaveforms.

Page297

comparatorchangesstate,stopsthecounter,andterminatestheconversioncycle.Thisprocessconvertstheanaloginputleveltoatimeintervaldurationthatis
obtainedbycountingtheinputclockpulses.IfVrefrepresentthenegativereferencevoltageandRCthetimeconstantoftheintegrator,thetimet 1neededfortheramp
toreachtheinputsignallevelis

Page298

Thetimet 1asafunctionoftheinputclockperiodandtheaccumulatedcountnisgivenby

Ofcourse,nmustbeanintegernumber,thenearesttot 1/Tc.ForNbitresolution,thefullscalemustbeatleastnF=2N,andforagiveninputlevelv in,theaccumulated

countninthecounteris

Thusnisthequantizedvalueanddigitalrepresentationoftheinputsignal.TheaccuracyoftheconverterisafunctionofthetimeconstantRC,thereferencevoltage
Vref,andtheclockperiod.
SeveralnonidealeffectsareassociatedwiththebasicsingleslopeA/DconverterofFig.7.38.Theseincludetheoffsetvoltageoftheintegratoropampand
comparator,theinaccuraciesassociatedwiththeinitialrampstartuppoint,andtheaccuracyofthereferencevoltageandRCtimeconstant.Improvedcircuit
techniquescanbeusedtoavoidtheseproblems.Onesuchcircuittechniqueusestheprincipleofdualslopeintegration.Thisisoneofthemostpopulartechniquesfor
highaccuracyA/Dconvertersandhasbeenusedextensivelyinpractice.
ThebasicblockdiagramofthedualslopeconverterisshowninFig.7.39a,togetherwiththeintegrator'soutputvoltagewaveform.Thistypeofconverteroffersa
significantadvantageoverthesingleslopeconvertersinthattheconversionscalefactorwillbeindependentoftheintegratortimeconstantandoftheclockfrequency.
Theoperationofthesystemisasfollows.Priortostartingtheconversion,theswitchSFisclosed,dischargingtheintegratingcapacitorC.Atthesametime,thecounter
isresetandtheswitchS1connectstheinputoftheintegratortotheinputvoltage.Atthebeginningoftheconversion,switchSFisopenedandatthesametimethe
counterstartscountingclockpulses.Theintegratorstartsfromaresetstateandintegratestheinputvoltageforapredeterminedperiodoftime,normallyequalto2N
clockcycles,whichcorrespondstothefullcountofthecounter.Attheendofthefirstphase,thevoltageattheoutputoftheintegratorisgivenby

whereTCistheclockperiodofthecounterandNintheresolutionoftheA/Dconverterinbits.
InthesecondphasethecounterisresettozeroandtheinputoftheintegratorisswitchedtoareferencevoltageVrefwhichhastheoppositepolaritywithrespectto
theinputsignal.Theintegratoroutputisnowrampingdownwhilethecounteragaincountstheclockpulsesstartingfromzero.Whentheintegratoroutputreaches

Page299

Figure7.39
(a)BasicblockdiagramofdualslopeA/Dconverter(b)integratoroutputwaveform.

zero,thecomparatorstopsthecounter.Thecountercontentnisthenstoredinalatch.Sinceinthesecondphasetheintegratordischargesfromitsinitialvoltagev oto
zeroinaperiodt 2=nTC,t 2isgivenby

Page300

Combiningeqs.(7.16)and(7.17),wehave

Therefore,thecountstoredinthedigitalcounterattheendofphase2isthedigitalequivalentoftheanaloginput.
Figure7.39bshowstheoutputwaveformoftheintegratorduringphases1and2.Asnotedearlier,thedurationofphase1isfixedat2NTC,whiletheintegratoroutput
slopevarieswiththemagnitudeoftheinputsignal.Thedurationofphase2,however,isvariable,andtherampslopeisaconstantdeterminedbythefixedvalueofthe
referencevoltage.
ThedualslopeA/Dconverterhasseveraladvantagesoverthesingleslopeconverter.Theaccuracyisindependentofclockfrequencyandtheintegratortimeconstant
RCbecausetheyaffecttheupanddownrampvoltagesinthesameway.Thedifferentiallinearityisexcellent,becausethedigitalcountergeneratesallcodesandall
codesareinherentlypresent.Theintegrationprovidesarejectionofhighfrequencynoiseandnoisecoupledthroughthepowersupplies.Forexample,ifonewishesto
rejectaspecificfrequency,suchas60Hzanditsharmonics,theintegrationtimeshouldbe16.67ms,whichsetsanupperlimitof30Hzontheconversionrate.This
makesthedualslopeA/Dconvertersuitableforhighaccuracyapplicationswithlowconversionrates.
ThebasicdualslopeconvertershowninFig.7.39hasamajorshortcoming:Itissensitivetothecomparatorandoperationalamplifieroffsetvoltages,whichshowup
aserrorsintheoutputdigitalword.Introducingautozeroingphasesintotheconversioncyclecanreducetheeffectoftheseerrors[19].Usingthesetechniques,
multipleslopeintegratingA/Dconverterscanbeusedinthe12to14bitresolutionandlinearityrange.
Problems
7.1.Foraunipolar10bitA/Dconverter,ifv in=2.376VandVref=5V,determinethedigitaloutputcodeandthequantizationerror.
7.2.Designa4bitflashA/DconvertersimilartotheoneshowninFig.7.12.Designthedecoderlogicforthe4bitdigitaloutputcode.
7.3.ForthetwostageautozeroedcomparatorofFig.7.14a,drawthetimingwaveformsattheoutputofthefirst,second,andthirdinverters,basedonthetiming
showninFig.7.14b.Assumethatv in=1VandVref=1.1V.
7.4.ProveEq.(7.8)forthecomparatorofFig.7.20.
7.5.ByanalyzingthecircuitofFig.7.28afivetimes,calculatethevaluesv xinthefiveconversioncyclesofv in=0.7Vref.

Page301

Figure7.40
Comparatoroffseteliminationmethod(forProblem7.7).

7.6.AnalyzetheeffectsofthestraycapacitancesCstandCsbbetweenthetopandbottomplatesofthecapacitorsandgroundinFig.7.28aonthedigitaloutput.
7.7.ThecircuitofFig.7.40canbeusedtoeliminatetheeffectofthecomparatoroffsetvoltageintheD/AconverterofFig.6.28a.Analyzetheoperationofthe
circuit.Findtheinputreferredoffsetvoltage.
7.8.Forthehybrid8bitA/DconverterofFig.7.35,drawthetimingwaveformsofthesuccessiveapproximation.Includethesamplingphaseandeightconsecutive
cycles.Assumethat|Vref|=5Vandv in=3.1V.Findthedigitaloutputcode.
7.9.FortheNbitresistivestringA/DconverterofFig.7.34,findanexpressionforthenumberofswitchesasafunctionofN.
7.10.Forthe16bitsingleslopeA/DconverterofFig.7.38a,whatistheworstcaseconversiontimeiftheclockfrequencyis2MHz?
7.11.RepeatProblem7.10forthedualslopeA/DconverterofFig.3.39a.
7.12.Forthe16bitA/DconverterofFig.7.38a,determinetheintegratingresistorRsothattheoutputoftheintegratorneverexceeds5V.Assumethat0<v in<5
V,Vref=5V,C=100pF,andtheclockrateis2MHz.
References
1.J.G.Peterson,IEEEJ.SolidStateCircuits,SC14(6),932937(1979).
2.C.W.Mangelsdorf,IEEEJ.SolidStateCircuits,SC25(1),184191(1990).
3.A.G.F.Dingwell,IEEEJ.SolidStateCircuits,SC14(6),926932(1979).
4.R.VandePlassche,IntegratedAnalogtoDigitalandDigitaltoAnalogConverters,KluwerAcademicPublishers,Dordrecht,TheNetherlands,1994.

Page302

5.J.Caruso,ActiveanalogaveragingcircuitandADCusingsame,U.S.patent5,298,814,Mar.29,1994.
6.N.Fukushima,T.Yamada,N.Kumazawa,Y.Hasegawa,andM.Soneda,ISSCCDig.Tech.Pap.,pp.1415,Feb.1989.
7.M.IshikawaandT.Tsukahara,ISSCCDig.Tech.Pap.,pp.1213,Feb.1989.
8.T.Shimizu,M.Hatto,andK.Maio,ISSCCDig.Tech.Pap.,pp.224225,Feb.1988.
9.R.J.VanDePlasscheandR.E.VanDeGrift,IEEEJ.SolidStateCircuits,SC14(6),938943(1979).
10.A.G.F.DingwallandV.Zazzu,IEEEJ.SolidStateCircuits,SC20(6),11381143(1985).
11.T.Sekino,ISSCCDig.Tech.Pap.,pp.4647,Feb.1981.
12.J.L.McCrearyandP.R.Gray.IEEEJ.SolidStateCircuits,SC10(6),371379(1975).
13.C.C.Shih,K.K.Lam,K.L.Lee,andR.W.Schalk,IEEEJ.SolidStateCircuits,SC22(6),990995(1987).
14.A.R.Hamad,IEEEJ.SolidStateCircuits,SC13(6),785791(1978).
15.T.P.Redfern,J.J.Connolly,Jr.,S.W.Chin,andT.M.Fredriksen,IEEEJ.SolidStateCircuits,SC14(6),912920(1979).
16.B.FotouhiandD.A.Hodges,IEEEJ.SolidStateCircuits,SC14(6),920926(1979).
17.H.S.Lee,D.A.Hodges,andP.R.Gray,IEEEJ.SolidStateCircuits,SC19(6),813819(1984).
18.D.H.Sheingold,AnalogDigitalConversionNotes,AnalogDevices,Norwood,Mass.,1977.
19.F.H.MuseandR.C.Huntington,ACMOSMonolithic3digitA/DconverterISSCCDig.Tech.Pap.,pp.144145,1976.
20.A.B.Grebene,BipolarandMOSAnalogIntegratedCircuitDesign,Wiley,NewYork,1984.

Page303

Chapter8
PracticalConsiderationsandDesignExamples
ThedesignoflowcostandhighperformancemixedsignalVLSIsystemsrequirescompactandpowerefficientanaloganddigitallibrarycells.Whilethedigitallibrary
cellsbenefitfromdownscalingoftheCMOSprocesstechnology,incontrast,analoglibrarycells,suchasopampsandcomparators,cannotbedesignedusing
minimumlengthcomponents,forreasonsofgain,dcoffsetvoltage,andotherfactors.Furthermore,thereductionofthepowersupplyvoltageinthetightergeometry
technologiesdoesnotnecessarilyresultinlowerpowerdissipationintheanalogcells,mainlybecauselowervoltageanalogcellsaremorecomplextodesignandthey
oftenrequirealargerquiescentcurrent.
InChapters4and5designtechniquesforhighperformanceCMOSopampsandcomparatorswerediscussedindetail.Inthischapterthedesignprinciples
presentedearlierinthebookareemployedtoworkoutseveraldesignexamplestoacquaintthereaderwiththeproblemsandtradeoffsinvolvedinopampand
comparatordesigns.PracticalconsiderationsinCMOSopampdesignsuchasdcbiasing,systematicoffsetvoltage,powersupply,andsubstratenoisecouplingare
discussedinsomedetail.
8.1
PracticalConsiderationsinCMOSOpAmpDesign
InSection4.1,severalnonidealeffects,whichcandegradetheperformanceofpracticalopamps,werelisted.Theminimizationoftheseeffectsisanimportantaspect
ofopampdesign.Thecorrespondingconsiderationsarediscussedbrieflynextforthemostimportantnonidealeffects.

Page304

Figure8.1
TwostageCMOSopamp.

1.FiniteGain.EarlierwediscussedtheavailablegainforvariousCMOSgainstagesandthespecialcircuitsthatmaybeutilized,suchascascodedevices,to
enhancethevoltagegainwithoutreducingthebandwidth.
2.FiniteLinearRange.Thisquestionwasalsodiscussedbrieflyandcircuitswereintroduced(see,e.g.,Figs.3.15and3.16)formaximizingtheallowablesignal
swing.
3.OffsetVoltage.AsdefinedinSection4.1,theinputreferredoffsetvoltagev in,offisthedifferentialinputvoltageneededtorestoretheoutputvoltagev outtozero.It
containstwocomponents:asystematicoffset,whichisduetoimproperdimensionsand/orbiasconditions,andarandomoffset,whichisduetotherandomerrors
inthefabricationprocess,resulting,forexample,inthemismatchofideallysymmetricaldevices.
Toillustratethegenerationofsystematicoffset(andwaystoavoidit),considerthesimpletwostageCMOSopampshowninFig.8.1.Thefirststate(Q1toQ5)isthe
differentialinput/singleendedoutputinputstageintroducedinFig.3.42theoutputstageisasingleendedgainstagewithadriverQ6andacurrentsourceloadQ7.
Clearly,ifthecircuithasnosystematicorrandomoffset,groundingbothinputterminals(asshown)resultsinv out=0.Theniftheoutputterminalisalsogrounded(as
showninFig.8.1),thecurrentIginthegroundingleadwillalsobezero.ThustheconditionforzerooffsetisequivalenttorequiringthatIg=0forgroundedinputand
outputterminalsthisinturnrequiresthatI6=I7.
Assumingsymmetryintheinputstage,(W/L)1=(W/L)2and(W/L)3=(W/L)4.Thenallcurrentsandvoltageswillalsobesymmetrical,andhenceVDS3=VDS4.Thenalso
VGS3=VGS6.IfthisvalueofVGS6resultsinI6beingequaltothesourcecurrentI7whenVDS6=0VDD=VDD,thenIg=

Page305

0,asrequired.Ifthisisnotthecase,thenIg 0andsystematicoffsetexists.Specifically,let
inputoffsetvoltageisclearly

denotethevalueofVGS6neededtomakeI6equaltoI7.Thenthe

whereAdisthevoltagegainoftheinputstage.Forexample,anerrorof0.1VinthebiasvoltageofQ6willresultina1mVinputoffsetifAd=100.
Assumingthatalldevicesareinsaturation,andneglectingchannellengthmodulationeffects,thevoltagesofQ3andQ4canbeexpressedas

HereVTpisthethresholdvoltageofthepchanneldevicesQ3andQ4,and istheconstanttransconductancefactorpCox/2ofthedraincurrentequationforPMOS
devices.Similarly,forQ6,

SubstitutingVGS6=VGS3andtherequiredconditionI6=I7intoEq.(8.3)yields

FromEqs.(8.2)and(8.4),thecondition

isobtainedforzerooffset.
TurningtoQ5andQ7,sincetheyhaveequalgatetosourcevoltages,neglectingchannellengthmodulation,weobtain

Combiningtheequationsabove,thedesignrelationsare

Page306

Physically,ifEq.(8.6)issatisfied,thecurrentI7inducedinQ7byitsgatetosourcevoltageVGS7andthecurrentI6inducedinQ6bythegatetosourcevoltageVGS6=
VDS4arethesame,andhencev out=0ispossiblewhenQ6andQ7areinsaturation.Ifthegatetosourcevoltagesarenotcompatibleandtheoutputterminalisopen
circuited,v outassumesanonzerovaluesuchthatthedrainvoltagesofQ6andQ7willcompensateforthediscrepanciesofthegatevoltages.ThismayalsoresultinQ6
orQ7operatingoutofsaturation.Itusuallyrepresentsamajorsystematicoffsetvoltageeffectandmayreducethegainandthebandwidthoftheopamp.
Tominimizetheeffectsofrandomprocessinducedchannellengthvariationsonthematchingofthedevices,andthustherandomoffset,thechannellengthsofQ3,Q4,
andQ6shouldbechosenequal.ThenthecurrentdensityId/WisthesameforthesedeviceswhenEq.(8.6)issatisfied,andtherequiredcurrentratiosaredetermined
bytheratiosofthewidths.Ifratiosaslargeas(orlargerthan)twoarerequired,thewidertransistorcanberealizedbytheparallelconnectionoftwo(ormore)''unit
transistors"ofthesizeofthenarrowerone.Note,however,thatthisprocessisinconflictwiththeguidelinesfortheminimizationofnoiseestablishedinSection4.7:
Accordingtothoserules,thetransconductancesoftheloaddevicesQ3andQ4shouldbelowwhilethatofQ6shouldbehighforhighgainandgoodhighfrequency
response.ThechannellengthsforallthreedevicesQ3,Q4,andQ6shouldbelongforhighoutputimpedanceandhighgain.WhilethishelpstoreducethenoiseofQ3
andQ4andincreasethegainofthedifferentialstage,itdecreasesthetransconductanceofQ6andhencereducesthegainofthesecondstage.Clearly,theoptimum
tradeoffamongtheseconflictingrequirementswillvaryfromapplicationtoapplication.
Therandomoffsetvoltagewillbeaffectedbyseveralfactors,includingmismatchbetweenthe(ideallysymmetrical)inputdevicesQ1andQ2and/orbetweentheload
devicesQ3andQ4.Thiscanbecausedeitherbygeometricalmismatchorbyaprocessgradientcausingdifferentthresholdvoltages.Assumefirstthatthecurrent
mirror(Q3Q4)isimperfect,sothat

Thedifferentialvoltagev G1v G2neededattheinputterminaltorestoresymmetryisclearly

Thusv off1canbereducedbyincreasingthetransconductancegmioftheinputdevicesorbyreducingthebiascurrentI0.
Assumenextthatthedimensionsandthethresholdvoltagesoftheinputdevicesaremismatchedwhiletheloaddevicesaresymmetrical.Thuslet

Page307

Clearly,itrequiresaninputoffsetvoltagev off2= VTtocanceltheeffectofthethresholdvoltagemismatch.Thegeometricmismatchcausesacurrentimbalance I1

2k 1(VGS1VT1)2.Thiscanbebalancedbyachangev off3inv G1suchthat

Here,weusedEq.(2.18)toexpressgmi,with 0.FromEq.(8.11),

Therefore,v off3canbereduced(ascouldv off1)byincreasing(W/L)1andthusgmiorbyreducingI0.BothwillreduceVGS1VT1.

Thevariationofthethresholdvoltage VTisindependentofI0orW/Litdependsonlyonprocessuniformity.ItcanbereducedbybuildingQ1andQ2fromunit
transistorsarrangedinacommoncentroidstructure[1,Chap.62].
4.CommonModeRejectionRatio(CMRR).AsdefinedinSection4.1,CMRR=AD/AC,whereADisthedifferentialgainandACisthecommonmodegain.Forthe
opampofFig.8.1,thecommonmoderejectionisprovidedbytheinputstage.ThevalueoftheCMRRforthisstagewasfoundearlierandwasgivenbyEq.(3.88)
as

AsexplainedinSection2.4,bothgmiandgmlareproportionalto
whileg0andgdiareproportionaltoI0.ThustherejectionratioisinverselyproportionaltoI0.
Valuesof103to104canreadilybeachieved,asEq.(8.13)shows.
IfamismatchexistsbetweenQ1andQ2suchthatgmi=(1+ )gm2,acommonmodevoltagev cwillcauseasmuchdifferentialoutputvoltageasadifferentialinput
voltage(gdi/gmi) v c(Problem8.1).ThusnowwehaveCMRR gmi/ gdi.Thisagainillustratestheimportanceofmakingtheinputdevicessymmetrical,using
commoncentroidgeometryifnecessary:A1%mismatchmaylowertheCMRRto60dB!
5.FrequencyResponse,SlewRate,Biasing,PowerDissipation.Therequirementsonthespeed(i.e.,highfrequencygainandslewrate)ofaCMOSamplifier
dependverymuchonitsapplication.Inswitchedcapacitorcircuits,mostopampsdrivecapacitiveloadsonly.Thespeedrequirementisthenthattheopampmustbe
abletochargetheloadcapacitanceCLandsettletowithinaspecifiedaccuracy(usually,0.1%ofthefinalvoltage)inaspecifiedtimeinterval.

Page308

Figure8.2
CMOSopampwithcapacitiveload.

Figure8.2showsthesimpleopampofFig.8.1supplementedbyafeedbackbranch(Q8,Cc)forcompensationanddrivingacapacitiveloadCL.Asexplainedin
Section4.6,theunitygainbandwidthofthestageisgivenby 0=gmi/Cc.Adetailedanalysisoftheperformanceofacompensatedopampusedtochargeor
dischargeacapacitorreveals[3,4]that(inlinearoperation)theconditionontheunitygainbandwidth,

isusuallysufficienttoguaranteeadequatespeed.HereTchisthetimeavailableforrechargingCLforatwophasecircuit,usually
frequency.

wheref cistheclock

Theminimumvalueofgmiisusuallydeterminedbytherequireddcgainandbynoiseconsiderations.Inaddition,thereisalsoanupperboundongmi/Cc,basedonthe
requirementthatthesecondpolefrequency|sp2|mustbeconsiderablyhigherthan 0.Often,|sp2|=3 0ischosen.This,asderivedin(4.57)to(4.62),requiresforour
circuitthat

AruleofthumbthatusuallyresultsinagoodcompromiseamongallrequirementsistochooseCc=CL.ThenEq.(8.14)givesalowerboundforgmiandEq.(8.15)a
lowerboundforgm6.
Forlargesignaloperation,theslewrateSroftheinputstagemustalsobeconsidered.FromEq.(4.94),Sr=I0/Cc.ForCc=CL,theminimumvalueofI0(thebias
currentoftheinputstage)isthusdetermined.Inaddition,for

Page309

thecircuitofFig.8.2,theslewrateoftheoutputalsoneedsattention.Forpositivegoingvout,theoutputcurrentiLissuppliedbyQ6.ThemagnitudeofiLislimitedonly
bythesizeofQ6,andthatofv outonlybythev DS6neededtokeepQ6insaturation.Fornegativevout,bycontrast,theoutputstagemustsinktheloadcurrentiL.Thisis
performedbyreducingI6belowIbiassothatI6=Ibias|iL|.
Themaximumvalue|iL|=IbiasisobtainedwhenI6=O,thatis,whenQ6iscutoff.Thenegativegoingslewrateduetotheoutputstageisthen

ThisestablishestheminimumvalueofIbias.NotethatbyEqs.(4.56)and(4.61),thetransconductancesoftheoutputdevices(hereQ6andQ7)mustbelargefor
stability.AlargeIbiaswillhelptosatisfythiswithmoderatesizedQ6andQ7.
ThedcpowerdissipatedbythecircuitofFig.8.1inthequiescentstateisthus

whereCc=CLhasbeenset.Therefore,thehighertheslewratesandthelargerCL,themoredcstandbypowerisneededbythestage.
UsingaclassABstagecanoftenreducethestandbycurrentoftheoutputstage.Theresultingcircuitwasdiscussedearlier(cf.Fig.4.15)andisreproducedinFig.
8.3.Thelevelshifterstage(Q9andQ10)shouldbedimensioned

Figure8.3
CMOSopampwithclassABoutputstage.

Page310

suchthatthevoltagesv GS6andv GS7,andhencethequiescentdraincurrentsofQ6andQ7,arenottoolarge.SincesignalvoltagesdrivethegatesofbothQ6andQ7,the

loadcurrentcannowbemuchlargerthanthebiascurrentforeitherpositiveornegativegoingv out.Theminimumvalueoftheoutputdcbiascurrentisthus
determinedonlybytherequirementonthetransconductancesgm6andgm7neededforagoodphasemargin.
ThevalueofthestandbycurrentI10willdeterminethelocationsofthezeroandthepoleofthesourcefollowerQ9Q10,asgivenbyEq.(3.103).Obviously,thepole
(whichisatalowerfrequency)willresultinapositivephaseshift,whilethehigherfrequencylefthalfplanezerowillcauseanegativephase,resultinginadipinthe
phasecharacteristic.Thelocationofthedipisdeterminedbythefrequencyofthepole,anditsdepthandwidthbytheseparationbetweenthepoleandthezero.The
minimumvalueofI10canbethusdeterminedsuchthatthedipmovestoasufficientlyhighfrequencywhereitaffectsonlyslightlythephaseshiftofthestageat 0.This
requirementgivestheminimumvalueofgm9,andthusofthebiascurrentI10.Forcingthezeroasclosetothepoleaspossiblecanreducethedepthofthedip.Itis
worthmentioningthatthesourcefollower'stimeresponse,duetothepresenceofthepolezeropair,willcontainanexponentialterm.Inthistermthetimeconstantis
determinedbythepolefrequency,whiletheamplitude(residue)isdeterminedbythedifferencebetweenthepoleandzerofrequencies.Increasingthepolefrequency
andreducingthedistancebetweenthepoleandzerowillthereforeimprovethetimeresponseaswell.
ThevoltageVbiasfortheopampsofFigs.8.2and8.3canbeobtainedusingthecircuitsofSection3.1.Inparticular,fortheopampofFig.8.1asupplyindependent
biasisdesirable.ThiswillkeepI0andIbiasindependentofthesupplyvoltages,andhencetheparameters,whichaffectthestability,unchanged.(Thedcpower
dissipationwill,ofcourse,varywiththesupplyvoltages.)ThusVbiasmaybeobtainedfromthecircuitofFig.3.5.
ForthecircuitofFig.8.3,bycontrast,supplyindependentbiasingcancauseproblems.Inparticular,ifI0remainsconstantwithsupplyvoltagevariation,VGS3does
alsoifI0remainsconstant,VGS9doestoo.HenceintheexpressionforthegatetosourcevoltageofQ7,

(VGS3VGS9)isinvariantofVDDandVSS.Therefore,allpowersupplychangesappeardirectlyinVGS7,andQ7cancutoffifVDDVSSdropssignificantly.
AsuitablebiascircuitfortheopampofFig.8.3isshowninFig.8.4.Whenthiscircuitisused,thedimensionsoftheNMOSdevicesQ5,Q10,andQ13areobviously
relatedby

Page311

Figure8.4
Biascircuitforthe
opampofFig.8.3.

Inaddition,thePMOStransistorsQ3,Q4,andQ11canbedimensionedsuchthat

holds.Thenwehave

Inaddition,wecandimensiontheNMOSdevicesQ9andQ12soastosatisfy

ThiswillcauseVGS9 VGS12,andusingEqs.(8.18)and(8.21),wefindthat

ThismatchingofvoltagesisindependentofVDDandVSS.
ThusifI7isthedesiredvalueoftheoutputbiascurrent,wemustchoosethedimensionsoftheNMOSdevicesQ7andQ13tosatisfy

Page312

Finally,sinceclearly

weshouldalsochoose

Notethatthischoiceofdimensionswillestablishthedesiredbiascurrentswithoutintroducinganysystematicoffsetvoltage.Assumenowthatthesupplyvoltagesvary
inthecircuit.ThenIrefwillchange,andsowillv GS11,v GS12,andv GS13.However,Q11,Q12,andQ13willcertainlycontinuetoconductinfact,theywillallalsoremainin
saturationsincetheirgatesanddrainsareconnected.ButsincethecurrentsandgatetosourcevoltagesofQ5,Q10,andQ7mirrorthoseofQ13,theytoowillconduct
andremaininsaturation.Also,sincethecurrentsandgatetosourcevoltagesofQ3,Q4,andQ6mirrorthoseofQ11,thesetransistorswillconductandremainsaturated.
Finally,theconductionandsaturationconditionsofQ9followfromthoseofQ12.Thusalltransistorshavestabilizeddcbiasconditions,andtheoperationofthecircuit
willbeinsensitivetoprocessvariations.
6.NonzeroOutputResistance.Thisisusuallyimportantonlyfortheoutputamplifieroftheoverallcircuit,whichmayhavetodrivealargecapacitiveand/orresistive
load.ThelowfrequencyoutputresistanceRoutoftheopampwithoutnegativefeedback(i.e.,openloop)isontheorderofrd/2foranunbufferedcircuit,suchasthat
showninFig.8.2or8.3.Hererdisthedrainresistanceoftheoutputdevices,ontheorderof0.1to1M .Forabufferedcircuit(suchasthatshowninFig.4.12),
theoutputimpedanceisaround1/gm,wheregmisthetransconductanceoftheoutputdevicehenceRout~1k .Inclosedloopoperation,theeffectiveoutput
impedanceisRout(1ACL)/A,whereAistheopenloopgainandACListheclosedloopgain(Problem8.3).SinceusuallyA>1000,theeffectiveclosedloop
impedanceisaround1k forunbufferedopamps,andverylow(ontheorderofafewohms)forbufferedones.Thisvalueissufficientlylowformostapplications.
7.NoiseandDynamicRange.ThesesubjectswerediscussedinsomedetailinSection4.7forCMOSopamps.Hencetheyarenotanalyzedhere.
8.PowerSupplyRejection.ThisisoneofthemostimportantnonidealeffectsinMOSanalogintegratedcircuits,forseveralreasons.First,severalcircuits(some
analog,somedigital)mayoperateoffthesamepowersupply.Henceanumberofanaloganddigitalsignalcurrentscanenterthesupplylines.Sincetheselineshave
nonzeroimpedances,digitalandanalogvoltagenoisewillbesuperimposedonthedcvoltageprovidedbythesupply.Iftheopampcircuitdoesnotrejectthisnoise,
thenoisewillappearatitsoutput,reducingthesignal/noiseratioandthedynamicrange.Second,ifswitchingregulatorsordc

Page313

voltagemultipliersareused,asubstantialamountofhighfrequencyswitchingnoisewillbepresentonthesupplyline.Finally,theclocksignalsofthevariouscircuits
fedfromthesamelinewillalsousuallyappearsuperimposedonthesupplyvoltagewithreducedbutnonzeroamplitude.
Inasampleddatacircuit(suchasaswitchedcapacitorcircuit),allsignalsaresampledperiodically.Thisresultsinafrequencymixing,andasaresultthehigh
frequencynoisewillbe"aliased"intothefrequencybandofthesignal.Henceanynoiseintheoverallfrequencyrangeisdetrimentalifitcanenterthesignalpath.
Themostlikelypaththroughwhichsupplynoisecanbecoupledtothesignalisviatheopamps.Thusahighvalueofthepowersupplyrejectionratio(PSRR),defined
inSection4.1astheratiooftheopenloopdifferentialgainADandthenoisegainApfromthesupplytotheopampoutput,isofgreatimportance.
Atlowfrequencies,thesupplynoiseiscoupledintotheopampmostlythroughthebiascircuitsandcanalsoenterduetotheasymmetriesinthedifferentialinput
stage.Athighfrequencies,ontheotherhand,thecapacitivebranchesmostlydeterminethenoisegain.ConsiderthecircuitsofFigs.8.2and8.3.Athighfrequencies,
thecompensationcapacitorCcbecomesnearlyashortcircuit,and(sincethedrainsourceresistancer8ofQ8issmallinthelinearregion),thegateanddrainvoltages
ofQ6arenearlyequal.AsshowninFig.8.5,therefore,theincrementaloutputvoltageduetothesupplynoisev nis
v out=v n+ v GS6=v n
sincev GS6=I7/gm7isconstant.ThusAp=1,independentoffrequency,forthisstage.TheoutputimpedanceofQ6drivingCLwiththisnoisevoltageislow,around1/gm6.
SincetheopenloopgainADdecreaseswithincreasingfrequencyatarateof6dB/octavewhileApstaysconstant,thePSRRduetonoiseinVDDdecreasesatthe
samerateasAD,reaching0dBneartheunitygainfrequency.

Figure8.5
Highfrequency
modeloftheop
ampoutputstage.

Page314

Figure8.6
Compensationschemeforimprovingthe
positivesupplyPSRR.

ThesituationismorefavorablewithrespecttonoiseontheVSSline.ThegainfornoiseenteringviaQ5isthelowcommonmodegain.AnynoiseenteringviaQ10andQ7
isaddedtothesignalandattenuatedatthesamerate(6dB/octave)asthesignalbytheloadcapacitorCLsincenowthenoiseoutputimpedanceishigh.
Aneffectivetechnique[5]forincreasingthePSRRfornoisecomingfromthepositivesupplyisillustratedinFig.8.6.IncontrasttothecircuitsofFigs.8.2and8.3,
whereQ8operatedasalinearresistorforbothfeedbackandfeedforwardsignals,Q8isnowbiasedinitssaturationregion.Henceinthefeedbackdirection(fromv out
throughCcandQ8tothegateofQ6)theresistanceis1/gm8,whileviewedfromnodeAthedrainofQ8showsahighimpedancerd8.Thus,whilethefeedback(andalso
thecompensation)remainsfunctional,thefeedforwardpathfornoiseisinterrupted.Specifically,ifVDDchanges,thesourcevoltageofQ6does,too,and(asexplained
earlier)thegatevoltageofv g6mustfollow.Now,however,theoutputterminalisnotshortedtov g6,andhencev outneednotfollowv G6.ThisreducesApconsiderablyat
highfrequencies.
ThecurrentsofthetwosourcesI(neededtokeepQ8initssaturatedregion)mustbecarefullymatched.Thisispossibleusingthestrategyexplainedinconnectionwith
Fig.8.4.Anymismatchwillintroduceasystematicoffsetvoltage.Also,theimpedanceatnodeAissomewhatreducedandthereforesoisthegainoftheinputstage.
Finally,duetotheaddeddevices,theinternallygeneratednoiseoftheopampisincreasedhowever,theeffectofincreasedPSRRusuallyoutweighsthisandthe
overallnoiseattheopampoutputisreduced.
Anotherpathforpowersupplynoiseinjectionisprovidedbythestray

Page315

Figure8.7
Parasiticcapacitancesaffectingthe
summingnodeAofanintegrator.

capacitances[6,7].ConsiderthecircuitofFig.8.7.Itillustratesatypicalswitchedcapacitorintegratorinoneofitsswitchedstates.Thetwoparallelconnected
transistorsQ1andQ2constitutetheswitch.TheparasiticjunctioncapacitancescouplingthedrainofQ1andthesourceofQ2tothesubstrate,aswellasthestray
capacitancesbetweenthelinesconnectedtotheinvertinginput(nodeA)andthesubstrateandpowerlines,areillustratedasCDDandCSS.(Asshown,thesecapacitors
containbothlinearandnonlinearcomponents.)Considertheeffectofv nD.SincenodeAisavirtualground,thenoisechargeenteringisCDDv nD.Thischargeflowsinto
CFandcausesanoutputnoisevoltage(CDD/CF)v nD.ThusthenoisegainisCDD/CF.Similarly,thenoisegainforv nSisCSS/CF.Sincethesignalgainisv out/v in=
C1/CF,thePSRRoftheintegratorisC1/(CSS+CDD).*ThusthePSRRcanbeincreasedbyminimizingthestraycapacitancesandbychoosingthevaluesofthe
capacitorsC1andCFsufficientlylargethelatter,ofcourse,increasestheoverallareaoccupiedonthechipbythestage.Toreducethestraycapacitancesand
therebytheinfluenceofthesubstratenoise,thedimensionsoftheswitchesshouldbechosenassmallaspossible,andwheneverfeasible,alllinesconnectedtothe
inputnodesoftheopampsshouldbeshieldedbygroundedpolysiliconordiffusionplanesplacedbetweenthelinesandthesubstrates.
Parasiticcapacitancesinsidetheopampalsocontributetothepowersupplynoisegain[7].Considertheequivalentcircuitoftheopampwithanexternalfeedback
capacitorCF,asshowninFig.8.8.ThefigurealsoillustratesthestraycapacitancesCgdandCgsoftheinputdeviceQ1.Noiseinthepositivelinewillappearatthe
drainsofQ3andQ4,andfromtheformerwillbecoupledtotheinputnodeAviaCgdandfromtheretotheoutputviaCF.Inaddition,variationsofthebiascurrentI0
duetothenoiseinVDDandVSSwillchangethegatetosourcevoltagesv gsofQ1andQ2by v gs ( I0/2)gmi.Thecorrespondingchangeinthesourcevoltageswillbe
coupledtonodeAbyCgs.Similarly,changesinVSSwillalterthethresholdvoltageVTnofQ1andQ2,unlessthesedevicesareplacedinanisolatedpwell.Theresulting
changein
*

ThiscalculationassumestheworstcaseconditionthatvnDandvnSarefullycorrelated.

Page316

Figure8.8
Equivalentcircuitoftheopampconnected
asanintegrator.

thesourcevoltageswillalsobecoupledtotheinputnodebyCgsandtotheoutputviaCF.Overall,itcanbeshown[7]thattherelations

givethepowersupplynoisegainsofthecircuit.Thetermscontaining I0/ VSSand I0/ VDDcanbeeliminatedbyusingsupplyindependentbiasingforthecurrent

sourceI0.The VTn/ VSStermcanbeeliminatedinCMOSamplifiersbyusingapwell(nwellforptypeinputdevices)forQ1andQ2,connectedtotheirsources.
Ifallthestepsabovearetakentoreducethenoisegain,theremaininggainis v out/ VDD Cgd/CF.Thiscan,inprinciple,bereducedbymakingQ1andQ2small
and/orCFlarge.Theformermeasure,however,resultsinanincreaseofinternallygeneratednoise,whilethelatterincreasesthechipareaneededbythestage.A
techniquethateliminatestheproblem,atthecostofaslightlyreducedcommonmodeinputrange,istousecascodecircuitry(Fig.8.9)intheinputstage.Theadded
devicesQ5andQ6thenbufferthedrainsofQ1andQ2fromthevariationsofVDDprovidedthatVbiasisindependentofthesupplyvoltages.
8.2
OpAmpDesignTechniquesandExamples
ThedesignofMOSopampsisnotanexactscientificprocess.Typically,thecircuitmustsatisfymanyrequirements,oftenconflictingones.Theopampperformance
parametersmostoftenspecifiedarecollectedinTable8.1.Otherimportantdesign

Page317

Figure8.9
CascodeCMOSdifferential
inputstage.
TABLE8.1.OpAmpPerformanceParameters

TheformulasinthiscolumnaregivenforthecircuitofFig.8.3.Setg m7andI10equal
tozerotoobtaintherelationsfortheamplifierofFig.8.2.

Page318

criteriaincludethenoiselevel,dynamicrange,outputimpedance,andtheareaoccupiedonthechip.Thespecificstepsfollowedinthedesigndependonthe
application,thecircuitchosen,andtherelativeimportanceofthevariouscriteria.
Toillustratetheprocess,thedevicesinthecircuitofFig.8.2willbedimensionedsuchthatthefollowingspecificationsaresatisfied:
Lowfrequencygain

A0=70dB

Unitygainfrequency

f 0=2MHz

Slewrate

Sr=4V/s

Commonmoderejection

CMRR=80dB

Phasemargin

>60

Loadimpedance

CL=10pF

dcsupplyvoltages

VDD=VSS=5V

Itwillbeassumedthatthetransconductancefactor
areassumedtobeVTn=1.2VandVTp=1V.

is30A/V2fortheNMOSdevicesand12A/V2forthePMOSdevices.Also,thethresholdvoltages

AsmentionedinSection8.1,itisusualtochoosethevalueofthecompensationcapacitorCcequaltoCL.Henceweset

Foranadequatephasemargin M,thefrequencyofthesecondpolesp2oftheopenloopgainshouldbesufficientlyhigherthan 0,theunitygainfrequency.AsFig.

4.22shows,for|sp2|~2 0thecontributionofthefactorj sp2tothephaseat = 0isabout30,andhencethephasemarginis60.Thus|sp2|=3 0givesamargin
greaterthan60.Thevalueofsp2canbefoundfromthesmallsignalequivalentcircuitoftheopampofFig.8.2,showninFig.8.10.Alternatively,wecanusethe
formula(4.55)derivedfromthecircuitofFig.4.28here,however,wemustreplacegm8bygm6(sinceQ6isnowtheoutputdriver)andomitgm9(sinceQ7,the

Figure8.10
SmallsignalequivalentcircuitoftheopampofFig.8.2.

Page319

loweroutputdevice,isusedmerelyasacurrentsource).AssumingthatCA gd7,

results.Therefore,asalreadygiveninEq.(8.15),

isthedesignequation.Thisgives

andhence

Thespecifiedslewraterequiresthatthebiascurrentoftheinputstagesatisfy

WecanthuschooseI0=40A.
AsexplainedinSection8.1[seethediscussionprecedingEq.(8.16)]thenegativegoingslewratelimitationduetotheuseofQ7asacurrentsourceis

Tomakethiseffectsmall,wecansetSr0=2.5Sr=10V/s.Then

Suchlargecurrentalsoenablestherealizationoftherequiredlargegm6withoutanexcessiveaspectratio(W/L)6.
FromEq.(8.6),toavoidsystematicoffsetvoltage,thecondition

musthold.Since,byEq.(2.18)gmisproportionalto

Eq.(8.33)to(8.36)giveforthetransconductanceoftheloads,

Page320

Atthispoint,anestimateofthelowfrequencygainA0andthecommonmoderejectionratiocanbefound.FromEq.(2.20)thedrainconductanceofaMOSFETis
approximately isthedcdraincurrent.Hence,fromFig.8.2orTable8.1,

whichcorrespondstoover76dBgain.Similarly,fromEq.(3.88),thecommonmoderejectioncanbeapproximatedasfollows:

whichcorrespondstoaboutan88dBcommonmoderejectionratio.
Bothvaluesexceedthespecifications.Ifthiswouldnothavebeenthecase,thespecificationswouldhavebeeninconsistent.ThiscanbeseenbyusingEqs.(8.29)to
(8.37)toexpresstheparametersenteringA0andCMRR:

Since,infact,nandpchanneldeviceshaveslightlydifferent values,thiscalculationgivesonlyaroughestimateofA0andtheCMRR.

Page321
*

ThusbothA0andCMRRarefullydeterminedby 0andtheslewrates. Theycanbeincreasedbychoosinggmiandgm6(andhencetherealizedvaluesof 0and|sp2|)

larger.
Next,thechannelresistancer8ofQ8isfoundsoastoplacethezeroszofAv(s)atadesirablelocation.SimpleanalysisbasedonFig.8.10showsthatforthecircuitof
Fig.8.2thezeroisat

andhencetherequiredresistanceisrelatedtothedesiredzerolocationszbytheformula

AsdiscussedinSection4.4,thereexistdifferentstrategiesforchoosingsz.Onepossibilityistousesz=sp2anotheristoshiftszto .Fortheformerchoice,usingEq.
(8.29)andCc=CL,weget

Forthelattercase,Rc=1/gm6 2.65k .(Notethatanevenlargerphasemargincanbeobtainedbychoosing|sz|onlyslightlyabove 0|sz|~1.2 0isusuallya

reasonablevalue.)HerewechoosethevaluegiveninEq.(8.45).NotethatQ8isclearlyinitslinearregion,sinceitsgateisatVSSwhileitsdcdraintosourcevoltageis
zero.Hence,byEq.(2.6),

Next,thedesignofthecurrentsourcesQ5andQ7isdiscussed.TheaspectratiosW/Lofthesetransistorsshouldnotbetoosmallsinceotherwiseforthegivencurrents
(I0,Ibias)therequired''excess"gatetosourcevoltage(v GSVT)willbelarge.Thisisinconvenient,sincethevoltagesvandv out(Fig.8.2)arenotallowedtodrop
belowVSS+v GSVTifQ5andQ7aretostayinsaturation.Hencealargev GSVTforQ5andQ7restrictsthevoltageswingandthusthedynamicrangeoftheopamp.
*

Insingleendedswitchedcapacitorcircuitswherethenoninvertinginputisgrounded,theCMRRassuchisnotveryimportant.

Page322

Ontheotherhand,theareasofQ5andQ7shouldnotbetoolarge,either.Onereasonisthat,ofcourse,realestateisveryexpensiveonthechiptheother,thatalarge
areaforQ5increasesthestraycapacitanceCwacrossthecurrentsource.Thiscapacitanceconsistsoftwoparallelconnectedreversebiasedjunctioncapacitancesthe
draintosubstratecapacitanceofQ5,andthepwelltosubstratecapacitanceofQ1andQ2.CWcausesadecreaseoftheCMRRathighfrequencies,sincethengd5in
Eq.(8.39)isreplacedbygd5+j Cw.Also,asexplainedinconnectionwithFigs.4.42to4.44,Cwcausesadistortioninthestepresponseoftheopamp.Alarge
straycapacitanceacrossQ7,causedbyalargedraindiffusion,willincreaseCLandhencereducethephasemargin.
ThusacompromiseshouldbefoundwhenQ5andQ7aredimensioned.FromEq.(2.8)theexcessgatetosourcevoltagesare

Assumingagainthat =12 A/V2forthePMOSdevices,andallowing0.5VexcessvoltageforbothQ5andQ7,weget

ToavoidshortchanneleffectswhichoccurforL<10mandwhichwouldincreasethedrainconductancegd,wechooseL5=L7=10m.ThenW5=54mandW7
=133mcanbeused.
WecannextcalculatetheaspectratiosofQ1toQ4andQ6fromtheirtransconductances.FromEq.(2.18),assumingthat| v Ds| 1,thetransconductanceisgivenby

Hencetheaspectratioscanbefoundfrom

andbyEq.(8.36),

Page323

AgainchoosingL=10mforalltransistors,W1=W2=66m,W3=W4=60m,andW6=300mresult.(Notethatoftennoiseconsiderationsrequirethatthe
widthoftheinputdevicesbechosenmuchlarger,say200mormore!)
Next,wecanestimatethe(common)dcbiasvoltagesatthedrainsofQ1toQ4.SincetheyallcarryadccurrentI0/2,wehave

SincethePMOSthresholdvoltageisVTP=1V,

HencethedrainsofQ1toQ4areatadcbiasvoltageVDD|v Gs3| 51.527=3.473V.

Thisisalsothedrainandsourcebiasvoltagev D8ofQ8,andhencefromEqs.(8.45)and(8.46),

HenceW8=L8=10mcanbeused.
Atthispointthedimensionsofalldeviceshavebeen(tentatively)determined,andwealsoknowthevaluesofallcurrents.ThedrainvoltagesofQ1andQ2havebeen
foundtheirsourcesare(for

=0)atavoltagevsuchthat

whichgives,forVTn 1.2V

sov 1.52V.
TheonlyremainingtaskistodesignabiaschainthatprovidesVbias.InEq.(8.48),Q5andQ7havebeendimensionedsuchthatv GS5=VTn+0.5V=1.7V.ThusVbias=
VSS+v GS5=3.3V.Thiscanbeachievedbythesimplecircuitshown

Page324

Figure8.11
Biascircuitforthe
opampofFig.8.2.

inFig.8.11.ChoosingthecurrentofthebiaschainIb=20A,theaspectratiosofQ9andQ10areeasilyfoundsincev GS9=0Vbias=3.3Vandv GS10=VbiasVSS=

1.7Vareknown,

HenceW9=10m,L9=66mandW10=27m,L10=10mcanbeused.
ItshouldbenotedthatVbiasandIbareinsensitivetovariationsofVDDbutnottochangesinVSS.IfVSS

Heretheprimedenoteschangedvalues.
FromEq.(8.60),

CombiningwithEq.(8.59),andsolvingfor

gives

V SS=VSS+ VSS,thenv GS9andv GS10alsochange,suchthat

Page325

Thusapositivechangeof+0.1VinVSSwillchangev GS10by

HenceVbias=VSS+v GS10changesby0.10.01915 0.081V.ThecorrespondingchangesinI0andIbiascanbefoundapproximatelyfrom

Ifthesechangesarenotacceptable,thebiasindependentcircuitofFig.4.4acanbeusedtoprovidev o1=Vbias.
Toverifytheaccuracyofthedesign,theoverallcircuitwasanalyzedusingthepopularprogramSPICE.Figure8.12showsthecomputedgainandphaseresponses

Figure8.12
GainandphaseresponsesfortheopampofFig.8.2.

Page326

Figure8.13
Stepresponseoftheopampforanegativeandapositiveinputstep.

ofthecircuitunderopencircuitconditions.Theunitygainbandwidthisabout2.5MHz,thedcgain84dB,andthephasemarginabout85.Thusthesespecifications
aremet.Theclosedloopslewrate(Sr)performanceoftheunitygainconnectedopampforanegativeandpositiveinputstepisillustratedinFig.8.13.The
maximumslopegivesSritisover5V/sinbothdirections.Hencethisrequirementisalsosatisfied.Figure8.14illustratesthecommonmodegainresponse.The
required80dBCMRRisclearlyobtainedacrossthefulldctounitygainfrequencyrange.
Thesystematicinputoffsetvoltagecanbeestimatedfromtheoutputvoltage forv in=0(Fig.8.15)asVoff 0.2mV.Thisisverylowandlikelytobenegligible
comparedtotherandomoffset.Forillustration,thegainsfornoiseenteringviathepositive(VDD)(Fig.8.16)aswellasthenegative(VSS)supplies(Fig.8.17)arealso
shown.AspredictedinSection8.1,thesupplyrejectionbecomesaproblemathigherfrequenciesat 0thePSRRisnear0dB.
Thelayoutgeometryoftheopamphasimportanteffectsonitsrisetime,overshoot,andhighfrequencyresponseaswellasonitssensitivitytoprocessvariations
anditsoffsetvoltage.Toachievegoodstepresponseandhighfrequencyresponse,thecomponentsoftheamplifiermustbearrangedsoastominimizetheline
lengths,especiallyforlinesconnectinghighimpedancenodes.Thedevicesandlinesoftheinputandoutputstagesshouldbewellseparated,toavoidspurious
feedbackeffects.Ifthenominaldesignoftheopampisdonecarefully,sothatnosystematicvoltageoffsetexists,somerandomoffsetmaystilloccurduetoerrorsin
theratiosof(nominally)matchedcomponents.Forexample,asdiscussedinSection8.1[seeEq.(8.11)],arelativeerror inthematchingoftheaspectratiosofthe
inputdevices

Page327

Figure8.14
Commonmodegainfrequencyresponse.

resultsinaninputreferredoffsetvoltagev off= (v GSVT)/2,wherev GSandVTarethegatetosourceandthresholdvoltagesoftheinputdevices,respectively.For

example,ifv GSVT=1Vand =1%,anoffsetvoltageof5mVresultsfromthissingleimperfection.Thismaybeunacceptableinsomecircuits.Similarly,a
matchingerror VTbetweenthethresholdvoltagesoftheinputdevicesresultsinanoffsetvoltageequalto VT.Again,thismaygiveanimpracticallylargeoffset.To
minimizetheseerrors,boththeinputdevicesandtheirloadsshouldbeplacedsidebyside,withidenticalgeometries,includingallconnectinglines.Matcheddevices
requiresharingthesamewell.Onlystraightlinechannelsshouldbeused,sincethegeometryofcornersofbentchannelsispoorlycontrolled.Ifhighaccuracyanda
lowoffsetvoltagearerequired,itisadvisabletosplitbothinputandloaddevicesintotwoormoreunittransistorsconnectedinparallelandarrangetheminacommon
centroidgeometrysimilartothatusedforaccuratecapacitancematching.Ifaheatsource(e.g.,highcurrentoutputstage)isnearthematchedelements,thelatter
shouldbelocatedsymmetricallywithrespecttoit,toensurematchedtemperatures.

Figure8.15
Circuittoestimateinput
dcoffsetvoltage.

Page328

Figure8.16
VddnoisegainresponsefortheopampofFig.8.2.

Figure8.17
VssnoisegainresponsefortheopampofFig.8.2.

Page329

Thecircuitgeometryalsohassomeeffectontheinternallygeneratednoise.Thus,asalreadymentioned,the1/fnoisemaybereducedbyusinglargerinputdevicesin
theopampschoosinglargercapacitorscanreducethewidebandandaliasednoise.Also,itwasobservedthatveryshortdevicesintroduce"hotelectron"noiseif
operatedatlargevoltages[8].Thisshouldbeavoidedbyusingincreasedchannellengthsforsuchdevices.
Asanillustrationofefficientlayoutprocedure,thelayoutofthesimpletwostagecompensatedCMOSopampofFig.8.2isillustratedinFig.8.18foraselfaligned
silicongatepwellprocess.Notethecommoncentroidlayoutandthesymmetryofthematcheddevices(Q1Q2andQ3Q4),theshortconnectinglines,theseparation
oftheinputandoutputlines,andthecompactarrangementoftheoverallstructure,resultinginasmalltotalopamparea.
Next,werepeatthedesignforthesamespecificationsbutusingthecircuitofFig.8.3withitsclassABoutputstage.Again,weselectCc=CL=10pF,andsince 0=
gmi/Cc,gmiisgivenbyEq.(8.32),asbefore.Also,I(determinedbytheslewrateandCc)remainsthesame,asgivenbyEq.(8.33).Bytheargumentleadingearlierto
Eq.(8.48),(W/L)5=5.4canagainbeused.ToobtainthespecifiedCMRR,fromEqs.(3.88)and(2.20),

HencethevaluesgiveninEq.(8.37)remainsuitable.Inconclusion,thedimensionsoftheinputstagecanremainunchangedforthenewcircuit,sincetheyare
determinedbythe(unchanged)requirementson 0,Sr,Cc,andCMRR.
UsingEq.(4.56)andchangingsubscriptsappropriately,thesecondpole

Hence,for|sp2|=3 0,nowtherelation

mustbesatisfied.Todeterminegm6andgm7individually,wenotethati6=i7andhencethebiasvoltagesmustsatisfy

asgiveninEq.(8.53),sincetheinputstageremainedunchanged.Also,assuggested

Page330

Figure8.18
LayoutofthetwostageCMOSopampofFig.8.2.

Page331

inEq.(8.23),thebiasvoltagesandcurrentscanbemadeinsensitivetoprocessvariationsifv GS7=v GS5=v GS10=VbiasVSS=3.3+5+1.7Vischosen.Hence,using

Eq.(2.18)and(8.69),

CombiningEqs.(8.68)and(8.71),weobtain

Toavoidsystematicoffset,asdiscussedinconnectionwithEq.(8.6),wemusthave

Since,fromEqs.(8.37)and(8.72),

andI0/2=20A,wefindthat 14.6.HenceL6=10mandW6=146mcanbeused.
Next,since =49 A,

Therefore,wecanchooseL7=10mandW7=64m.
Finally,thetransistorsQ9andQ10ofthelevelshifterwillbedimensioned.Asbefore,

leadsto

Page332

Here,asFig.8.3shows,v GS9=VDDVSS+v DS4v GS7=101.5271.7 6.77Vandv GS10=v GS7=1.7V.Hence

Thetransconductancegm9ofQ9canbefoundfromthephaseshiftintroducedbythepolezeropairduetothestraycapacitancesloadingthesourceterminalofQ9.
SincethesourcefollowerQ9Q10drivesthese,thepoleandzeroarelocatednearsp3 gm9/Cp.Estimating(pessimistically)Cp=0.5pF,andrequiring|sp3|=3 0to
makethecontributionofthispoletothephaseat 0small,weobtain

HenceW9=10mandL9=176mcanbeused.FromEq.(8.78),

Therefore,L10=10mandW10=71mcanbechosen.ThecommoncurrentofQ9andQ10isthen

AsexplainedinSection8.1,thebiaschaincircuitofFig.8.4canbiasthiscircuit.ThedesignformulasfortheaspectratioshavebeenderivedinSection8.1andgiven
byEqs.(8.19)to(8.25).ChoosingIref=I0/2=20A,weget

Page333

HencewecanuseL11=10,W11=60,L12=466,W12=10,andL13=10,W13=27,allinm.
Thecompensationbranchofthecircuitremainsunchangedifweagainchoosesz=sp2.Thisisbecausesp2remainedat3 0,andthedcpotentialofthedrainofQ8
alsoremainedthesame.HencewecanonceagainuseW8=L8=10m.
SPICEanalysisoftheclassABamplifierwiththeaspectratioscalculatedaboveindicatesthatthedcbiasvoltageoftheoutputterminalisunsuitableforproper
operation.Itsvalueistoolow(about4.5V)toallowQ7tosaturate.Thisoccursonlyunderopencircuitconditionsandisaconsequenceofthesimplifying
assumptions,primarilytheneglectofthechannellengthmodulationfactor(1+ v DS),madeinthecalculations.Theproblemisanartificialone,sincethecircuitnever
functionswithoutadcloadand/orfeedback.Addinga1M loadresistorbetweentheoutputterminalandground,orafeedbackresistorof(say)100M between
theinvertinginputterminal

andtheoutputterminaloftheopamp,theoutputvoltagereturnstoavaluesufficienttokeepbothQ6andQ7insaturation.

Asanexerciseindesign,however,aswellasawaytoshowhowtoreducesystematicoffset,wearenextgoingtoredesigntheoutputstagesoastoobtaina
satisfactorydcbiasvalueforv outevenunderopencircuitconditions.TheSPICEanalysisforthecircuitgavev GS6=1.572V,v GS7=1.821V,and ,wemusthave,
byEq.(2.11),

Thisrelationnowincludesthechannellengthmodulationeffectandishencemoreaccurate.
Substituting =0.03V1,aswellasthegivenvalues,(W/L)6 50/9results.ThusW6=164m,L6=10m,W7=50m,andL7=9mcanbeused.Theresulting
outputbiasvoltageisonly0.04V.
Figure8.19showsthegainandphaseresponsesoftheredesignedcircuitunderopencircuitedoutputconditions.Theunitygainbandwidthisagainnear2.5MHz,
whilethedcgainisover90dB.Thephasemarginisover83thisismorethanadequateandindicatesthatthebiascurrentofQ6,Q7,Q9,andQ10(andthustheir
transconductances)canbereducedandstilladequatestabilitymaintained.Thiswasnotattempted.ThecommonmodegainresponseisshowninFig.8.20,the
CMRRisover80dBacrossthefullfrequencyrange0to 0.Thesystematicinputreferredoffsetvoltageisnegligible.
Theslewrateperformanceoftheopampforpositiveandnegativevoltageinputstepswascomputedandwasfoundtobearound5V/sforbothpolarities.Thegain
responseforVDDandVSSnoiseareillustratedinFigs.8.21and8.22,respectively.ThelayoutoftheopampofFig.8.3isillustratedinFig.8.23.
Thedesignofa3VCMOSsinglestagefoldedcascadeopampispresentednext.Thedesignwillbebasedona0.6msilicongatebulkCMOSnwellprocess.

Page334

Figure8.19
GainandphaseresponseoftheopampofFig.8.3.

Figure8.20
CommonmodegainresponseoftheopampofFig.8.3.

Page335

Figure8.21
VDDnoisegainresponseoftheopampofFig.8.3.

Figure8.22
VSSnoisegainresponseoftheopampofFig.8.3.

Page336

Figure8.23
LayoutofthetwostageclassABCMOSopampofFig.8.3.

Page337

Figure8.24
Foldedcascodesinglestageopamp.

Thesinglestagefoldedcascadeopampwasdiscussedearlier(cf.Fig.4.10)andisreproducedinFig.8.24.ThedevicesinthecircuitofFig.8.24aredimensioned
suchthatthefollowingspecificationsaresatisfied:
Lowfrequencygain

A0 65dB

Unitygainfrequency

f 0 5MHz

Slewrate

Sr 10V/s

Phasemargin

>60

Loadimpedance

CL=10pF

dcsupplyvoltages

VDD=3V,VSS=0V

Itwillbeassumedthatthetransconductancefactork' Cox/2is55A/V2forNMOSand22A/V2forthePMOStransistors.Also,thethresholdvoltagesare
assumedtobeVTn=0.8VandVTp=0.9V.TheopampperformanceparametersaresummarizedinTable8.2.
Forthespecifiedslewrateitisnecessarythatthebiascurrentoftheinputstagesatisfy

WecanthenchooseI0=150A.
TABLE8.2.SingleStageFoldedCascodeOpAmpPerformanceParameters

Page338

Figure8.25
VBEbasedbiasgenerator
forthefoldedcascodeopamp.

Foraunitygainfrequencyof5MHzweshouldchoosegm1from

Thetransconductanceoftheinputdevicesisgivenby

Hencetheaspectratiosoftheinputdevicescanbefoundfrom

choosingL=2mforthetransistorsW1=W2=30mresults.Notethatnoiseconsiderationsrequirethewidthoftheinputdevicestobechosenlarger,sayW1=W2
=200mormore.
Basedonthevaluesabove,a VBEbasedsupplyindependentbiascircuitwillbedesignedtooperatetheopampwithmaximumoutputvoltageswing.Sincethe
powersupplyis3V,thereisnotenoughheadroomtousethehighperformancecascodeloadbiasgeneratorcircuitshowninFig.3.6b.Therefore,thesupply
independentbiasgeneratorofFig.3.6awillbeusedinstead.ThebiascircuitisshowninFig.8.25,whereM=8.IfwesetthebiasstandbycurrentIbias,to75A,
fromEq.(3.13)wehave

Page339

FortransistorsQ20toQ23inthebiasgenerator,wechooseL=2mforthechannellengthsandW=80mforthechannelwidths.
ThecompleteopampandthebiasgeneratorareshowninFig.8.26.TransistorsQ24andQ28formcurrentmirrorsandareusedtobiasalldevicesintheopamp.The
currentsinQ25andQ26are75A.Ifweselect(W/L)26=80/2,thenforQ5andQ6tocarry150Awehave(W/L)5=(W/L)6=160/2.Foreaseofphysicallayoutwe
shouldalsochoose(W/L)1c=(W/L)2c=160/2.TomaximizetheoutputvoltageswingtheW/LratioofQ25canbecalculatedfromEq.(4.15)andisgivenby

InordertobiasQ5andQ6slightlyabovethesaturationvoltage,wewillselect(W/L)25=25/2.IftheW/LratiosofQ3,Q4,Q3c,andQ4carealsoselectedas160/2,then
fromEq.(4.14)wehave

OnceagaintoensurethatQ3andQ4bothoperatewellinthesaturationregion,theW/LratioofQ28willbeselectedas(W/L)28=38/2.Finally,theW/LratioofQ7will
beselectedas160/2,whichwillsettheopamptailcurrentto150A.
Asdiscussedearlier,thecapacitiveloadactsasthecompensationcapacitorfortheopamp.Thelargerthecapacitiveload,thegreaterthephasemarginandnarrower
theunitygainfrequencyoftheopamp.
Toverifytheaccuracyofthedesign,theoverallcircuitwasanalyzedusingSPICE.Theresultsoftheanalysisshowedthat(VDS)Q5=(VDS)Q6=157mVand(VDS)Q4=
(VDS)Q3=205mV,while(VDsat)Q5=(VDsat)Q6=144mVand(VDsat)Q4=(VDsat)Q3=199mV.ThusQ3,Q4,Q5,andQ6wereallbiasedontheedgeofthesaturation
region.Alsosince(VDsat)Q4C=196mVand(VDsat)Q2C=93mV,theoutputvoltagerangeisgivenby

whichsimplifiesto

Page340

Figure8.26
CompleteCMOSfoldedcascodeopampwithsupplyindependent VBEbasedbiascircuit.

Page341

Figure8.27
OpenloopgainandphaseresponseoftheopampofFig.8.26.

Utilizingtheimprovedbiasingschemeprovidesmaximumsignalswingattheopampoutput.
Figure8.27showsthecomputedgainandphaseresponsesofthecircuitunderopenloopconditions.Theunitygainbandwidthisabout10MHz,thedcgain70dB,
andthephasemargin79.Sothetargetspecificationsaremet.Theslewrate(Sr)performanceisillustratedinFig.8.28.Themaximumslewratefornegativeand
positiveinputsstepsare11.5V/s.Hencethisrequirementisalsosatisfied.Toestimatethesystematicdcoffsetvoltage,theopampswasconnectedasaunitygain
bufferwiththepositiveinputconnectedto1.5Vtheoutputwasestimatedat1.5003V,whichcorrespondstoa0.3mVsystematicdcoffsetvoltage.Thisisverylow
andlikelytobenegligiblecomparedtotherandomoffset.The VBEbasedbiasgeneratorofFig.8.25needsastartupcircuit,whichisnotshown.Intheactual
implementationastartupcircuitsimilartotheoneshowninFig.3.5ishighlyrecommended.Figure8.29showsthephysicallayoutofthesinglestagefoldedcascode
opampofFig.8.26.
ThenextexamplediscussesabufferedCMOSopampthatisabletodriveasmallresistiveloadontheorderof50 .Thisexampleconsistsofthecombinationof
theunbufferedsinglestagefoldedcascodeopampofFig.8.26andtheoutputstageofFig.4.72.Thedesignwillbebasedonthesameperformancespecificationof
thepreviousexamplewiththeaddedrequirementthattheopampwillbedrivinga50 resistiveleadwithasignalswingof2Vfora3V(1.5V)dcsupply
voltage.

Page342

Figure8.28
StepresponseoftheopampofFig.8.26
fornegativeandpositivesteps.

TheschematicofthebufferedopampisshowninFig.8.30a,wheredevicesQ8toQ11havebeenaddedtothecircuitofFig.8.28toformtheoutputstage.Thebias
circuitisshowninFig.8.30b.IthasalsobeenmodifiedbyaddingdevicesQ30toQ35toprovidebiasvoltagesfortheoutputstage.Next,thedevicesintheoutputstage
andbiascircuitwillbedimensionedtosatisfytheoutputdriverequirements.
InsteadystatethecurrentthroughtransistorQ4andQ4c(I=75A)isequallydividedbetweenQ8andQ9,sothateachcarriesacurrentequalto37.5A.FromEqs.
(4.127)and(4.128)wehave

Page343

Figure8.29
LayoutofthesinglestagefoldedcascodeopampofFig.8.26.

Page344

Figure8.30
(a)CMOSbufferopamp.(b) VBEbasedbiascircuit.

Page345

HenceQ31andQ8andQ34andQ9,willhavethesamegatetosourcevoltageandwillcarrythesamedraincurrents,equaltoIb=37.5A.Therefore,asdescribedin
Section4.9andgivenbyEq.(4.129),thestandbycurrentoftheoutputdevicesQ10andQ11isgivenby

TheexternalloadresistanceRLdeterminestheloadcurrentandthusthedimensionsoftheoutputdevicesQ10andQ11.AssumethattheresistanceoftheloadRLthatis
accoupledtotheoutputoftheopampis50 .Thenforanoutputsignalwith2Vpeaktopeakvoltageswings,theopampoutputvariesfrom0.5to2.5V.The
maximumsourceandsinkcurrentsmaybecalculatedfrom

Duringthenegativehalfcycleoftheoutputvoltageswing,thedrainoftransistorQ10pullsto0.5VanditsgateispulleduptowardthepositivesupplyVDD.Tokeep
thegainstageoutputdevicesinthesaturationregion,thegatevoltagepositiveswingshouldbelimitedtoVDD+2(VDSat)Q4+(VDS)Q8 2.5V.InthisrangetheNMOS
transistorQ10willoperateinthelinearregionanditscurrentcanbecalculatedfromEq.(2.10)as

TheW/LratioofQ10cannowbecalculatedfromEq.(8.103)andisgivenby

ForL10=0.8mfromEq.(8.104)wehaveW10 400m.

Page346

Thedimensionsofthepchanneloutputdevicecanbecalculatedusingthesameprocedure.Again,usingEq.(2.10),wehave

SoforL11=0.8mfromEq.(8.106)wehaveW11 1100m.
Assumingastandbycurrentof300Aintheoutputstage,theaspectratiosofQ32andQ35canbecalculatedfromEq.(8.100):

HenceL32=L35=0.8m,W35=50m,andW32=137.5mcanbeused.
TheonlyremainingtaskistodesignthebiaschainconsistingofdevicesQ30,Q31,Q32andQ33,Q34,Q35.ThedimensionsofQ31andQ34shouldbeselectedsuchthat
devicesQ30andQ32remaininsaturation.Tomeetthisconditionthefollowingtwoequationsshouldbesatisfied:

ThephysicallayoutoftheopampcanbeconsiderablysimplifiedifthedimensionsofQ31andQ34areselectedthesameasQ32andQ35.Thisassumptionwillbe
validatedlater.
Figure8.30ashowsthebufferedopampwiththetwofeedbackbranches(R0,Cc0andR1,Cc1)addedforfrequencycompensation.AsexplainedinSection8.1,the
unitygainbandwidthoftheopampisgivenby 0=gmi/Cc,whereCc=Cc0+Cc1andgmiisthetransconductanceoftheinputdevicepair.Thevalueofthe
compensationcapacitanceCccanbedeterminedfromknowledgeoftheopamp

Page347
6

unitygainbandwidthandthetransconductanceoftheinputdevicepair.For 0=2 510 (5MHzbandwidth)and

thecompensationcapacitorcanbecalculatedasCc=8.12104/(2 5106) 26pF.Assumingthatthetwocompensationcapacitorsareequal,wehaveCc0=

Cc1=13pF.
Atthispointthedimensionsofalldeviceshavebeen(tentatively)determined,andwealsoknowthevalueofallcurrents.Toverifytheaccuracyofthedesign,the
overallcircuitwasanalyzedusingSPICE.Figure8.31showsplotsofthegainandphaseresponsesunderopenloopconditions.Thedcgainwithoutloadresistanceis
107.9dB,theunitygainbandwidthis8MHz,andthephasemarginabout90.ThefinaldeviceaspectratiosareshowninFig.8.30a.Basedonaworstcase
analysis,inordertosatisfytheminimumloadcurrentrequirements,thewidthsoftheoutputdevicesQ10andQ11wereincreasedtoW10=800mandW11=1100m,
respectively.Additionally,thedimensionsofQ35andQ32weremodifiedbasedonEqs.(8.107)and(8.108),toW35=100mandW32=200m.Finally,thechoices

Figure8.31
GainandphaseresponsesoftheopampofFig.8.30a.

Page348

Figure8.32
Testcircuittocomputetheoutputdriveperformance.

W8=W31=W32=200mandW9=W34=W35=100mwereverifiedtosatisfytheconditionsgivenbyEqs.(8.109)and(8.110).Theoutputdriveperformanceof
theopampwascomputedbyusingtheinvertinggaintestcircuitillustratedinFig.8.32.Theoutputofthetestcircuitforasinewaveinputsignalwith2Vpeakto
peakamplitudeisshowninFig.8.33.
Intheexamplesabove,theassumptionismadethatthecurrentsintwotransistorswithequalgatetosourceanddraintosourcevoltageshavethesameratioastheir

Figure8.33
OutputresponseoftheinvertinggaintestcircuitofFig.8.32.

Page349

dimensions.OnesuchexampleisthecurrentintransistorQ10,whichisdesignedtobeeighttimesthecurrentofQ35.Inpracticeduetomask,photolithographic,and
etchvariationstherearedifferencesinthedrawnvaluesofWandL.Inotherwords,itisnotguaranteedthatatransistorwithanaspectratioofW/L=1600/0.8will
carryeighttimesthecurrentofanothertransistorwithanaspectratioofW/L=200/0.8eveniftheybothhavethesamegatetosourceanddraintosourcevoltages.
Forimprovedperformance,theproperlayouttechniqueistoimplementthe1:8aspectratiousingeightduplicatesofaunittransistor.ThiswaytolerancesofLandW
willnotaffectthecurrentratio.Thisstrategyshouldbeusedinallcurrentmirrorsusedtomultiplycurrentandfunctionasacurrentamplifier.
8.3
ComparatorDesignTechniquesandExamples
Inthissection,designproceduresfortwotypesofcomparatorsarediscussed.Onceagainthedesignwillbebasedonthe0.6mnwellCMOSprocessofSection
8.2.InthefirstexamplethetaskistodesignthethreestagedirectcoupledcomparatorofFig.5.19toswitchstatewithaminimumoverdrivevoltageontheorderof
250Vinlessthan200ns.Intheworstcasetheinputwillchangefromalevelthatdrivesthecomparatortosomeinitialsaturatedcondition,toanoppositelevel
barelyinexcessof250V.TheschematicofthethreestagedirectcoupledcomparatorwithaVBEbasedbiasgeneratorisshowninFig.8.34.Itconsistsoftwo
directcoupledresistiveloaddifferentialgainstagesfollowedbyatwostagedifferentialcomparator.
Afterthecomparisonphase,theoutputswingofthecomparatorshouldbeequaltothefullpowersupplyvoltage,VDD=3V.Asaresult,theoverallgainofthe
comparatormustbeatleast(3V/250V)=12,000V/V.Ifthethirdcomparatorstageprovidesaminimumgainof60,therequiredcombinedgainfromthefirsttwo
stageswillbe200,or
foreachofthefirsttwostages.Theresponsetimeofthethirdstagedifferentialcomparatorislargelydeterminedbyitsparasitic
capacitances,thecurrentssuppliedbytransistorsQ17andQ19,andtheamountoftheoverdrivevoltageavailableattheinputofthedifferentialstage.Thebiascurrentis
givenby

Assumingthat(W/L)17=(W/L)19=(W/L)6,thecurrentsoftransistorsQ17andQ19willbe100A.Wewillchoosethedimensionsoftheinputstagesourcecoupled
transistorsasL13=L14=1mandW13=W14=200m,andL15=L16=L18=2mandW15=W16=W18=40mfortransistorsQ15,Q16,andQ18.Sincetheoverall
gainofthefirsttwostagesisapproximatelyAd 200,soa250Vdifferentialsignalattheinputofthefirststagewillappearasa50mVoverdrivesignalattheinput
ofthethirdstage.ItwasverifiedthroughSPICEsimula

Page350

Figure8.34
Directcoupledthreestagecomparatorcircuit.

Page351

tionthatadifferentialoverdrivesignalof50mVwillcausethethirdstagecomparatortoswitchinlessthan50ns.
Thenextstepinthedesignprocessistoselectcomponentandcurrentvaluesforthetworesistiveloaddifferentialamplifiers.Using(W/L)9=(W/L)12=2(W/L)6,the
differentialstagetailcurrentswillbeI0=2100=200A.ThenifwechooseR1=R2=R3=R4=RB=7000 ,thevoltagedropacrosstheloadsofthedifferential
amplifierswillbeVRL=7000(200106)/2=0.7V.ThisresultsinanoutputbiasvoltageofVo=30.7=2.3V,whichisanadequatevaluefora3Vpower
supplyvoltage.Inaddition,themaximumoutputvoltageswingofthedifferentialstageisawellcontrolledvaluegivenby Vo=2001067000=1.4V.Thegain
oftheresistiveloaddifferentialamplifierwasderivedearlierandisgivenbyEq.(5.12)as

wheregmiisthetransconductanceoftheNMOSinputdevices.ForthetargetgainofAd=14.2thetransconductancecanbecalculatedfromEq.(8.112)as

UsingthetransconductancefactorfortheNMOStransistorgiveninSection8.2
fromthefollowingrelationship:

theaspectratiosoftheinputdevicescanbecalculated

whereIi=I0/2=100A.Substitutingthevalueofgmi=2.03103mhosintoEq.(8.114),theW/Lratiocanbecalculatedas(W/L)i 182.Onceagain,usinga
channellengthofLi=1mforallinputstagesourcecoupleddevicesresultsinW7=W8=W10=W11=182mforthechannelwidths.Forsimplicityandadded
margin,thechannelwidthswereincreasedto200m.
Theresponsetimeoftheresistiveloaddifferentialamplifierisdeterminedmainlybytheresistanceoftheloadandtheparasiticcapacitancesconnectedtotheoutput
nodes.Theparasiticsincludethejunctioncapacitancesofthedraindiffusionandthegatetosource(CGs)capacitancesofthedevicesthatloadtheoutputnode.For
thecomparatorofFig.8.34anestimateofthetotalcapacitancesattheoutputofthedifferentialstageis1.5pF.Hencethetransientresponsetimeconstantofeach
differentialamplifierisontheorderof 0=1.510127000=10.5ns,whichiswellwithinthelimitsoftherequired200nsresponsetime.
AtthispointthedimensionsofalldeviceshavebeendeterminedandtheschematicofthethreestagecomparatorandthecorrespondingdevicesizesareshowninFig.
8.34.ToverifytheaccuracyofthedesignaSPICEsimulationwascarriedouttoanalyzethecircuit.Asinglepowersupplyvoltageof3Vwasusedandoneinput

Page352

Figure8.35
ResponseofthecomparatorofFig.8.34toa250Voverdrive.

ofthecomparatorwasconnectedto1.5V,whichwasconsideredtobeanalogground.Foraworstcasecondition,theinputoverdrivewasvariedfrom0V(heavily
saturatedcondition)to1.50025V(250Vabovethe1.5Vreferencegroundvoltage).TheactualresultoftheSPICEsimulationisillustratedinFig.8.35.Asthe
figureshows,theresponsetimeisontheorderof105ns,whichisclearlywellwithintherequired200nsdesignlimit.
Thelastexampleofthissectiondealswiththedesignofacomparatorwithhysteresis.Thehysteresisisacharacteristicofthecomparatorwhichchangestheinput
thresholdvoltageasafunctionoftheoutputlevel.ComparatorswithhysteresiswerediscussedinSection5.4.Thepurposeofthisexampleistodesignacomparator
with76mVhysteresisbasedontheregenerativedifferentialamplifierofFig.5.23.ThecompleteschematicofthecomparatorwiththeoutputstageandaVBEbased
biasgeneratorisshowninFig.8.36.ThebiascurrentwascalculatedintheprecedingexampleasIB=100A.Assumingthat(W/L)0=2(W/L)16,thetailcurrentof
theregenerativedifferentialamplifierwillbeI0=200A.WenextchoosethedimensionsoftheinputsourcecoupleddevicepairsasW1=W2=100mandL1=L2
=2m.Forsimplicityweassumethatplus(+1.5V)andminus(1.5V)suppliesareusedandthatthegateofQ2istiedtoanalogground(0V).Thusthepurpose
ofthisexampleistocalculatethedimensionsoftheremainingdevicessothatthecomparatorexhibitspositiveandnegativethresholdpointsof+38mVand38mV,
respectively.

Page353

Figure8.36
Comparatorwithhysteresis.

ThetriggerpointsoftheregenerativecomparatorofFig.8.36werecalculatedinChapter5asEqs.(5.28)and(5.29)andisrepeatedhereforconvenience:

wherethe(W/L)irepresenttheaspectratiooftheinputdevicesand =(W/L)5/(W/L)3=(W/L)6/(W/L)4.UsingthetransistordeviceparametersgiveninSection8.2
(k n=55106A/V2),wehave

SimplifyingEq.(8.116)andsolvingfor

weget

SolvingEq.(8.117)yields 1.5.Usingthisvalueof ,theaspectratiooftheloadtransistorscanbecalculatedfromthefollowingrelationship:

UsingL=2mforalltransistorsinEq.(8.118)resultsinthefollowingrelationshipbetweenthechannelwidths:

Page354

Figure8.37
SimulationresultsofthecomparatorofFig.8.36withhysteresis.

Next,usingW3=W4=40m,thewidthsoftransistorsQ5andQ6canbecalculatedfromEq.(8.119)asW5=W6=60m.Finally,areasonablechoiceforthewidths
ofthetransistorsinthedifferentialtosingleendedconverteris

where,onceagain,L=2mhasbeenassumedforthelengthsofalltransistorsintheoutputstage.
InthisexampletheaspectratiosofthedeviceswereselectedinsuchawaythatEq.(8.118)wassatisfied.Thechoicesoftheactualdevicedimensions,however,
weresomewhatarbitrary.Anothercriterionthatwasignoredinthisanalysisisthecomparatortransientresponsetime.Thesizesofthedevicesdeterminethevaluesof
theparasiticcapacitancesatthecriticalnodes,whichaffectthetransientresponse.Imposingarequirementontheminimumresponsetimesetsanadditionalcondition
thatcanbeusedfortheoptimumselectionofthedevicedimensions.
ThecircuitofFig.8.36wassimulatedonSPICEandthesimulationresultsareillustratedinFig.8.37.Noticethatastheinputstartsfromanegativevalueandgoes
positive,theoutputdoesnotmakeatransitionuntiltheinputreachesthepositivethreshold,38mV.Oncetheoutputswitchesstate,theeffectivethresholdischanged
to38mV.Whentheinputreturnsinthedirectionofitsoriginalnegativevalue,theoutputdoesnotchangeuntiltheinputreachesthenegativetrippointof38mV.
Theamountofthehysteresisshouldnormallybeequaltoorgreaterthanthelargestexpectednoiseamplitude.

Page355

Figure8.38
Opampwithnonzerooutputimpedance(Problem8.4).

Problems
8.1.IntheinputstageofthecircuitofFig.8.2,assumethatQ1andQ2areimperfectlymatchedsuchthatgm1=(1+ )gm2.Showthatifacommonmodevoltagev c
existsattheinput,thecorrespondingCMRRis(1/ )gmi/gdi.
8.2.ProveEq.(8.17)forthecircuitofFig.8.1.
8.3.FindthedcoffsetvoltageoftheopampofFig.8.6ifthecurrentsofthetwosourcesshownasIaremismatchedby .
8.4.ShowthatinthecircuitofFig.8.38,theeffectiveoutputimpedanceisRout=(Ac+1)/A,whereAc Z2/Z1istheclosedloopgainofthestage.AssumethatA
|Z1|and|Z2|.
References
1.P.R.GrayandR.G.Meyer,AnalysisandDesignofAnalogIntegratedCircuits,Wiley,NewYork,1977.
2.O.H.Schade,Jr.,IEEEJ.SolidStateCircuits,SC3(6),791798(1978).
3.G.C.Temes,IEEEJ.SolidStateCircuits,SC15(3),358361(1980).
4.K.MartinandA.S.Sedra,IEEETrans.Circuits,Syst.,CAS28(8),822829(1981).
5.P.R.GrayandR.G.Meyer,IEEEJ.SolidStateCircuits,SC17(6),969982(1982)
6.W.C.Black,D.J.Allstat,andR.A.Reid,IEEEJ.SolidStateCircuits,SC15(6)929938(1980).
7.K.Ohara,P.R.Gray,W.M.Baxter,C.F.Rahim,andJ.L.McCreary,IEEEJ.SolidStateCircuits,SC15(6),10051013(1980).
8.P.R.Gray,R.W.Brodersen,D.A.Hodges,T.C.Chai,R.Kameshiro,andK.C.Hsieh,Proc.Int.Symp.CircuitsSyst.,pp.419422,1982.

Page357

Index
A
Acceptors,18
ADC,seeAnalogtodigitalconverter
A/Dconverter,seeAnalogtodigitalconverter
Analogtodigitalconverter(ADC):
basicprinciples,255263
differentialnonlinearity(DNL),261
gainerror,261
integralnonlinearity(INL),261
linearconversionrange,258
missingcodeerror,261
offseterror,260
quantizationerror,258
signaltonoiseratio(SNR),260
whitenoise,260
chargeredistribution,284
countingandtracking,294295
flash,9,263270
integrating,295300
intermeshedladdersubranging,278
interpolatingflash,257,270273
lowspeedconverters,257
Nyquistrateconverters,257
oversampling,14
resistorcapacitorhybrid,284
resistorstringcircuit,284
servo,295
singleslope,257
subranging,274
successiveapproximation,9,257,282294
twostepflash,273282
Amplitudemodulator,seeModulators
Analogsystems,12
Autozeroingcomparator,177182
B
Bandgapreferencevoltage,45
Biascircuits,4855
deltaVBEbased,53
supplyindependent,5053
temperaturedependence,53
thresholdbased,50
VBEbased,51
Bodeplot,114
Bodyeffect,2930
BubbleerrorsinflashADCs,265
Builtinvoltage,20
Bulk,23
C
Cascode:
currentsource,59
highswing,61
improvedhighswing,62
gainstage,68
frequencyresponse,91
Channel,23
Channellengthmodulation,25
ChargemodeDACs,231234
singlestage,231
twostage,233
ChargeredistributionADCs,290291
Clockfeedthrough,140,183,268
Clockperiod,3
CMFB,seeCommonmodefeedback

Page358

CMOS:
differentialstagewithcascodeload,102
process,4445
CMR,seeCommonmoderange
CMRR,seeCommonmoderejectionratio
Commoncentroid,327
Commonmoderange(CMR),126
differentialstage,127128
singlestagecascodeopamp,129131
Commonmodefeedback(CMFB),142143
continuoustime,143147
switchedcapacitor,147148
Commonmoderejectionratio(CMRR),96,307
Comparators:
autozeroing,177182
cascadedinverters,180
differential,182192
fullydifferential,198205
offset,175
canceled,185186,198
overdrive,177182
regenerative,192197
resistiveload,190
switchedcapacitor,181187
CountingADCs,295
Currentmirrors,5563
cascodecurrentsource,59
highswingcascodecurrentsource,61
improvedhighswingcascodecurrentsource,62
Wilsoncurrentsource,57
CurrentmodeDACs,238244
segmented,244252
D
DAC,seeDigitaltoanalogconverter
D/Aconverters,seeDigitaltoanalogconverters
Deltasigma:
converter,14,214
modulator,15
Depletion:
modeFET,28
region,20
Dielectricconstant,21
Differentialamplifier,7784
Differentialcomparators,182191
gainenhanced,188
offsetcanceled,185186
regenerative,192197
resistiveload,190
switchedcapacitor,187189
DifferentialnonlinearityinDACs,218
Differentialnonlinearityerror(DNL),261
Differentialstageconstantgm ,169170
Diffusion,19
Digitalsystems,1
Digitaltoanalogconverter(DAC):
basicprinciples,214218
differentialnonlinearity(DNL),218
gainerror,218
integralnonlinearity(INL),216
leastsignificantbit(LSB),215
LSB,seeLeastsignificantbit
monotonicity,218
mostsignificantbit(MSB),215
MSB,seeMostsignificantbit
offsetbinarycode,215216
offseterror,215
one'scomplementcode,215216
signmagnitudecode,215216
two'scomplementcode,215216
chargemode,231234
currentmode,238244
deltasigma,214
hybrid,234238
intermeshedladder,221222
Nyquistrate,214
oversampling,214
resistiveladder,219221
segmentedcurrentmode,244252
voltagemode,218231
DNL,seeDifferentialnonlinearity
Dopants,18
Drain,23
Drift,23
Dualslopeconverters,257
Dynamichysteresis,193
Dynamiclatches,205
Dynamicrange,312
ofCMOSopamps,126132
F
FlashA/Dconverters,263270
bubbleerrors,265
interpolating,270273
thermometercode,263
Foldedcascodesinglestageopamp,104106
Frequencycompensation,112,116,156,162,167
Frequencyresponse,97,307
ofMOSamplifiers,8492
cascodestage,87
differentialstage,91
sourcefollower,89
withactiveload,85
Fullwaverectifier,9
Fullydifferentialamplifier,12,140148
Fullydifferentialcomparators,198205

Page359

Fullydifferentialopamps,140148
commonmodefeedback,142143
G
Gainerror:
inADCs,261
inDACs,218
Gainmargin,114
Gainstages,6374
activeload,65
cascode,68
doublecascode,71
frequencyresponse,84
MOStransistorload,64
resistiveload,63
Gate,23
H
Hole,18
Hybrid:
DACs,234238
resistercapacitorADCs,292293
Hysteresis,193
I
IGFET,28
Impactionization,40
INL,seeIntegralnonlinearityerror
Inputoffsetstorage(IOS),198
Integralnonlinearity:
inADCs,261
inDACs,218
Integralnonlinearityerror(INL),261
IntegratingADCs,295300
dualslope,296,298
singleslope,296
Interpolatingconverter,257
InterpolatingflashADCs,270273
Inversionlayer,23
IOS,seeInputoffsetstorage
J
JFET,29
L
Latches,205208
dynamic,105
Latchup,41
Leastsignificantbit(LSB),215
Linearconversionrange,258
Loopgain,113
LSB,seeLeastsignificantbit
M
Metaloxidesemiconductors(MOS),21
Millercapacitance,200
Millereffect,68
MissingcodeerrorinADCs,261
Mobility,24
Modulators,6
MonotonicityinDACs,218
MOS,seeMetaloxidesemiconductor
structure,21
capacitor,21
transistors,2127
unitsandconstantsfor,30
MOSFET,seeMOStransistor
MOStransistor(MOSFET):
bodyeffect,2930
bulk,23
depletionmode,28
drain,23
currentrelationsfor,31
inversionlayer,23
linearregion,24
nchannel,25
parasiticcapacitances,3336
source,22
substrate,23
thresholdvoltage,23
unitsandconstantsfor,30
Mostsignificantbit(MSB),215
MSB,seeMostsignificantbit
N
nchanneltransistor(NMOS),25
NestedMillercompensation,112124
NMOS,seenchanneltransistor
NoiseinCMOSopamps,137140
NoiseinMOSFETs,4144
flicker1/fnoise,44
shotnoise,41
thermalnoise,42
Noiseinopamps,97,312
nwell,45
O
Offsetbinarycode,215216
OffseterrorinADCs,260
OffseterrorsinDACs,215
Offsetvoltage,96
Offsetcanceledcomparators,185186,198
One'scomplementcode,215216
OOS,seeOutputoffsetstorage
Opamps,seeOperationalamplifiers
Operationalamplifiers(OpAmps),95100
compensation,112126
dynamicrange,126132
finitegain,304
finitelinearrange,304
fullydifferential,12,140148
noise,137140
offsetvoltage,304
outputstages,149164
practicalconsiderations,303
railtorailinputstages,164170

Page360

Operationalamplifiers(OpAmps)(Continued)
randomoffset,304
slewrate,133137
systematicoffset,304
transientresponse,133
Outputoffsetstorage(OOS),200
Outputstages,149164
classAB,149
combinedclassABandclassB,159160
complementarypushpull,156
pushpull,156,162
Outputvoltageswing,127
twostageopamp,129
Oversamplingconverter,14,214
P
Parasiticcapacitances,3339
PCA,seeProgrammablecapacitorarray
pchanneltransistor,seePMOS
Peakdetector,9
Permitivity,21
Phasemargin,114
Pinchoff,25
Pinchoffvoltage,29
PMOS,26
pnjunction,18
Polesplittingcapacitor,112,156,162,167
compensation,117121
Powersupplyrejection(PSR),312
Powersupplyrejectionratio(PSRR),99,313
Programmablecapacitorarray(PCA),9,231232
PSR,seePowersupplyrejection
PSRR,seePowersupplyrejectionratio
Q
Quantizationerror,258
R
Railtorailinputstages,164170
Rectifiers,seeFullwaverectifier
Regenerativecomparators,192197
Relativepermitivity,seeDielectricconstant
Replicabiasing,190
Resistiveloaddifferentialstages,190191
S
Sampleandholdcircuit,228229
SAR,seeSuccessiveapproximationregister
Saturation,25
Saturationcurrent,20
SC,seeSwitchedcapacitorbranchSwitchedcapacitorcircuitsSwitchedcapacitorfilters
Schmitttriggers,192197
SegmentedcurrentmodeDAC,244252
selfcalibrating,248252
SelfcalibratingcurrentDACs,248252
Semiconductors,1721
ntype,18
ptype,18
ServoADCs,295
Signmagnitudecode,215216
SignaltoNoiseRatio(SNR),260
Singleslopeconverters,257
Singlestageoperationalamplifiers,100106
Slewrate,307
ofopamps,97,133137
SNR,seeSignaltonoiseratio
Source,22
followers,7476
StabilityandcompensationofCMOSamplifiers,112126
SubrangingADCs,274
Substrate,23
Subthresholdregion,seeWeakinversion
SuccessiveapproximationADC,257,282284
SuccessiveApproximationRegister(SAR),282
Switchedcapacitor:
branch,3
circuits,3
comparators,182187
filters,4,6
sampleandholdcircuit,228
invertingamplifier,228
noninvertingamplifier,228
T
Thermometercode,263
Thermometertypedecoder,239
Thresholdvoltage,23
Transientresponseofopamps,133
Two'scomplementcode,215216
Twostageoperationalamplifiers,106112
U
Unitygainfrequency,114,132
V
VoltagemodeDACs,218231
intermeshedladder,221222
resistiveladder,219221
twostage,222227
Voltagereference,45
W
Weakinversion,39
Whitenoise,42
Wilson'scurrentsource,57
Z
Zeronullingresistor,156,162,167