2015 International Conference on Industrial Instrumentation and Control (ICIC)

College of Engineering Pune, India. May 28-30, 2015

Floating Point FPGA Architecture of PID Controller

Jagannath Wadgaonkar1 , Kalyani Bhole2 , Prateek Singh 3
Department of Instrumentation and Control
College of Engineering Pune, India 411005
1 jagannath.vw@gmail.com, 2 kab.instru@coep.ac.in, 3 prateek29singh@gmail.com
AbstractProportional Integral Derivative (PID) Controller
is most well-known and consistent with industry. It is applied
to many applications such as ow, temperature, motor control,
robotic applications, biomedical applications, etc. Many applications demands fast response. Parallel implementation of proportional, integral, derivative action accelerates its response which
can be achieved by using eld programmable gate arrays (FPGA).
Floating point implementation of PID gives more truthfulness. In
this paper, a sincere effort has been made to design and implement
the oating point parallel architecture of PID controller using
SPARTAN 3E(XC3S-500e) FPGA.

Keywords: FPGA, HDL verilog, Matlab, system generator,

IEEE 754.
I.

I NTRODUCTION

The accurate temperature control is one of the important

parameter in many industries, this can be achieved by using
PID controller. PID controllers are used in various elds like
Building automation, Bio-instruments, process automation.
Also it is used in many industries like chemical, beverages,
petroleum, process industry etc, where the most accurate
control is to be required . L.Charabi el.al published their
research work on efcient design methodology for FPGA
implementation of control system [1]. FPGA implementation
have the advantages that they are relatively cheap and exible
as compared to other hardware implementations. In this paper,
we implemented the PID controller in FPGA. The FPGA is
very fast and most efcient integrated circuit. The hardware
description language(HDL) is used in FPGA to communicate
with hardware which is very easily interfaced with them, Logic
gates are used in FPGA as a memory blocks, these logic gates
are interconnected with each other due to these feature it performs complex functions and compute fast response. J. Lima,
R. Menotti, J. M. Cardoso, and E. Marques introduced the
methodology of FPGA based PID controllers [2]. FPGA gives
us many advantages like fast I/O system, parallel computation
bidirectional, and solving complex functions etc, which result
in cost reduction.

[3], where they discussed on the context of a comparison of

distributed arithmetic(DA) based and multiplier based design.
Compared the slices and clock cycle, found that they used
437 slices and 406 ip ops(FFs) and we use 244 slices and
129 FFs. Prof Dr.Udaykumar R.Y and his team implemented
the low power digital PID controllers on FPGA [4] its seems
that they required Minimum period:- 13.152ns, Maximum
output required time after clock: 20.391ns. In 2011, Yajuna
Chen and Qinghai Wu published their work on Design and
implementation of PID controller based on FPGA and genetic
algorithm in FPGA [5], their implementation utilizes more
resources.
S.L.Jung, M.Y.Chang, J.Y.Jyang, L.C. Yeh, and Y.Y.Tzou,
proposed the FPGA based control IC for ac-voltage regulation
[6] in 1999, where they designed the FPGA based control IC.
The major focus is on implementing minimum mathematical
algorithmic operation. Due to this it provides high accuracy
in minimum time period also using minimum adders and
multipliers result in minimum time period for program scan.
The structure of paper is fragmented in IV sections. Section
II explains PID controller, Section III focuses on FPGA implementation of PID controller where as Subsection 1 demonstrate
Fixed to oating point conversion (FFPC) and subsection 2
explains Proposed Architecture of FFPC, subsection 3 exhibits
Proposed Architecture of PID controller. In section III reveals
Results and Discussion where next section IV Concludes the
work.

II.

PID C ONTROLLER

Proportional Integral Derivative (PID) controller is most

widely used algorithm for many industries. It performs proportional, integral, derivative action on the error signal and generates a control signal accordingly. The mathematical equation
of PID controller is shown in below equation
t
PID= Kp*e(t) + Ki 0 e(t) dt+Kdd/dt e(t)(1)

The scientist Elmer sperry developed a concept of rst

PID controller in 1911, thereafter scientist Ricolas minorsky
published the theoretical analysis of PID controller and apply
this on ship steering. In 1990s PID was developed through
early theoretical concepts (ziglor nicolas, cohan coon method).
A conclusion of this paper is that proposed work introduces
oating point FPGA architecture of PID controller.
Yeun Fong Chan, M.Moallem and Wei Wang developed
and implemented the modular FPGA based PID controller
978-1-4799-7165-7/15/$31.00 2015 IEEE

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Fig. 1.

Block diagram of PID

The set point(SP) is xed in the PID controller, when the

sensor senses the plant output (PV) then this output is feedback
to PID controller, where the PV and SP are compared with
each other and the corrective signal is produced. L.Samet, and
N. Masmoudi explained the multi loop control in digital PID
controller [7].
The output signal of PID controller is a summation of (P
+ I + D) which is corrected error signal. We can obtain the
desired system response by adjusting the corresponding gain
values (Kp, Ki, Kd ) respectively, for P, I and D action. These
gain values are nothing but the corrective factors which are
used as constant.
III.

TABLE I.
Single
Double

Sign
1
1

TABLE 1

Exponent
8
11

Fraction
23
52

Bias
127
1023

In xed numbers always there is some absolute error this

error is removed by using the oating point method. Floating
point numbers provides very large range due to these it reach
a high domain from very small numbers that is close to zero.
Due to these the controller output moves very exactly as per the
sensor output changes. Fig.2 shows the conversion of FFPC.

FPGA I MPLEMENTATION

The use of FPGA gives an advance feature in embedded

advancement. The FPGA benets the design lifecycle, it saves
time and integrate software and hardware in the design phase.
The development platform used in this paper is Xilinx:ISE design tools, system Edition:-14.7, Hardware:- SPARTAN
3E(XC3S-500e).
The FPGA implementation gives many advantages like recongurable architecture, low power consumption(best suitable
for biomedical application), variable clock frequency, handle
dense logic and memory elements offering very high logic
capacity, parallism of FPGA gives high speed
A. Fixed To Floating Point Converter (FFPC)
In many industries there, is a requirement of precise
output then there is a need to convert the xed numbers to
oating point numbers. Fixed to oating point conversion is a
conception of numeric stability. When the system requests an
accurate output means varying scales, then the oating point
numbers are preferred.
Proposed xed to oating point architecture IEEE 7542008 binary oating number representation is used worldwide
and accepted with its standard representation as single precision and double precision. Representations of single precision
oating-point data in the binary interchange formats are encoded in 32 bits in the three elds. IEEE 754 single precision
oating point representation number is represented as
Number=(-1)sign x b exponent x signicant - - - - - - - - - (2)
For binary format single precision and double precision
oating point parameter allocation is as shown in table I. Data
interchange between xed to oating point requires number of
clocks. This time requirement can be reduced by decoding
repeated steps in terms of digital logic. There are several
ways to represent real numbers on computers. Fixed point
places a radix point somewhere in the middle of the digits,
and is equivalent to using integers that represent portions
of some unit. IEEE oating point numbers have three basic
components: the sign, the exponent, and the mantissa. The
mantissa is composed of the fraction and an implicit leading
digit (explained below). The exponent base (2) is implicit
and need not be stored. The following table shows the layout
for single (32-bit) and double (64-bit) precision oating-point
values.
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Fig. 2.

Floating point conversion

B. Proposed Architecture Of Fixed to Floating Point Conversion (FFPC)

We have designed and implemented the arithmetic unit
operations on oating point conversion (FPC).J.Liang and his
team Contributes a lot in research of Floating point generation
from xed point numbers [8].The conversion of xed to
oating point (FFPC) is an important action in arithmetic
operations. To provide the demand of high resolution and
exactness,lead progress in the direction of oating point operations.

Fig. 4.

Fig. 3.

Architecture of PID

For the Integral output (I), the corrected error signal is

added to the previous signal and then its output is multiplied
to integral gain (Ki). Similarly the subtraction of previous
signal from corrected error signal and then multiplication
with derivative gain (Kd) gives derivative output (D). Various
algorithmic implementations are shown by S.F.Oberman and
M.Flynn in 1997 conference [10]. The nal output of PID
controller is the summation of the (P+I+D).

Architecture of FFPC

There is a digital relation in between xed point exponent

and the required shift. Using the gate level implementation in
FFPC, which greatly reduced the embedded and improved the
performance of the plant. Floating point conversion is hard but
the representation is very easier than xed point. Conversion of
the FFPC gives compensations like, it saves process execution
time. Fig.3 shows the gate level implementation of (FPC),
using logic gates.

Mathematical representation of discrete PID controller is

realized in terms of basic operations. Such as addition and
subtraction, which are easy to implement using FPGA. proportional, integral and derivative control actions are parallel
implemented. This proposed architecture is converted into
Hardware description language(HDL) i.e. veriolg using Xilinxs ISE platform. This algorithm is then simulated and tested
using MATLAB system generator toolbox.
IV.

M ATHEMATICAL R EPRESENTATION OF D ISCRETE PID

CONTROLLER

C. Proposed Architecture Of PID Controller

The proposed architecture shows the how the parallel process execution is to be done in FPGA, where the M. Moallem
shows the implementation of PID control algorithm in FPGA
technology [9]. Where as the multiplication of corrected error
signal (e) and proportional gain (Kp) gives proportional output
(P).
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The PID algorithm is the most popular feedback controller

used within the industries. It has been successfully used for
over 50 years. It is a robust easily understood algorithm that
can provide excellent control performance despite the varied
dynamic characteristics of processes.Action of PID controller
is dened by equation
 t
e(t)
e(t) dt + Kd
(1)
u(t) = Kp e(t) + Ki
dt
0
For hardware implementation, this equation is converted
into discrite form.Discrete derivative is represented by equation
2
f (k) f (k 1)
(2)
y(k) =
Ts

Where as discrete integration is given by equation 3


(f (k) f (k 1))
y(k) = y(t)dt = y(k 1) +
T s (3)
2
y(k) y(k 1) =

Ts
(f (k) f (k 1))
2

(4)

Ts
f (z)
2(1 + z 1 )

(5)

TABLE III.

Logic
Number of Flip Flops
Number of input LUTs
Number of Slices

P ROPOSED

Used
129
391
244

Available
9,312
9,312
4,656

Utilize
1%
5%
6%

By taking Z transform
y(z) (1 z 1 ) =

T s(1 + z 1 )
f (z)
2(1 z 1 )

(6)

(f (k) f (k 1))
Ts

(7)

(1 z 1 )
f (z)
Ts

(8)

y(z) =
Discrite derivative
y(k) =
Z transform

y(z) =
PID controller

u(t) = Kp e(t) + Ki

t
0

e(t) dt + Kd

e(t)
dt

(9)
Fig. 5.

Response of PID

Fig. 6.

Wavescope of PID Controller

substituting derivative and integral from equations 8 and 6,we

get
T s(1 + z 1 )
1 z 1
U (z)

= K p + Ki
+
K
d
E(z)
2(1 z 1 )
Ts
U (z)
1
)
E(z) (1 z
1
1
(1z )(1z )
Ts
U (z)
E(z) = Kp
Kd 1 Kd 2
2 Ts z Ts z

= Kp (1 z 1 ) + Ki T s(1z
2

(10)
+ Kd
(11)

Kp Z 1 +

(Ki T s)
2

U(z)(1-z1 ) = (Kp + (Ki 2T s) +

(Ki T s)
1 Kd
d
2 K
+ T s E(z)z 2
2
T s )E(z)z

(Ki T s) 1
z
2

Kd
T s )E(z)

(12)

Kd
Ts

+ (Kp +
(13)

U(k)=u(k+1)+a*e(k)+b*e(k-1)+c*e(k-2)

(14)

Where
a=Kp +

(Ki T s)
2

b=-Kp +

(Ki T s)
2

Kd
Ts

d
2K
Ts

c=Kd T s
V.

Table III shows resource utilization of proposed PID controller. While comparing the Table I & Table II it utilizes the
less space in the FPGA, so the system response is greatly
increased. Also the g 4. shows the Response of PID in
MATLAB/SIMULINK, where we set the settling time as 100.
In g 5. the output Wavescope of PID controller is shown,
where these results clearly shows the superior controlled output
of PID controller.

R ESULT AND D ISCUSSION

TABLE II.

Logic
Number of Flip Flops
Number of input LUTs
Number of Slices

C ONVENTIONAL

Used
406
708
437

Available
9,312
9,312
4,656

Utilize
4%
7%
9%

VI.
Table II shows the results of resource utilization of conventional PID controller in FPGA, where it shows the used
slices, FFs and LUTs in FPGA SPARTAN 3E, also shows the
number of percentage used compared to availability[3].
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C ONCLUSION

In this complete work, we presented the novel approach of

oating point architecture of PID controller. The major focus
is on oating point implementation, which is very important
in control system to control plant accurately. The complete

work explain in this paper is implemented using XILINX

development platform, also we gone through experiment. The
complete system is connected to Matlab/simulink, where the
system generator toolbox is used to test the simulation result.
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