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NOTES ON MOSFET BASED ON SEDRA AND SMITH

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INTRODUCTION

3-terminal devices are more useful than 2-terminal devices since they are used in

applications ranging from amplification to digital logic and memories.

Principle: Voltage between two terminals is used to control current through the third

terminal.

o Device acts as a current source useful in amplification

o In extreme case control signal can be used in causing current in the third

terminal to switch from 0 to large value ( allowing the device to act as a

switch), which is the basic building block for digital circuits and memories.

3-terminal devices are

o BJT: Bipolar Junction Transistor

o MOSFET: Metal Oxide Semiconductor Field Effect Transistor.

MOOSFET is most widely used in design and fabrication of Integrated Circuits(ICs).

Advantages of MOSFET are

o Small size

o Manufacturing process simple

o Consumes less power

o ICs can be fabricated using MOSFETs , with few or no resistors

Thus >200 million MOSFETs can be packed in single IC of 100 mm2 area.

Two types of MOSFETs 1. Enhancement Type 2. Depletion Type

Device Structure

Two heavily doped n-type regions (n+ source and n+ drain) are created in the

substrate.

A thin layer of insulator SiO2 of thickness 2-50nm is grown on the surface of

substrate covering the area between source and drain regions.

Metal contacts are also made to source, drain and substrate.

Modern MOSFETs use poly-silicon to form the gate electrode in place of metal.

MOSFET also known as Insulated Gate FET (IGFET) since gate is insulated from

substrate.

Substrate forms p-n junction with source and drain.

These are kept reverse biased in normal operation.

Since drain is always positive w.r.t source the p-n junction can be cut-off by simply

connecting the substrate to the source.

Thus MOSFET can be considered as a 3-terminal device, Source (S), Drain (D) and

Gate (G).

The voltage applied to the Gate (vGS) controls the current flowing from Drain to

Source (iD) in the region labelled Channel Region.

This channel region has Length L of 0.1 m to 3m and Width W of 0.2 m to 100

m.

MOSFET is a symmetrical device i.e., drain and source can be interchanged.

If no bias to the gate is given MOSFET acts as two back to back diodes, namely n+

drain and p-type substrate one diode and p-type substrate and n+ source other

diode.

These back to back diodes prevent current conduction from drain to source when a

voltage vDS is applied i.e., the path between drain and source has very high

resistance (10 12 ohms).

If source and drain are grounded and positive voltage vGS is applied to gate, the

majority carriers (holes) in the p-type substrate below the gate (in the channel

region)are repelled and pushed downward into the substrate, leaving behind bound

negative charges associated with the acceptor atoms.

Also the positive gate voltage attracts electrons (majority carriers) from both n+

source and n+ drain regions in between the source and drain.

Now if a positive voltage is applied between drain and source, current flows through

the induced region carried by mobile electrons.

This induced region forms a channel for current flow from drain to source. Therefore

this MOSFET is called the n-channel MOSFET or NMOS Transistor.

The induced channel is also known as inversion layer because it is created by

inverting the substrate surface from p-type to n-type.

The value of vGS at which sufficient quantity of electrons accumulate in the channel

region to form a conducting channel is called the threshold voltage Vt whose typical

value is 0.5 to 1V.

The gate and channel form a parallel plate capacitor with oxide layer acting as the

dielectric.

A small vDS (=50mV) causes a current iD to flow through the induced n channel from D

to S.

Magnitude of iD depends on the density of electrons in the channel, which is

dependent upon vGS.

Specifically for vGS = Vt, the channel is just induced and current is negligibly small.

As vGS exceeds Vt more electrons are attracted into the channel, resulting in a

channel of increased conductance and decreased resistance.

This conductance is proportional to (vGS-Vt) also known as the effective voltage or

overdrive voltage.

Also the current iD is proportional to (vGS-Vt) as well as vDS.

Fig below shows the sketch of iD vs vDS for different values of vGS (for small values of

vGS).

MOSFET acts as a linear resistance here and its value is infinite for vGS<=Vt and

decreases as vGS exceeds Vt.

Since channel size increases as vGS exceeds Vt, MOSFET is called enhancement

type MOSFET or enhancement mode MOSFET.

vDS appears as a voltage drop across the length of the channel, i.e., as we move

from source to drain the voltage between gate and the point on the channel

decreases from vGS at the source to vGS-vDS at the drain.

The channel depth is proportional to this voltage, i.e., channel is deepest at source

end and shallowest at the drain end.

Also as vDS is increased the channel becomes more tapered as shown in the fig 1

below and its resistance increases correspondingly. Thus iD vs vDS curve bends as

shown in the fig 2.

As vDS is increased, when vDS= vGS-Vt, the channel depth at the drain becomes almost

zero and the channel is said to have pinched off.

If vDS is increased beyond this, it will have no effect and the drain current saturates

and MOSFET is said to have entered the saturation region of operation. Thus vDS

sat = vGS Vt.

For every vGS>=Vt there is a corresponding vDS sat and the device operates in the

saturation region when vDS>= vDS sat. And the region where vDS < vDS sat is called the

triode region

Derivation of iD vs vDS

If vGS>Vt and vDS<vGS-Vt then Triode Region

If vGS>Vt and vDS>=vGS-Vt then Saturation Region

Consider the triode region at which the channel is tapered as shown in the figure

below.

Gate and channel region form a parallel plate capacitor with oxide acting as

dielectric.

The capacitance /unit area Cox is then given by

Cox = ox/tox ; where tox is the thickness of oxide layer and the permittivity

ox =3.9 o=3.9 x 8.854 x 10 -12 = 3,45 x 10 -11 F/m

Consider an infinitesimal strip dx of gate at distance x from source. The capacitance

of this strip is Cox W dx.

The charge stored on this strip is

......................................(1)

Voltage vDS produces electric field along the channel, this electric field at the point x

is written as

E(x) = -dv(x)/dx

The electric field causes electric charge to drift towards the drain with velocity dx/dt

given by

dx/dt = - n E(x) = -n dv(x)/dx

.....................................(2)

where n is the mobility of electrons.

The resulting drift current is given by

i= dq/dt = (dq/dx )(dx/dt)

Substituting from (1) and (2) we get

i = -n Cox W [ vGS v(x)-Vt] dv(x)/dx

This is the source to drain current. Therefore the drain current is

iD= -i = n Cox W [ vGS v(x)-Vt] dv(x)/dx

i.e., iD dx = n Cox W [ vGS v(x)-Vt] dv(x)

Integrating both sides we get

iD dx =

substituting this the current equation in the saturation becomes

iD = (n Cox ) (W/L) [ (vGS -Vt )2)]

substituting kn = n Cox known as process trans-conductance parameter we get

iD = kn (W/L) [ (vGS -Vt ) vDS ( vDS 2/2)] in triode region

iD = (1/2)kn (W/L) [ (vGS -Vt )2)]

in saturation region

The p-channel MOSFET

Substrate

Charge carriers

vGS and vDS

iD

Size

Speed

Supply voltage

n-channel

p-type

Electrons

Positive

D to S

Smaller

Faster

Lower

p-channel

n-type

Holes

Negative

S to D

Bigger

Slower

Higher

Dominant IC technology for both analog and Digital even though somewhat more

difficult to fabricate than NMOS.

CMOS has taken over many applications which were using bipolar devices.

Fig below shows a cross section of CMOS chip.

CUURENT-VOLTAGE CHARACTERSTICS

Circuit Symbol

fabricated on a specially created region called n-well.

PMOS and NMOS are separated by a thick SiO2 region.

We assumed that when vGS < Vt then iD=0 and device is cut-off .

However a small drain current flows. In this sub-threshold region of operation iD is

exponentially related to vGS

There are special but growing number of applications that make use of sub-threshold

region of operation.

Fig below the circuit symbols of NMOS.

Spacing between two vertical lines representing gate and channel indicates the

insulation (dielectric SiO2 layer).

Arrowhead represents the polarity of NMOS.

It also represents p-type body and n-channel

MOSFET is a symmetrical device; however it is useful to designate one as Source

and other as drain.

The simplified symbols are shown in fig where body is connected to source.

Fig 1 shows the NMOS with voltages vDS and vGS applied and with normal direction of

current flow.

Fig 2 shows a typical set of iDvDS curves, which show three distinct regions; cut-off,

triode and saturation.

The Saturation is used to operate the MOSFET as a amplifier.

The Cut-off and Triode region are used to operate as a switch.

o The device is Cut-off when vGS<Vt .

o In the Triode Region vGS>Vt

........

(induced channel)

and vDS<vGS-Vt ........

(conduction channel)

and the drain current is given by

iD = kn (W/L) [ (vGS -Vt ) vDS ( vDS 2/2)]

o In the linear region vDS is sufficiently small then we can neglect vDS2, then

we get

iD = kn (W/L) [ (vGS -Vt ) vDS]

o Then the resistance is given by

rDS = (vDS/iD)at (vGS=VGS) = [kn (W/L) (VGS -Vt )]-1

o

Vov = VGS>Vt

...... (induced channel)

and vDS>=vGS-Vt ......... (pinched off channel)

and the drain current is given by

iD = (1/2)kn (W/L) [ (vGS -Vt )2)]

At the boundary

o vDS = vGS-Vt

The figures below so the vGS vs iD curve and the Large signal equivalent circuits

o

iD. This means incremental resistance looking into drain of a saturated MOSFET

is infinite.

However this is only an approximation.

Once the channel is pinched off at the drain end, further increase in vDS moves

the pinch off point slightly away from drain towards the source, creating a

depletion region at the end of channel and drain, as shown in the fig 1 below

effectively reducing the channel length from L to L. This phenomenon is called

Channel Length Modulation.

Now the voltage across the channel will be vDSsat = vGS Vt and vDS-vDSsat appears

across the depletion region.

Now the drain current is given by

iD= (1/2) Kn (W/(L- L))( vGS Vt)2

= (1/2) Kn (W/(L(1- L/L)))( vGS Vt)2

= (1/2) Kn (W/L)(1+L/L)( vGS Vt)2

where L/L << 1

if we assume L vDS i.e., L = vDS where is the process technology

parameter with dimension m/V we get

iD = (1/2) Kn (W/L) (1+ /L vDS) ( vGS Vt)2

consider = /L where is the process technology parameter with dimension

V-1 we get

iD = (1/2) Kn (W/L) ( vGS Vt)2 (1+ vDS) ......................(1)

The change in current iD due to channel length modulation is given by

iD = (1/2) Kn (W/L)( vGS Vt)2 vDS

.......................(2)

Because of the channel length modulation the iD vs vDS characteristic is as shown

below in fig 2

FIG 1

FIG 2

Substituting this in (1) gives

0 = (1+ vDS)

i.e., vDS = -1/

...............................(4)

from (3) and (4) we get

VA = 1/

process technology dependent with dimension V/m (typical values 5 to 50)

This VA is called Early Voltage.

(2) gives that for a change in vDS their is a change in iD

Therefore the Output Resistance is given by

ro = (iD/ vDS)-1 at vGS = VGS constant

= [ (1/2) Kn (W/L)( VGS Vt)2 ]-1

Which can be written as

ro = 1/( ID ) = VA/ID ...............................(5)

where ID the drain current is given without channel width modulation given by

ID = (1/2) Kn (W/L)( VGS Vt)2

i.e., output resistance is inversely proportional to drain current. The large signal

model incorporating ro is as shown below

Characteristics of a pmos

In cut off

vGS > Vt

Triode region

vGS <= Vt and vDS >vGS-Vt

and current iD is given by

iD = kp (W/L) [ (vGS -Vt ) vDS ( vDS 2/2)] where kp= p Cox and p=0.25 to 0.5 n

Saturation Region vGS <= Vt and vDS <=vGS-Vt

and current iD is given by

iD = ()kp (W/L) (vGS -Vt ) 2(1+ vDS)

Source is connected o substrate to keep substrate to channel p-n junction cut off

To maintain all MOSFETs (in a IC) substrate to channel junction in cutoff

condition, the substrate is connected to most ve power supply for nmos( & most

+ve for pmos)

This results in a large depletion region.

The effect of this VSB is that, the threshold voltage Vt required to overcome the

cutoff is increased & it is given by the equation

Vt =Vt0 + (

2f +VSB

2f

) ................................(6)

Where Vt0 is the threshold voltage when VSB = 0, f is the physical parameter with

2 f = 0.6 and is fabrication process parameter, given by

=

Where q is electronic charge 1.6 X 10-19 C, NA is acceptor doping concentration of

p-substrate and Si =permittivity of Si = 11.7 0 = 11.7 x 8.854 x 10-12 =1.04 x 10-10

has dimensions of

and

V

, VSB is +ve for reverse biasing

Equation (6) gives that an incremental change in VSB gives an incremental

change in Vt which in turn results in incremental change in iD.

i.e., body voltage controls iD & body acts as another gate. This phenomenon is

known as Body Effect and is known as Body Effect Parameter.

Temperature Effects

| Vt | decreases by about 2 mV for every 1o C rise in temperature.

This increases the drain current as temperature is increased.

Also Kn decreases with temperature & its effect is a dominant one giving a overall

effect of decreasing the drain current as temperature increases.

As drain voltage is increased to a high value (20 to 150), Avalanche Breakdown

occurs. This results in rapid increase in current ( known as Weak Avalanche).

Another breakdown occurs at lower voltage ( 20 V), which occurs in devices

having shorter channels called Punch Through (zener). The depletion region of

drain now extends till the source, resulting in a large drain current.

Both the above does result in permanent damage.

Another breakdown is when gate to source voltage exceeds 30 V. This ruptures

the SiO2 layers and leads to permanent damage.

MOSFET has high input resistance & very small input capacitance, thus a

amount of static charge on the capacitance can cause its breakdown voltage to

exceed. Protection mechanisms such as clamping diodes are used to avoid this

In the saturation region MOSFET acts as a voltage controlled current source i.e.,

changes in vGS give rise to changes in iD.

Thus MOSFET can be used as a Trans-conductance Amplifier.

The relationship between vGS and iD is highly nonlinear( Square Law).

To linearize it we provide dc biasing where operate the MOSFET at a dc voltage

VGS & corresponding ID & then superimpose the voltage signal vgs to be amplified

on the dc voltage VGS .

If vgs is kept small, the resulting change in drain current can be made nearly

proportional to vgs.

Fig (a) shows circuit of a Common Source (CS) MOSFET amplifier and fig (b)

shows the output characteristic of the MOSFET circuit.

i.e., iD vGS

Also from fig (a)

vo = vDS = VDD RD iD.

Thus giving a voltage amplifier.

vo for various values of vi can be found & plotted and the plot for the same is

known as Transfer Characteristic.

vDS = VDD RD iD.

i.e., iD = (VDD/ RD) (1/RD) vDS

The above equation is a straight line ( linear ) representation between iD and vGS

with the line drawn in fig (b) having a slope of 1/RD.

Since RD is considered as Load Resistor, the straight line is known is called the

Load Line.

Since vGS = vI, we see that the MOSFET is cut off, iD = 0 and vo = vDS = vDD and

MOSFET will be operating at pt A in fig (b) above.

As vI increases MOSFET turns ON, iD increases and vD decreases. Since vo = vDS

is initially high compared to vGS the MOSFET is in saturation and operating point

moves from point A to point B.

A point Q, known as quiescent operating point is identified close to the middle of

point A to point B where vGS = VIQ = VGSQ , vDS = VOQ = VDSQ & iD = IDQ

Saturation region continues until vo decreases to the point that is below vI -Vt

(point B). At this point (pinch off Point) vDS = vGS-Vt & MOS enters the triode

region.

At B, VOB = VIB Vt

For vI > Vt the transistor is deeper into saturation region.

Eventually vO decreases towards zero, when vI = VDD & operating point is at C

Using all the above discussion we can plot vI vs vO giving a Transfer

Characteristic as shown in the fig (c) below

Operation as a Switch

When vI < Vt the MOS is cot off ( turned OFF) resulting in vO = VDD.

When vI VDD , the MOS operates around C & is turned ON (triode region) & vO is

very small i.e., vO = VOC

Thus Common Source (CS) MOS can be used as a logic inverter with low

voltage close to 0 and high voltage close to VDD

However CMOS device acts as a better inverter.

The device is dc biased closed to the middle of characteristic curve.

This dc biased point is known as Quiescent Operating Point (Q).

The input signal to be amplified vi is superimposed on VIQ (input quiescent

voltage).

vi is kept sufficiently small so as to operate the device in almost linear segment of

the transfer curve, resulting in a proportional output voltage vo.

However vo will be larger vi than by a factor Av (voltage gain of the amplifier) at Q

given by

Av = ( dvo /dvi ) at vI = VIQ

This voltage gain equal to the slope of the transfer characteristic at point Q and is

negative and hence CS amplifier is inverting.

Also vo will be superimposed on VOQ = VDSQ

This should be such a value as to give maximum output signal swing i.e., it

should be lower than VDD and higher than VOB by a sufficient amount.

If VDSQ is close to VDD , the positive portion of the input signal will be clipped.

If VDSQ is close to VOB , the negative portion of the input signal will be clipped

Further value of RD should be chosen properly because it determines the transfer

curve. This is illustrated in the fig below

The cut off region segment XA, where vI < Vt & vO = VDD.

The saturation segment AQB, where vI > Vt & vO >vI- Vt.

Substituting iD from

iD = (1/2) Kn (W/L) ( vI Vt)2

into vO = VDD RD iD. Gives

Then the incremental voltage gain is given by

Av = ( dvo /dvi ) at vI = VIQ

= (1/2) x 2 x RD Kn (W/L) ( vIQ Vt)

...................... ......................(2)

Substituting in (1) vI = VIQ & vO = VOQ we get

VOQ = VDD (1/2) RD Kn (W/L) (VIQ Vt)2

VDD VOQ = (1/2) RD Kn (W/L) (VIQ Vt)2

RD Kn (W/L) =2 (VDD VOQ)/ (VIQ Vt)2

Av = 2 (VDD VOQ)/ (VIQ Vt)

= 2 VRD / VOV

Where VRD is the voltage across drain voltage and VOV is the overdrive voltage

o Fixing of biasing point or biasing or bias design

Biasing Establishment of an appropriate dc operating point for the MOS.

The bias point is characterised by

o Stable & predictable dc current ID

o Dc drain to source voltage VGS

That ensures operation of transistor in the saturation region for all

expected input signal levels.

Fix the gate to source voltage VGS so as to provide the desired ID.

VGS can be derived either from

o VDD , by using appropriate voltage divider network.

OR

o Suitable reference voltage in the system

However biasing by fixing VGS is not a good approach.

In saturation region ID vs VGS is given by

ID = (1/2) n Cox (W/L) (VGS Vt )2

The value Vt -the threshold voltage, Cox -the oxide capacitance & W/L vary widely

among devices.

Also both Vt and n are temperature dependent i.e., even we fix VGS , the ID will be

temperature dependent.

This can be emphasized by the curve given below where the spread for ID will be

large for the two curves with same VGS.

VG = VGS + RS ID ............................................(1)

Also RS provides negative feedback ( hence called Degenerative Resistance)

i.e., for an increase in ID, for any reason equation (1) gives VGS decreases because of

fixed VG. However ID is proportional to VGS, therefore ID decreases providing a

stabilizing effect.

Fig(b) above shows the variability of ID which is comparatively small for fixed VG. Also

variability of ID decreases as VG and RS are made larger.

Possible biasing implementation are shown below

Fig (c) shows a voltage divider network with the source resistance.

Fig (d) shows coupling capacitance that blocks the dc and passes only the ac signal.

Fig (e) shows the implementation with two power supplies, with a dc ground

established at the gate.

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