Вы находитесь на странице: 1из 30

University of Technical Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 8:
Integrated Circuits

Nguyen Thanh Hai, PhD


1

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits

8.1
8.2
8.3
8.4
8.5
8.6
8.7

TTL and CMOS Families


Data sheet
The loading and the Fan-out
Open-Collector/Open-Drain Outputs
Tristate (Three-State) Logic Outputs
TTL Driving CMOS
CMOS Driving TTL

2
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.1 TTL and CMOS Families
CMOS Family

Large
impendence

TTL Family

E
B

Ohm law:
R=U/I
Nguyen Thanh Hai, PhD

TransistorTransistor Logic (TTL)


Complementary metaloxidesemiconductor (CMOS)

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.2 Data sheet

4
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.2 Data sheet

5
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.3 TTL Loading and the Fan-out
-VIH (min) High - Level Input Voltage
-VIL(max) Low - Level Input Voltage

-VOH (min) High - Level Output Voltage


-VOL(max) Low - Level Output Voltage
-IIH High - Level Input Current

-IIL Low - Level Input Current


-IOH High-Level Output Current
-IOL Low - Level Output Current
6
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.3 TTL Loading and the Fan-out
Performance ratings

74

74S 74LS 74AS 74ALS 74F

Propagation delay (ns)

9.5

1.7

Power dissipation (mW)

10

20

1.2

Speed-power product (pJ)

90

60

19

13.6

4.8

18

Max. clock rate (MHz)

35

125

45

200

70

100

Fan-out (same series)

10

20

20

40

20

33

VOH(min)_V

2.4

2.7

2.7

2.5

2.5

2.5

VOL(max)_V

0.4

0.5

0.5

0.5

0.5

0.5

VIH(min)_mV

2.0

2.0

2.0

2.0

2.0

2.0

VIL(max)_mV

0.8

0.8

0.8

0.8

0.8

0.8

Voltage parameters

Table-1
7
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.3 TTL Loading and the Fan-out

Source

8
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.3 TTL Loading and the Fan-out

Sink

9
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.3 TTL Loading and the Fan-out
- To calculate for driving many inputs

I OL

I IL

I IL

-Output of a logic gate can drive inputs


-Fan-out is also called loading factor:
the fan-out value of the output can drive
the maximum number of the logic
inputs.
I IL

10
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits

11
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits

12
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.1: How many 74ALS00 NAND gate inputs can be
driven by a 74ALS00 NAND gate output?
Solution: According to 74ALS00 data sheet, one finds
IOL(max) = 8 mA (Low output); IIL (max) = 0.1 mA (Low input)
IOH(max) = 400 uA (High output); IIH(max) = 20 uA (High input)

Fan-out
Fan-out (LOW) = IOL(max)/IIL(max)=8 mA/0.1 mA = 80. Then, the
number of inputs possibly driven in the LOW state is 80.
Fan-out (HIGH) = IOH(max)/IIH(max)=400 uA/20 uA = 20. Then, the
number of inputs possibly driven in the HIGH state is 20.
High and Low states are not the same, so we can choose so that the
74ALS00 can drive up to 20 other 74ALS00 NAND gates.
13

Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.2: A 74LS00 NAND gate output is driving three 74SXX gate
inputs and one 7406 input. Determine if there is a loading problem.
Solution:
1. Add all of the IIH values:
3.(IIH for 74S) + 1.(IIH for 74)
Total = 3.(50 uA) + 1.(40 uA) = 190 uA
IOH for the 74LS output is 400 uA (max) > 190 uA. This satisfies the
HIGH output.
2. Add all of the IIL values:
3.(IIL for 74S) + 1.(IIL for 74)
Total = 3.(2 mA) + 1.(1.6 mA) = 7.6 mA
IOL for the 74LS output is 8 mA (max) > 7.6 mA. This satisfies the LOW
output.
14
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.4 Open-Collector/Open-Drain Outputs

Rp is connected
outside

Rp
(external )

V0

Q3 ON

V0 = VOL 0.4 V

Q3 OFF

V0 = VOL = +5 V

Nguyen Thanh Hai, PhD

V0 at the
output

Rp = 10k is small enough for the


minimum below VOH and IOL(max)

15

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.4 Open-Collector/Open-Drain Outputs

16
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.4 Open-Collector/Open-Drain Outputs
5 V

10 k

Output A.B.C

Symbolizes the
wired-AND
connection

74LS05(open-collector)
or
74HC05(open-drain)

-Only pulling outputs LOW


-Sharing the same wire for transmitting in a logic level
Nguyen Thanh Hai, PhD

17

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.4 Open-Collector/Open-Drain Outputs
24 V

74LS112
J

7406

CLK
K

24 V, 25 mA

V0

Transistor shown for illustrative purposes


-7406 buffer between FF and Lamp

-Lamp acting as the pull-up resistor for the open-collector output


-Q = 1, the lamp is on and otherwise Q = 0, it is off.
Nguyen Thanh Hai, PhD

18

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.4 Open-Collector/Open-Drain Outputs
5 V

Rs
74HCT74
D

7406

CLK
Q

-In this case, 7406 open-collector output is to drive an indicator LED.


-The resistor Rs is for limiting the current
19
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.5 Tristate (Three-State) Logic Outputs
V
LOW

ON

V
HIGH

HIGH

OFF

OE 1
enabled

LOW

ON

OE 1
enabled

(a)
OFF

HIGH
or
LOW

(b)

HI - Z

OFF

OE 0
disabled
Nguyen Thanh Hai, PhD

OFF

(c)
20

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.5 Tristate (Three-State) Logic Outputs
74LS126

74LS125
A

E
E
E

0
1

A
Hi-Z

0
1

Hi-Z
A

21
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.5 Tristate (Three-State) Logic Outputs
74LS126

74LS126
A
Disabled

EA

EA

B
EB

C
EC
Nguyen Thanh Hai, PhD

Common
bus

To other
circuits

B
Enabled

EB

5 V
C
Disabled

EC

To other
circuits
22

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.6 TTL Driving CMOS
5 V

10 k

CMOS

TTL

10 V

5 V

74LS112

10 K

CMOS

74LS07

CLK
Q

TTL
Nguyen Thanh Hai, PhD

External pull-up
resistor is used
when TTL drive
COMS

TTL

A 7407 opencollector buffer can


be used to interface
TTL to high-voltage
COMS
23

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
8.7 CMOS Driving TTL
VDD 15 V

VDD 5 V

15 V
0

VCC 5 V

5V
0

C
4001B

4050B

CMOS

CMOS

VDD=+15V

VDD=+5V

74LS00
CMOS
VCC=+5V

A 4050B buffer simply passes the 4001B output signal to the 74LS loads
with the assurance that a logic 0 will pull LS inputs to their LOW state.
24
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.3:

25
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.4:

26
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.5:

27
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits
Example 8.6:

28
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits

-Take a look Examples from pages


- Answer Review questions
- Homework

29
Nguyen Thanh Hai, PhD

University of Technical Education


Faculty of Electrical & Electronic Engineering

Integrated Circuits

The End

30
Nguyen Thanh Hai, PhD

Вам также может понравиться