Embedded Systems Programming

Software Power Management for

Embedded Systems

Guided by:

Presented by:

Professor Prabhat Ranjan

Abhishek Agarwal (200101229)

DA-IICT

Anuj Jain (200101036)

Ritwik Kumar (200101002)

Outline
Why power management?
Software and Hardware Approaches
Where power is consumed?
Techniques for power estimation
Approaches explored
Other techniques

Why Power Management?

Following reasons make power management very crucial for
embedded systems:
Mostly powered by low and limited power sources like small batteries.
High power consumption places constraints on reliability of device.
Increase in heat dissipation increases the size of the device.
Costly packaging and cooling requirements like fans etc to handle heat
dissipated.

Software and Hardware Approaches

Hardware Power Management:
Transistor level optimization.
Reducing the applied voltage
Decreasing the circuit capacitances.

Software Power Management:

Software designing for intelligent memory access.
Instruction level optimization.
Software designing for Intelligent waiting.
General software designing for minimizing power consumption
Designing to reduce 0
1 or 1
0 transitions.

Where Power is Consumed?

Power is dissipated in various forms:
1.

Interconnect power



2.

Memory power



3.

Resistances and Parasitic Capacitances.

Transitions because of change in data results in charging and discharging of
capacitors.
Depends on type of memory
Depends on the number of access, the size of the memory (code and data), the
number of ports used.

CPU power



Instruction fetch, decode and execution results in power consumption.

Depends on current withdrawn by each instruction.

Techniques for power estimation

Models used for power estimations are:
Instruction level power model.
Module level power model.

Basic guidelines:
Power dissipated is directly proportional to current withdrawn by
processor.
Power = Dynamic Power (charging or discharging of capacitances) +
Static/leakage Power (leakage current) +
Short Circuit Power ( during rising or falling edge of clock)

Approaches Explored
Mode based power management
High level abstraction
Post Compilation optimization
Register label optimization
Direct cache access

Mode based power management

Use of different power modes.
Idle mode:
Processor core is shut down; peripherals and interrupts remain
powered.
Consumes less power, with little overhead to enter and exit.

Intelligent waiting.
puts processor in idle mode, when all threads are blocked-waiting for
an interrupt.
And, any interrupt can wake up processor from idle mode.
Tries to enter idle mode as often as possible.
e.g. polling for some status flag.
Interrupt based.
Timer based.

Mode based power management

Event Reduction
Tries to keep processor in idle mode as long as possible.
Alters the way process interrupts the processor, so that minimum mode
transition occurs.
Example:
Variable timeouts
Direct Memory Access (DMA)

High level abstraction

Less number of instructions
Research towards efficient software can be exploited
e.g.

 Function call
Call by value
Call by reference
Global variables
Dynamic vs. Static binding
Polymorphism

Post-compilation Optimizations
Loop unrolling
Increases instruction level parallelism by decreasing
the number of control statements
Energy of a loop a a + b / (n + 1)
Diminishing returns
Energy per loop increases but for whole program
decreases

Post-compilation Optimizations
Software pipelining
Each iteration of software pipelined code is formed from
instructions chosen from different iterations in the original code
segment.
Number of stalls is reduced.

Eliminating recursions & including inlining

Stack is used for preserving context of each call
Total switched capacitance decreases significantly

Register label optimization

Focuses on instruction register and instruction data bus
Bit switching consumes energy in instruction register and even more in
instruction data bus when fetch path is longer
0 0 transitions also consume energy due to switching of clock
transistors but can be taken care of by guarding the clocks at input of
the register
Greedy algorithm used for optimization of labels

Direct Cache Access

Saves energy by reducing the need of hardware repeated tag checks
for cache lines.
Software instructs the hardware to remember the location of cache
lines using DAR (Direct Address Registers).
Selects the cache line with at least two references and places the
dominant reference in one of the DARs.
Reference to dominant reference places the location of cache line in
one of the DARs and for any other reference to the line no other tag
checks are performed.

Direct Cache Access

Example Instructions:

Direct cache access reduces the number of tag checks by 1876% and energy consumption by 9-40% of the total data cache
access energy.

Other techniques
Dynamic clock and voltage adjustment without
noticeably affecting performance.
Intelligent shutdown: avoiding reboot procedure
coupled with optimized sleep mode power consumption.
Dynamic Power management: refers to power management in
real time during the execution of the program
Instruction level optimization: by reducing the number of
instructions or by changing the types of instruction.

References

Software power optimizations in an embedded systems by Vishal Dalal et.al.

Minimizing software power consumption through reduction of of Data
memory access by Shan li et.al.
Direct Addressed Caches for Reduced Power Consumption by Emmett
Witchel et.al.
A web-based energy exploration tool for embedded systems by Hojun shim
Power analysis of embedded software: A first step towards software power
optimization by Vivek Tiwari et.al.
Energy Issues in Software Design of Embedded Systems by A Chatzigiou
Instruction Level Power Model Of Microcontroller by Chaitali Chakrabarti
Techniques for Low Energy Software by Huzefa Mehtal et.al.
Software Power Estimation and Optimization for High Performance, 32-bit
Embedded Processors by Jeffrey Russel et.al.
A Multi-Level Strategy for Software Power Estimation by F Salice et.al.

Software Power Management

Thank You