Electronics for Telecommunications

8 PLL and frequency

q
y synthesizers
y
General structure and specification parameters of a PLL
Phase detectors
Working principle and butterfly characteristics and PLL
Linear model in phase locked conditions
Loop filter design criteria
Applicative
pp
examples:
p
Clock synchronization
DSB-AM and SSB-AM coherent demodulators
FM demodulator

Indirect, direct and hybrid frequency synthesizers

Direct digital synthesizers (DDS)
1

Overview

A PLL is a feedback circuit, in which the feedback signal is used to

lock the instant phase of an input signal
In steady
steady-state
state conditions:
IN= OUT
IN-OUT=const
Aout=const

VIN(AIN,IN, IN)+noise+distortion

PLL

VOUT(AOUT,OUT, OUT)

Some applications
Angular analog (FM, PM) and digital (FSK, PSK) demodulators
Modems
Clock recovery and synchronization Digital PLL
USB transceivers
Frequency synthesizers
Radio TX/RX
2

General block diagram of a PLL

VIN(AIN, IN, IN)

Phase
Detector

vd

Loop
Filter F(s)
()

vc

VCO

Vout=(AOUT OUT,OUT)

A PLL consists of 3 basic blocks:

A phase detector: generates an output voltage Vd whose mean value is proportional
t the
to
th phase
h
diff
difference. In
I general:
l Vd=f(
f( IN-OUT, IN-
OUT, IN+OUT, IN+
OUT)
A loop filter F(s) which extracts the low-frequency content out of Vd
A Voltage Controlled Oscillator (VCO): generates a sine wave whose frequency is a
function of Vc
d OUT
OUT = f (V c )
dt
st
Around the free-running pulsation c, a 1 order approximation holds
OUT= |OUT-c|= kcVc
3

Phase detectors - 1
V1(1, 1)
V2(2, 2)

Phase
detector

Vd(1-2, 1+2, 1-2, 1+2)

Phase detectors are non-linear circuits to compare frequencies and

phases of two input signals
If 1 = 2 Vd=f(1 - 2)
If 1 2 Vd=f(1 - 2 )

Analog phase detectors are analog 4-quadrant multipliers

Example: sine waves
v 1 (t ) = V1 sin (1t + 1 )
v d = K m (v 1 v 2 ) = K m

v 2 (t ) = V2 cos ( 2 t + 2 )

V1 V2
V V
sin[(1 2 )t + (1 2 )] + K m 1 2 sin[(1 + 2 )t + (1 + 2 )]
2
2

Using a suitable low pass-filter only the first component feeds the VCO

If 1 = 2, and
d ffor smallll values
l
off 1 - 2 v d K m

V1 V2
(1 2 ) = K d (1 2 )
2
4

Phase detectors - 2

Digital phase detectors are used to calculate the phase differences

between two periodic binary waveforms (0 and Vmax). In this case:
=

where T is the period and is the time difference between them

In this case Vd = K d is calculated as the time average of Vd

Some implementations:
1) Periodic signals with 50% duty cycle: XOR logic gate

2
Vd =
Ts
2
=
Ts

Ts

vd(t )dt =

Ts
2 vd
0

(t )dt =Vmax

Kd
Note: linear behaviour between 0 and
5

Phase detectors - 3
2) Impulsive waveform: S-R Flip-Flop

VIN

VOUT

SET

vd
Kd =

CLR

Vmax
2

3) Periodic signals with a duty cycle different from 50%: the simplest solution
is to calculate the derivative of both signals to obtain a train of impulses
6

Performance parameters of a PLL

Free-running
F
i ffrequency c off the
th VCO
Capture range: frequency range around c in which a PLL is able to lock an
input signal.
It depends
d
d on the
th parameters
t
off the
th filter
filt F(
F(s))
Lock range: frequency range around c in which a PLL is able to track the
pulsation IN of the input signal once it is locked
It depends
d
d only
l on th
the DC gain
i off th
the filt
filter F(0)
In general, Lock range > Capture range
Lock range

-lock

-capture c

capture

lock

=[c-lock, c +lock ]

Capture range =[c-capture, c +capture ]

Equivalent noise bandwidth: ratio between the output power and the spectral
noise
i d
density
it off an iinputt white
hit ((phase)
h
) noise
i

BN =

1
2 H max

2 0

H ( j ) d
2

Working principle of a PLL

A PLL is a non-linear system. Its behaviour consists of:
a transient phase (nonlinear behaviour) capture
and a steady-state
steady state phase (quasi-linear
(quasi linear behaviour) phase lock

Open Loop Analysis

Ass me that the PLL loop is open before the VCO
Assume
VIN(AIN, IN, IN)

Phase
Detector

vd

Loop
Filter F(s)

vc

VCO

Vout=(AOUT OUT,OUT)

VCO is free-running c=constant and OUT=c

Ac

Vc = Kd F[ j (IN c )] sin[(IN c )t + (IN OUT ) + Arg{F[ j (IN c )]}]

Ac

Butterfly characteristic - 1
Closed Loop Analysis
1. Assume to close the loop at a time t0 and that VIN is a input sine wave with
INc Vc0
2. A transient phase begins (capture) during which Vc=f(IN - c) and
OUT=c+OUT(Vc) OUT oscillates with an amplitude which is a function of
|F[j(IN -
OUT)]| Vc is not a sine wave and the mean value is different from 0
OUT tends to shift towards IN
3. In order to lock the input signal (i.e. OUT=IN) the frequency of input signal must
be within the capture range. Finding the capture range is difficult. A rough
estimate can be obtained if we consider that when lock is reached Vc must be a
constant, i.e. OUT=IN =c+KcVlock and that |Vc(t0)|>|Vlock|
Kd F[ j (IN c )] > Vlock =

IN c
Kc

IN c < KcKd F[ j (IN c )]

capture is the value of IN meeting the previous condition
9

Butterfly characteristic - 2
4. When OUT =IN (phase lock) Vc (in-out) whose DC component Vc 0 enable
the VCO to keep the lock (stable working point)
5 If IN(t) changes
5.
h
iin titime OUT tracks
t k IN within
ithi th
the llock
k range. lock is
i lilimited
it d b
by
the properties of the phase comparator
Example:
p analog
g comparator
p
works approximately
pp
y in the range
g [-/2,, /2]
Vc (t ) Kd F (0)(IN OUT )

IN OUT max <

Vc

-/2

/2 IN-
OUT

Vcmax =

OUT c
Kc

c KcKd F (0)

lock c
Kc

< Kd F (0)

< IN < c + KcKd F (0)

2
Due to the low-pass characteristics of F(s) lock> capture

lock

In the following only the phase lock condition will be described analytically
10

Butterfly characteristic - 3
Starting from IN<<c |IN- OUT| out of
F(s) band Vc0
When IN-c=-capture the PLL locks. This is
the intersection point between open-loop Vc
envelope and VCO characteristic

Case 1: IN

-capture
lock

As VCO is linear and PLL is locked:

IN=OUT Vc=(IN-c)/Kc=d/Kc linear:
th operating
the
ti point
i t moves on VCO
characteristic
c Vc=0.
0. When IN>
lock, Vc
When IN=
grows again at a constant rate until lock.
Afterwards, Vc amplitude drops and lock is
g signal
g
lost oscillating
Starting from IN>>c an opposite behaviour
can be observed asymmetric (butterfly
characteristic

-lock
0

capture

Case 2: IN

11

Linear model in phase locked conditions

After the transient ends and the PLL locks, the PLL can be modelled as
a linear feedback system
Hypotheses
The PLL is in a lock condition (OUT =
IN)
A linear approximation holds for all blocks of the PLL
IN and OUT are assumed as the input and output signal of the PLL

Laplace domain analysis

Phase det.

Vd = K d [ IN (s ) OUT (s )]

Loop filter

Vc (s ) = F (s ) Vd (s )

VCO

OUT (s ) = s OUT (s ) = K cV c (s )

H (s ) =

OUT (s )
K c K d F (s )
=
IN (s ) s + K c K d F (s )

12

Loop filter design criteria 1

IN(s)

Kd

vd

F(s)

vc

Kc/s

OUT(s)

The loop filter transfer function F(s) is closely related to the the order of the PLL
and it affects its performances
KcKd
(
)
H
s
=
No loop filter: F(s)=1
F(s) 1
s + KcKd
|H(j)|dB

0 dB

KcKd

The PLL can be modelled as a 1-st order linear system

PLL 3 dB bandwidth is given by KcKd

Advantages:
g
capture lock

Disadvantages: spurious components due to phase

comparator nonlinearities, out-of-band noise and
double-frequency
doub
e eque cy terms
e s affects
a ec s VCO
CO be
behaviour
a ou a
low-pass filter is required in any case
13

Loop filter design criteria 2

1-order passive filter (RC cell)
R
C

H (s ) =

1
F (s ) =
1 + sRC

1 =

1
RC

H (s ) =

KcKd
RCs 2 + s + K c K d

Open loop pole

1
RC
s
s
+
+1
Kc Kd KcKd

n =

s 2 2
+
+1
n2 n

|H(j)|dB

1
2

KcKd
= K c K d 1
RC
1
1
=
K c K d RC
2

Resonance
pulsation

1
KcKd

The PLL can be modelled as a 2-nd order linear system

y
PLL 3 dB bandwidth is given by ~n

0 dB

Advantages:
g
open
p loop
p 3 dB bandwidth |1| can be
set independently from PLL bandwidth n noise and
spurious rejection better VCO stability
~n

g
If n increases decreases
Disadvantages:
resonance close to n oscillations may occur
14

Loop filter design criteria 3

1-order filter with a zero in the transfer function (R1R2C)
R1

F (s ) =

R2

1+ sCR 2
1 + s (R1 + R 2 )C

C
H (s ) =

2 =

1
R 2C

Open
p loop
p zero

1 =

1
(R1 + R 2 )C

Open loop pole

K c K d (sCR 2 + 1)

s 2 (R1 + R 2 )C + s (CR 2K c K d ) + K c K d

|H(j)|dB

0 dB

n =

KcKd
=
(R1 + R 2 )C

1
1
R 2C +
2
KcKd

K c K d 1

Resonance
pulsation

Damping factor

KcKd
(R1 + R 2 )C

~n
Advantages: In this case we have a further degree of freedom in PLL design. In fact, by
1
g R2 so that =
we can have a maximallyy flat frequency
q
y response
p
within PLL
choosing
2
bandwidth
15

A datasheet example

The LM565 and LM565C are

general purpose PLL

Contain a stable, highlylinear VCO and a double

balanced phase detector with
good carrier suppression

16

Example: clock synchronization

External
clock fclk

Phase
Detector

F(s)

Delay

Logic
circuit

Output
clock
l k fclk

When clocking high-frequency circuits (e.g. FPGA), the clock delays between
different part o the circuit can differ considerably clock skew at the output

In this case the signal frequency is correct: only the phase has to be tuned

Delayy lock loops

p ((DLLs)) are a p
particular kind of PLL whose p
purpose
p
is to
synchronize an input clock reference with the signals output from PADs

p of a chain of flip-flops
p p or variable current inverters
A variable delayy line made up
enables a fine phase tuning of the phase shift phase error depends on F(s)
17

Example: FM demodulator
vm(t)
xin(t)

BPF

Phase
Detector

vd(t)

F(s)

vc(t)

VCO

vout((t))
Received signal

When the PLL is locked

u (t ) = Ac cos [c t + (t )]

(1)

(t ) = 2k f m( )d

(2)

VCO

v out (t ) = Av cos [c t + out (t )] (3)

out (t ) = 2k c v c ( )d
t

(4)

v c (t )

Ac Av
F (0 ) ( (t ) out (t )) (5)
2
v c (t ) is approx. constant

By replacing (2) and (4) into (5) and

differentiating both members

m(t )

kc
v c (t )
kf
18

Example: DSB and SSB demodulators

r(t)

Balanced u(t) Low-pass

Modulator
filter

BPF

Phase Lock
Loop

m(t)

c(t)

PLLs can be used to recover the carrier from the input signal in the case of DSBAM signals
From this point of view, a PLL can be considered as a narrowband filter, whose
central frequency tracks the carrier frequency fluctuations

u (t ) = r (t )c (t ) = Ac m(t )cos (c t + 1 )cos (c t + 2 ) =

=

Ac m(t )
A m(t )
cos (1 2 ) + c
cos (2c t + 1 + 2 )
2
2

A low-pass filter eliminates the double frequency components

A similar approach can be followed also to demodulate SSB signals

19

Frequency synthesizers

Frequency synthesizer: system that, using one or more stable frequency

references as input signals, is able to generate periodic waveforms at variable
frequencies within a given (usually wide) range

Frequency synthesizers are widely used in RX/TX equipment to tune the radio
over different channels.
channels

Possible techniques

Indirect frequency synthesis: it relies on the operating principles of PLLs

Direct frequency synthesis: it is based on analog techniques using mixers

mixers,
dividers and filters now used only in high frequency electronics

Hybrid frequency synthesis: it is a combination of previous techniques

Direct digital synthesis (DDS): it is based on a computing device and a D/A

converter
20

Indirect frequency synthesizers

Ref.

fr

Phase
Detector

F(s)

VCO

Programmable binary counter

fout/M

1/M

fout

Control inputs
When the PLL is locked, it must be fr= fout /M
/ fout = Mfr

If a programmable binary counter is used, the feedback waveform is digital with

a very small duty-cycle
duty cycle, but its frequency is fout
o t /M slow device

Main problem: jitter in the period of the output waveform when M is large due to
the fact that the phase detectors operates only on fr edges between two
edges
d
th
the synthesizers
th i
iis ffree running
i because
b
of:
f
The limited stability of the VCO free-running frequency fc>> fr
The variable delay of the binary counter

This scheme can be used for instance for clock multiplying

21

Improving performances - 1
Solution 1
Ref.

fr

Phase
Detector

F(s)

Programmable
binary counter

fout/(MK)

1/M

VCO

Fixed
Fi
d ffrequency
divider= prescaler

fout/K

1/K

fout

Control inputs

A prescaler is faster than a programmable counter and it also allows a lower jitter
fout = Mfr with M=MK frequency range and resolution are the same as
before
By partitioning the divider in two sections, faster components can be used
lower variability of the waveform period
22

Improving performances - 2
Solution 2
fr

Ref
Ref.

1/N

fout/N

Phase
Detector

Control inputs

F(s)

VCO

Programmable
g
binary
y counter

fout/M

fout

1/M

1/K

Control inputs

By inserting a further programmable counter in addition to the prescaler

prescaler,
both the resolution and the range of frequencies can be greatly increased
fout = (M K/N)fr : the control parameters are set by software through a P
Sometimes the 1/N divider is before the output
23

Fractional frequency synthesizers

Ref.

fr

Phase
D t t
Detector

F(s)
()

VCO

Programmable binary counter

fs

fout

N/N+1

Control

If the
th divider
di id iis switched
it h d b
between
t
N and
d N+1
N 1 with
ith a d
duty
t cycle
l D
D 1 D
f s = f out +

N
N
+
+1
1

f out = f r

N (N + 1)
N+D

The phase detector can operate at a higher frequency than in integer case
Divider switching causes Vc and Vd voltage fluctuations compensation is
required
24

Direct frequency synthesizers

Ref.

fr

Harmonic
generator
g

Bandpass
filter

Nfr

The signal from the oscillator is passed to a non-linear circuit

(h
(harmonic
i generator
t network),
t
k) which
hi h iis d
designed
i
d tto produce
d
a
certain amount of harmonics having a given amplitude

An adjustable
A
dj t bl filter
filt (usually
(
ll a resonantt circuit)
i it) extracts
t t the
th wished
i h d
component

With current technologies, up to n=1000 harmonics can be generated

This scheme is the most used at microwave frequencies

In some cases a PLL-based synthesizer can be used instead of an

oscillator
ill t as iinputt reference
f
signal
i
l
25

Frequency-conversion synthesizers
Multiple
Crystal
Oscillators
(e.g. 1-9
1 9 kHz)

f1

f2

Bandpass
Filter

f1+ff2

This kind of synthesizers are based on heterodyne principle, i.e.:

v 1 (t ) = V1 sin (2f1t + 1 )
v out =

Multiple
Crystal
Oscillators
(e.g. 10-90
10 90 kHz)

v 2 (t ) = V2 cos (2f2 t + 2 )

V1 V 2
V V
sin [2 (f2 f1 )t + ( 2 1 )] + 1 2 sin [2 (f1 + f2 )t + ( 1 + 2 )]
2
2

The band-pass filter removes the low-frequency beat. A high-pass filter is

not
o su
suitable,
ab e, because it does not
o filter
e the
e spu
spurious
ous IM co
components
po e s suc
such
as (2f1+f2) and (2f2+f1)
26

Hybrid frequency synthesizers

Ref.

fr

fout

Phase
Detector

F(s)

Programmable
binary counter

1/M

VCO
fL

(fout- fL) Low-pass

C t l iinputs
Control
t

filter

(fout+ fL),
(fout- fL)

It combines frequency-conversion synthesis and indirect synthesis

fL is generated by a local oscillator. In a locked state fout= Mfr+fL

Th frequency
The
f
conversion
i scheme
h
enables
bl a fi
fine ttuning
i off fout

The frequency jitter is lower than in typical indirect PLL synthesizers

27

Direct digital synthesizers (DDS) - 1

fck

Acc

Look-up
Table

DAC

Low-pass
filter

The waveform samples are contained in a local memory as a look

look-up
up table

The look-up table data are read sequentially in a circular way and converted by a
high accuracy Digital-to-analog converter (DAC). The output filter reconstructs
the analog waveform through interpolation

Waveform resolution depends on look-up table word width and DACs resolution

Signal frequency is a function of the increment between two subsequent samples

28

Direct Digital Synthesizers (DDS) - 2

Advantages compared with indirect frequency synthesizers

Low phase noise (there is no any VCO)

Frequency resolution can be improved by increasing the length

of the accumulator.

Waveform resolution can also be improved using interpolation

techniques

Rapid switching between two waveforms with different

frequencies: unlike PLLs there is no need for a transient phase
to lock the new frequency value

Discrete-time signals can be modulated directly (PSK or FSK),

p y by
y changing
g g the reading
g order
simply
29