VLSI TRAINING COURSE CONTENT :

1. VLSI Design Flow

2. SoC Architecture Concepts
3. On-Chip Bus Protocols (AXI4.0, OCP3.0)
4. Peripheral Bus Protocols(USB3.0/PCIEx Gen3)
5. Advanced Verilog for Verification
6. SystemVerilog for Advanced Verification
7. ASIC Verification Concepts
8. ASIC Verification Methodologies : OVM & UVM
9. PERL Automation
10. PROJECTS : Module(IP) Level Verification Projects
o

Project#1 : SystemVerilog Based Project based Complex IP (USB, Ethernet,

MemCtrl, Bridge, etc)

Project#2 :SV & OVM/UVM Based Project based on Complex IP (UART, KBD,
Bridge, etc)

11. System on Chip(SoC) Verification Concepts

12. Mock Interviews & Group Discussions
13. Student assignments for weekday practice
Detailed Course Structure :
1. VLSI Design Flow
o SoC Design Flow
o

IP Design Flow

ASIC/FPGA Flow

2. SoC Architecture Concepts

o

ARM Processor Architecture

L1/L2/L3/L4 Interconnects

On-Chip Bus Protocols

Bridge Protocols

Controllers Modules

Peripheral bus Protocols

L1/L2 Cache, On-chip memory

Boot sequence & Sub System Bringup

Low Power Design Techniques

3. On-Chip Bus Protocols (AXI4.0, OCP3.0)

o

Signal Descriptions

Channel Handshake

Addressing Options

Atomic Accesses

Response Signalling

Ordering Model

Data buses

Unaligned Transfers

Clock, Reset

AXI4 Specific revision updates

4. Peripheral Bus Protocols(USB3.0/PCIEx Gen3)

o

USB3.0 Architectural Overview

Data Flow Model

Physical Layer

Link Layer

Protocol Layer

5. Advanced Verilog for Verification

o

Event Regions and Event Scheduling

Tasks and Functions

Race Conditions

Randomization

File I/O operations

TB Constructs

Self Checking Testbenches

6. SystemVerilog for Advanced Verification

o

Arrays

Data Types and Data Declarations

Classes

Operators and Expressions

Scheduling Semantics

Procedural Statements and control flow

Processes & Threads

Tasks and Functions

Random Constraints

Inter Process synchronization and communication

Clocking blocks, Program Block, Assertions

Coverage, Interface

System Tasks and System Functions

Compiler Directives

DPI

7. ASIC Verification Concepts

o

SoC Verification

Module Level Verification

Constrained Random Verification

Coverage Driven Verification

Directed Verification

Assertion Based Verification

8. ASIC Verification Methodologies : OVM & UVM

o

OVM/UVM TB Architecture

Stimulus Modeling

Creating OVCs and Environment

OVM Simulation Phases

TLM Overview

Configuring TB Environment

OVM Sequences and Sequencers

Connecting multiple OVCs

Creating TB infrastructure

Advanced OVM/UVM Concepts

9. PERL Automation
o

Data types and Objects

Regular Expressions & Subroutines

Regression environment setup

PERL in verification environment setup

10. PROJECTS : Module(IP) Level Verification Projects

o

Project#1 : SystemVerilog Based Project

Project#2 :SystemVerilog & OVM/UVM Based Project

Project designs : Complex module

(USB/Ethernet/KBD/MemContrlr/Bridge protocols etc)

Specification analysis

Verification Plan creation

Feature & Scenario Listing down

TB architecture creation

Building Top level verification environment

TB component coding and integration

Sanity test case and environment bring up

Complete test case coding

Building regression test suite

Functional coverage and code coverage analysis

11. System on Chip(SoC) Verification Concepts

o

Project Category : Medium complex SoC

TB Architecture creation

Building top level verification environment

TB component coding and integration

Sanity test case and environment bring up

Complete test case coding

Functional, Timing, Power &Performance Tests

Reset Value, Register access, Interrupt, Power Related, Functional Tests

Building regression test suite

12. Mock Interviews & Group Discussions

o

Mock Interviews covering all aspects of Functional Verification

Group discussion on Project assigned to students

13. Assignments provided to student during course

o

VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols

Verification of PCIEx Physical Layer LTSSM FSM from scrach

Functional Verifcation of UART/AXI-DMA/OCP2AXI Bridge from scratch

PERL for VLSI & Functional Verification Course Structure:

1. Introduction to PERL
2. Fundamentals of PERL
3. Operators and Conditions
4. Regular Expressions

5. Loops
6. Working with Files
7. Arguments
8. PERL Modules
9. Objects and Object oriented PERL
10. PERL for VLSI & Functional Verification
Detailed Course Structure :
1. Introduction to PERL
o What is PERL?
o

PERL Scripts

Print Functions

Literals

Quoting Rules

2. Fundamentals of PERL
o

Variables and Scalars

Arrays and Slices

Associative Arrays

Standard Input and Output

Predefined file Handles

3. Operators and Conditions

o

String, Assignment, Arithmetic Operators

Relational and Equality Operators

Logical operators

4. Regular Expressions
o

Simple Statements and Modifies

Pattern Matching

The tr function

Pattern Matching

5. Loops
o

Labels and Blocks

While, Until, For

Labels, Loops and loop control

Foreach

6. Working with Files

o

User Defined file handles

Open file for Writing, Reading, Appending

Open for pipes

Close, eof functions

7. Arguments
o

@ARGV array command line arguments

ARGV and the Shift functions

Array Built-in Functions

Functions: grep, split, join, slice, pop, push

Functions: shift, unshift, reverse, sort, chop, chomp

Associative Array Functions

8. PERL Modules
o

Subroutines

Passing by reference, value

Return statement

Standard Perl Library

@INC Array

Packages and .pl files

Require function

Modules and .pm Files

9. Objects and Object Oriented PERL

o

Object oriented PERL

Classes

my function

objects, methods

destructors

Inheritance

Derives classes

10. PERL for VLSI & Functional Verification

o

Setting up regression

Creating Testbench Environment Structure

Developing testcases

Handling regression logs

Makefile creation

UVM RAL Model Creation Script

Regression result speadsheet creation

Regression result HTML creation

Recursive directory manipulation