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Microprocessors and Interfacing
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INTRODUCTION
G.Vijaya Santhi,Asst.Prof.
* For more details visit - www.worldwebsites8.blogspot.com &/ www.yoursww8.tk | Admin: N.Rajeev *
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8085 Internal Architecture and Instruction set
Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.
Arithmetic Logic Unit
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The ALU performs the actual numerical and logic operation such as add, subtract,
AND, OR, etc. Uses data from memory and from Accumulator to perform
arithmetic. Always stores result of operation in Accumulator.
Registers
The 8085/8080A-programming model includes six registers, one accumulator, and

one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack
pointer and the program counter. They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B,C,D,E,H, and L as shown in the figure. They can be combined as
register pairs - BC, DE, and HL - to perform some 16-bit operations. The
programmer can use these registers to store or copy data into the registers by using
data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are
listed in the Table and their bit positions in the flag register are shown in the Figure
below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor
uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is
set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding
of flag is essential in writing assembly language programs.
Program Counter (PC)
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This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer. The stack concept is explained
in the chapter "Stack and Subroutines."
Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and decodes or
interprets the instruction. Decoded instruction then passed to next stage.
Memory Address Register
Holds address, received from PC, of next program instruction. Feeds the address bus
with addresses of location of the program under execution.
Control Generator
Generates signals within uP to carry out the instruction which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.
Register Selector
This block controls the use of the register stack in the example. Just a logic circuit
which switches between different registers in the set will receive instructions from
Control Unit.
General Purpose Registers

uP requires extra registers for versatility. Can be used to store additional data during a
program. More complex processors may have a variety of differently named registers.
Microprogramming
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How does the P knows what an instruction means, especially when it is only a
binary number? The microprogram in a uP/uC is written by the chip designer and tells
the uP/uC the meaning of each instruction uP/uC can then carry out operation.
2. 8085 System Bus
Typical system uses a number of busses, collection of wires, which transmit binary
numbers, one bit per wire. A typical microprocessor communicates with memory and
other devices (input and output) using three busses: Address Bus, Data Bus and
Control Bus.
Address Bus
One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts
memory to open the designated box. Data (binary) can then be put in or taken
out.The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A
16 bit binary number allows 216 different numbers, or 32000 different numbers, ie
0000000000000000 up to 1111111111111111. Because memory consists of boxes,
each with a unique address, the size of the address bus determines the size of memory,
which can be used. To communicate with memory the microprocessor sends an
address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The
memory the selects box number 3 for reading or writing data. Address bus is
unidirectional, ie numbers only sent from microprocessor to memory, not other way.
Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits),
how many wires does the address bus need, in order to be able to specify an address in
this memory? Note: the memory is organized in groups of 8 bits per location,
therefore, how many locations must you be able to specify?
Data Bus
Data Bus: carries data, in binary form, between P and other external units, such as
memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and
P size helps determine performance of P. The Data Bus typically consists of 8
wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data",
ie information, results of arithmetic, etc, between memory and the microprocessor.
Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If
only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger
number have to be broken down into chunks of 255. This slows microprocessor. Data
Bus also carries instructions from memory to the microprocessor. Size of the bus
therefore limits the number of possible instructions to 256, each specified by a
separate number.
Control Bus
Control Bus are various lines which have specific functions for coordinating and
controlling uP operations. Eg: Read/NotWrite line, single binary digit. Control
whether memory is being written to (data stored in mem) or read from (data taken
out of mem) 1 = Read, 0 = Write. May also include clock line(s) for
timing/synchronising, interrupts, reset etc. Typically P has 10 control lines.
Cannot function correctly without these vital control signals.
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The Control Bus carries control signals partly unidirectional, partly bi-directional.
Control signals are things like "read or write". This tells memory that we are either
reading from a location, specified on the address bus, or writing to a location
specified. Various other signals to control and coordinate the operation of the system.
Modern day microprocessors, like 80386, 80486 have much larger busses. Typically
16 or 32 bit busses, which allow larger number of instructions, more memory
location, and faster arithmetic. Microcontrollers organized along same lines, except:
because microcontrollers have memory etc inside the chip, the busses may all be
internal. In the microprocessor the three busses are external to the chip (except for the
internal data bus). In case of external busses, the chip connects to the busses via
buffers, which are simply an electronic connection between external bus and the
internal data bus.
3. 8085 Pin description.

Properties
Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
Serial In/Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K bytes of memory
The Intel 8085A is a new generation, complete 8 bit parallel central processing unit
(CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit
address bus and the 8bit data bus. Figures are at the end of the document.
Pin Description
The following describes the function of each pin:
A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)
appear on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and Halt
modes.
ALE (Output)
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Address Latch Enable: It occurs during the first clock cycle of a machine state and
enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:

S1 S0
O O
0 1
1 0
1 1
HALT
WRITE
READ
FETCH
S1 can be used as an advanced R/W status.
RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data
Bus is available for the data transfer.
WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory
or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt
modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data
Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as
soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
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HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and
that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA goes
low.
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During
this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt
service routine. The INTR is enabled and disabled by software. It is disabled by Reset
and immediately after an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD
during the Instruction cycle after an INTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA
flipflops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
X1, X2 (Input)
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Crystal or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and
Halt modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a
RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
Vcc
+5 volt supply.
Vss
Ground Reference.
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4. 8085 Functional Description
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The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt
supply. Its basic clock speed is 3 MHz thus improving on the present 8080's
performance with higher system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.
The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit
Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address
is sent out. The lower 8bits are latched into the peripherals by the Address Latch
Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory
or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and one
non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus
control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status strobe.
The status is partially encoded, and provides the user with advanced timing of the
type of bus transfer being done. IO/M cycle status signal is provided directly also.
Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address
are multiplexed with the data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or peripheral address latch. This
also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR
is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5.
7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable.
The three RESTART interrupts cause the internal execution of RST (saving the
program counter in the stack and branching to the RESTART address) if the interrupts
are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the
internal execution of a RST independent of the state of the interrupt enable or masks.
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The interrupts are arranged in a fixed priority that determines which interrupt is to be
recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,
RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into
account the priority of a routine that was started by a higher priority interrupt. RST
5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of
the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized just as any other interrupt
but has the highest priority. It is not affected by any flag or mask. The TRAP input is
both edge and level sensitive.
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower
8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read
and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O
port address is copied on both the upper and lower half of the address. As in the 8080,
the READY line is used to extend the read and write pulse lengths so that the 8085A
can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is
through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and
8355 will have the following features:
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
4 8bit l/O Ports
1 6bit l/O Port
4 Interrupt Levels
Serial In/Serial Out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing
technique. With this technique, an area of memory address space is assigned for l/O
address, thereby, using the memory address for I/O manipulation. The 8085A CPU
can also interface with the standard memory that does not have the multiplexed
address/data bus.
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5. The 8085 Programming Model

In the previous tutorial we described the 8085 microprocessor registers in reference to
the internal data operations. The same information is repeated here briefly to provide
the continuity and the context to the instruction set and to enable the readers who
prefer to focus initially on the programming aspect of the microprocessor.
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The 8085 programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer
and the program counter. They are described briefly as follows.
ACCUMULATOR A
(8)
FLAG REGISTER
(8)
(8)
(8)
(8)
(8)
(8)
Stack Pointer (SP)
(16)
(16)
Data Bus
Address Bus
8 Lines Bidirectional
16 Lines unidirectional
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are identified as
B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs BC, DE, and HL - to perform some 16-bit operations. The programmer can use these
registers to store or copy data into the registers by using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flags
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The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit
positions in the flag register are shown in the Figure below. The most commonly used
flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions.
D7
D6
D5
D4
AC
D3
D2
D1
D0
CY
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is
set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding
of flag is essential in writing assembly language programs.
This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer.
This programming model will be used in subsequent tutorials to examine how these
registers are affected after the execution of an instruction.
6. The 8085 Addressing Modes

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit
number (00H to FFH). Similarly, a destination can be a register or an output port. The
sources and destination are operands. The various formats for specifying operands are
called the ADDRESSING MODES. For 8085, they are:
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1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
Immediate addressing
Data is present in the instruction. Load the immediate data to the destination provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.

Example: MOV Rd, Rs
Direct addressing
Used to accept data from outside devices to store in the accumulator or send the data
stored in the accumulator to the outside device. Accept the data from the port 00H and
store them into the accumulator or Send the data from the accumulator to the port
01H.
Example: IN 00H or OUT 01H
Indirect Addressing
This means that the Effective Address is calculated by the processor. And the
contents of the address (and the one following) is used to form a second address. The
second address is where the data is stored. Note that this requires several memory
accesses; two accesses to retrieve the 16-bit address and a further access (or accesses)
to retrieve the data which is to be loaded into the register.
7. Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a
specific function. The entire group of instructions, called the instruction set,
determines what functions the microprocessor can perform. These instructions can be
classified into the following five functional categories: data transfer (copy)
operations, arithmetic operations, logical operations, branching operations, and
machine-control operations.
Data Transfer (Copy) Operations
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This group of instructions copy data from a location called a source to another
location called a destination, without modifying the contents of the source. In
technical manuals, the term data transfer is used for this copying function. However,
the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification.
The various types of data transfer (copy) are listed below together with examples of
each type:
Types
1. Between Registers.
Examples
1. Copy the contents of the register B into

register D.
2. Specific data byte to a register or a 2. Load register B with the data byte 32H.
memory location.
3. Between a memory location and a 3. From a memory location 2000H to register

register.
B.
4. Between an I/O device and the 4.From an
accumulator.
accumulator.
input
keyboard
to
the
Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction,

increment, and decrement.
Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is
stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the
contents of register B cannot be added directly to the contents of the register C). The
instruction DAD is an exception; it adds 16-bit data directly in register pairs.
Subtraction - Any 8-bit number, or the contents of a register, or the contents of a
memory location can be subtracted from the contents of the accumulator and the
results stored in the accumulator. The subtraction is performed in 2's compliment, and
the results if negative, are expressed in 2's complement. No two other registers can be
subtracted directly.
Increment/Decrement - The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such
as BC) can be incremented or decrement by 1. These increment and decrement
operations differ from addition and subtraction in an important way; i.e., they can be
performed in any one of the registers or in a memory location.
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Logical Operations
These instructions perform various logical operations with the contents of the
accumulator.
AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of

a memory location can be logically ANDed, Ored, or Exclusive-ORed with the
contents of the accumulator. The results are stored in the accumulator.
Rotate- Each bit in the accumulator can be shifted either left or right to the next
position.
Compare- Any 8-bit number, or the contents of a register, or a memory location can
be compared for equality, greater than, or less than, with the contents of the
accumulator.
Complement - The contents of the accumulator can be complemented. All 0s are
replaced by 1s and all 1s are replaced by 0s.
Branching Operations
This group of instructions alters the sequence of program execution either

conditionally or unconditionally.
Jump - Conditional jumps are an important aspect of the decision-making process in

the programming. These instructions test for a certain conditions (e.g., Zero or Carry
flag) and alter the program sequence when the condition is met. In addition, the
instruction set includes an instruction called unconditional jump.
Call, Return, and Restart - These instructions change the sequence of a program
either by calling a subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.
Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing.
The microprocessor operations related to data manipulation can be summarized in

four functions:
1. copying data
2. performing arithmetic operations
3. performing logical operations
4. testing for a given condition and alerting the program sequence
Some important aspects of the instruction set are noted below:
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ARCHITECTURE OF 8086
G.Vijaya Santhi,Asst.Prof
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Microprocessors and interfacing
INTERNAL REGISTERS OF 8086
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The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the
status register, with 9 of bits implemented for status and control flags.
Most of the registers contain data/instruction offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the loworder byte of the word, and AH contains the high-order byte. Accumulator can be used
for I/O operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte. BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the loworder byte of the word, and CH contains the high-order byte. Count register can be used
in Loop, shift/rotate instructions and as a counter in string manipulation,.
Data register consists of two 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the loworder byte of the word, and DH contains the high-order byte. Data register can be used as
a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
instructions.
Other registers:
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Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.
Addressing Modes
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is
located. This addressing mode works with SI, DI, BX and BP registers.
Based :- 8-bit or 16-bit instruction operand is added to the contents of a base register
(BX or BP), the resulting value is a pointer to location where data resides.
Indexed :- 8-bit or 16-bit instruction operand is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed :- the contents of a base register (BX or BP) is added to the contents of
an index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement :- 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is
a pointer to location where data resides.
Memory
Program, data and stack memories occupy the same memory space. As the most of the
processor instructions use 16-bit pointers the processor can effectively address only 64
KB of memory.
To access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of memory
(see the "Registers" section below).
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16-bit pointers and data are stored as:

address: low-order byte
address+1: high-order byte
Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code segment,
as well as for far jumps anywhere within 1 MB of memory.
All conditional jump instructions can be used to jump within approximately +127 to 127 bytes from current instruction.
Data memory - the processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word data
from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd
memory addresses, but it is not recommended for performance reasons (see "Data
Memory" above).
Reserved locations:
0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer
in format segment: offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address.
Interrupts
The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps to
interrupt processing routine address of which is stored in location 4 * <interrupt type>.
Interrupt processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts can be caused by:
INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the
CPU processes this interrupt it clears TF flag before calling the interrupt processing
routine.
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Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape
opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts.
FLAGS REGISTER
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Flags Register - determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the type of
the result, and to determine conditions to transfer control to other parts of the program.
Generally you cannot access these registers directly.
1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For
example when you add bytes 255 + 1 (result is not in range 0...255). When there is
no overflow this flag is set to 0.
2. Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in
result, and to 0 when there is odd number of one bits.
3. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4
bits).
4. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to
0.
5. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to
0. (This flag takes the value of the most significant bit.)
6. Trap Flag (TF) - Used for on-chip debugging.
7. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from
external devices.
8. Direction Flag (DF) - this flag is used by some instructions to process data chains,
when this flag is set to 0 - the processing is done forward, when this flag is set to 1
the processing is done backward.
9. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when
you add bytes 100 + 50 (result is not in range -128...127).
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ADDRESSING MODES OF 8086
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INSTRUCTION SET OF 8086
Notes:
When two operands are required for an instruction they are separated by comma. For example:
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REG, memory
When there are two operands, both operands must have the same size (except shift and rotate instructions).
For example:
AL, DL
DX, AX
m1 DB ?
AL, m1
m2 DW ?
AX, m2
Some instructions allow several operand combinations. For example:

memory, immediate
REG, immediate
memory, REG
REG, SREG
These marks are used to show the state of the flags:

1- instruction sets this flag to 1.
0- instruction sets this flag to 0.
r - flag value depends on result of the instruction.
? - flag value is undefined (maybe 1 or 0).
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Instructions in alphabetical order:

Instruction
Operands
Description
ASCII Adjust after Addition.

Corrects result in AH and AL after addition when working with BCD values.
It works according to the following Algorithm:
if low nibble of AL > 9 or AF = 1 then:
AL = AL + 6
AH = AH + 1
AF = 1
CF = 1
AF = 0
CF = 0
else
AAA
No operands
in both cases:
clear the high nibble of AL.
Example:
MOV AX, 15 ; AH = 00, AL = 0Fh
AAA
; AH = 01, AL = 05
RET
C Z S O P A
r ? ? ? ? r
ASCII Adjust before Division.

Prepares two BCD values for division.
AAD
No operands
Algorithm:
AL = (AH * 10) + AL
AH = 0
Example:
MOV AX, 0105h ; AH = 01, AL = 05
AAD
; AH = 00, AL = 0Fh (15)
RET
C Z S O P A
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? r r ? r ?
ASCII Adjust after Multiplication.

Corrects the result of multiplication of two BCD values.
Algorithm:
AAM
AH = AL / 10
AL = remainder
No operands
Example:
MOV AL, 15 ; AL = 0Fh
AAM
; AH = 01, AL = 05
RET
C Z S O P A
? r r ? r ?
ASCII Adjust after Subtraction.

Corrects result in AH and AL after subtraction when working with BCD values.
Algorithm:
AAS
No operands
AL = AL - 6
AH = AH - 1
AF = 1
CF = 1
AF = 0
CF = 0
else
in both cases:
clear the high nibble of AL.
Example:
MOV AX, 02FFh ; AH = 02, AL = 0FFh
AAS
; AH = 01, AL = 09
RET
C Z S O P A
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r ? ? ? ? r
Add with Carry.
ADC
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Algorithm:
operand1 = operand1 + operand2 + CF

Example:
STC
; set CF = 1
MOV AL, 5 ; AL = 5
ADC AL, 1 ; AL = 7
RET
C Z S O P A
r r r r r r
Add.
ADD
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
AND
Algorithm:
operand1 = operand1 + operand2

Example:
MOV AL, 5 ; AL = 5
ADD AL, -3 ; AL = 2
RET
C Z S O P A
r r r r r r
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Logical AND between all bits of two operands. Result is stored in operand1.
These rules apply:
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
Example:
MOV AL, 'a'
; AL = 01100001b
AND AL, 11011111b ; AL = 01000001b ('A')
RET
C Z S O P
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0 r r 0 r
Transfers control to procedure, return address is (IP) is pushed to stack. 4-byte

address may be entered in this form: 1234h:5678h, first value is a segment second
value is an offset (this is a far call, so CS is also pushed to stack).
Example:
ORG 100h ; directive to make simple .com file.
CALL
procedure
name
label
4-byte
address
CALL p1
ADD AX, 1
RET
; return to OS.
p1 PROC ; procedure declaration.

MOV AX, 1234h
RET ; return to caller.
p1 ENDP
C Z S O P A
unchanged
Convert byte into word.

Algorithm:
if high bit of AL = 1 then:
CBW
No operands
AH = 255 (0FFh)
AH = 0
else
Example:
MOV AX, 0 ; AH = 0, AL = 0
MOV AL, -5 ; AX = 000FBh (251)
CBW
; AX = 0FFFBh (-5)
RET
C Z S O P A
unchanged
Clear Carry flag.
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Algorithm:
CLC
No operands
CF = 0
C
Clear Direction flag. SI and DI will be incremented by chain instructions: CMPSB,

CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW.
Algorithm:
CLD
No operands
DF = 0
D
Clear Interrupt enable flag. This disables hardware interrupts.

Algorithm:
CLI
No operands
IF = 0
I
CMC
Complement Carry flag. Inverts value of CF.

Algorithm:
No operands
if CF = 1 then CF = 0
if CF = 0 then CF = 1
C
r
Compare.
Algorithm:
operand1 - operand2
result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to
result.
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REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
CMP
Example:
MOV AL, 5
MOV BL, 5
CMP AL, BL ; AL = 5, ZF = 1 (so equal!)
RET
C Z S O P A
r r r r r r
Compare bytes: ES:[DI] from DS:[SI].

Algorithm:
CMPSB
DS:[SI] - ES:[DI]
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
o SI = SI + 1
o DI = DI + 1
else
No operands
o
o
o
SI = SI - 1
DI = DI 1
DS:[SI] - ES:[DI]
C Z S O P A
r r r r r r
Compare words: ES:[DI] from DS:[SI].

Algorithm:
CMPSW
No operands
DS:[SI] - ES:[DI]
if DF = 0 then
o
o
SI = SI + 2
DI = DI + 2
o
o
SI = SI - 2
DI = DI - 2
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else
C Z S O P A
r r r r r r
Convert Word to Double word.

Algorithm:
if high bit of AX = 1 then:
DX = 65535 (0FFFFh)
DX = 0
else
CWD
No operands
Example:
MOV DX, 0 ; DX = 0
MOV AX, 0 ; AX = 0
MOV AX, -5 ; DX AX = 00000h:0FFFBh
CWD
; DX AX = 0FFFFh:0FFFBh
RET
C Z S O P A
unchanged
Decimal adjust After Addition.

Corrects the result of addition of two packed BCD values.
Algorithm:
DAA
No operands
AL = AL + 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL + 60h
CF = 1
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Example:
MOV AL, 0Fh ; AL = 0Fh (15)
DAA
; AL = 15h
RET
C Z S O P A
r r r r r r
Decimal adjust After Subtraction.

Corrects the result of subtraction of two packed BCD values.
Algorithm:
AL = AL - 6
AF = 1
if AL > 9Fh or CF = 1 then:
DAS
No operands
AL = AL - 60h
CF = 1
Example:
MOV AL, 0FFh ; AL = 0FFh (-1)
DAS
; AL = 99h, CF = 1
RET
C Z S O P A
r r r r r r
Decrement.
Algorithm:
DEC
REG
memory
operand = operand - 1
Example:
MOV AL, 255 ; AL = 0FFh (255 or -1)
DEC AL
; AL = 0FEh (254 or -2)
RET
Z S O P A
r r r r r
CF - unchanged!
Unsigned divide.
Algorithm:
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when operand is a byte:

AL = AX / operand
AH = remainder (modulus)
when operand is a word:
AX = (DX AX) / operand
DX = remainder (modulus)
DIV
REG
memory
Example:
MOV AX, 203 ; AX = 00CBh
MOV BL, 4
DIV BL
; AL = 50 (32h), AH = 3
RET
C Z S O P A
? ? ? ? ? ?
Halt the System.
HLT
No operands
Example:
MOV AX, 5
HLT
C Z S O P A
unchanged
Signed divide.
Algorithm:
IDIV
REG
memory

AL = AX / operand
AH = remainder (modulus)
AX = (DX AX) / operand
DX = remainder (modulus)
Example:
MOV AX, -203 ; AX = 0FF35h
MOV BL, 4
IDIV BL
; AL = -50 (0CEh), AH = -3 (0FDh)
RET
C Z S O P A
? ? ? ? ? ?
Signed multiply.
Algorithm:
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AX = AL * operand.
(DX AX) = AX * operand.
IMUL
REG
memory
Example:
MOV AL, -2
MOV BL, -4
IMUL BL
; AX = 8
RET
C Z S O P A
r ? ? r ? ?
CF=OF=0 when result fits into operand of IMUL.
IN
AL, im.byte
AL, DX
AX, im.byte
AX, DX
Input from port into AL or AX.

Second operand is a port number. If required to access port number over 255 DXregister should be used.
Example:
IN AX, 4 ; get status of traffic lights.
IN AL, 7 ; get status of stepper-motor.
C Z S O P A
unchanged
Increment.
Algorithm:
operand = operand + 1
INC
REG
memory
Example:
MOV AL, 4
INC AL
; AL = 5
RET
Z S O P A
r r r r r
CF - unchanged!
Interrupt numbered by immediate byte (0..255).

INT
immediate
byte
Algorithm:
Push to stack:
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o flags register
o CS
o IP
IF = 0
Transfer control to interrupt procedure
Example:
MOV AH, 0Eh ; teletype.
MOV AL, 'A'
INT 10h
; BIOS interrupt.
RET
C Z S O P A I
unchanged
Interrupt 4 if Overflow flag is 1.

Algorithm:
if OF = 1 then INT 4
INTO
No operands
Example:
; -5 - 127 = -132 (not in -128..127)
; the result of SUB is wrong (124),
; so OF = 1 is set:
MOV AL, -5
SUB AL, 127 ; AL = 7Ch (124)
INTO
; process error.
RET
Interrupt Return.
Algorithm:
IRET
Pop from stack:

o
o
o
No operands
IP
CS
flags register
C Z S O P A
popped
JA
label
Short Jump if first operand is Above second operand (as set by CMP instruction).
Unsigned.
Algorithm:
if (CF = 0) and (ZF = 0) then jump
Example:
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ORG 100h
MOV AL, 250
CMP AL, 5
JA label1
PRINT 'AL is not above 5'
JMP exit
label1:
PRINT 'AL is above 5'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Above or Equal to second operand (as set by CMP
instruction). Unsigned.
Algorithm:
if CF = 0 then jump
Example:
label
JAE
ORG 100h
MOV AL, 5
CMP AL, 5
JAE label1
PRINT 'AL is not above or equal to 5'
JMP exit
label1:
PRINT 'AL is above or equal to 5'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Below second operand (as set by CMP instruction).
Unsigned.
JB
label
Algorithm:
if CF = 1 then jump
Example:
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ORG 100h
MOV AL, 1
CMP AL, 5
JB label1
PRINT 'AL is not below 5'
JMP exit
label1:
PRINT 'AL is below 5'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Below or Equal to second operand (as set by CMP
Algorithm:
if CF = 1 or ZF = 1 then jump
Example:
JBE
label
ORG 100h
MOV AL, 5
CMP AL, 5
JBE label1
PRINT 'AL is not below or equal to 5'
JMP exit
label1:
PRINT 'AL is below or equal to 5'
exit:
RET
C Z S O P A
unchanged
Short Jump if Carry flag is set to 1.

Algorithm:
JC
label
if CF = 1 then jump
Example:
ORG 100h
MOV AL, 255
ADD AL, 1
JC label1
PRINT 'no carry.'
JMP exit
label1:
PRINT 'has carry.'
exit:
RET
C Z S O P A
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unchanged
Short Jump if CX register is 0.

Algorithm:
if CX = 0 then jump
Example:
JCXZ
label
ORG 100h
MOV CX, 0
JCXZ label1
PRINT 'CX is not zero.'
JMP exit
label1:
PRINT 'CX is zero.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Equal to second operand (as set by CMP instruction).
Signed/Unsigned.
Algorithm:
JE
if ZF = 1 then jump
Example:
label
ORG 100h
MOV AL, 5
CMP AL, 5
JE label1
PRINT 'AL is not equal to 5.'
JMP exit
label1:
PRINT 'AL is equal to 5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Greater then second operand (as set by CMP
instruction). Signed.
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Algorithm:
if (ZF = 0) and (SF = OF) then jump
Example:
JG
label
ORG 100h
MOV AL, 5
CMP AL, -5
JG label1
PRINT 'AL is not greater -5.'
JMP exit
label1:
PRINT 'AL is greater -5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Greater or Equal to second operand (as set by CMP
Algorithm:
if SF = OF then jump
Example:
JGE
label
ORG 100h
MOV AL, 2
CMP AL, -5
JGE label1
PRINT 'AL < -5'
JMP exit
label1:
PRINT 'AL >= -5'
exit:
RET
C Z S O P A
unchanged
JL
label
Short Jump if first operand is Less then second operand (as set by CMP
Algorithm:
if SF <> OF then jump
Example:
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ORG 100h
MOV AL, -2
CMP AL, 5
JL label1
PRINT 'AL >= 5.'
JMP exit
label1:
PRINT 'AL < 5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Less or Equal to second operand (as set by CMP
Algorithm:
if SF <> OF or ZF = 1 then jump

Example:
label
JLE
ORG 100h
MOV AL, -2
CMP AL, 5
JLE label1
PRINT 'AL > 5.'
JMP exit
label1:
PRINT 'AL <= 5.'
exit:
RET
C Z S O P A
unchanged
JMP
label
4-byte
address
Unconditional Jump. Transfers control to another part of the program. 4-byte

address may be entered in this form: 1234h:5678h, first value is a segment second
value is an offset.
Algorithm:
always jump
Example:
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ORG 100h
MOV AL, 5
JMP label1 ; jump over 2 lines!
PRINT 'Not Jumped!'
MOV AL, 0
label1:
PRINT 'Got Here!'
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Above second operand (as set by CMP
Algorithm:
if CF = 1 or ZF = 1 then jump
Example:
JNA
label
ORG 100h
MOV AL, 2
CMP AL, 5
JNA label1
PRINT 'AL is above 5.'
JMP exit
label1:
PRINT 'AL is not above 5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Above and Not Equal to second operand (as set
by CMP instruction). Unsigned.
Algorithm:
JNAE
label
if CF = 1 then jump
Example:
ORG 100h
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MOV AL, 2
CMP AL, 5
JNAE label1
PRINT 'AL >= 5.'
JMP exit
label1:
PRINT 'AL < 5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Below second operand (as set by CMP
Algorithm:
if CF = 0 then jump
Example:
JNB
label
ORG 100h
MOV AL, 7
CMP AL, 5
JNB label1
PRINT 'AL < 5.'
JMP exit
label1:
PRINT 'AL >= 5.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Below and Not Equal to second operand (as set
by CMP instruction). Unsigned.
JNBE
Algorithm:
label
if (CF = 0) and (ZF = 0) then jump

Example:
ORG 100h
MOV AL, 7
CMP AL, 5
JNBE label1
PRINT 'AL <= 5.'
JMP exit
label1:
PRINT 'AL > 5.'
exit:
RET
C Z S O P A
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unchanged
Short Jump if Carry flag is set to 0.

Algorithm:
if CF = 0 then jump
Example:
JNC
label
ORG 100h
MOV AL, 2
ADD AL, 3
JNC label1
PRINT 'has carry.'
JMP exit
label1:
PRINT 'no carry.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Equal to second operand (as set by CMP
instruction). Signed/Unsigned.
Algorithm:
JNE
if ZF = 0 then jump
Example:
label
ORG 100h
MOV AL, 2
CMP AL, 3
JNE label1
PRINT 'AL = 3.'
JMP exit
label1:
PRINT 'Al <> 3.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Greater then second operand (as set by CMP
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Algorithm:
if (ZF = 1) and (SF <> OF) then jump
Example:
JNG
label
ORG 100h
MOV AL, 2
CMP AL, 3
JNG label1
PRINT 'AL > 3.'
JMP exit
label1:
PRINT 'Al <= 3.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Greater and Not Equal to second operand (as set
by CMP instruction). Signed.
Algorithm:
if SF <> OF then jump

Example:
JNGE
label
ORG 100h
MOV AL, 2
CMP AL, 3
JNGE label1
PRINT 'AL >= 3.'
JMP exit
label1:
PRINT 'Al < 3.'
exit:
RET
C Z S O P A
unchanged
JNL
label
Short Jump if first operand is Not Less then second operand (as set by CMP
Algorithm:
if SF = OF then jump
Example:
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ORG 100h
MOV AL, 2
CMP AL, -3
JNL label1
PRINT 'AL < -3.'
JMP exit
label1:
PRINT 'Al >= -3.'
exit:
RET
C Z S O P A
unchanged
Short Jump if first operand is Not Less and Not Equal to second operand (as set by
CMP instruction). Signed.
Algorithm:
if (SF = OF) and (ZF = 0) then jump

Example:
label
JNLE
ORG 100h
MOV AL, 2
CMP AL, -3
JNLE label1
PRINT 'AL <= -3.'
JMP exit
label1:
PRINT 'Al > -3.'
exit:
RET
C Z S O P A
unchanged
Short Jump if Not Overflow.

JNO
label
Algorithm:
if OF = 0 then jump
Example:
; -5 - 2 = -7 (inside -128..127)
; the result of SUB is correct,
; so OF = 0:
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ORG 100h
MOV AL, -5
SUB AL, 2 ; AL = 0F9h (-7)
JNO label1
PRINT 'overflow!'
JMP exit
label1:
PRINT 'no overflow.'
exit:
RET
C Z S O P A
unchanged
Short Jump if No Parity (odd). Only 8 low bits of result are checked. Set by CMP,
SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 0 then jump
Example:
label
JNP
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNP label1
PRINT 'parity even.'
JMP exit
label1:
PRINT 'parity odd.'
exit:
RET
C Z S O P A
unchanged
Short Jump if Not Signed (if positive). Set by CMP, SUB, ADD, TEST, AND, OR,
XOR instructions.
JNS
label
Algorithm:
if SF = 0 then jump
Example:
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ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNS label1
PRINT 'signed.'
JMP exit
label1:
PRINT 'not signed.'
exit:
RET
C Z S O P A
unchanged
Short Jump if Not Zero (not equal). Set by CMP, SUB, ADD, TEST, AND, OR,
XOR instructions.
Algorithm:
if ZF = 0 then jump
Example:
JNZ
label
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JNZ label1
PRINT 'zero.'
JMP exit
label1:
PRINT 'not zero.'
exit:
RET
C Z S O P A
unchanged
JO
Short Jump if Overflow.

Algorithm:
label
if OF = 1 then jump
Example:
; -5 - 127 = -132 (not in -128..127)
; the result of SUB is wrong (124),
; so OF = 1 is set:
org 100h
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MOV AL, -5
SUB AL, 127 ; AL = 7Ch (124)
JO label1
PRINT 'no overflow.'
JMP exit
label1:
PRINT 'overflow!'
exit:
RET
C Z S O P A
unchanged
Short Jump if Parity (even). Only 8 low bits of result are checked. Set by CMP,
Algorithm:
if PF = 1 then jump
Example:
JP
label
ORG 100h
MOV AL, 00000101b ; AL = 5
OR AL, 0
; just set flags.
JP label1
PRINT 'parity odd.'
JMP exit
label1:
exit:
RET
C Z S O P A
unchanged
Short Jump if Parity Even. Only 8 low bits of result are checked. Set by CMP,
JPE
Algorithm:
label
if PF = 1 then jump
Example:
ORG 100h
MOV AL, 00000101b ; AL = 5
OR AL, 0
; just set flags.
JPE label1
PRINT 'parity odd.'
JMP exit
label1:
exit:
RET
C Z S O P A
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unchanged
Short Jump if Parity Odd. Only 8 low bits of result are checked. Set by CMP, SUB,
ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 0 then jump
Example:
JPO
label
ORG 100h
MOV AL, 00000111b ; AL = 7
OR AL, 0
; just set flags.
JPO label1
JMP exit
label1:
PRINT 'parity odd.'
exit:
RET
C Z S O P A
unchanged
Short Jump if Signed (if negative). Set by CMP, SUB, ADD, TEST, AND, OR,
XOR instructions.
Algorithm:
JS
if SF = 1 then jump
Example:
label
ORG 100h
MOV AL, 10000000b ; AL = -128
OR AL, 0
; just set flags.
JS label1
PRINT 'not signed.'
JMP exit
label1:
PRINT 'signed.'
exit:
RET
C Z S O P A
unchanged
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Short Jump if Zero (equal). Set by CMP, SUB, ADD, TEST, AND, OR, XOR
instructions.
Algorithm:
if ZF = 1 then jump
Example:
JZ
label
ORG 100h
MOV AL, 5
CMP AL, 5
JZ label1
PRINT 'AL is not equal to 5.'
JMP exit
label1:
PRINT 'AL is equal to 5.'
exit:
RET
C Z S O P A
unchanged
Load AH from 8 low bits of Flags register.

Algorithm:
LAHF
No operands
AH = flags register
AH bit: 7 6 5 4 3 2 1 0
[SF] [ZF] [0] [AF] [0] [PF] [1] [CF]
bits 1, 3, 5 are reserved.
C Z S O P A
unchanged
Load memory double word into word register and DS.

Algorithm:
LDS
REG,
memory
REG = first word

DS = second word
Example:
ORG 100h
LDS AX, m
RET
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m DW 1234h
DW 5678h
END
AX is set to 1234h, DS is set to 5678h.

C Z S O P A
unchanged
Load Effective Address.

Algorithm:
REG,
memory
LEA
REG = address of memory (offset)
Example:
MOV BX, 35h
MOV DI, 12h
LEA SI, [BX+DI] ; SI = 35h + 12h = 47h
Note: The integrated 8086 assembler automatically replaces LEA with a more
efficient MOV where possible. For example:
org 100h
LEA AX, m
; AX = offset of m
RET
m dw 1234h
END
C Z S O P A
unchanged
Load memory double word into word register and ES.

Algorithm:
LES
REG,
memory
REG = first word

ES = second word
Example:
ORG 100h
LES AX, m
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RET
m DW 1234h
DW 5678h
END
AX is set to 1234h, ES is set to 5678h.

C Z S O P A
unchanged
Load byte at DS:[SI] into AL. Update SI.

Algorithm:
AL = DS:[SI]
if DF = 0 then
o SI = SI + 1
else
SI = SI - 1
Example:
LODSB
No operands
ORG 100h
LEA SI, a1
MOV CX, 5
MOV AH, 0Eh
m: LODSB
INT 10h
LOOP m
RET
a1 DB 'H', 'e', 'l', 'l', 'o'

C Z S O P A
unchanged
Load word at DS:[SI] into AX. Update SI.

Algorithm:
AX = DS:[SI]
if DF = 0 then
o SI = SI + 2
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else
LODSW
No operands
SI = SI - 2
Example:
ORG 100h
LEA SI, a1
MOV CX, 5
REP LODSW ; finally there will be 555h in AX.

RET
a1 dw 111h, 222h, 333h, 444h, 555h

C Z S O P A
unchanged
Decrease CX, jump to label if CX not zero.

Algorithm:
CX = CX - 1
if CX <> 0 then
o jump
else
LOOP
label
no jump, continue
Example:
ORG 100h
MOV CX, 5
label1:
PRINTN 'loop!'
LOOP label1
RET
C Z S O P A
unchanged
Decrease CX, jump to label if CX not zero and Equal (ZF = 1).
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Algorithm:
CX = CX - 1
if (CX <> 0) and (ZF = 1) then
o jump
else
LOOPE
label
no jump, continue
Example:
; Loop until result fits into AL alone,
; or 5 times. The result will be over 255
; on third loop (100+100+100),
; so loop will exit.
ORG 100h
MOV AX, 0
MOV CX, 5
label1:
PUTC '*'
ADD AX, 100
CMP AH, 0
LOOPE label1
RET
C Z S O P A
unchanged
Decrease CX, jump to label if CX not zero and Not Equal (ZF = 0).
Algorithm:
LOOPNE
label
CX = CX - 1
o jump
else
o
no jump, continue
Example:
; Loop until '7' is found,

; or 5 times.
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ORG 100h
MOV SI, 0
MOV CX, 5
label1:
PUTC '*'
MOV AL, v1[SI]
INC SI
; next byte (SI=SI+1).
CMP AL, 7
LOOPNE label1
RET
v1 db 9, 8, 7, 6, 5
C Z S O P A
unchanged
Decrease CX, jump to label if CX not zero and ZF = 0.

Algorithm:
CX = CX - 1
o jump
else
LOOPNZ
label
no jump, continue
Example:
; Loop until '7' is found,
; or 5 times.
ORG 100h
MOV SI, 0
MOV CX, 5
label1:
PUTC '*'
MOV AL, v1[SI]
INC SI
; next byte (SI=SI+1).
CMP AL, 7
LOOPNZ label1
RET
v1 db 9, 8, 7, 6, 5
C Z S O P A
unchanged
Decrease CX, jump to label if CX not zero and ZF = 1.

Algorithm:
CX = CX - 1
o jump
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else
LOOPZ
label
no jump, continue
Example:
; Loop until result fits into AL alone,
; or 5 times. The result will be over 255
; on third loop (100+100+100),
; so loop will exit.
ORG 100h
MOV AX, 0
MOV CX, 5
label1:
PUTC '*'
ADD AX, 100
CMP AH, 0
LOOPZ label1
RET
C Z S O P A
unchanged
MOV
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
SREG,
memory
memory,
SREG
REG, SREG
SREG, REG
Copy operand2 to operand1.
The MOV instruction cannot:
set the value of the CS and IP registers.

copy value of one segment register to another segment register (should
copy to general register first).
copy immediate value to segment register (should copy to general register
first).
Algorithm:
operand1 = operand2
Example:
ORG 100h
MOV AX, 0B800h ; set AX = B800h (VGA memory).
MOV DS, AX
; copy value of AX to DS.
MOV CL, 'A'
; CL = 41h (ASCII code).
MOV CH, 01011111b ; CL = color attribute.
MOV BX, 15Eh
; BX = position on screen.
MOV [BX], CX
; w.[0B800h:015Eh] = CX.
RET
; returns to operating system.
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C Z S O P A
unchanged
Copy byte at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:
ES:[DI] = DS:[SI]
if DF = 0 then
o SI = SI + 1
o DI = DI + 1
else
o
o
MOVSB
No operands
SI = SI - 1
DI = DI - 1
Example:
ORG 100h
CLD
LEA SI, a1
LEA DI, a2
MOV CX, 5
REP MOVSB
RET
a1 DB 1,2,3,4,5
a2 DB 5 DUP(0)
C Z S O P A
unchanged
Copy word at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:
MOVSW
No operands
ES:[DI] = DS:[SI]
if DF = 0 then
o SI = SI + 2
DI = DI + 2
o
o
SI = SI - 2
DI = DI - 2
else
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Example:
ORG 100h
CLD
LEA SI, a1
LEA DI, a2
MOV CX, 5
REP MOVSW
RET
a1 DW 1,2,3,4,5
a2 DW 5 DUP(0)
C Z S O P A
unchanged
Unsigned multiply.
Algorithm:
REG
memory
Example:
MOV AL, 200 ; AL = 0C8h
MOV BL, 4
MUL BL
; AX = 0320h (800)
RET
C Z S O P A
MUL

AX = AL * operand.
(DX AX) = AX * operand.
r ? ? r ? ?
CF=OF=0 when high section of the result is zero.
Negate. Makes operand negative (two's complement).
NEG
REG
memory
Algorithm:
Invert all bits of the operand

Add 1 to inverted operand
Example:
MOV AL, 5 ; AL = 05h

NEG AL
; AL = 0FBh (-5)
NEG AL
; AL = 05h (5)
RET
C Z S O P A
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r r r r r r
No Operation.
Algorithm:
NOP
No operands
Do nothing
Example:
; do nothing, 3 times:
NOP
NOP
NOP
RET
C Z S O P A
unchanged
Invert each bit of the operand.

Algorithm:
REG
memory
OR
if bit is 1 turn it to 0.
if bit is 0 turn it to 1.
Example:
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
C Z S O P A
NOT
unchanged
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
Logical OR between all bits of two operands. Result is stored in first operand.
These rules apply:
1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0
Example:
MOV AL, 'A'
; AL = 01000001b
OR AL, 00100000b ; AL = 01100001b ('a')
RET
C Z S O P A
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0 r r 0 r ?
Output from AL or AX to port.

First operand is a port number. If required to access port number over 255 DXregister should be used.
OUT
im.byte, AL
im.byte, AX
DX, AL
DX, AX
Example:
MOV AX, 0FFFh ; Turn on all
OUT 4, AX ; traffic lights.
MOV AL, 100b ; Turn on the third

OUT 7, AL ; magnet of the stepper-motor.
C Z S O P A
unchanged
Get 16 bit value from the stack.

Algorithm:
REG
SREG
memory
Example:
MOV AX, 1234h
PUSH AX
POP DX ; DX = 1234h
RET
C Z S O P A
POP
operand = SS:[SP] (top of the stack)

SP = SP + 2
unchanged
Pop all general purpose registers DI, SI, BP, SP, BX, DX, CX, AX from the stack.
SP value is ignored, it is Popped but not set to SP register).
POPA
No operands
Note: this instruction works only on 80186 CPU and later!

Algorithm:
POP DI
POP SI
POP BP
POP xx (SP value ignored)
POP BX
POP DX
POP CX
POP AX
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C Z S O P A
unchanged
Get flags register from the stack.

Algorithm:
POPF
No operands
flags = SS:[SP] (top of the stack)

SP = SP + 2
C Z S O P A
popped
Store 16 bit value in the stack.
Note: PUSH immediate works only on 80186 CPU and later!

Algorithm:
PUSH
REG
SREG
memory
immediate
SP = SP - 2
SS:[SP] (top of the stack) = operand
Example:
MOV AX, 1234h
PUSH AX
POP DX ; DX = 1234h
RET
C Z S O P A
unchanged
PUSHA
No operands
Push all general purpose registers AX, CX, DX, BX, SP, BP, SI, DI in the stack.
Original value of SP register (before PUSHA) is used.
Note: this instruction works only on 80186 CPU and later!
Algorithm:
PUSH AX
PUSH CX
PUSH DX
PUSH BX
PUSH SP
PUSH BP
PUSH SI
PUSH DI
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C Z S O P A
unchanged
Store flags register in the stack.

Algorithm:
PUSHF
No operands
SP = SP - 2
SS:[SP] (top of the stack) = flags
C Z S O P A
unchanged
Rotate operand1 left through Carry Flag. The number of rotates is set by operand2.
When immediate is greater then 1, assembler generates several RCL xx,
1instructions because 8086 has machine code only for this instruction (the same
principle works for all other shift/rotate instructions).
RCL
memory,
immediate
REG,
immediate
memory, CL
REG, CL
Algorithm:
shift all bits left, the bit that goes off is set to CF and previous value of CF
is inserted to the right-most position.
Example:
STC
; set carry (CF=1).
MOV AL, 1Ch
; AL = 00011100b
RCL AL, 1
; AL = 00111001b, CF=0.
RET
C O
r r
OF=0 if first operand keeps original sign.
RCR
memory,
immediate
REG,
Rotate operand1 right through Carry Flag. The number of rotates is set by
operand2.
immediate
Algorithm:
memory, CL
REG, CL
shift all bits right, the bit that goes off is set to CF and previous value of
CF is inserted to the left-most position.
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Example:
STC
; set carry (CF=1).
MOV AL, 1Ch
; AL = 00011100b
RCR AL, 1
; AL = 10001110b, CF=0.
RET
C O
r r
Repeat following MOVSB, MOVSW, LODSB, LODSW, STOSB, STOSW

instructions CX times.
Algorithm:
check_cx:
if CX <> 0 then
REP
chain
instruction
do following chain instruction

CX = CX - 1
go back to check_cx
exit from REP cycle
else
Z
r
Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1

(result is Equal), maximum CX times.
Algorithm:
check_cx:
REPE
chain
instruction
if CX <> 0 then

CX = CX - 1
if ZF = 1 then:
o go back to check_cx
else
o
exit from REPE cycle
else
exit from REPE cycle
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Example:
see cmpsb.asm in c:\emu8086\examples\.
Z
r

(result is Not Equal), maximum CX times.
Algorithm:
check_cx:
if CX <> 0 then
REPNE
chain
instruction

CX = CX - 1
if ZF = 0 then:
else
exit from REPNE cycle
else
exit from REPNE cycle
Z
r

(result is Not Zero), maximum CX times.
REPNZ
chain
instruction
Algorithm:
check_cx:
if CX <> 0 then

CX = CX - 1
if ZF = 0 then:
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else
exit from REPNZ cycle
else
exit from REPNZ cycle
Z
r

(result is Zero), maximum CX times.
Algorithm:
check_cx:
if CX <> 0 then
REPZ
chain
instruction

CX = CX - 1
if ZF = 1 then:
else
exit from REPZ cycle
else
exit from REPZ cycle
Z
r
RET
No operands
or even
immediate
Return from near procedure.
Algorithm:
Pop from stack:

o IP
if immediate operand is present: SP = SP + operand
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Example:
ORG 100h ; for COM file.
CALL p1
ADD AX, 1
RET
; return to OS.
p1 PROC ; procedure declaration.

MOV AX, 1234h
RET ; return to caller.
p1 ENDP
C Z S O P A
unchanged
Return from Far procedure.

Algorithm:
RETF
No operands
or even
immediate
Pop from stack:

o IP
o CS
if immediate operand is present: SP = SP + operand
C Z S O P A
unchanged
Rotate operand1 left. The number of rotates is set by operand2.
ROL
Algorithm:
memory,
immediate
REG,
immediate
memory, CL
REG, CL
shift all bits left, the bit that goes off is set to CF and the same bit is
inserted to the right-most position.
Example:
MOV AL, 1Ch
; AL = 00011100b
ROL AL, 1
; AL = 00111000b, CF=0.
RET
C O
r r
Rotate operand1 right. The number of rotates is set by operand2.

Algorithm:
shift all bits right, the bit that goes off is set to CF and the same bit is
inserted to the left-most position.
Example:
MOV AL, 1Ch
; AL = 00011100b
ROR AL, 1
; AL = 00001110b, CF=0.
RET
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ROR
memory,
immediate
REG,
immediate
memory, CL
REG, CL
C O
r r
Store AH register into low 8 bits of Flags register.

Algorithm:
SAHF
No operands
flags register = AH
AH bit: 7 6 5 4 3 2 1 0
[SF] [ZF] [0] [AF] [0] [PF] [1] [CF]
bits 1, 3, 5 are reserved.
C Z S O P A
r r r r r r
Shift Arithmetic operand1 Left. The number of shifts is set by operand2.

Algorithm:
SAL
memory,
immediate
REG,
immediate
memory, CL
REG, CL
Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.
Example:
MOV AL, 0E0h
; AL = 11100000b
SAL AL, 1
; AL = 11000000b, CF=1.
RET
C O
r r
SAR
memory,
immediate
REG,
immediate
memory, CL
REG, CL
Shift Arithmetic operand1 Right. The number of shifts is set by operand2.

Algorithm:
Shift all bits right, the bit that goes off is set to CF.
The sign bit that is inserted to the left-most position has the same value as
before shift.
Example:
MOV AL, 0E0h
; AL = 11100000b
SAR AL, 1
; AL = 11110000b, CF=0.
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MOV BL, 4Ch

; BL = 01001100b
SAR BL, 1
; BL = 00100110b, CF=0.
RET
C O
r r

Subtract with Borrow.
Algorithm:
SBB
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
operand1 = operand1 - operand2 - CF

Example:
STC
MOV AL, 5
SBB AL, 3 ; AL = 5 - 3 - 1 = 1
RET
C Z S O P A
r r r r r r
Compare bytes: AL from ES:[DI].

Algorithm:
SCASB
No operands
ES:[DI] - AL
if DF = 0 then
o DI = DI + 1
else
DI = DI - 1
C Z S O P A
r r r r r r
Compare words: AX from ES:[DI].

Algorithm:
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ES:[DI] - AX
if DF = 0 then
o DI = DI + 2
SCASW
No operands
else
DI = DI - 2
C Z S O P A
r r r r r r
Shift operand1 Left. The number of shifts is set by operand2.

Algorithm:
SHL
memory,
immediate
REG,
immediate
memory, CL
REG, CL
Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.
Example:
MOV AL, 11100000b
SHL AL, 1
; AL = 11000000b, CF=1.
RET
C O
r r
Shift operand1 Right. The number of shifts is set by operand2.
SHR
Algorithm:
memory,
immediate
REG,
immediate
memory, CL
REG, CL
Shift all bits right, the bit that goes off is set to CF.
Zero bit is inserted to the left-most position.
Example:
MOV AL, 00000111b
SHR AL, 1
; AL = 00000011b, CF=1.
RET
C O
r r

Set Carry flag.
Algorithm:
No operands
CF = 1
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STC
Set Direction flag. SI and DI will be decremented by chain instructions: CMPSB,

CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW.
Algorithm:
STD
No operands
DF = 1
D
Set Interrupt enable flag. This enables hardware interrupts.

Algorithm:
STI
No operands
IF = 1
I
Store byte in AL into ES:[DI]. Update DI.
STOSB
Algorithm:
No operands
ES:[DI] = AL
if DF = 0 then
o DI = DI + 1
else
DI = DI - 1
Example:
ORG 100h
LEA DI, a1
MOV AL, 12h
MOV CX, 5
REP STOSB
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RET
a1 DB 5 dup(0)
C Z S O P A
unchanged
Store word in AX into ES:[DI]. Update DI.

Algorithm:
ES:[DI] = AX
if DF = 0 then
o DI = DI + 2
else
STOSW
No operands
DI = DI - 2
Example:
ORG 100h
LEA DI, a1
MOV AX, 1234h
MOV CX, 5
REP STOSW
RET
a1 DW 5 dup(0)
SUB
C Z S O P A
unchanged
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
Subtract.
Algorithm:
operand1 = operand1 - operand2
Example:
MOV AL, 5
immediate
SUB AL, 1
; AL = 4
RET
C Z S O P A
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r r r r r r
Logical AND between all bits of two operands for flags only. These flags are
effected: ZF, SF, PF. Result is not stored anywhere.
These rules apply:
TEST
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
Example:
MOV AL, 00000101b
TEST AL, 1
; ZF = 0.
TEST AL, 10b
; ZF = 1.
RET
C Z S O P
0 r r 0 r
Exchange values of two operands.

Algorithm:
operand1 < - > operand2
XCHG
REG,
memory
memory,
REG
REG, REG
Example:
MOV AL, 5
MOV AH, 2
XCHG AL, AH ; AL = 2, AH = 5
XCHG AL, AH ; AL = 5, AH = 2
RET
C Z S O P A
unchanged
Translate byte from table.

Copy value of memory byte at DS:[BX + unsigned AL] to AL register.
XLATB
No operands
Algorithm:
AL = DS:[BX + unsigned AL]
Example:
ORG 100h
LEA BX, dat
MOV AL, 2
XLATB ; AL = 33h
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RET
dat DB 11h, 22h, 33h, 44h, 55h
C Z S O P A
unchanged
Logical XOR (Exclusive OR) between all bits of two operands. Result is stored in
first operand.
These rules apply:
XOR
REG,
memory
memory,
REG
REG, REG
memory,
immediate
REG,
immediate
1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0
Example:
MOV AL, 00000111b
XOR AL, 00000010b ; AL = 00000101b
RET
C Z S O P A
0 r r 0 r ?
ASSEMBLER DIRECTIVES OF 8086
Variables
Variable is a memory location. For a programmer it is much easier to have some value be kept in a variable named
"var1" then at the address 5A73:235B, especially when you have 10 or more variables.
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Our compiler supports two types of variables: BYTE and WORD.

Syntax for a variable declaration:
name DB value
name DW value
DB - stays for Define Byte.

DW - stays for Define Word.
name - can be any letter or digit combination, though it should start with a letter. It's possible to declare unnamed
variables by not specifying the name (this variable will have an address but no name).
value - can be any numeric value in any supported numbering system (hexadecimal, binary, or decimal), or "?"
symbol for variables that are not initialized.
As you probably know from part 2 of this tutorial, MOV instruction is used to copy values from source to
destination.
Let's see another example with MOV instruction:
ORG 100h
MOV AL, var1

MOV BX, var2
RET
; stops the program.
VAR1 DB 7
var2 DW 1234h
Copy the above code to emu8086 source editor, and press F5 key to compile and load it in the emulator. You should
get something like:
As you see this looks a lot like our example, except that variables are replaced with actual memory locations. When
compiler makes machine code, it automatically replaces all variable names with their offsets. By default segment is
loaded in DS register (when COM files is loaded the value of DS register is set to the same value as CS register code segment).
In memory list first row is an offset, second row is a hexadecimal value, third row is decimal value, and last row is
an ASCII character value.

Compiler is not case sensitive, so "VAR1" and "var1" refer to the same variable.
The offset of VAR1 is 0108h, and full address is 0B56:0108.
The offset of var2 is 0109h, and full address is 0B56:0109, this variable is a WORD so it occupies 2 BYTES. It is
assumed that low byte is stored at lower address, so 34h is located before 12h.
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You can see that there are some other instructions after the RET instruction, this happens because disassembler has
no idea about where the data starts, it just processes the values in memory and it understands them as valid 8086
instructions (we will learn them later).
You can even write the same program using DB directive only:
ORG 100h ; just a directive to make a simple .com file
(expands into no code).
DB 0A0h
DB 08h
DB 01h
DB 8Bh
DB 1Eh
DB 09h
DB 01h
DB 0C3h
DB 7
DB 34h
DB 12h
Copy the above code to emu8086 source editor, and press F5 key to compile and load it in the emulator. You should
get the same disassembled code, and the same functionality!
As you may guess, the compiler just converts the program source to the set of bytes, this set is called machine code,
processor understands the machine code and executes it.
ORG 100h is a compiler directive (it tells compiler how to handle the source code). This directive is very important
when you work with variables. It tells compiler that the executable file will be loaded at the offset of 100h (256
bytes), so compiler should calculate the correct address for all variables when it replaces the variable names with
their offsets. Directives are never converted to any real machine code.
Why executable file is loaded at offset of 100h? Operating system keeps some data about the program in the first
256 bytes of the CS (code segment), such as command line parameters and etc.
Though this is true for COM files only, EXE files are loaded at offset of 0000, and generally use special segment
for variables. Maybe we'll talk more about EXE files later.
Arrays
Arrays can be seen as chains of variables. A text string is an example of a byte array, each character is presented as
an ASCII code value (0..255).
Here are some array definition examples:

a DB 48h, 65h, 6Ch, 6Ch, 6Fh, 00h
b DB 'Hello', 0
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b is an exact copy of the a array, when compiler sees a string inside quotes it automatically converts it to set of
bytes. This chart shows a part of the memory where these arrays are declared:
You can access the value of any element in array using square brackets, for example:
MOV AL, a[3]
You can also use any of the memory index registers BX, SI, DI, BP, for example:
MOV SI, 3
MOV AL, a[SI]
If you need to declare a large array you can use DUP operator.
The syntax for DUP:
number DUP ( value(s) )

number - number of duplicate to make (any constant value).
value - expression that DUP will duplicate.
for example:
c DB 5 DUP(9)
is an alternative way of declaring:
c DB 9, 9, 9, 9, 9
one more example:

d DB 5 DUP(1, 2)
is an alternative way of declaring:
d DB 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
Of course, you can use DW instead of DB if it's required to keep values larger then 255, or smaller then 128. DW cannot be used to declare strings.
Getting the Address of a Variable
There is LEA (Load Effective Address) instruction and alternative OFFSET operator. Both OFFSETand LEA can
be used to get the offset address of the variable.
LEA is more powerful because it also allows you to get the address of an indexed variables. Getting the address of
the variable can be very useful in some situations, for example when you need to pass parameters to a procedure.
Reminder:
In order to tell the compiler about data type,
these prefixes should be used:
BYTE PTR - for byte.
WORD PTR - for word (two bytes).
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For example:
BYTE PTR [BX] ; byte access.
or
WORD PTR [BX] ; word access.
emu8086 supports shorter prefixes as well:
b. - for BYTE PTR

w. - for WORD PTR
in certain cases the assembler can calculate the data type automatically.
Here is first example:

ORG 100h
MOV AL, VAR1

moving it to AL.
LEA
BX.
BX, VAR1
; check value of VAR1 by
; get address of VAR1 in
MOV BYTE PTR [BX], 44h

of VAR1.
MOV AL, VAR1
moving it to AL.
; modify the contents
RET
VAR1 DB 22h
END
Here is another example, that uses OFFSET instead of LEA:

ORG 100h
MOV AL, VAR1
moving it to AL.
MOV BX, OFFSET VAR1

in BX.
; get address of VAR1
MOV BYTE PTR [BX], 44h

of VAR1.
; modify the contents
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MOV AL, VAR1

moving it to AL.
RET
VAR1 DB 22h
END
Both examples have the same functionality.
These lines:
LEA BX, VAR1
MOV BX, OFFSET VAR1
are even compiled into the same machine code: MOV BX, num
num is a 16 bit value of the variable offset.
Please note that only these registers can be used inside square brackets (as memory pointers):BX, SI, DI, BP!
(see previous part of the tutorial).
Constants
Constants are just like variables, but they exist only until your program is compiled (assembled). After definition of
a constant its value cannot be changed. To define constants EQU directive is used:
name EQU < any expression >
For example:
k EQU 5
MOV AX, k
The above example is functionally identical to code:

MOV AX, 5
You can view variables while your program executes by selecting "Variables" from the "View" menu of emulator.
To view arrays you should click on a variable and set Elements property to array size. In assembly language there
are not strict data types, so any variable can be presented as an array.
Variable can be viewed in any numbering system:
HEX - hexadecimal (base 16).
BIN - binary (base 2).
OCT - octal (base 8).
SIGNED - signed decimal (base 10).
UNSIGNED - unsigned decimal (base 10).
CHAR - ASCII char code (there are 256 symbols, some symbols are invisible).
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You can edit a variable's value when your program is running, simply double click it, or select it and
click Edit button.
It is possible to enter numbers in any system, hexadecimal numbers should have "h" suffix, binary "b" suffix, octal
"o" suffix, decimal numbers require no suffix. String can be entered this way:
'hello world', 0
(this string is zero terminated).
Arrays may be entered this way:
1, 2, 3, 4, 5
(the array can be array of bytes or words, it depends whether BYTE or WORD is selected for edited variable).
Expressions are automatically converted, for example:

when this expression is entered:
5+2
it will be converted to 7 etc...
a) Ascii addition:
Simple Programs
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data segment
num1 dw 0039h
num2 db 35h
result dw 01 dup(0)
data ends
code segment
assume ds:data,cs:code
start:mov ax,data
mov ds,ax
mov ax,num1
mov bl,num2
add ax,bl
aaa
add ax,3030h
mov result,ax
hlt
code ends
end start
b) Ascii Subtraction:
data segment
num1 dw 0039h
num2 db 35h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov bl,num2
sub ax,bl
aas
add ax,3030h
mov result,ax
hlt
code ends
end start
c) Ascii Multiplication:
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data segment
num1 dw 3436h
num2 db 37h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov bl,num2
and ax,0f0fh
and bl,0fh
div bl
aad
add ax,3030h
mov result,ax
hlt
code ends
end start
d) Ascii Division:
data segment
num1 dw 3436h
num2 db 37h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov bl,num2
and ax,0f0fh
and bl,0fh
aad
div bl
add ax,3030h
mov result,ax
hlt
code ends
end start
Programs on Arithmetic Operations

a) Addition:
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data segment
num1 dw 1234h
num2 dw 4321h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov bx,num2
add ax,bx
mov result,ax
hlt
code ends
end start
result: Location
0000h
0001h
0002h
0003h
0004h
0005h
data
34h
12h
21h
43h
55h
55h
b) Subtraction:
data segment
num1 dw 4321h
num2 dw 1111h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov bx,num2
sub ax,bx
mov result,ax
hlt
code ends
end start
result: Location
21h
43h
11h
11h
10h
32h
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0000h
0001h
0002h
0003h
0004h
0005h
data
c) Multiplication:
data segment
num1 dw 1111h
num2 dw 1111h
result dw 04 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov dx,num2
mul bx
mov result,ax
mov result+2,dx
hlt
code ends
end start
result: Location
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
data
11h
11h
11h
11h
10h
32h
34h
12h
d) Division:
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data segment
num1 dw 3210h
num2 dw 1234h
num3 dw 1111h
result dw 01 dup(0)
data ends
code segment
start:mov ax,data
mov ds,ax
mov ax,num1
mov dx,num2
mov bx,num3
div bx
mov result,ax
mov result+2,dx
hlt
code ends
end start
result: Location
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
data
10h
32h
34h
12h
11h
11h
11h
11h
00h
00h
Programs on sorting the numbers
a) Ascending Order
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data segment
num db 09h,06h,07h
data ends
code segment
start:
mov ax,data
mov ds,ax
mov dl,02h
step3:mov cl,dl
mov si,offset num
step2:mov al,[si]
cmp al,[si+1]
ja step1
xchg al,[si+1]
mov [si],al
step1:inc si
dec cl
jnz step2
dec dl
jnz step3
hlt
code ends
end start
result: Location
Input: 0000h
0001h
0002h
Output 0000h
0001h
0002h
data
09h
06h
07h
06h
07h
09h
b) Descending order:
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data segment
num db 09h,06h,07h
data ends
code segment
start:
mov ax,data
mov ds,ax
mov dl,02h
step3:mov cl,dl
mov si,offset num
step2:mov al,[si]
cmp al,[si+1]
jb step1
xchg al,[si+1]
mov [si],al
step1:inc si
dec cl
jnz step2
dec dl
jnz step3
hlt
code ends
end start
data
Input :0000h
0001h
0002h
Output:0000h
0001h
0002h
06h
07h
09h
09h
06h
07h
result: Location
Programs on String Manipulations

a) Block Transfer:
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data segment
num db 32h,30h,29h,25h
num2 db 04 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
mov es,ax
mov si,offset num
mov di,offset num2
mov cl,04h
rep movsb
hlt
code ends
end start
result: Location
data
Input: 0000h
0001h
0002h
0003h
Output 0004h
0005h
0006h
0007h
32h
30h
29h
25h
32h
30h
29h
25h
b) Block Transfer:
data segment
num db 32h,30h,29h,25h
num2 db 04 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
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mov es,ax
mov si,offset num
mov di,offset num2
mov bx,0004h
step:
dec bx
lodsb
mov [bx][di],al
jnz step
hlt
code ends
end start
result: Location
data
Input: 0000h
0001h
0002h
0003h
Output 0004h
0005h
0006h
0007h
32h
30h
29h
25h
25h
29h
30h
32h
c) Insertion of a string:
data segment
num1 db 32h,30h,29h,25h
num2 db 26h,31h
place dw 0001h
length1 db 04h
length2 db 02h
result db 07 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
mov es,ax
mov si,offset num1
mov bx,offset num2
mov di,offset result
mov cl,length1
mov ch,length2
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back:
cmp si,place
je li
here:
lodsb
stosb
dec cl
jnz back
hlt
li:
mov al,[bx]
mov [di],al
inc di
inc bx
dec ch
jnz li
jmp here
code ends
end start
data
Input: 0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
Output:000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
32h
30h
29h
25h
26h
31h
01h
00h
04h
02h
32h
30h
26h
31h
29h
25h
result: Location
d) Deletion of a string:
data segment
giv db 32h,30h,29h,25h
place dw 0000h
lgiv dw 0004h
ldel dw 0002h
result db 06 dup(0)
data ends
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code segment
start:
mov ax,data
mov ds,ax
mov es,ax
mov si,offset giv
mov di,offset result
mov cx,0000h
back:
cmp si,place
je li
lodsb
stosb
inc cx
here:
cmp cx,lgiv
jb back
hlt
li:
add cx,ldel
add si,ldel
jmp here
code ends
end start
data
Input: 0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
Output:000Ah
000Bh
32h
30h
29h
25h
00h
00h
04h
00h
02h
00h
29h
25h
result: Location
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Programs on Conversions
a)
BCD to Hexa conversion:
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data segment
num1 db 32h
result dw 01 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
mov al,num1
mov bl,num1
mov cl,04h
and al,0f0h
and bl,0fh
shr al,cl
mov ch,0ah
mul ch
add al,bl
mov result,al
hlt
code ends
end start
b)
Hexa to Ascii coded BCD :
data segment
num1 db 22h
result dw 01 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
mov al,num1
mov ah,00h
mov bl,0ah
div bl
xchg al,ah
add ax,3030h
mov result,ax
hlt
code ends
end start
Packed to unpacked BCD:
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c)
data segment
num1 db 32h
result dw 01 dup(0)
data ends
code segment
start:
mov ax,data
mov ds,ax
mov al,num1
mov bl,num1
and al,0fh
and bl,0f0h
mov cl,04h
shr bl,cl
mov ah,bl
add ax,3030h
mov result,ax
hlt
code ends
end start
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PIN DIAGRAM OF 8086
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Signal Description of 8086
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The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged
in a 40 pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor
mode ) and other function in maximum mode configuration (multiprocessor mode ).
The 8086 signals can be categorised in three groups. The first are the signal having
common functions in minimum as well as maximum mode.
The second are the signals which have special functions for minimum mode and third
are the signals having special functions for maximum mode.
The following signal descriptions are common for both modes.
AD15-AD0 : These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the data bus
during T2, T3, Tw and T4.
These lines are active high and float to a tristate during interrupt acknowledge and local
bus hold acknowledge cycles.
A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines.
During T1 these are the most significant address lines for memory operations.
During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2,T3,Tw and T4.
The status of the interrupt enable flag bit is updated at the beginning of each clock
cycle.
The S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as in below fig.
These lines float to tri-state off during the local bus hold acknowledge. The status line S6
is always low .
The address bit are separated from the status bit using latches controlled by the ALE
signal.
S4
S3
0
0
1
1
0
1
0
1
Indication
Alternate Data
Stack
Code or none
Data
G.Vijaya Santhi,Asst.prof
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BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher
order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8
and is used to derive chip selects of odd address memory bank or peripherals. BHE is low
during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus. The status information is available during T2, T3
and T4. The signal is active low and tristated during hold. It is low during T1 for the first
pulse of the interrupt acknowledge cycle.
0
0
1
0
1
0
Whole word
Upper byte from or to even
address
odd address
Lower byte from or to even address
RD Read : This signal on low indicates the peripheral that the processor is performing
s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of
any read cycle. The signal remains tristated during the hold acknowledge.
READY : This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086. the signal is active high.
INTR-Interrupt Request : This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is active
high and internally synchronized.
TEST : This input is examined by a WAIT instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
CLK- Clock Input : The clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle.
MN/MX : The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode.
The following pin functions are for the minimum mode operation of 8086.
M/IO Memory/IO : This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. This line becomes active high in
the previous T4 and remains active till final T4 of the current cycle. It is tristated during
local bus hold acknowledge .
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INTA Interrupt Acknowledge : This signal is used as a read strobe for interrupt
acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.
ALE Address Latch Enable : This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches. This
signal is active high and is never tristated.
DT/R Data Transmit/Receive: This output is used to decide the direction of data flow
through the transreceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low.
DEN Data Enable : This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to
separate the data from the multiplexed address/data signal. It is active from the middle of
T2 until the middle of T4. This is tristated during hold acknowledge cycle.
HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus access.
The processor, after receiving the HOLD request, issues the hold acknowledge signal on
HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.
At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and is should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will
release the local bus during T4 provided :
1.The request occurs on or before T2 state of the current cycle.
2.The current cycle is not operating over the lower byte of a word.
3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin function are applicable for maximum mode operation of 8086.
S2, S1, S0 Status Lines : These are the status lines which reflect the type of operation,
being carried out by the processor. These become activity during T4 of the previous cycle
and active during T1 and T2 of the current bus cycles.
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Indication
Interrupt Acknowledge
Read I/O port
Write I/O port
Halt
Code Access
Read memory
Write memory
Passive
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S2
0
0
0
0
1
1
1
1
LOCK : This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low.
The LOCK signal is activated by the LOCK prefix instruction and remains active until
the completion of the next instruction. When the CPU is executing a critical instruction
which requires the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus.
The 8086, while executing the prefixed instruction, asserts the bus lock signal output,
which may be connected to an external bus controller.
By prefetching the instruction, there is a considerable speeding up in instruction

execution in 8086. This is known as instruction pipelining.
At the starting the CS:IP is loaded with the required address from which the execution is
to be started. Initially, the queue will be empty an the microprocessor starts a fetch
operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd
or two bytes at a time, if the CS:IP address is even.
The first byte is a complete opcode in case of some instruction (one byte opcode
instruction) and is a part of opcode, in case of some instructions ( two byte opcode
instructions), the remaining part of code lie in second byte.
The second byte is then decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as instruction data.
The queue is updated after every byte is read from the queue but the fetch cycle is
initiated by BIU only if at least two bytes of the queue are empty and the EU may be
concurrently executing the fetched instructions.
The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the program.
The fetch operation of the next instruction is overlapped with the execution of the
current instruction. As in the architecture, there are two separate units, namely Execution
unit and Bus interface unit.
While the execution unit is busy in executing an instruction, after it is completely
decoded, the bus interface unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status.
QS0
Indication
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QS1
0
0
1
1
0
1
0
1
No operation
First byte of the opcode from the queue
Empty queue
Subsequent byte from the queue
RQ/GT0, RQ/GT1 Request/Grant : These pins are used by the other local bus master
in maximum mode, to force the processor to release the local bus at the end of the
processor current bus cycle.
Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
RQ/GT pins have internal pull-up resistors and may be left unconnected.
Request/Grant sequence is as follows:
1.A pulse of one clock wide from another bus master requests the bus access to 8086.
2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it
will enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely
to be disconnected from the local bus of the system.
3.A one clock wide pulse from the another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the next clock
cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses.
There must be at least one dead clock cycle after each bus exchange.
The request and grant pulses are active low.
For the bus request those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as in case of HOLD and HLDA in
minimum mode.

The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
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Minimum Mode 8086 System
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
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The remaining components in the system are latches, transreceivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the system.
Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
They are controlled by two signals namely, DEN and DT/R.
The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
Usually, EPROM are used for monitor storage, while RAM for users program storage. A
system may contain I/O devices.
The working of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than qualitatively describing the operations.
The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and
also M / IO signal. During the negative going edge of this signal, the valid address is
latched on the local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO
signal indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.
The read (RD) signal causes the address device to enable its data bus drivers. After RD
goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high. When the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.
A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending
the address in T1, the processor sends the data to be written to the addressed location.
The data remains on the bus until middle of T4 state. The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O
word to be read or write.
The M/IO, RD and WR signals indicate the type of data transfer as specified in table
below.
T1
T2
T3
TW
T4
T1
Clk
ALE
BHE
A19 A16
S7 S3
ADD / DATA
A15 A0
Valid data D15 D0
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ADD / STATUS
WR
DEN
DT / R
Write Cycle Timing Diagram for Minimum Mode
Hold Response sequence: The HOLD pin is checked at leading edge of each clock
pulse. If it is received active by the processor before T4 of the previous cycle or during T1
state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting master.
The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.
Clk
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HOLD
HLDA
Bus Request and Bus Grant Timings in Minimum Mode System
Maximum Mode 8086 System
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information .
In the maximum mode, there may be more than one microprocessor in the system
configuration.
The components in the system are same as in the minimum mode system.
The basic function of the bus controller chip IC8288, is to derive control signals like RD
and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by
the processor on the status lines.
The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.
It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance
of the MCE/PDEN output depends upon the status of the IOB pin.
If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it
acts as peripheral data enable used in the multiple bus configurations.
INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to
an interrupting device.
IORC, IOWC are I/O read command and I/O write command signals respectively .
These signals enable an IO interface to read or write the data from or to the address port.
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The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
All these command signals instructs the memory to accept or send data from or to the
bus.
For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.
Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.
DEN
DT/ R
S1
IORC
8288
IOWT
S2
MWTC
AEN
IOB
CEN AL MRDC
Clk
S0
Reset
Clk
Generator
RDY 8284
S0
S1
S2
Reset
Clk
Ready
+ 5V
8086
AD6-AD15
A16-A19
CLK
A/D
Latches
DT/R
DEN
Control bus
DIR
Data
buffer
Address bus
BHE A0
A
dd
bu
CS0H CS0L RD
WR
Memory
CS WR RD
Peripheral
Data bus
Maximum Mode 8086 System.
R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as
on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
If reader input is not activated before T3, wait state will be inserted between T3 and T4.
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Timings for RQ/ GT Signals :

The request/grant response sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.
When a request is detected and if the condition for HOLD request are satisfied, the
processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1
(next) state.
When the requesting master receives this pulse, it accepts the control of the bus, it sends
a release pulse to the processor using RQ/GT pin.
T1
T2
One bus cycle

T3
T4
T1
Clk
ALE
S2 S0
Add/Status
Add/Data
Inactive
Active
BHE, A19 A16
A15 A0
Active
S7 S3
D15 D0
MRDC
DT / R
DEN
Memory Read Timing in Maximum Mode
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T1
T2
One bus cycle

T3
T4
T1
Clk
ALE
S2 S0
Active
ADD/STATUS
BHE
ADD/DATA
A15-A0
Inactive
Active
S7 S3
Data out D15 D0
AMWC or AIOWC
MWTC or IOWC
DT / R
high
DEN
Memory Write Timing in Maximum mode.
Clk
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RQ / GT
Another master
request bus access
CPU grant bus
Master releases
RQ/GT Timings in Maximum Mode.
Minimum Mode Interface
When the Minimum mode operation is selected, the 8086 provides all control signals
needed to implement the memory and I/O interface.
The minimum mode signal can be divided into the following basic groups : address/data
bus, status, control, interrupt and DMA.
Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long
and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit
address gives the 8086 a 1Mbyte memory address space. More over it has an independent
I/O address space which is 64K bytes in length.
The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0
through A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB
and D0 LSB.
When acting as a data bus, they carry read/write data for memory, input/output data for
I/O devices, and interrupt type codes from an interrupt controller.
Vcc
GND
INTR
A0-A15,A16/S3 A19/S6
INTA
Interrupt
interface
Address / data bus

TEST
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D0 D15
NMI
8086
MPU
RESET
ALE
BHE / S7
M / IO
HOLD
DMA
interface
Memory I/O
controls
DT / R
RD
HLDA
WR
Vcc
DEN
Mode select
READY
MN / MX
CLK clock
Block Diagram of the Minimum Mode 8086 MPU
Status signal:
The four most significant address lines A19 through A16 are also multiplexed but in this
case with status signals S6 through S3. These status bits are output on the bus at the same
time that data are transferred over the other bus lines.
Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal
segment registers are used to generate the physical address that was output on the address
bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the
segment address.
Status line S5 reflects the status of another internal characteristic of the 8086. It is the
logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.
S3
Segment Register
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S4
Extra
Stack
Code / none
Data
Memory segment status codes.
Control Signals :
The control signals are provided to support the 8086 memory I/O interfaces. They
control functions such as when the bus is to carry a valid address in which direction data
are to be transferred over the bus, when valid write data are on the bus and when to put
read data on the system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on
the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse
at ALE.
Another control signal that is produced during the bus cycle is BHE bank high enable.
Logic 0 on this used as a memory enable signal for the most significant byte half of the
data bus D8 through D1. These lines also serves a second function, which is as the S7
status line.
Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress
and in which direction data are to be transferred over the bus.
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The logic level of M/IO tells external circuitry whether a memory or I/O transfer is
taking place over the bus. Logic 1 at this output signals a memory operation and logic 0
an I/O operation.
The direction of data transfer over the bus is signaled by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into memory or output to an I/O device.
On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.
The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is
in progress. The 8086 switches WR to logic 0 to signal external device that valid write or
output data are on the bus.
On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN ( data
enable) and it signals external devices when they should put data on the bus.
There is one other control signal that is involved with the memory and I/O interface.
This is the READY signal.
READY signal is used to insert wait states into the bus cycle such that it is extended by
a number of clock periods. This signal is provided by an external clock generator device
and can be supplied by the memory or I/O sub-system to signal the 8086 when they are
ready to permit the data transfer to be completed.
Interrupt signals : The key interrupt interface signals are interrupt request (INTR) and
interrupt acknowledge ( INTA).
INTR is an input to the 8086 that can be used by an external device to signal that it need
to be serviced.
Logic 1 at INTR represents an active interrupt request. When an interrupt request has
been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0
at the INTA output.
The TEST input is also related to the external interrupt interface. Execution of a WAIT
instruction causes the 8086 to check the logic level at the TEST input.
If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086
no longer executes instructions, instead it repeatedly checks the logic level of the TEST
input waiting for its transition back to logic 0.
As TEST switches to 0, execution resume with the next instruction in the program. This
feature can be used to synchronize the operation of the 8086 to an event in external
hardware.
There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and
the reset interrupt RESET.
On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service
routine. The RESET input is used to provide a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service
routine.
DMA Interface signals :The direct memory access DMA interface of the 8086
minimum mode consist of the HOLD and HLDA signals.
When an external device wants to take control of the system bus, it signals to the 8086
by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the
8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3
through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.
The 8086 signals external device that it is in this state by switching its HLDA output to
logic 1 level.
Maximum Mode Interface
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When the 8086 is set for the maximum-mode configuration, it provides signals for
implementing a multiprocessor / coprocessor system environment.
By multiprocessor environment we mean that one microprocessor exists in the system
and that each processor is executing its own program.
Usually in this type of system environment, there are some system resources that are
common to all processors.
They are called as global resources. There are also other resources that are assigned to
specific processors. These are known as local or private resources.
Coprocessor also means that there is a second processor in the system. In this two
processor does not access the bus at the same time.
One passes the control of the system bus to the other and then may suspend its operation.
In the maximum-mode 8086 system, facilities are provided for implementing allocation
of global resources and passing bus control to other microprocessor or coprocessor.
INIT
S0
S1
S2
LOCK
CLK
INTR
TEST
NMI
CRQLCK
RESB
SYSB/RESB
ANYREQ
AEN
Vcc GND
LOCK
CLK
S0
S2
RESET
8289
Bus
MN/MX
BPRN
BCLK
CLK AEN IOB
IOB
DEN
DT/ R
ALE
8086 MPU
Multi Bus
BREQ
CLK AEN IOB

S0
S1
8288 Bus
S2
controller
S1
BUSY
CBRQ
BPRO
MRDC
AMWC
MWTC
IORC
IOWC
AIOWC
INTA
MCE / PDEN
DEN
DT / R
ALE
A0-A15,
A16/S3-A19/S6
D0 D15
BHE
RD
READY
QS1, QS0
Local bus control

RQ / GT1 RQ / GT0
8086 Maximum mode Block Diagram
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8288 Bus Controller Bus Command and Control Signals:

8086 does not directly provide all the signals that are required to control the memory,
I/O and interrupt interfaces.
Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced
by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each
bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.
Status Inputs
CPU Cycles
S2
S1
S0
0
0
0
0
0
0
1
1
0
1
0
1
Interrupt Acknowledge
Instruction Fetch
Read Memory
1
1
Write Memory
Read I/O Port

Write I/O Port
Halt
Passive
8288
Command
INTA
IORC
IOWC, AIOWC
None
MRDC
MRDC
MWTC, AMWC
None
Bus Status Codes
The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read
cycle is to be performed.
In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals
provide the same functions as those described for the minimum system mode. This set of
bus commands and control signals is compatible with the Multibus and industry standard
for interfacing microprocessor systems.
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The output of 8289 are bus arbitration signals:

Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority
in (BPRN), bus request (BREQ) and bus clock (BCLK).
They correspond to the bus exchange signals of the Multibus and are used to lock other
processor off the system bus during the execution of an instruction by the 8086.
In this way the processor can be assured of uninterrupted access to common system
resources such as global memory.
Queue Status Signals : Two new signals that are produced by the 8086 in the
maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit
queue status code, QS1QS0.
Following table shows the four different queue status.
QS1
QS0
Queue Status
0 (low)
No Operation. During the last clock cycle, nothing was

taken from the queue.
First Byte. The byte taken from the queue was the first byte
of the instruction.
Queue Empty. The queue has been reinitialized as a result

of the execution of a transfer instruction.
1 (high)
Subsequent Byte. The byte taken from the queue was a

subsequent byte of the instruction.
Queue status codes
Local Bus Control Signal Request / Grant Signals: In a maximum mode

configuration, the minimum mode HOLD, HLDA interface is also changed. These two
are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a
prioritized bus access mechanism for accessing the local bus.
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Memory interface of a minimum mode 8088 system:
- The figure below shows the memory interface circuit of an 8088

based system operating in minimum mode.
- The 8088s memory system uses a single 1-Mega X 8 bit

memory bank with Physical Address from 00000H to FFFFFH.
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- The 20-bit
( 5 Hex digit)
physical address
supplied by the
addressbus (A0-A19) is
used to select the
memory location
required to be
accessed via
data-bus (D0-D7)
Physical
addressH
00000
Memory
spaces
3
4
00001 H
5 AH
00002 H
Address
Bus
A0 A19
.
.
.
.
.
FFFFE H
FFFFF H
1-MByte
bytewide
Main
memory
storage in
8088
system
D0 - D7
Data
Bus
8 CH
A 6H
Accessing a Byte-data in a 8088-based Memory System:
- In 8088 system, one bus cycle is required to complete the

process of applying valid physical address and accessing
(reading or writing) a byte data from that memory location.
Accessing a Word-data in a 8088-based Memory System:

- Two bus cycles are required to access a word data in an 8088
memory system. The 1st bus cycle access the least significant
byte (LSB) of the stored word, as show in figure below.
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- During the 2nd bus cycle, the physical address in automatically

incremented to access the most significant byte of the word.
Hardware Organization of 8086 Memory Locations:
- The 8086 systems have two 0.5 Mega X 8 bit memory banks
- Data-bytes associated with even-addresses reside in low bank

and odd-address reside in high bank. Address pins A1 to A19
selects the storage locations, whereas A0 and BHE pins are
used to enable high or low memory banks.
Inverter
Accessing a Byte-data in a 8086-based Memory System:

- The two bank memory module of 8086 based storage system
requires one bus-cycle to read/write a data-byte.
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- To access a Byte of data in Low-bank, valid address is provided

via address pins A1 to A19 together with A0=0 and BHE=1.
Accessing a Byte-data in a 8086 System (Contd):

- Similarly to access a Byte of data in High-bank, valid address in
pins A1 to A19, A0=1 and BHE=0 are required to access the
data through D8 to D15 of the data-bus.
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- These signals disable the Low bank and enable the High bank
to transfer (in/out) data through D8 to D15 of the data-bus.
Accessing a Unaligned Word-data in a 8086 System:

- For odd-addressed (unaligned) words (with odd P.A of the
LSB), two bus-cycles are required to access the Word-data.
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- During the 1st bus-cycle, odd addressed LSB of the word is

accessed from the High-memory -bank via D8 to D15 of data bus
Accessing a Unaligned Word-data in a 8086 (Contd):

- During 2nd bus-cycle, P.A. is auto-incremented to access the
even address MSB of the word from the Low bank via D0 to D7.
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- Note that A0 and BHE signals are reset (violet) accordingly to

enable the required memory bank.
Accessing a Alighted Word-data in a 8086 System:
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- For even-addressed (aligned) words, only one bus-cycle is

needed to access the word, as both low and high banks are
activated at the same time using A0=0 and BHE=0
- Note that during this bus-cycle, all 16-bit data is transferred via
D0 to D15 of the data bus.
8237 DMA CONTROLLER

DMA: What it is and How it Works
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Direct Memory Access (DMA) is a method of allowing data to be moved from one location to
another in a computer without intervention from the central processor (CPU).
The way that the DMA function is implemented varies between computer architectures, so this
discussion will limit itself to the implementation and workings of the DMA subsystem on the
IBM Personal Computer (PC), the IBM PC/AT and all of its successors and clones.
The PC DMA subsystem is based on the Intel 8237 DMA controller. The 8237 contains four
DMA channels that can be programmed independently and any one of the channels may be
active at any moment. These channels are numbered 0, 1, 2 and 3. Starting with the PC/AT, IBM
added a second 8237 chip, and numbered those channels 4, 5, 6 and 7.
The original DMA controller (0, 1, 2 and 3) moves one byte in each transfer. The second DMA
controller (4, 5, 6, and 7) moves 16-bits from two adjacent memory locations in each transfer,
with the first byte always coming from an even-numbered address. The two controllers are
identical components and the difference in transfer size is caused by the way the second
controller is wired into the system.
The 8237 has two electrical signals for each channel, named DRQ and -DACK. There are
additional signals with the names HRQ (Hold Request), HLDA (Hold Acknowledge), -EOP (End
of Process), and the bus control signals -MEMR (Memory Read), -MEMW (Memory Write), IOR (I/O Read), and -IOW (I/O Write).
The 8237 DMA is known as a fly-by DMA controller. This means that the data being moved
from one location to another does not pass through the DMA chip and is not stored in the DMA
chip. Subsequently, the DMA can only transfer data between an I/O port and a memory address,
but not between two I/O ports or two memory locations.
Note: The 8237 does allow two channels to be connected together to allow memory-to-memory
DMA operations in a non-fly-by mode, but nobody in the PC industry uses this scarce resource
this way since it is faster to move data between memory locations using the CPU.
In the PC architecture, each DMA channel is normally activated only when the hardware that
uses a given DMA channel requests a transfer by asserting the DRQ line for that channel.
A Sample DMA transfer

Here is an example of the steps that occur to cause and perform a DMA transfer. In this example,
the floppy disk controller (FDC) has just read a byte from a diskette and wants the DMA to place
it in memory at location 0x00123456. The process begins by the FDC asserting the DRQ2 signal
(the DRQ line for DMA channel 2) to alert the DMA controller.
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The DMA controller will note that the DRQ2 signal is asserted. The DMA controller will then
make sure that DMA channel 2 has been programmed and is unmasked (enabled). The DMA
controller also makes sure that none of the other DMA channels are active or want to be active
and have a higher priority. Once these checks are complete, the DMA asks the CPU to release
the bus so that the DMA may use the bus. The DMA requests the bus by asserting the HRQ
signal which goes to the CPU.
The CPU detects the HRQ signal, and will complete executing the current instruction. Once the
processor has reached a state where it can release the bus, it will. Now all of the signals normally
generated by the CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are placed in a tristated condition (neither high or low) and then the CPU asserts the HLDA signal which tells the
DMA controller that it is now in charge of the bus.
Depending on the processor, the CPU may be able to execute a few additional instructions now
that it no longer has the bus, but the CPU will eventually have to wait when it reaches an
instruction that must read something from memory that is not in the internal processor cache or
pipeline.
Now that the DMA is in charge, the DMA activates its -MEMR, -MEMW, -IOR, -IOW output
signals, and the address outputs from the DMA are set to 0x3456, which will be used to direct
the byte that is about to transferred to a specific memory location.
The DMA will then let the device that requested the DMA transfer know that the transfer is
commencing. This is done by asserting the -DACK signal, or in the case of the floppy disk
controller, -DACK2 is asserted.
The floppy disk controller is now responsible for placing the byte to be transferred on the bus
Data lines. Unless the floppy controller needs more time to get the data byte on the bus (and if
the peripheral does need more time it alerts the DMA via the READY signal), the DMA will
wait one DMA clock, and then de-assert the -MEMW and -IOR signals so that the memory will
latch and store the byte that was on the bus, and the FDC will know that the byte has been
transferred.
Since the DMA cycle only transfers a single byte at a time, the FDC now drops the DRQ2 signal,
so the DMA knows that it is no longer needed. The DMA will de-assert the -DACK2 signal, so
that the FDC knows it must stop placing data on the bus.
The DMA will now check to see if any of the other DMA channels have any work to do. If none
of the channels have their DRQ lines asserted, the DMA controller has completed its work and
will now tri-state the -MEMR, -MEMW, -IOR, -IOW and address signals.
Finally, the DMA will de-assert the HRQ signal. The CPU sees this, and de-asserts the HOLDA
signal. Now the CPU activates its -MEMR, -MEMW, -IOR, -IOW and address lines, and it
resumes executing instructions and accessing main memory and the peripherals.
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For a typical floppy disk sector, the above process is repeated 512 times, once for each byte.
Each time a byte is transferred, the address register in the DMA is incremented and the counter
in the DMA that shows how many bytes are to be transferred is decremented.
When the counter reaches zero, the DMA asserts the EOP signal, which indicates that the
counter has reached zero and no more data will be transferred until the DMA controller is
reprogrammed by the CPU. This event is also called the Terminal Count (TC). There is only one
EOP signal, and since only one DMA channel can be active at any instant, the DMA channel that
is currently active must be the DMA channel that just completed its task.
If a peripheral wants to generate an interrupt when the transfer of a buffer is complete, it can test
for its -DACKn signal and the EOP signal both being asserted at the same time. When that
happens, it means the DMA will not transfer any more information for that peripheral without
intervention by the CPU. The peripheral can then assert one of the interrupt signals to get the
processors' attention. In the PC architecture, the DMA chip itself is not capable of generating an
interrupt. The peripheral and its associated hardware is responsible for generating any interrupt
that occurs. Subsequently, it is possible to have a peripheral that uses DMA but does not use
interrupts.
It is important to understand that although the CPU always releases the bus to the DMA when
the DMA makes the request, this action is invisible to both applications and the operating
system, except for slight changes in the amount of time the processor takes to execute
instructions when the DMA is active. Subsequently, the processor must poll the peripheral, poll
the registers in the DMA chip, or receive an interrupt from the peripheral to know for certain
when a DMA transfer has completed.
DMA Page Registers and 16Meg address space limitations
You may have noticed earlier that instead of the DMA setting the address lines to 0x00123456 as
we said earlier, the DMA only set 0x3456. The reason for this takes a bit of explaining.
When the original IBM PC was designed, IBM elected to use both DMA and interrupt controller
chips that were designed for use with the 8085, an 8-bit processor with an address space of 16
bits (64K). Since the IBM PC supported more than 64K of memory, something had to be done to
allow the DMA to read or write memory locations above the 64K mark. What IBM did to solve
this problem was to add an external data latch for each DMA channel that holds the upper bits of
the address to be read to or written from. Whenever a DMA channel is active, the contents of that
latch are written to the address bus and kept there until the DMA operation for the channel ends.
IBM called these latches Page Registers.
So for our example above, the DMA would put the 0x3456 part of the address on the bus, and
the Page Register for DMA channel 2 would put 0x0012xxxx on the bus. Together, these two
values form the complete address in memory that is to be accessed.
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Because the Page Register latch is independent of the DMA chip, the area of memory to be read
or written must not span a 64K physical boundary. For example, if the DMA accesses memory
location 0xffff, after that transfer the DMA will then increment the address register and the DMA
will access the next byte at location 0x0000, not 0x10000. The results of letting this happen are
probably not intended.
Note: Physical 64K boundaries should not be confused with 8086-mode 64K Segments,
which are created by mathematically adding a segment register with an offset register. Page
Registers have no address overlap and are mathematically OR-ed together.
To further complicate matters, the external DMA address latches on the PC/AT hold only eight
bits, so that gives us 8+16=24 bits, which means that the DMA can only point at memory
locations between 0 and 16Meg. For newer computers that allow more than 16Meg of memory,
the standard PC-compatible DMA cannot access memory locations above 16Meg.
To get around this restriction, operating systems will reserve a RAM buffer in an area below
16Meg that also does not span a physical 64K boundary. Then the DMA will be programmed to
transfer data from the peripheral and into that buffer. Once the DMA has moved the data into this
buffer, the operating system will then copy the data from the buffer to the address where the data
is really supposed to be stored.
When writing data from an address above 16Meg to a DMA-based peripheral, the data must be
first copied from where it resides into a buffer located below 16Meg, and then the DMA can
copy the data from the buffer to the hardware. In FreeBSD, these reserved buffers are called
Bounce Buffers. In the MS-DOS world, they are sometimes called Smart Buffers.
Note: A new implementation of the 8237, called the 82374, allows 16 bits of page register to be
specified and enables access to the entire 32 bit address space, without the use of bounce buffers.
DMA Operational Modes and Settings
The 8237 DMA can be operated in several modes. The main ones are:
Single
A single byte (or word) is transferred. The DMA must release and re-acquire the bus for
each additional byte. This is commonly-used by devices that cannot transfer the entire
block of data immediately. The peripheral will request the DMA each time it is ready for
another transfer.
The standard PC-compatible floppy disk controller (NEC 765) only has a one-byte
buffer, so it uses this mode.
Block/Demand
Once the DMA acquires the system bus, an entire block of data is transferred, up to a
maximum of 64K. If the peripheral needs additional time, it can assert the READY signal
to suspend the transfer briefly. READY should not be used excessively, and for slow
peripheral transfers, the Single Transfer Mode should be used instead.
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The difference between Block and Demand is that once a Block transfer is started, it runs
until the transfer count reaches zero. DRQ only needs to be asserted until -DACK is
asserted. Demand Mode will transfer one more bytes until DRQ is de-asserted, at which
point the DMA suspends the transfer and releases the bus back to the CPU. When DRQ
is asserted later, the transfer resumes where it was suspended.
Older hard disk controllers used Demand Mode until CPU speeds increased to the point
that it was more efficient to transfer the data using the CPU, particularly if the memory
locations used in the transfer were above the 16Meg mark.
Cascade
This mechanism allows a DMA channel to request the bus, but then the attached
peripheral device is responsible for placing the addressing information on the bus instead
of the DMA. This is also used to implement a technique known as Bus Mastering.
When a DMA channel in Cascade Mode receives control of the bus, the DMA does not
place addresses and I/O control signals on the bus like the DMA normally does when it is
active. Instead, the DMA only asserts the -DACK signal for the active DMA channel.
At this point it is up to the peripheral connected to that DMA channel to provide address
and bus control signals. The peripheral has complete control over the system bus, and can
do reads and/or writes to any address below 16Meg. When the peripheral is finished with
the bus, it de-asserts the DRQ line, and the DMA controller can then return control to the
CPU or to some other DMA channel.
Cascade Mode can be used to chain multiple DMA controllers together, and this is
exactly what DMA Channel 4 is used for in the PC architecture. When a peripheral
requests the bus on DMA channels 0, 1, 2 or 3, the slave DMA controller asserts
HLDREQ, but this wire is actually connected to DRQ4 on the primary DMA controller
instead of to the CPU. The primary DMA controller, thinking it has work to do on
Channel 4, requests the bus from the CPU using HLDREQ signal. Once the CPU grants
the bus to the primary DMA controller, -DACK4 is asserted, and that wire is actually
connected to the HLDA signal on the slave DMA controller. The slave DMA controller
then transfers data for the DMA channel that requested it (0, 1, 2 or 3), or the slave DMA
may grant the bus to a peripheral that wants to perform its own bus-mastering, such as a
SCSI controller.
Because of this wiring arrangement, only DMA channels 0, 1, 2, 3, 5, 6 and 7 are usable
with peripherals on PC/AT systems.
Note: DMA channel 0 was reserved for refresh operations in early IBM PC
computers, but is generally available for use by peripherals in modern systems.
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When a peripheral is performing Bus Mastering, it is important that the peripheral

transmit data to or from memory constantly while it holds the system bus. If the
peripheral cannot do this, it must release the bus frequently so that the system can
perform refresh operations on main memory.
The Dynamic RAM used in all PCs for main memory must be accessed frequently to
keep the bits stored in the components charged. Dynamic RAM essentially consists of
millions of capacitors with each one holding one bit of data. These capacitors are charged
with power to represent a 1 or drained to represent a 0. Because all capacitors leak, power
must be added at regular intervals to keep the 1 values intact. The RAM chips actually
handle the task of pumping power back into all of the appropriate locations in RAM, but
they must be told when to do it by the rest of the computer so that the refresh activity will
not interfere with the computer wanting to access RAM normally. If the computer is
unable to refresh memory, the contents of memory will become corrupted in just a few
milliseconds.
Since memory read and write cycles count as refresh cycles (a dynamic RAM refresh
cycle is actually an incomplete memory read cycle), as long as the peripheral controller
continues reading or writing data to sequential memory locations, that action will refresh
all of memory.
Bus-mastering is found in some SCSI host interfaces and other high-performance
peripheral controllers.
Autoinitialize
This mode causes the DMA to perform Byte, Block or Demand transfers, but when the
DMA transfer counter reaches zero, the counter and address are set back to where they
were when the DMA channel was originally programmed. This means that as long as the
peripheral requests transfers, they will be granted. It is up to the CPU to move new data
into the fixed buffer ahead of where the DMA is about to transfer it when doing output
operations, and to read new data out of the buffer behind where the DMA is writing when
doing input operations.
This technique is frequently used on audio devices that have small or no hardware
sample buffers. There is additional CPU overhead to manage this circular buffer, but
in some cases this may be the only way to eliminate the latency that occurs when the
DMA counter reaches zero and the DMA stops transfers until it is reprogrammed.
Programming the DMA

The DMA channel that is to be programmed should always be masked before loading any
settings. This is because the hardware might unexpectedly assert the DRQ for that channel, and
the DMA might respond, even though not all of the parameters have been loaded or updated.
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Once masked, the host must specify the direction of the transfer (memory-to-I/O or I/O-tomemory), what mode of DMA operation is to be used for the transfer (Single, Block, Demand,
Cascade, etc), and finally the address and length of the transfer are loaded. The length that is
loaded is one less than the amount you expect the DMA to transfer. The LSB and MSB of the
address and length are written to the same 8-bit I/O port, so another port must be written to first
to guarantee that the DMA accepts the first byte as the LSB and the second byte as the MSB of
the length and address.
Then, be sure to update the Page Register, which is external to the DMA and is accessed through
a different set of I/O ports.
Once all the settings are ready, the DMA channel can be un-masked. That DMA channel is now
considered to be armed, and will respond when the DRQ line for that channel is asserted.
Refer to a hardware data book for precise programming details for the 8237. You will also need
to refer to the I/O port map for the PC system, which describes where the DMA and Page
Register ports are located. A complete port map table is located below.
Internal Block Diagram of 8237
DMA Port Map

All systems based on the IBM-PC and PC/AT have the DMA hardware located at the same I/O
ports. The complete list is provided below. Ports assigned to DMA Controller #2 are undefined
on non-AT designs.
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0x00-0x1f DMA Controller #1 (Channels 0, 1, 2 and 3)

DMA Address and Count Registers
0x00
0x00
0x01
0x01
0x02
0x02
0x03
0x03
0x04
0x04
0x05
0x05
0x06
0x06
0x07
0x07
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
Channel 0 starting address

Channel 0 current address
Channel 0 starting word count
Channel 0 remaining word count
DMA Command Registers
0x08
0x08
0x09
0x09
0x0a
0x0a
0x0b
0x0b
0x0c
0x0c
0x0d
write
read
write
read
write
read
write
read
write
read
write
Command Register
Status Register
Request Register
Single Mask Register Bit
Mode Register
Clear LSB/MSB Flip-Flop
Master Clear/Reset
0x0d
0x0e
0x0e
0x0f
0x0f
read
write
read
write
read
Temporary Register (not available on newer versions)

Clear Mask Register
Write All Mask Register Bits
Read All Mask Register Bits (only in Intel 82374)
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0xc0-0xdf DMA Controller #2 (Channels 4, 5, 6 and 7)
DMA Address and Count Registers

0xc0
0xc0
0xc2
0xc2
0xc4
0xc4
0xc6
0xc6
0xc8
0xc8
0xca
0xca
0xcc
0xcc
0xce
0xce
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read

DMA Command Registers
0xd0
0xd0
0xd2
0xd2
0xd4
0xd4
0xd6
0xd6
0xd8
0xd8
0xda
write
read
write
read
write
read
write
read
write
read
write
Command Register
Status Register
Request Register
Single Mask Register Bit
Mode Register
Clear LSB/MSB Flip-Flop
Master Clear/Reset
0xda
0xdc
0xdc
0xde
0xdf
read
write
read
write
read
Temporary Register (not present in Intel 82374)

Clear Mask Register
Write All Mask Register Bits
Read All Mask Register Bits (only in Intel 82374)
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0x80-0x9f DMA Page Registers

0x87
r/w
Channel 0 Low byte (23-16) page Register
0x83
r/w
0x81
r/w
0x82
r/w
0x8b
r/w
0x89
r/w
0x8a
r/w
0x8f
r/w
Low byte page Refresh
0x400-0x4ff 82374 Enhanced DMA Registers
The Intel 82374 EISA System Component (ESC) was introduced in early 1996 and includes a
DMA controller that provides a superset of 8237 functionality as well as other PC-compatible
core peripheral components in a single package. This chip is targeted at both EISA and PCI
platforms, and provides modern DMA features like scatter-gather, ring buffers as well as direct
access by the system DMA to all 32 bits of address space.
If these features are used, code should also be included to provide similar functionality in the
previous 16 years worth of PC-compatible computers. For compatibility reasons, some of the
82374 registers must be programmed after programming the traditional 8237 registers for each
transfer. Writing to a traditional 8237 register forces the contents of some of the 82374 enhanced
registers to zero to provide backward software compatibility.
0x401
0x403
0x405
0x407
0x4c6
0x4ca
0x4ce
0x487
0x483
0x481
0x482
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Channel 0 High byte (bits 23-16) word count

Channel 0 High byte (bits 31-24) page Register
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
write
read
write
read
read
write
write
write
write
write
write
write
read

High byte page Refresh
Channel 0 Stop Register (bits 7-2)
Channels 0-3 Chaining Mode Register
Channel Interrupt Status Register
Channels 4-7 Chaining Mode Register
Chaining Mode Status
Chain Buffer Expiration Control Register
Channel 0 Scatter-Gather Command Register
Channel 0 Scatter-Gather Status Register
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0x48b
0x489
0x48a
0x48f
0x4e0
0x4e1
0x4e2
0x4e4
0x4e5
0x4e6
0x4e8
0x4e9
0x4ea
0x4ec
0x4ed
0x4ee
0x4f4
0x4f5
0x4f6
0x4f8
0x4f9
0x4fa
0x4fc
0x4fd
0x4fe
0x40a
0x40a
0x4d4
0x4d4
0x40c
0x410
0x411
0x412
0x413
0x415
0x416
0x417
0x418
read
read
read
read
read
read
r/w
r/w
r/w
r/w
r/w
r/w
r/w

Channel 0 Scatter-Gather Descriptor Table Pointer Register
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0x419
0x41a
0x41b
0x41d
0x41e
0x41f
0x420-0x423
0x424-0x427
0x428-0x42b
0x42c-0x42f
0x434-0x437
0x438-0x43b
0x43c-0x43f
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PIO 8255
The parallel input-output port chip 8255 is also called as programmable

peripheral input-output port. The Intels 8255 is designed for use with Intels 8bit, 16-bit and higher capability microprocessors. It has 24 input/output lines
which may be individually programmed in two groups of twelve lines each, or
three groups of eight lines. The two groups of I/O pins are named as Group A and
Group B. Each of these two groups contains a subgroup of eight I/O lines called
as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A
contains an 8-bit port A along with a 4-bit port. C upper.
The port A lines are identified by symbols PA0-PA7 while the port C lines are
identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing
lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and
port C lower can be used in combination as an 8-bit port C.
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Both the port C are assigned the same address. Thus one may have either three 8bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can
function independently either as input or as output ports. This can be achieved by
programming the bits of an internal register of 8255 called as control word
register ( CWR ).
The internal block diagram and the pin configuration of 8255 are shown in fig.
The 8-bit data bus buffer is controlled by the read/write control logic. The
read/write control logic manages all of the internal and external transfers of both
data and control words.
RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to
the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is
used to interface the 8255 internal data bus with the external system data bus.
This buffer receives or transmits data upon the execution of input or output
instructions by the microprocessor. The control words or status information is also
transferred through the buffer.
The signal description of 8255 are briefly presented as follows :
PA7-PA0: These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into the control word
register.
PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or
input buffers lines.
This port also can be used for generation of handshake lines in mode 1 or mode
2.
PC3-PC0 : These are the lower port C lines, other details are the same as PC7PC4 lines.
PB0-PB7 : These are the eight port B lines which are used as latched output lines
or buffered input lines in the same way as port A.
RD : This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.
WR : This is an input line driven by the microprocessor. A low on this line
indicates write operation.
CS : This is a chip select line. If this line goes low, it enables the 8255 to respond
to RD and WR signals, otherwise RD and WR signal are neglected.
A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e. three
ports and a control word register as given in table below.
In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus,
the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.
D0-D7 : These are the data bus lines those carry data or control word to/from the
microprocessor.
RESET : A logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
WR
1
1
1
1
CS
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
Input (Read) cycle

Port A to Data bus
Port B to Data bus
Port C to Data bus
CWR to Data bus
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RD
0
0
0
0
RD
1
1
1
1
WR
0
0
0
0
CS
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
Output (Write) cycle

Data bus to Port A
Data bus to Port B
Data bus to Port C
Data bus to CWR
RD
X
1
WR
X
1
CS
1
0
A1
X
X
A0
X
X
Function
Data bus tristated
Data bus tristated
Control Word Register
Block Diagram of 8255 (Architecture)
It has a 40 pins of 4 groups.

Data bus buffer
Read Write control logic
Group A and Group B controls
Port A, B and C
Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to
system databus. Data is transmitted or received by the buffer on execution of
input or output instruction by the CPU.
Control word and status information are also transferred through this unit.
Read/Write control logic: This unit accepts control signals ( RD, WR ) and also
inputs from address bus and issues commands to individual group of control
blocks
( Group A, Group B).
It has the following pins.
a) CS Chipselect : A low on this PIN enables the communication between CPU
and 8255.
1.
2.
3.
4.
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b) RD (Read) A low on this pin enables the CPU to read the data in the ports or the
status word through data bus buffer.
c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to
the control register through the data bus buffer.
d) RESET: A high on this pin clears the control register and all ports are set to the
input mode
e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins
control the selection of one of the 3 ports.
Group A and Group B controls : These block receive control from the CPU and
issues commands to their respective ports.
Group A - PA and PCU ( PC7 PC4)
Group B - PCL ( PC3 PC0)
Control word register can only be written into no read operation of the CW
register is allowed.
a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes mode 0, mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports and can be used as control signals for port A
and port B. it can be programmed in mode 0.
D2
D1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Selected bits of port C

D0
D1
D2
D3
D4
D5
D6
D7
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D3
BSR Mode : CWR Format
8
2
5
5
PA
PA6 PA7
PCU
PC4 PC7
PCL
PC0-PC3
PB
PB0 PB7
8
2
5
5
PA
PCU
PCL
PB
PC
PB0 PB7
Port A and Port C acting as

O/P. Port B acting as I/P
All Output
PA
PA3
PA2
PA1
PA0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
Vcc
PB7
PB6
PB5
PB4
PB3
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RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8255A
8255A Pin Configuration
PA0-PA7
D0-D7
CS
PC4-PC7
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RESET
8255A
PC0-PC3
A0
PB0-PB7
A1
RD
Vcc
WR
GND
Signals of 8255
Group A
control
PA0-PA7
Group A
Port A(8)
1
Data
bus
Group A
Port C
upper(4)
PC7-PC4
Group B
Port C
Lower(4)
PC0-PC3
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D0-D7
8 bit int data bus
RD
WR
READ/
WRITE
Control
Logic
A0
A1
RESET
Group B
control
Group B
Port B(8)
PB7-PB0
CS
Block Diagram of 8255
D7
D6
D5
Mode for
Port A
D4
D3
PA
PC U
D2
Mode
for PB
D1
PB
D0
PC L
Mode Set flag

1- active
0- BSR mode
Group - A
1 Input
PC u
0 Output
1 Input
PA
0 Output
00
mode 0
Mode
01 mode 1
Select
of PA
10 mode 2
Group - B
PCL
PB
Mode
Select
1 Input
0 Output
1 Input
0 Output
0 mode- 0
1 mode- 1
Control Word Format of 8255
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Modes of Operation of 8255

These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset
mode (BSR).
In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode
only port C (PC0-PC7) can be used to set or reset its individual port bits.
Under the I/O mode of operation, further there are three modes of operation of
8255, so as to support different types of applications, mode 0, mode 1 and mode
2.
BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending
on D0 of the control word. The bit to be set or reset is selected by bit select flags
D3, D2 and D1 of the CWR as given in table.
I/O Modes :
a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output
mode. This mode provides simple input and output capabilities using each of the three
ports. Data can be simply read from and written to the input and output ports
respectively, after appropriate initialisation.
D2
D1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Selected bits of port C

D0
D1
D2
D3
D4
D5
D6
D7
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D3
BSR Mode : CWR Format
8
2
5
5
PA
PA6 PA7
PCU
PC4 PC7
PCL
PC0-PC3
PB
PB0 PB7
PA
8
2
5
5
PA
PCU
PCL
PB
PC
PB0 PB7
Port A and Port C acting as

O/P. Port B acting as I/P
All Output
Mode 0
The salient features of this mode are as listed below:

1. Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower )
are available. The two 4-bit ports can be combinedly used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configuration are
possible.
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All these modes can be selected by programming a register internal to 8255

known as CWR.
The control word register has two formats. The first format is valid for I/O modes
of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid
for bit set/reset (BSR) mode of operation. These formats are shown in following
fig.
1
X
X
X
0-for BSR mode
Bit select flags

D3, D2, D1 are from 000 to 111 for bits PC0 TO PC7
0- Reset
1- Set
I/O Mode Control Word Register Format and

BSR Mode Control Word Register Format
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b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input
and output action of the specified port. Port C lines PC0-PC2, provide strobe or
handshake lines for port B. This group which includes port B and PC0-PC2 is called as
group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for port
A. This group including port A and PC3-PC5 from group A. Thus port C is utilized for
generating handshake signals. The salient features of mode 1 are listed as follows:
1. Two groups group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and
outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and
PC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may
be used as independent data lines.
The control signals for both the groups in input and output modes are explained as
follows:
Input control signal definitions (mode 1 ):
STB( Strobe input ) If this lines falls to logic low level, the data available at 8bit input port is loaded into input latches.
IBF ( Input buffer full ) If this signal rises to logic 1, it indicates that data has
been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low
on STB and is reset by the rising edge of RD input.
INTR ( Interrupt request ) This active high output signal can be used to
interrupt the CPU whenever an input device requests the service. INTR is set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled
by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig.
INTR is reset by a falling edge of RD input. Thus an external input device can be
request the service of the processor by putting the data on the bus and sending the
strobe signal.
Output control signal definitions (mode 1) :
OBF (Output buffer full ) This status signal, whenever falls to low, indicates
that CPU has written data to the specified output port. The OBF flip-flop will be
set by a rising edge of WR signal and reset by a low going edge at the ACK input.
ACK ( Acknowledge input ) ACK signal acts as an acknowledgement to be
given by an output device. ACK signal, whenever low, informs the CPU that the
data transferred by the CPU to the output device through the port is received by
the output device.
INTR ( Interrupt request ) Thus an output signal that can be used to interrupt
the CPU when an output device acknowledges the data received from the CPU.
INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR
input. The INTEA and INTEB flags are controlled by the bit set-reset mode of
PC6 and PC2 respectively.
Input control signal definitions in Mode

1
1
1/0 X X X
1 X
D7 D6 D5 D4 D3 D2 D1 D0
X X
X 1
D7 D6 D5 D4 D3 D2 D1 D0
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1 - Input
0 - Output
For PC6 PC7
PB0 PB7
PA0 PA7
INTEA
PC4
PC5
PC3
RD
INTEB
STBA
IBFA
PC6 PC7
STBB
PC0
INTR
IBFB
I/O
RD
Mode 1 Control Word Group B
I/P
Mode 1 Control Word Group A

I/P
INTRA
PC2
PC1
STB
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IBF
INTR
RD
DATA
from
Mode 1 Strobed Input Data Transfer
WR
OBF
INTR
ACK
Data OP to
Port
Mode 1 Strobed Data Output
Output control signal definitions Mode 1

1
1/0 X X X
1 X
D7 D6 D5 D4 D3 D2 D1 D0
X X
X 1
D7 D6 D5 D4 D3 D2 D1 D0
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1 - Input
0 - Output
For PC4 PC5
PA0 PA7
INTEA
PC7
PC6
PC3
WR
OBF
A
ACK
A
INTRA
PC4 PC5
Mode 1 Control Word Group A
1.
2.
3.
4.
5.
INTEB
PB0
PB7
PC1
PC2
OBF
PC0
INTRB
ACKB
I/O
Mode 1 Control Word Group B
Mode 2 ( Strobed bidirectional I/O ): This mode of operation of 8255 is also

called as strobed bidirectional I/O. This mode of operation provides 8255 with an
additional features for communicating with a peripheral device on an 8-bit data
bus. Handshaking signals are provided to maintain proper data flow and
synchronization between the data transmitter and receiver. The interrupt
generation and other functions are similar to mode 1.
In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd
and WR signals decide whether the 8255 is going to operate as an input port or
output port.
The Salient features of Mode 2 of 8255 are listed as follows:
The single 8-bit port in group A is available.
The 8-bit port is bidirectional and additionally a 5-bit control port is available.
Three I/O lines are available at port C.( PC2 PC0 )
Inputs and outputs are both latched.
The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake
signals for the 8-bit data transfer on port A.
Control signal definitions in mode 2:
INTR (Interrupt request) As in mode 1, this control signal is active high and is
used to interrupt the microprocessor to ask for transfer of the next data byte
to/from it. This signal is used for input ( read ) as well as output ( write )
operations.
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Control Signals for Output operations:

OBF ( Output buffer full ) This signal, when falls to low level, indicates that the
CPU has written data to port A.
ACK ( Acknowledge ) This control input, when falls to logic low level,
acknowledges that the previous data byte is received by the destination and next
byte may be sent by the processor. This signal enables the internal tristate buffers
to send the next data byte on port A.
INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset
mode with PC6.
Control signals for input operations :
STB (Strobe input ) A low on this line is used to strobe in the data into the input
latches of 8255.
IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises
to logic 1. This can be used as an acknowledge that the data has been received
by the receiver.
The waveforms in fig show the operation in Mode 2 for output as well as input
port.
Note: WR must occur before ACK and STB must be activated before RD.
WR
OBF
INTR
ACK
STB
IBF
Data bus
Data from 8085
Data towards
8255
RD
Mode 2 Bidirectional Data Transfer
The following fig shows a schematic diagram containing an 8-bit bidirectional

port, 5-bit control port and the relation of INTR with the control pins. Port B can
either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2.
Mode 2 is not available for port B. The following fig shows the control word.
The INTR goes high only if either IBF, INTE2, STB and RD go high or OBF,
INTE1, ACK and WR go high. The port C can be read to know the status of the
peripheral device, in terms of the control signals, using the normal I/O
instructions.
D6
D5
D4
D3
D2
D1
D0
1/0
1/0
1/0
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D7
1/0 mode
Port A
mode 2
Port B mode
0-mode 0
1- mode 1
PC2 PC0
1 - Input
0 - Output
Port B
1- I/P
0-O/P
Mode 2 control word
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PC3
INTR
PA0-PA7
INTE 1
INTE 2
RD
PC7
PC6
OBF
PC4
STB
PC5
IBF
ACK
WR
I/O
Mode 2 pins
Interfacing a Microprocessor To Keyboard
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1.
When you press a key on your computer, you are activating a switch. There are
many different ways of making these switches. An overview of the construction
and operation of some of the most common types.
Mechanical key switches: In mechanical-switch keys, two pieces of metal are
pushed together when you press the key. The actual switch elements are often
made of a phosphor-bronze alloy with gold platting on the contact areas. The key
switch usually contains a spring to return the key to the nonpressed position and
perhaps a small piece of foam to help damp out bouncing.
Some mechanical key switches now consist of a molded silicon dome with a
small piece of conductive rubber foam short two trace on the printed-circuit board
to produce the key pressed signal.
Mechanical switches are relatively inexpensive but they have several
disadvantages. First, they suffer from contact bounce. A pressed key may make
and break contact several times before it makes solid contact.
Second, the contacts may become oxidized or dirty with age so they no longer
make a dependable connection.
Higher-quality mechanical switches typically have a rated life time of about 1
million keystrokes. The silicone dome type typically last 25 million keystrokes.
Membrane key switches: These switches are really a special type of mechanical
switches. They consist of a three-layer plastic or rubber sandwich.
The top layer has a conductive line of silver ink running under each key position.
The bottom layer has a conductive line of silver ink running under each column of
keys.
When u press a key, you push the top ink line through the hole to contact the
bottom ink line.
The advantages of membrane keyboards is that they can be made as very thin,
sealed units.
They are often used on cash registers in fast food restaurants. The lifetime of
membrane keyboards varies over a wide range.
Capacitive key switches: A capacitive keyswitch has two small metal plates on
the printed circuit board and another metal plate on the bottom of a piece of foam.
When u press the key, the movable plate is pushed closer to fixed plate. This
changes the capacitance between the fixed plates. Sense amplifier circuitry detects
this change in capacitance and produce a logic level signal that indicates a key has
been pressed.
The big advantages of a capacitive switch is that it has no mechanical contacts to
become oxidized or dirty.
A small disadvantage is the specified circuitry needed to detect the change in
capacitance.
Capacitive keyswitches typically have a rated lifetime of about 20 million
keystrokes.
Hall effect keyswitches: This is another type of switch which has no mechanical
contact. It takes advantage of the deflection of a moving charge by a magnetic
field.
2.
3.
4.
2.
3.
4.
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A reference current is passed through a semiconductor crystal between two

opposing faces. When a key is pressed, the crystal is moved through a magnetic
field which has its flux lines perpendicular to the direction of current flow in the
crystal.
Moving the crystal through the magnetic field causes a small voltage to be
developed between two of the other opposing faces of the crystal.
This voltage is amplified and used to indicate that a key has been pressed. Hall
effect sensors are also used to detect motion in many electrically controlled
machines.
Hall effect keyboards are more expensive because of the more complex switch
mechanism, but they are very dependable and have typically rated lifetime of 100
million or more keystrokes.
Key
Motion
HALL
VOLTAGE
Reference
Current
Magnetic Field
HALL EFFECT
Keyboard Circuit Connections and Interfacing
In most keyboards, the keyswitches are connecting in a matrix of rows and

columns, as shown in fig.
We will use simple mechanical switches for our examples, but the principle is
same for other type of switches.
Getting meaningful data from a keyboard, it requires the following three major
tasks:
1. Detect a keypress.
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2. Debounce the keypress.

3. Encode the keypress
Three tasks can be done with hardware, software, or a combination of two,
depending on the application.
1. Software Keyboard Interfacing:
Circuit connection and algorithm : The following fig (a) shows how a
hexadecimal keypad can be connected to a couple of microcomputer ports so the
three interfacing tasks can be done as part of a program.
The rows of the matrix are connected to four output port lines. The column lines
of matrix are connected to four input-port lines. To make the program simpler, the
row lines are also connected to four input lines.
When no keys are pressed, the column lines are held high by the pull-up resistor
connected to +5V. Pressing a key connects a row to a column. If a low is output
on a row and a key in that row is pressed, then the low will appear on the column
which contains that key and can be detected on the input port.
If you know the row and column of the pressed key, you then know which key
was pressed, and you can convert this information into any code you want to
represent that key.
The following flow chart for a procedure to detect, debounce and produce the hex
code for a pressed key.
An easy way to detect if any key in the matrix is pressed is to output 0s to all
rows and then check the column to see if a pressed key has connected a low to a
column.
In the algorithm we first output lows to all the rows and check the columns over
and over until the column are all high. This is done before the previous key has
been released before looking for the next one. In the standard keyboard
terminology, this is called two-key lockout.
KEYBOARD
ZERO TO ALL
ROWS
OUTPUT ZERO
TO ONE ROW
D
E
READ
COLUMNS
E
N
C
O
D
E
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READ
COLUMNS
NO
ALL
KEYS
OPEN ?
YES
READ
COLUMNS
NO
KEY
PRESSE
D?
YES
WAIT 20ms
D
E
T
E
C
T
READ
COLUMNS
NO
B
O
U
N
C
E
KEY
PRESSED
?
YES
NO
KEY
FOUND
?
YES
CONVERT TO
HEX
RETURN
FLOW CHART
Once the columns are found to be all high, the program enters another loop, which
waits until a low appears on one of the columns, indicating that a key has been
pressed. This second loop does the detect task for us. A simple 20-ms delay
procedure then does the debounce task.
After the debounce time, another check is made to see if the key is still pressed. If
the columns are now all high, then no key is pressed and the initial detection was
caused by a noise pulse or a light brushing past a key. If any of the columns are
still low, then the assumption is made that it was a valid keypress.
The final task is to determine the row and column of the pressed key and convert
this row and column information to the hex code for the pressed key. To get the
row and column information, a low is output to one row and the column are read.
If none of the columns is low, the pressed key is not in that row. So the low is
rotated to the next row and the column are checked again. The process is repeated
until a low on a row produces a low on one of the column.
The pressed key then is in the row which is low at that time.
The connection fig shows the byte read in from the input port will contain a 4-bit
code which represents the row of the pressed key and a 4-bit code which represent
the column of the pressed key.
Error trapping: The concept of detecting some error condition such as no match
found is called error trapping. Error trapping is a very important part of real
programs. Even in simple programs, think what might happen with no error trap if
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two keys in the same row were pressed at exactly at the same time and a column
code with two lows in it was produced.
This code would not match any of the row-column codes in the table, so after all
the values in the table were checked, assigned register in program would be
decremented from 0000H to FFFFH. The compare decrement cycle would
continue through 65,536 memory locations until, by change the value in a
memory location matched the row-column code. The contents of the lower byte
register at hat point would be passed back to the calling routine. The changes are
1 in 256 that would be the correct value for one of the pressed keys. You should
keep an error trap in a program whenever there is a chance for it.
2. Keyboard Interfacing with Hardware: For the system where the CPU is too
busy to be bothered doing these tasks in software, an external device is used to do
them.
One of a MOS device which can be do this is the General Instruments AY5-2376
which can be connected to the rows and columns of a keyboard switch matrix.
The AY5-2376 independently detects a keypress by cycling a low down through
the rows and checking the columns. When it finds a key pressed, it waits a
debounce time.
If the key is still pressed after the debounce time, the AY5-2376 produces the 8bit code for the pressed key and send it out to microcomputer port on 8 parallel
lines. The microcomputer knows that a valid ASCII code is on the data lines, the
AY5-2376 outputs a strobe pulse.
The microcomputer can detect this strobe pulse and read in ASCII code on a
polled basis or it can detect the strobe pulse on an interrupt basis.
With the interrupt method the microcomputer doesnt have to pay any attention to
the keyboard until it receives an interrupt signal.
So this method uses very little of the microcomputer time. The AY5-2376 has a
feature called two-key rollover. This means that if two keys are pressed at nearly
the same time, each key will be detected, debounced and converted to ASCII.
The ASCII code for the first key and a strobe signal for it will be sent out then the
ASCII code for the second key and a strobe signal for it will be sent out and
compare this with two-key lockout.
+ 5V
Output port 01
D0
E
A
F
B
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D1
D2
D3
10K
Input port
D7
02
D
7 6
D
6 5
D
5 4
D
4 3
D
3 2
D
2 1
D0
Fig: (a) Port connections
Example
Interface a 4 * 4 keyboard with 8086 using 8255 an write an ALP for detecting a
key closure and return the key code in AL. The debounce period for a key is
10ms. Use software debouncing technique. DEBOUNCE is an available 10ms
delay routine.
Solution: Port A is used as output port for selecting a row of keys while Port B is
used as an input port for sensing a closed key. Thus the keyboard lines are
selected one by one through port A and the port B lines are polled continuously
till a key closure is sensed. The routine DEBOUNCE is called for key
debouncing. The key code is depending upon the selected row and a low sensed
column.
+ 5V
10
K
RESET
LOWR
IORD
PA3
PA2
PA1
10
K
E
A
10K
10K
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D0-D7
10
K
10
K
8255
A15
A12
A13
A14
A0
A2
A1
A1
A0
CS
PA0
10K
10K
PB3
PB2
PB1
PB0
Interfacing 4 * 4 Keyboard
The higher order lines of port A and port B are left unused. The address of port A
and port B will respectively 8000H and 8002H while address of CWR will be
8006H. The flow chart of the complete program is as given. The control word for
this problem will be 82H. Code segment CS is used for storing the program code.
Key Debounce : Whenever a mechanical push-button is pressed or released once,
the mechanical components of the key do not change the position smoothly, rather
it generates a transient response .
START
Initialise 8255 row,
column counter and key
code reg.
Key
Closed
Yes
Wait for Debounce
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No
Set row counter
row
Counter =0 ?
Ground one row
Read Column counter
Decrement row counter
Set column counter
No
Check for key pressed

Is the key
found ?
No
Increment code register

Decrement column counter
Transfer code to accumulator

STOP
column
counter=0?
Flow chart
These transient variations may be interpreted as the multiple key pressure and
responded accordingly by the microprocessor system.
To avoid this problem, two schemes are suggested: the first one utilizes a bistable
multivibrator at the output of the key to debounce .
The other scheme suggests that the microprocessor should be made to wait for the
transient period ( usually 10ms ), so that the transient response settles down and
reaches a steady state.
A logic 0 will be read by the microprocessor when the key is pressed.
In a number of high precision applications, a designer may have two options- the
first is to have more than one 8-bit port, read (write) the port one by one and then
from the multibyte data, the second option allows forming 16-bit ports using two
8-bit ports and use 16-bit read or write operations.
Logic 1
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+5V
V0
Logic 0
Key pressed
Key released
Response
A Mechanical Key
Logic 0
Key released
Interfacing To Alphanumeric Displays

To give directions or data values to users, many microprocessor-controlled
instruments and machines need to display letters of the alphabet and numbers. In
systems where a large amount of data needs to be displayed a CRT is used to
display the data. In system where only a small amount of data needs to be
displayed, simple digit-type displays are often used.
There are several technologies used to make these digit-oriented displays but we
are discussing only the two major types.
These are light emitting diodes (LED) and liquid-crystal displays (LCD).
LCD displays use very low power, so they are often used in portable, batterypowered instruments. They do not emit their own light, they simply change the
reflection of available light. Therefore, for an instrument that is to be used in lowlight conditions, you have to include a light source for LCDs or use LEDs which
emit their own light.
Alphanumeric LED displays are available in three common formats. For
displaying only number and hexadecimal letters, simple 7-segment displays such
as that as shown in fig are used.
To display numbers and the entire alphabet, 18 segment displays such as shown in
fig or 5 by 7 dot-matrix displays such as that shown in fig can be used. The 7segment type is the least expensive, most commonly used and easiest to interface
with, so we will concentrate first on how to interface with this type.
1. Directly Driving LED Displays: Figure shows a circuit that you might connect to
a parallel port on a microcomputer to drive a single 7-segment , common-anode
display. For a common-anode display, a segment is tuned on by applying a logic
low to it.
The 7447 converts a BCD code applied to its inputs to the pattern of lows
required to display the number represented by the BCD code. This circuit
connection is referred to as a static display because current is being passed
through the display at all times.
Each segment requires a current of between 5 and 30mA to light. Lets assume
you want a current of 20mA. The voltage drop across the LED when it is lit is
about 1.5V.
The output low voltage for the 7447 is a maximum of 0.4V at 40mA. So assume
that it is about 0.2V at 20mA. Subtracting these two voltage drop from the supply
voltage of 5V leaves 3.3V across the current limiting resistor. Dividing 3.3V by
20mA gives a value of 168 for the current-limiting resistor. The voltage drops
across the LED and the output of 7447 are not exactly predictable and exact
current through the LED is not critical as long as we dont exceed its maximum
rating.
2. Software-Multiplexed LED Display:
The circuit in fig works for driving just one or two LED digits with a parallel
output port. However, this scheme has several problem if you want to drive, eight
digits.
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The first problem is power consumption. For worst-case calculations, assume that
all 8 digits are displaying the digit 8, so all 7 segments are all lit. Seven segment
time 20mA per segment gives a current of 140mA per digit. Multiplying this by 8
digits gives a total current of 1120mA or 1.12A for 8 digits.
A second problem of the static approach is that each display digit requires a
separate 7447 decoder, each of which uses of another 13mA. The current required
by the decoders and the LED displays might be several times the current required
by the reset of the circuitry in the instrument.
To solve the problem of the static display approach, we use a multiplex method,
example for an explanation of the multiplexing.
The fig shows a circuit you can add to a couple of microcomputer ports to drive
some common anode LED displays in a multiplexed manner. The circuit has only
one 7447 and that the segment outputs of the 7447 are bused in parallel to the
segment inputs of all the digits.
The question that may occur to you on first seeing this is: Arent all the digits
going to display the same number? The answer is that they would if all the digits
were turned on at the same time. The tricky of multiplexing displays is that only
one display digit is turned on at a time.
The PNP transistor is series with the common anode of each digit acts as on/off
switch for that digit. Heres how the multiplexing process works.
The BCD code for digit 1 is first output from port B to the 7447. the 7447 outputs
the corresponding 7-segment code on the segment bus lines. The transistor
connected to digit 1 is then turned on by outputting a low to the appropriate bit of
port A. All the rest of the bits of port A are made high to make sure no other digits
are turned on. After 1 or 2 ms, digit 1 is turned off by outputting all highs to port
A.
The BCD code for digit 2 is then output to the 7447 on port B, and a word to turn
on digit 2 is output on port A.
After 1 or 2 ms, digit 2 is turned off and the process is repeated for digit 3. the
process is continued until all the digits have had a turn. Then digit 1 and the
following digits are lit again in turn.
A procedure which is called on an interrupt basis every 2ms to keep these displays
refreshed wit some values stored in a table. With 8 digits and 2ms per digit, you
get back to digit 1 every 16ms or about 60 times a second.
This refresh rate is fast enough so that the digits will each appear to be lit all time.
Refresh rates of 40 to 200 times a second are acceptable.
The immediately obvious advantages of multiplexing the displays are that only
one 7447 is required, and only one digit is lit at a time. We usually increase the
current per segment to between 40 and 60 mA for multiplexed displays so that
they will appear as bright as they would if they were not multiplexed. Even with
this increased segment current, multiplexing gives a large saving in power and
parts.
The software-multiplexed approach we have just described can also be used to
drive 18-segment LED devices and dot-matrix LED device. For these devices,
however you replace the 7447 in fig with ROM which generates the required
segment codes when the ASCII code for a character is applied to the address
inputs of the ROM.
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+5V
150
Each
+5V
13 12
a
b
Vcc
11 10
c
d
9 15 14
e
f
g
BI 5
7447
RBI 4
GND
+5V
B
1
C
2
D
6
LT 3
BCD INPUTS
Circuit for driving single 7-segment LED display with 7447
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D0
D1
D2
D3
D4
D5
D6
R1
R2
Q1
R3
R5
R4
Q2
Q3
Q5
Q4
R7
R6
Q6
Q7
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OUTPUT
PORT
A
+ 5V
MSD
+5V
OUTPUT
PORT
B
D0
D1
D2
D3
150
150
150
Vcc
GND
150
150
150
LSD
150
7447
Liquid Crystal Display
Liquid Crystal displays are created by sandwiching a thin 10-12 m layer of a

liquid-crystal fluid between two glass plates. A transparent, electrically
conductive film or backplane is put on the rear glass sheet. Transparent sections
of conductive film in the shape of the desired characters are coated on the front
glass plate.
When a voltage is applied between a segment and the backplane, an electric field
is created in the region under the segment. This electric field changes the
transmission of light through the region under the segment film.
There are two commonly available types of LCD : dynamic scattering and fieldeffect.
The Dynamic scattering types of LCD: It scrambles the molecules where the field
is present. This produces an etched-glass-looking light character on a dark
background.
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Field-effect types use polarization to absorb light where the electric field is
present. This produces dark characters on a silver- gray background.
Most LCDs require a voltage of 2 or 3 V between the backplane and a segment to
turn on the segment.
We cannot just connect the backplane to ground and drive the segment with the
outputs of a TTL decoder. The reason for this is a steady dc voltage of more than
about 50mV is applied between a segment and the backplane.
To prevent a dc buildup on the segments, the segment-drive signals for LCD must
be square waves with a frequency of 30 to 150 Hz.
Even if you pulse the TTL decoder, it still will not work because the output low
voltage of TTL devices is greater than 50mV.
CMOS gates are often used to drive LCDs.
The Following fig shows how two CMOS gate outputs can be connected to drive
an LCD segment and backplane.
The off segment receives the same drive signal as the backplane. There is never
any voltage between them, so no electric field is produced. The waveform for the
on segment is 180 out of phase with the backplane signal, so the voltage between
this segment and the backplane will always be +V.
The logic for this signal, a square wave and its complement. To the driving gates,
the segment-backplane sandwich appears as a somewhat leaky capacitor.
The CMOS gates can be easily supply the current required to charge and
discharge this small capacitance.
Older inexpensive LCD displays turn on and off too slowly to be multiplexed the
way we do LED display.
At 0c some LCD may require as mush as 0.5s to turn on or off. To interface to
those types we use a nonmultiplexed driver device.
More expensive LCD can turn on and off faster, so they are often multiplexed
using a variety of techniques.
In the following section we show you how to interface a nonmultiplexed LCD to a
microprocessor such as SDK-86.
Intersil ICM7211M can be connected to drive a 4-digit, nonmultiplexed, 7segment LCD display.
The 7211M input can be connected to port pins or directly to microcomputer bus.
We have connected the CS inputs to the Y2 output of the 74LS138 port decoder.
According to the truth table the device will then be addressable as ports with a
base address of FF10H. SDK-86 system address lines A2 is connected to the
digit-select input (DS2) and system address lines A1 is connected to the DS1
input. This gives digit 4 a system address of FF10H.
A8-A15 A5-A7
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2 A1 A0 M/IO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Y Output
Selected
00
1
2
3
4
5
6
7
System Base
Address
F F 0
0
F F 0
8
F F 1
0
F F 1
8
F F 0
1
F F 0
9
F F 1
1
F F 1
9
Device
8259A #1
8259A #2
8254
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1
1
1
1
1
1
1
1
A4 A3
ALL OTHER STATES
NONE
Fig : Truth table for 74LS138 address decoder
Digit 3 will be addressed at FF12H, digit 2 at FF14H and digit 1 at FF16H.

The data inputs are connected to the lower four lines of the SDK-86 data bus. The
oscillator input is left open. To display a character on one of the digits, you
simply keep the 4-bit hex code for that digit in the lower 4 bits of the AL register
and output it to the system address for that digit.
The ICM7211M converts the 4-bit hex code to the required 7-segment code.
The rising edge of the CS input signal causes the 7-segment code to be latched in
the output latches for the address digit.
An internal oscillator automatically generates the segment and backplane drive
waveforms as in fig . For interfacing with the LCD displays which can be
multiplexed the Intersil ICM7233 can be use.
D4
Segment Outputs
ICM7211M
D3
D2
Segment Outputs
Segment Outputs
D1
Segment Outputs
7 Wide Driver
7 Wide Driver
7 Wide Driver
7 Wide Driver
7 Wide Latch
EN
7 Wide Latch
EN
7 Wide Latch
EN
7 Wide Latch
EN
Programmable
4 to 7 Decoder
Programmable
4 to 7 Decoder
Programmable
4 to 7 Decoder
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Programmable
4 to 7 Decoder
AD0
AD1
AD2
AD3
A1
A2
Data
4 bit
latch
Enable
DS1
DS2
2to4
Decoder
2 bit
Latch
Enable
Enable
74LS138 CS1
Y2
CS2
One
Shot
Oscillator
16KHz Free
Running
/ 128
Back
Plane
Driver
Enable
Back Plane
Output
+5 V OSC Enable
Enable Detector
Fig : Circuit for interfacing four LCD digits to an SDK-86 bus using ICM7211M
Interfacing Digital To Analog Converters
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INTERFACING DIGITAL TO ANALOG CONVERTERS: The digital to analog

converters convert binary number into their equivalent voltages. The DAC find
applications in areas like digitally controlled gains, motors speed controls, programmable
gain amplifiers etc.
AD 7523 8-bit Multiplying DAC : This is a 16 pin DIP, multiplying digital to
analog converter, containing R-2R ladder for D-A conversion along with single pole
double thrown NMOS switches to connect the digital inputs to the ladder.
The pin diagram of AD7523 is shown in fig the supply range is from +5V to
+15V, while Vref may be any where between -10V to +10V. The maximum
analog output voltage will be any where between -10V to +10V, when all the
digital inputs are at logic high state.
Usually a zener is connected between OUT1 and OUT2 to save the DAC from
negative transients. An operational amplifier is used as a current to voltage
converter at the output of AD to convert the current out put of AD to a
proportional output voltage.
G.VIjaya Santhi,Asst.Prof
It also offers additional drive capability to the DAC output. An external feedback
resistor acts to control the gain. One may not connect any external feedback
resistor, if no gain control is required.
EXAMPLE: Interfacing DAC AD7523 with an 8086 CPU running at 8MHZ and
write an assembly language program to generate a sawtooth waveform of period
1ms with Vmax 5V.
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Solution: Fig shows the interfacing circuit of AD 74523 with 8086 using 8255.
program gives an ALP to generate a sawtooth waveform using circuit.
;make all ports output
;start voltage for ramp
ASSUME
CS:CODE
CODE SEGMENT
START
:MOV AL,80h
OUT CW, AL
AGAIN
:MOV AL,00h
BACK :
OUT PA, AL
INC AL
CMP AL, 0FFh
JB
BACK
JMP AGAIN
CODE ENDS
END
START
+5V
+10V
15
14
16
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RFB
PA7
MSB
OUT1 1
8255A
PA0
LSB
OUT2
11
VZ
V0
AD7523
CS
GND
Fig: Interfacing of AD7523
In the above program, port A is initialized as the output port for sending the
digital data as input to DAC. The ramp starts from the 0V (analog), hence AL
starts with 00H. To increment the ramp, the content of AL is increased during
each execution of loop till it reaches F2H.
After that the saw tooth wave again starts from 00H, i.e. 0V(analog) and the
procedure is repeated. The ramp period given by this program is precisely
1.000625 ms. Here the count F2H has been calculated by dividing the required
delay of 1ms by the time required for the execution of the loop once. The ramp
slope can be controlled by calling a controllable delay after the OUT instruction.
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Interfacing Analog to Digital Data Converters
In most of the cases, the PIO 8255 is used for interfacing the analog to digital
converters with microprocessor.
We have already studied 8255 interfacing with 8086 as an I/O port, in previous
section. This section we will only emphasize the interfacing techniques of analog
to digital converters with 8255.
The analog to digital converters is treaded as an input device by the
microprocessor, that sends an initialising signal to the ADC to start the analogy to
digital data conversation process. The start of conversation signal is a pulse of a
specific duration.
The process of analog to digital conversion is a slow process, and the
microprocessor has to wait for the digital data till the conversion is over. After the
conversion is over, the ADC sends end of conversion EOC signal to inform the
microprocessor that the conversion is over and the result is ready at the output
buffer of the ADC. These tasks of issuing an SOC pulse to ADC, reading EOC
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signal from the ADC and reading the digital output of the ADC are carried out by
the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOC pulse till the active
edge of EOC signal is called as the conversion delay of the ADC.
It may range any where from a few microseconds in case of fast ADC to even a
few hundred milliseconds in case of slow ADCs.
The available ADC in the market use different conversion techniques for
conversion of analog signal to digitals. Successive approximation techniques and
dual slope integration techniques are the most popular techniques used in the
integrated ADC chip.
General algorithm for ADC interfacing contains the following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end of conversion processes.
4. Read digital data output of the ADC as equivalent digital output.
5. Analog input voltage must be constant at the input of the ADC right from the start
of conversion till the end of the conversion to get correct results. This may be
ensured by a sample and hold circuit which samples the analog signal and holds it
constant for a specific time duration. The microprocessor may issue a hold signal
to the sample and hold circuit.
6. If the applied input changes before the complete conversion process is over, the
digital equivalent of the analog input calculated by the ADC may not be correct.
ADC 0808/0809 :
The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive
approximation converters. This technique is one of the fast techniques for analog
to digital conversion. The conversion delay is 100s at a clock frequency of 640
KHz, which is quite low as compared to other converters. These converters do not
need any external zero or full scale adjustments as they are already taken care of
by internal circuits. These converters internally have a 3:8 analog multiplexer so
that at a time eight different analog conversion by using address lines ADD A, ADD B, ADD C. Using these address inputs, multichannel data acquisition
system can be designed using a single ADC. The CPU may drive these lines using output
port lines in case of multichannel applications. In case of single input applications, these
may be hardwired to select the proper input.
There are unipolar analog to digital converters, i.e. they are able to convert only
positive analog input voltage to their digital equivalent. These chips do no contain
any internal sample and hold circuit.
Analog /P
selecte
Address lines
B
I/P0
I/P1
I/P2
I/P3
I/P4
I/P5
I/P6
I/P7
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If one needs a sample and hold circuit for the conversion of fast signal into
equivalent digital quantities, it has to be externally connected at each of the
analog inputs.
Vcc
GND
Vref +
Vref _
I/P0 I/P7
ADD A,B,C
O7 O0
SOC
EOC
OE
CLK
Supply pins +5V

GND
Reference voltage positive +5 Volts maximum.
Reference voltage negative 0Volts minimum.
Analog inputs
Address lines for selecting analog inputs.
Digital 8-bit output with O7 MSB and O0 LSB
Start of conversion signal pin
End of conversion signal pin
Output latch enable pin, if high enables output
Clock input for ADC
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SOC
I/P 0
CLOCK
EOC
I/P 1
Control and
Timing unit
and .A.R.
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I/P2
I/P3
8 Channel
Analog
Multiplexer
I/P4
256 R
Register
ladder and
Switch tree
I/P5
I/P6
I/P7
V ref +
C B
Address
V ref _
8-bit
O/P
O/P
Latch
O/P
Enable
Block Diagram of ADC 0808 / 0809
CLOCK
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START
ALE
EO C
OE
O/P
Timing Diagram of ADC 0808
Example: Interfacing ADC 0808 with 8086 using 8255 ports. Use port A of 8255
for transferring digital data output of ADC to the CPU and port C for control
signals. Assume that an analog input is present at I/P2 of the ADC and a clock
input of suitable frequency is available for ADC.
Solution: The analog input I/P2 is used and therefore address pins A,B,C should
be 0,1,0 respectively to select I/P2. The OE and ALE pins are already kept at +5V
to select the ADC and enable the outputs. Port C upper acts as the input port to
receive the EOC signal while port C lower acts as the output port to send SOC to
the ADC.
Port A acts as a 8-bit input data port to receive the digital data output from the
ADC. The 8255 control word is written as follows:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0
The required ALP is as follows:
MOV AL, 98h
;initialise 8255 as
OUT CWR, AL
;discussed above.
MOV AL, 02h
;Select I/P2 as analog
OUT Port B, AL
;input.
MOV AL, 00h
;Give start of conversion
OUT Port C, AL
; pulse to the ADC
MOV AL, 01h
OUT Port C, AL
MOV AL, 00h
OUT Port C, AL
WAIT: IN
AL, Port C
;Check for EOC by
RCR
JNC WAIT
IN
AL, Port A
HLT
; reading port C upper and

;rotating through carry.
;If EOC, read digital equivalent in AL
;Stop.
Vref +
Vref +
+5V
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CS
+5V
PA7 PA0
D0 D 7
A2
Clock up
O7 O0
PC7
EOC
PC0
SOC
A1
Vcc
OE
Reset
IORD
IOWR
8255
+5V
Analog
I/P
Voltage
ADC
0808
ALE
A
GND
PB0
PB1
PB2
Interfacing 0808 with 8086
INTERFACING STEPPER MOTOR
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Stepper motor is a device used to obtain an accurate position control of rotating shafts. A stepper
motor employs rotation of its shaft in terms of steps, rather than continuous rotation as in case of
AC or DC motor. To rotate the shaft of the stepper motor, a sequence of pulses is needed to be
applied to the windings of the stepper motor, in proper sequence. The numbers of pulses required
for complete rotation of the shaft of the stepper motor are equal to the number of internal teeth
on its rotor. The stator teeth and the rotor teeth lock with each other to fix a position of the shaft.
With a pulse applied to the winding input, the rotor rotates by one teeth position or an angle x.
the angle x may be calculated as: x = 360 / no. of rotor teeth .After the rotation of the shaft
through angle x, the rotor locks it self with the next tooth in the sequence on the internal surface
of the stator. The typical schematic of a typical stepper motor with four windings is as shown
below.
The stepper motors have been designed to work with digital circuits. Binary level pulses of 0-5V
are required at its winding inputs to obtain the rotation of the shafts. The sequence of the pulses
can be decided, depending upon the required motion of the shaft. By suitable sequence of the
pulses the motor can be used in three modes of operation.
Two phase ON (high torque)

Half stepping (low torque)
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One phase ON (medium torque)
WORKING:8255 is interfaced with 8086 in I/O mapped I/O. port C (PC0, PC1, PC2, PC3) is used to give
pulse sequence to stepper motor. The 8255 provides very less current which will not be able to
drive stepper motor coils so each of the winding of a stepper motor needs to be interfaced using
high speed switching Darlington transistors with max 1A, 80V rating with heat sink, with the
output port of 8255. Output the sequence in correct order to have the desired direction to rotate
the motor.
Assembly Language Program to rotate Stepper Motor in Clockwise direction
MODEL SMALL
.STACK 100
.DATA
PORTA EQU FFC0H ; PORTA ADDRESS
PORTB EQU FFC2H ; PORTB ADDRESS
PORTC EQU FFC4H ; PORTC ADDRESS
CWR EQU FFC6H ; CONTROL PORT ADDRESS
PHASEC EQU 03H
PHASEB EQU 06H ; SEQUENCE IN SERIES TO ROTATE MOTOR
PHASED EQU 0CH ; IN CLOCKWISE DIRECTION
PHASEA EQU 09H
.CODE
START:
MOV AL,@DATA
MOV DX,CTL
OUT DX,AL
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AGAIN:
MOV AL,PHASEC
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP:
LOOP UP
MOV AL,PHASEB
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP1:
LOOP UP1
MOV AL,PHASED
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP2:
LOOP UP2
MOV AL,PHASEA
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP3:
LOOP UP3
JMP AGAIN ; REPEATE OUTPUT SEQUENCE
INT 03H
END START
Assembly Language Program to rotate Stepper Motor in Anticlockwise direction
MODEL SMALL
.STACK 100
.DATA
PORTA EQU FFC0H ; PORTA ADDRESS
PORTB EQU FFC2H ; PORTB ADDRESS
PORTC EQU FFC4H ; PORTC ADDRESS
CWR EQU FFC6H ; CONTROL PORT ADDRESS
PHASEC EQU 03H
PHASEA EQU 09H ; SEQUENCE IN SERIES TO ROTATE MOTOR

PHASED EQU 0CH ; IN ANTICLOCKWISE DIRECTION
PHASEB EQU 06H
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.CODE
START:
MOV AL,@DATA
MOV DX,CTL
OUT DX,AL
AGAIN:
MOV AL,PHASEC
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP:
LOOP UP
MOV AL,PHASEA
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP1:
LOOP UP1
MOV AL,PHASED
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP2:
LOOP UP2
MOV AL,PHASEB
MOV DX,PORTC
OUT DX,AL
MOV CX,0FFFFH
UP3:
LOOP UP3
JMP AGAIN ; REPEATE OUTPUT SEQUENCE
INT 03H
END START
DATA TRANSFER INSTRUCTIONS
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GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS:

MOV
PUSH
POP
XCHG
XLAT
SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION:
IN
OUT
SPECIAL ADDRESS TRANSFER INSTRUCTION
LEA
LDS
LES
FLAG TRANSFER INSTRUCTIONS:
LAHF
SAHF
PUSHF
POPF
MOV Instruction - MOV destination, source
MOV Instruction - The MOV instruction copies a word or a byte of data from a specified
source to a specified destination .
MOV op1, op2
Example:
MOV CX, 037AH
; MOV 037AH into the CX.
MOV AX, BX
;Copy the contents of register BX to AX
MOV DL,[BX]
;Copy byte from memory at BX
;to DL , BX contains the offset of byte in DS.
PUSH Instruction - PUSH source
PUSH Instruction - PUSH instruction decrements the stack pointer by 2 and copies a word
from a specified source to the location in the stack segment where the stack pointer pointes.
Example:
PUSH BX ;Decrement SP by 2 and copy BX to stack
PUSH DS ;Decrement SP by 2 and copy DS to stack
PUSH TABLE[BX] ;Decrement SP by 2 and copy word
;from memory in DS at
;EA = TABLE + [BX] to stack .

POP Instruction - POP destination
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POP Instruction - POP instruction copies the word at the current top of the stack to the operand
specified by op then increments the stack pointer to point to the next stack.
Example:
POP DX
;Copy a word from top of the stack to
; DX and increments SP by 2.
POP DS
; Copy a word from top of the stack to
; DS and increments SP by 2.
POP TABLE [BX]
;Copy a word from top of stack to memory in DS with
;EA = TABLE + [BX].
XCHG Instruction - Exchange XCHG destination, source
XCHG Instruction - The Exchange instruction exchanges the contents of the register with the
contents of another register (or) the contents of the register with the contents of the memory
location. Direct memory to memory exchange are not supported.
XCHG op1, op2
The both operands must be the same size and one of the operand must always be a
register .
Example:
XCHG AX, DX
;Exchange word in AX with word in DX
XCHG BL, CH
;Exchange byte in BL with byte in CH
XCHG AL, Money [BX]
;Exchange byte in AL with byte
;in memory at EA.
XLAT/
XLATB Instruction - Translate a byte in AL
Example:
MOV BX,0000H
MOV AL,CODE
XLAT
IN AX, A_TO_D ;Input a word from port 4AH to AX

For a variable port IN instruction, the port address is loaded in DX register before IN instruction.
DX is 16 bit. Port address range from 0000H FFFFH.
Example:
MOV DX, 0FF78H ;Initialize DX point to port

IN AL, DX
;Input a byte from a 8 bit port
;0FF78H to AL
IN AX, DX
;Input a word from 16 bit port to
;0FF78H to AX.
OUT Instruction - Output a byte or word to a port

OUT port, accumulator AL or AX.
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OUT Instruction - The OUT instruction copies a byte from AL or a word from AX or a double
from the accumulator to I/O port specified by op. Two forms of OUT instruction are available :
(1) Port number is specified by an immediate byte constant, ( 0- 255 ).It is also called as fixed
port form. (2) Port number is provided in the DX register( 0 65535 )
Example:
(1)
OUT 3BH, AL
Copy the contents of the AL to port 3Bh
OUT 2CH,AX
;Copy the contents of the AX to port 2Ch
(2)
MOV DX, 0FFF8H ;Load desired port address in DX
OUT DX, AL
; Copy the contents of AL to
;FFF8h
OUT DX, AX
;Copy content of AX to port
;FFF8H
LDS Instruction - Load register and Ds with words from memory LDS register, memory
address of first word
LDS Instruction - This instruction loads a far pointer from the memory address specified by
op2 into the DS segment register and the op1 to the register.
LDS op1, op2
Example:
LDS BX, [4326]
; copy the contents of the memory at
displacement 4326H in DS to BL, contents of the 4327H
to BH. Copy contents of
4328H and 4329H in DS to DS register.
LEA Instruction - Load effective address-LEA register, source
LEA Instruction - This instruction indicates the offset of the variable or memory location
named as the source and put this offset in the indicated 16 bit register.
Example:
LEA BX, PRICE
;Load BX with offset of PRICE
;in DS
LEA BP, SS:STAK ;Load BP with offset of STACK
;in SS
LEA CX, [BX][DI] ;Load CX with EA=BX + DI
LES Instruction - Load register and ES with words from memory LES register, memory
address of first word.
LAHF Instruction - Copy low byte of flag

register to AH
LAHF Instruction - LAHF instruction copies the value of SF, ZF, AF,PF, CF, into bits of 7, 6,
4, 2, 0 respectively of AH register. This LAHF instruction was
provided to make conversion of assembly language programs written for 8080 and 8085 to 8086
easier.
SAHF Instruction Copy AH register to low byte of flag register
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SAHF Instruction - SAHF copies the value of bits 7, 6, 4, 2, 0 of the AH register into the SF,
ZF, AF, PF, and CF respectively. This instruction was provided to make easier conversion of
assembly language program written for 8080 and 8085 to 8086.
PUSHF Instruction - This instruction decrements the SP by 2 and copies the word in flag
register to the memory location pointed to by SP.
POPF Instruction - This instruction copies a word from the two memory location at the top of
the stack to flag register and increments the stack pointer by 2.
8086 Instruction Set Summary
file:///D|/notes/8086inst.html
8086 Instruction
Set Summary
ASCII adjust
for addition,
subtraction,
division
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AAA, AAS, AAM,
codes 30-39)
AAD
Data Transfer Instructions
DAA, DAS
Decimal adjust for addition, subtraction (binary coded decimal numbers)
Transfer Instructions
MOV
Move byte or word to register or memory
IN, OUT
Input byte or word from port, output word to port
LEA
Load effective address
LDS, LES
Load pointer using data segment, extra segment
JMP Unconditional jump (short ?127/8, near ?32K, far between segments)
Conditional jumps:
PUSH, POP Push word onto stack, pop word off stack
XCHG
Exchange byte or word
XLAT
Translate byte using look-up table
JA (JNBE) Jump if above (not below or equal)? +127, -128 range only
JAE (JNB) Jump if above or equal(not below)? +127, -128 range only
Logical Instructions
JB (JNAE) Jump if below (not above or equal)? +127, -128 range only
JBE (JNA) Jump if below or equal (not above)? +127, -128 range only
NOT Logical NOT of byte or word (one's complement)
JE (JZ)
AND Logical AND of byte or word
JG (JNLE) Jump if greater (not less or equal)? +127, -128 range only
OR
JGE (JNL) Jump if greater or equal (not less)? +127, -128 range only
Logical OR of byte or word
Jump if equal (zero)? +127, -128 range only
XOR Logical exclusive-OR of byte or word
JL (JNGE) Jump if less (not greater nor equal)? +127, -128 range only
TEST Test byte or word (AND without storing)
JLE (JNG) Jump if less or equal (not greater)? +127, -128 range only
JC, JNC
Jump if carry set, carry not set? +127, -128 range only
JO, JNO
Jump if overflow, no overflow? +127, -128 range only
JS, JNS
Jump if sign, no sign? +127, -128 range only
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Shift and Rotate Instructions
SHL, SHR Logical shift left, right byte or word? by 1 or CL
JNP (JPO) Jump if no parity (parity odd)? +127, -128 range only
SAL, SAR Arithmetic shift left, right byte or word? by 1 or CL
JP (JPE)
Jump if parity (parity even)? +127, -128 range only
ROL, ROR Rotate left, right byte or word? by 1 or CL
RCL, RCR Rotate left, right through carry byte or word? by 1 or CL
Loop control:
Arithmetic Instructions
LOOP
Loop unconditional, count in CX, short jump to target address
ADD, SUB
Add, subtract byte or word
LOOPE (LOOPZ)
Loop if equal (zero), count in CX, short jump to target address
ADC, SBB
Add, subtract byte or word and carry (borrow)
LOOPNE (LOOPNZ) Loop if not equal (not zero), count in CX, short jump to target address
INC, DEC
Increment, decrement byte or word
JCXZ
NEG
Negate byte or word (two's complement)
CMP
Compare byte or word (subtract without storing)
MUL, DIV
Multiply, divide byte or word (unsigned)
Jump if CX equals zero (used to skip code in loop)
Subroutine and Interrupt Instructions
IMUL, IDIV Integer multiply, divide byte or word (signed)
CALL, RET Call, return from procedure (inside or outside current segment)
CBW, CWD Convert byte to word, word to double word (useful before multiply/divide)
INT, INTO Software interrupt, interrupt if overflow

IRET
Return from interrupt
Adjustments after arithmetic operations:
String Instructions
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MOVS
Move byte or word string
MOVSB, MOVSW Move byte, word string

CMPS
Compare byte or word string
SCAS
Scan byte or word string (comparing to A or AX)
LODS, STOS
Load, store byte or word string to AL or AX
Repeat instructions (placed in front of other string operations):
REP
Repeat
REPE, REPZ
Repeat while equal, zero
REPNE, REPNZ Repeat while not equal (zero)
Processor Control Instructions

Flag manipulation:
STC, CLC, CMC Set, clear, complement carry flag

STD, CLD
Set, clear direction flag
STI, CLI
Set, clear interrupt enable flag
LAHF, SAHF
Load AH from flags, store AH into flags
PUSHF, POPF
Push flags onto stack, pop flags off stack
Coprocessor, multiprocessor interface:
ESC
Escape to external processor interface
LOCK Lock bus during next instruction

Inactive states:
NOP No operation
WAIT Wait for TEST pin activity
HLT
Halt processor

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8259A
If we are working with an 8086, we have a problem here because the 8086 has
only two interrupt inputs, NMI and INTR.
If we save NMI for a power failure interrupt, this leaves only one interrupt for all
the other applications. For applications where we have interrupts from multiple
source, we use an external device called a priority interrupt controller ( PIC ) to
the interrupt signals into a single interrupt input on the processor.
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Architecture and Signal Descriptions of 8259A
The architectural block diagram of 8259A is shown in fig1. The functional

explication of each block is given in the following text in brief.
Interrupt Request Register (RR): The interrupts at IRQ input lines are handled
by Interrupt Request internally. IRR stores all the interrupt request in it in order to
serve them one by one on the priority basis.
In-Service Register (ISR): This stores all the interrupt requests those are being
served, i.e. ISR keeps a track of the requests being served.
INTA
D0-D7
Control Logic
Data Bus
Buffer
RD
WR
A0
Read/
Write
Logic
IN Service
Register
ISR
CS
CAS0
CAS1
CAS2
INT
Cascade
Buffer/
Comparator
SP / EN
Priority
Resolver
Interrupt
Request
Register
IRR
IR0
IR1
IR7
Interrupt Mask Register

IMR
Internal Bus
Fig:1
8259A Block Diagram
Priority Resolver : This unit determines the priorities of the interrupt requests
appearing simultaneously. The highest priority is selected and stored into the
corresponding bit of ISR during INTA pulse. The IR0 has the highest priority
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while the IR7 has the lowest one, normally in fixed priority mode. The priorities
however may be altered by programming the 8259A in rotating priority mode.
Interrupt Mask Register (IMR) : This register stores the bits required to mask
the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver.
Interrupt Control Logic: This block manages the interrupt and interrupt
acknowledge signals to be sent to the CPU for serving one of the eight interrupt
requests. This also accepts the interrupt acknowledge (INTA) signal from CPU
that causes the 8259A to release vector address on to the data bus.
Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus
to the microprocessor system data bus. Control words, status and vector
information pass through data buffer during read or write operations.
Read/Write Control Logic: This circuit accepts and decodes commands from the
CPU. This block also allows the status of the 8259A to be transferred on to the
data bus.
Cascade Buffer/Comparator: This block stores and compares the IDs all the
8259A used in system. The three I/O pins CASO-2 are outputs when the 8259A is
used as a master. The same pins act as inputs when the 8259A is in slave mode.
The 8259A in master mode sends the ID of the interrupting slave device on these
lines. The slave thus selected, will send its preprogrammed vector address on the
data bus during the next INTA pulse.
CS: This is an active-low chip select signal for enabling RD and WR operations
of 8259A. INTA function is independent of CS.
WR : This pin is an active-low write enable input to 8259A. This enables it to
accept command words from CPU.
RD : This is an active-low read enable input to 8259A. A low on this line enables
8259A to release status onto the data bus of CPU.
D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to
control word or from status word registers. This also carries interrupt vector
information.
CAS0 CAS2 Cascade Lines : A signal 8259A provides eight vectored
interrupts. If more interrupts are required, the 8259A is used in cascade mode. In
cascade mode, a master 8259A along with eight slaves 8259A can provide upto
64 vectored interrupt lines. These three lines act as select lines for addressing the
slave 8259A.
PS/EN : This pin is a dual purpose pin. When the chip is used in buffered mode, it
can be used as buffered enable to control buffer transreceivers. If this is not used
in buffered mode then the pin is used as input to designate whether the chip is
used as a master (SP =1) or slave (EN = 0).
INT : This pin goes high whenever a valid interrupt request is asserted. This is
used to interrupt the CPU and is connected to the interrupt input of CPU.
IR0 IR7 (Interrupt requests) :These pins act as inputs to accept interrupt
request to the CPU. In edge triggered mode, an interrupt service is requested by
raising an IR pin from a low to a high state and holding it high until it is
acknowledged, and just by latching it to high level, if used in level triggered
mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
Vcc
A0
INTA
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
INT
SP / EN
CAS2
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CS
WR
RD
D7
D6
D5
D4
D3
D2
D1
D0
CAS0
CAS1
GND
8259A
15
Fig : 8259 Pin Diagram
INTA ( Interrupt acknowledge ): This pin is an input used to strobe-in 8259A

interrupt vector data on to the data bus. In conjunction with CS, WR and RD pins,
this selects the different operations like, writing command words, reading status
word, etc.
The device 8259A can be interfaced with any CPU using either polling or
interrupt. In polling, the CPU keeps on checking each peripheral device in
sequence to ascertain if it requires any service from the CPU. If any such service
request is noticed, the CPU serves the request and then goes on to the next device
in sequence.
After all the peripheral device are scanned as above the CPU again starts from
first device.
This type of system operation results in the reduction of processing speed because
most of the CPU time is consumed in polling the peripheral devices.
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In the interrupt driven method, the CPU performs the main processing task till it
is interrupted by a service requesting peripheral device.
The net processing speed of these type of systems is high because the CPU serves
the peripheral only if it receives the interrupt request.
If more than one interrupt requests are received at a time, all the requesting
peripherals are served one by one on priority basis.
This method of interfacing may require additional hardware if number of
peripherals to be interfaced is more than the interrupt pins available with the CPU.
Interrupt Sequence in an 8086 system
1.
2.
3.
4.
The Interrupt sequence in an 8086-8259A system is described as follows:

One or more IR lines are raised high that set corresponding IRR bits.
8259A resolves priority and sends an INT signal to CPU.
The CPU acknowledge with INTA pulse.
Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive data during this
period.
5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an
8-bit pointer on to a data bus from where it is read by the CPU.
6. This completes the interrupt cycle. The ISR bit is reset at the end of the second
INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise
ISR bit remains set until an appropriate EOI command is issued at the end of
interrupt subroutine.
Command Words of 8259A
1.
2.
The command words of 8259A are classified in two groups

Initialization command words (ICW) and
Operation command words (OCW).
Initialization Command Words (ICW): Before it starts functioning, the 8259A
must be initialized by writing two to four command words into the respective
command word registers. These are called as initialized command words.
If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It contains the
control bits for edge/level triggered mode, single/cascade mode, call address
interval and whether ICW4 is required or not.
If A0=1, the control word is recognized as ICW2. The ICW2 stores details
regarding interrupt vector addresses. The initialisation sequence of 8259A is
described in form of a flow chart in fig 3 below.
The bit functions of the ICW1 and ICW2 are self explanatory as shown in fig
below.
ICW1
ICW2
A : IN CASCADE MODE ?
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NO (SINGLE =1)
YES (SINGLE =0)
ICW3
NO (IC4 =0)
B : IS ICW4 NEEDED ?
YES (IC4 = 1)
ICW4
Ready to Accept
Interrupt Request
Fig 3: Initialisation Sequence of 8259A
A0
0
D7
A7
D6
A6
D5
A5
A7-A5 of Interrupt
vector address MCs
80/85 mode only
D4
1
D3
D2
LTIM ADI
ICW1
D1
D0
SNGL IC4
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1 = ICW4 Needed
0 = No ICW4
1 Single
0 - Cascaded
1 Level Triggered
0 Edge Triggered
ICW2
A0
1
D7
T7
D6
D5
D4
D3
T6
T5
T4
T3
D2
A10
Call Address Interval

1 Interval of 4 bytes
0 Interval of 8 bytes.
D1
D0
A9
A8
T7 T3 are A3 A0 of interrupt address

A10 A9, A8 Selected according to interrupt request level.
They are not the address lines of Microprocessor
A0
=1
selects ICW2
Fig 4 : Instruction Command Words ICW1 and ICW2
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
Once ICW1 is loaded, the following initialization procedure is carried out

internally.
The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive.
IMR is cleared.
IR7 input is assigned the lowest priority.
Slave mode address is set to 7.
Special mask mode is cleared and status read is set to IRR.
If IC4 = 0, all the functions of ICW4 are set to zero. Master/Slave bit in ICW4 is
used in the buffered mode only.
In an 8085 based system A15-A8 of the interrupt vector address are the respective
bits of ICW2.
In 8086 based system A15-A11 of the interrupt vector address are inserted in
place of T7 T3 respectively and the remaining three bits A8, A9, A10 are
selected depending upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7.
ICW1 and ICW2 are compulsory command words in initialization sequence of
8259A as is evident from fig, while ICW3 and ICW4 are optional. The ICW3 is
read only when there are more than one 8259A in the system, cascading is used (
SNGL=0 ).
The SNGL bit in ICW1 indicates whether the 8259A in the cascade mode or not.
The ICW3 loads an 8-bit slave register. It detailed functions are as follows.
k. In master mode [ SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-bit slave

register will be set bit-wise to 1 for each slave in the system as in fig 5.
l. The requesting slave will then release the second byte of a CALL sequence. In
slave mode [ SP=0 or if BUF =1 and M/S = 0 in ICW4] bits D2 to D0 identify the
slave, i.e. 000 to 111 for slave 1 to slave 8. The slave compares the cascade inputs
with these bits and if they are equal, the second byte of the CALL sequence is
released by it on the data bus.
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Master mode ICW3

D5
D4
D6
D3
A0
D7
S7
S6
S5
S4
S3
D2
S2
D1
S1
D0
S0
Sn = 1-IRn Input has a slave

= 0 IRn Input does not have a slave
Slave mode ICW3
A0
D7
D6
D5
D4
D3
D2
D1
D0
ID2
ID1
ID0
D2D1D0 000 to 111 for IR0 to IR7 or slave 1 to slave 8
A0
D7
D6
ICW4
D5
D4
0
D3
SFNM BUF
D2
M/S
D1
D0
AEOI PM
Fig : ICW3 in Master and Slave Mode, ICW4 Bit Functions
ICW4: The use of this command word depends on the IC4 bit of ICW1. If IC4=1,
IC4 is used, otherwise it is neglected. The bit functions of ICW4 are described as
follow:
SFNM: If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN
acts as enable output and the master/slave is determined using the M/S bit of
ICW4.
M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave. If BUF = 0, M/S
is to be neglected.
AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.
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PM : If the PM bit is 0, the Mcs-85 system operation is selected and if PM=1,

8086/88 operation is selected.
Operation Command Words: Once 8259A is initialized using the previously
discussed command words for initialisation, it is ready for its normal function, i.e.
for accepting the interrupts but 8259A has its own way of handling the received
interrupts called as modes of operation. These modes of operations can be
selected by programming, i.e. writing three internal registers called as operation
command words.
In the three operation command words OCW1, OCW2 and OCW3 every bit
corresponds to some operational feature of the mode selected, except for a few
bits those are either 1 or 0. The three operation command words are shown in fig
with the bit selection details.
OCW1 is used to mask the masked and if it is 0 the request is enabled. In OCW2
the three bits, R, SL and EOI control the end of interrupt, the rotate mode and
their combinations as shown in fig below.
The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected
for operation, if SL bit is active i.e. 1.
The details of OCW2 are shown in fig.
In operation command word 3 (OCW3), if the ESMM bit, i.e. enable special mask
mode bit is set to 1, the SMM bit is neglected. If the SMM bit, i.e. special mask
mode. When ESMM bit is 0 the SMM bit is neglected. If the SMM bit. i.e. special
mask mode bit is 1, the 8259A will enter special mask mode provided ESMM=1.
If ESMM=1 and SMM=0, the 8259A will return to the normal mask mode. The
details of bits of OCW3 are given in fig along with their bit definitions.
A0
D7
M7
D6
D5
D4
M6
M5
M4
D3
M3
D2
D1
D0
M2
M1
M0
1 Mask Set
0 Mask Reset
Fig (a) : OCW1
A0
0
Reset Special 0
1
Mask
Set Special
1
Mask
No
D7
D6
D5
ESMM SMM
D4
0
D3
D2
D1
D0
RR
RIS
Fig (b) :
0
1
0
1
1 Poll
Command
0 No Poll
Command
Fig : Operation Command Words
0
0
1
1
0
1
0
1
No Action
Read IRR on
next RD pulse
Read IRR on
next RD pulse
Fig (c) :OCW2

A0
1
D7
R
D6
D5
D4
SL
EOI
D3
0
D2
D1
D0
L1
L2
1
1
0
0
2
0
1
0
3
0
1
0
4
0
0
1
5
1
0
1
6
0
1
1
7
1
1
1
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0
0
0
0
L0
END OF
INTERRUPT
AUTOMATIC
ROTATION
SPECIFIC
ROTATION
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
0
0
NON-SPECIFIC EOI COMMAND

SPECIFIC EOI COMMAND
ROTATE ON NON-SPECIFIC EOI MODE (SET)
ROTATE IN AUTOMATIC EOI MODE (SET)
ROTATE IN AUTOMATIC EOI (CLEAR)
ROTATE ON SPECIFIC EOI COMMAND
SET PRIORITY COMMAND*
NO OPERATION
* - In this Mode L0 L2 are used
Fig : Operation Command Word
Operating Modes of 8259
The different modes of operation of 8259A can be programmed by setting or

resting the appropriate bits of the ICW or OCW as discussed previously. The
different modes of operation of 8259A are explained in the following.
Fully Nested Mode : This is the default mode of operation of 8259A. IR0 has the
highest priority and IR7 has the lowest one. When interrupt request are noticed,
the highest priority request amongst them is determined and the vector is placed
on the data bus. The corresponding bit of ISR is set and remains set till the
microprocessor issues an EOI command just before returning from the service
routine or the AEOI bit is set.
If the ISR ( in service ) bit is set, all the same or lower priority interrupts are
inhibited but higher levels will generate an interrupt, that will be acknowledge
only if the microprocessor interrupt enable flag IF is set. The priorities can
afterwards be changed by programming the rotating priority modes.
End of Interrupt (EOI) : The ISR bit can be reset either with AEOI bit of ICW1
or by EOI command, issued before returning from the interrupt service routine.
There are two types of EOI commands specific and non-specific. When 8259A is
operated in the modes that preserve fully nested structure, it can determine which
ISR bit is to be reset on EOI.
When non-specific EOI command is issued to 8259A it will be automatically reset
the highest ISR bit out of those already set.
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When a mode that may disturb the fully nested structure is used, the 8259A is no
longer able to determine the last level acknowledged. In this case a specific EOI
command is issued to reset a particular ISR bit. An ISR bit that is masked by the
corresponding IMR bit, will not be cleared by non-specific EOI of 8259A, if it is
in special mask mode.
Automatic Rotation : This is used in the applications where all the interrupting
devices are of equal priority.
In this mode, an interrupt request IR level receives priority after it is served while
the next device to be served gets the highest priority in sequence. Once all the
device are served like this, the first device again receives highest priority.
Automatic EOI Mode : Till AEOI=1 in ICW4, the 8259A operates in AEOI
mode. In this mode, the 8259A performs a non-specific EOI operation at the
trailing edge of the last INTA pulse automatically. This mode should be used only
when a nested multilevel interrupt structure is not required with a single 8259A.
Specific Rotation : In this mode a bottom priority level can be selected, using L2,
L1 and L0 in OCW2 and R=1, SL=1, EOI=0.
The selected bottom priority fixes other priorities. If IR5 is selected as a bottom
priority, then IR5 will have least priority and IR4 will have a next higher priority.
Thus IR6 will have the highest priority.
These priorities can be changed during an EOI command by programming the
rotate on specific EOI command in OCW2.
Specific Mask Mode: In specific mask mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupt from other levels,
which are not masked.
Edge and Level Triggered Mode : This mode decides whether the interrupt
should be edge triggered or level triggered. If bit LTIM of ICW1 =0 they are edge
triggered, otherwise the interrupts are level triggered.
Reading 8259 Status : The status of the internal registers of 8259A can be read
using this mode. The OCW3 is used to read IRR and ISR while OCW1 is used to
read IMR. Reading is possible only in no polled mode.
Poll Command : In polled mode of operation, the INT output of 8259A is
neglected, though it functions normally, by not connecting INT output or by
masking INT input of the microprocessor. The poll mode is entered by setting
P=1 in OCW3.
The 8259A is polled by using software execution by microprocessor instead of the
requests on INT input. The 8259A treats the next RD pulse to the 8259A as an
interrupt acknowledge. An appropriate ISR bit is set, if there is a request. The
priority level is read and a data word is placed on to data bus, after RD is
activated. A poll command may give more than 64 priority levels.
D7
D6
D5
D4
D3
D2
w2
w1
D0
w0
Binary code of
highest priority
level
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If = 1, there is an interrupt
D1
Fig : Data Word of 8259
Special Fully Nested Mode : This mode is used in more complicated system,
where cascading is used and the priority has to be programmed in the master
using ICW4. this is somewhat similar to the normal nested mode.
In this mode, when an interrupt request from a certain slave is in service, this
slave can further send request to the master, if the requesting device connected to
the slave has higher priority than the one being currently served. In this mode, the
master interrupt the CPU only when the interrupting device has a higher or the
same priority than the one current being served. In normal mode, other requests
than the one being served are masked out.
When entering the interrupt service routine the software has to check whether this
is the only request from the slave. This is done by sending a non-specific EOI can
be sent to the master, otherwise no EOI should be sent. This mode is important,
since in the absence of this mode, the slave would interrupt the master only once
and hence the priorities of the slave inputs would have been disturbed.
Buffered Mode: When the 83259A is used in the systems where bus driving
buffers are used on data buses. The problem of enabling the buffers exists. The
8259A sends buffer enable signal on SP/ EN pin, whenever data is placed on the
bus.
Cascade Mode : The 8259A can be connected in a system containing one master
and eight slaves (maximum) to handle upto 64 priority levels. The master controls
the slaves using CAS0-CAS2 which act as chip select inputs (encoded) for slaves.
In this mode, the slave INT outputs are connected with master IR inputs. When a
slave request line is activated and acknowledged, the master will enable the slave
to release the vector address during second pulse of INTA sequence.
The cascade lines are normally low and contain slave address codes from the
trailing edge of the first INTA pulse to the trailing edge of the second INTA
pulse. Each 8259A in the system must be separately initialized and programmed
to work in different modes. The EOI command must be issued twice, one for
master and the other for the slave.
A separate address decoder is used to activate the chip select line of each 8259A.
Following Fig shows the details of the circuit connections of 8259A in cascade
scheme.
ADDRESS BUS
A1
A1
A1
CONTROL BUS
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DATA BUS
INT
CAS0-CAS2
A0
CS A0 D0-D7 INT
Master
SP/E
M7 M6 M5 M4 M3 M2 M1 M0
Vcc
CS A0 D0-D7 INT
SP/E
Slave 0
IR7
IR0
INT
CS
INT
D0-D7
Slave 7
IR7
IR0
INT
Fig : 8259A in Cascade Mode
INTERRUPT SERVICES DOS, BIOS, EMS AND MOUSE

Intel Defined CPU Exception Table (see notes)
IBM PC Hardware Interrupt Table (in order of priority)
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Interrupt Table as Implemented by System BIOS/DOS

INT 5 - Print Screen
INT 8 - System timer
INT 9 - Keyboard Interrupt (Hardware Handler)

INT 10 - Video BIOS Services
INT 10,0 - Set Video Mode
INT 10,1 - Set Cursor Type
INT 10,2 - Set Cursor Position
INT 10,3 - Read Cursor Position and Size

INT 10,4 - Read Light Pen Position
INT 10,5 - Select Active Display Page

INT 10,6 - Scroll Window Up
INT 10,7 - Scroll Window Down
INT 10,8 - Read Character and Attribute at Cursor Position
INT 10,9 - Write Character and Attribute at Cursor Position
INT 10,A - Write Character Only at Current Cursor Position
INT 10,B - Set Color Palette
INT 10,C - Write Graphics Pixel at Coordinate

INT 10,D - Read Graphics Pixel at Coordinate
INT 10,E - Write Text in Teletype Mode
INT 10,F - Get Video State

INT 10,10 - Set/Get Palette Registers (EGA/VGA)
INT 10,11 - Character Generator Routine (EGA/VGA)
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INT 10,12 - Video Subsystem Configuration (EGA/VGA)

INT 10,13 - Write String (BIOS versions from 1/10/86)
INT 10,14 - Load LCD Character Font (convertible only)
INT 10,15 - Return Physical Display Parms (convertible)

INT 10,1A - Video Display Combination (VGA)
INT 10,1B - Video BIOS Functionality and State Information (MCGA/VGA)

Video BIOS Dynamic Functionality State Table (MCGA/VGA)
Video BIOS Static Functionality Table
INT 10,1C - Save/Restore Video State (VGA only)
INT 10,FE - Get DESQView/TopView Virtual Screen Regen Buffer
INT 10,FF - Update DESQView/TopView Virtual Screen Regen Buffer

INT 11 - BIOS Equipment Determination / BIOS Equipment Flags
INT 12 - Memory Size Determination
INT 13 - Diskette BIOS Services
For more information see the following topics:

INT 13,0 - Reset Disk System
INT 13,1 - Disk Status
INT 13,2 - Read Disk Sectors
INT 13,3 - Write Disk Sectors

INT 13,4 - Verify Disk Sectors
INT 13,5 - Format Disk Track

INT 13,6 - Format Track and Set Bad Sector Flags (XT & portable)
INT 13,7 - Format Drive Starting at Specified Track (XT & portable)
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INT 13,8 - Get Current Drive Parameters (XT & newer)

INT 13,A - Read Long Sector (XT & newer)
INT 13,B - Write Long Sectors (XT & newer)

INT 13,C - Seek to Cylinder (XT & newer)
INT 13,D - Alternate Disk Reset (XT & newer)
INT 13,E - Read Sector Buffer (XT & portable only)
INT 13,F - Write Sector Buffer (XT & portable only)

INT 13,10 - Test for Drive Ready (XT & newer)
INT 13,11 - Recalibrate Drive (XT & newer)
INT 13,12 - Controller RAM Diagnostic (XT & portable only)

INT 13,13 - Drive Diagnostic (XT & portable only)
INT 13,14 - Controller Internal Diagnostic (XT & newer)
INT 13,15 - Read DASD Type (XT BIOS from 1/10/86 & newer)
INT 13,16 - Change of Disk Status (XT BIOS from 1/10/86 & newer)
INT 13,17 - Set DASD Type for Format (XT BIOS from 1/10/86 & newer)
INT 13,18 - Set Media Type for Format (BIOS date specific)
INT 13,19 - Park Fixed Disk Heads (AT & newer)

INT 13,1A - Format Unit (PS/2 model 50+)
INT 14 - BIOS Asynchronous Communications Services

BIOS Asynchronous Communications Services (Status)
INT 14,0 - Initialize Communications Port Parameters

INT 14,1 - Send Character to Communications Port
INT 14,2 - Receive Character from Communications Port
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INT 14,3 - Get Serial Port Status

INT 14,4 - Serial Port Extended Initialization (PS/2 & later systems)
INT 14,5 - Extended Communication Port Control (PS/2 & later systems)
INT 15 - System BIOS Services
For more information see the following topics:
INT 15,0 - Turn Cassette Motor On (PC,PCjr only)
INT 15,1 - Turn Cassette Motor Off (PC,PCjr only)
INT 15,2 - Read Blocks from Cassette (PC,PCjr only)

INT 15,3 - Write Blocks to Cassette (PC,PCjr only)
INT 15,F - Format Periodic Interrupt (PS/2 only)
INT 15,20 - PRINT.
INT 15,21 - Power On Self Test (POST) Error Log (PS/2 except 30)
INT 15,40 - Read / Modify Profiles (convertible only)
INT 15,41 - Wait on External Event (convertible only)
INT 15,42 - Request System Power Off (convertible only)

INT 15,43 - Read System Status (convertible only)
INT 15,44 - (De)activate Internal Modem Power (convertible)

INT 15,4F - Keyboard Intercept (BIOS date specific)
INT 15,80 - Device Open
INT 15,81 - Device Close
INT 15,82 - Program Termination

INT 15,83 - Event Wait
INT 15,84 - Joy-Stick Support
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INT 15,85 - System Request Key Pressed

INT 15,86 - Elapsed Time Wait (AT and PS/2)
INT 15,87 - Move Block to/from Extended Memory

INT 15,88 - Extended Memory Size Determination
INT 15,89 - Switch Processor to Protected Mode
INT 15,90 - Device Busy
INT 15,91 - Interrupt Complete
INT 15,C0 - Return System Configuration Parameters (PS/2 only)
INT 15,C1 - Return Extended BIOS Data Area Segment (PS/2 only)
INT 15,C2 - Pointing Device BIOS Interface (PS/2 only)
INT 15,C3 - Enable/Disable Watchdog Timer (PS/2)
INT 15,C4 - Programmable Option Select (PS/2)
INT 16 - Keyboard BIOS Services
For more information, see the following topics:
INT 16,0 - Wait for Keypress and Read Character

INT 16,1 - Get Keyboard Status
INT 16,2 - Read Keyboard Flags
INT 16,3 - Set Keyboard Typematic Rate (AT+)

INT 16,4 - Keyboard Click Adjustment (AT+)
INT 16,5 - Keyboard Buffer Write (AT+)
INT 16,10 - Extended Wait for Keypress and Read Character (AT+)
INT 16,11 - Extended Get Keyboard Status (AT+)
INT 16,12 - Extended Get Keyboard Status (AT+)
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INT 17 - Printer BIOS Services

INT 17,0 - Print Character
INT 17,1 - Initialize Printer Port
INT 17,2 - Read Printer Port Status

INT 19 - Bootstrap Loader
INT 1A - System and Real Time Clock BIOS Services

INT 1A,0 - Read System Clock Counter
INT 1A,1 - Set System Clock Counter
INT 1A,2 - Read Time From Real Time Clock (XT 286,AT,PS/2)
INT 1A,3 - Set Time on Real Time Clock (XT 286,AT,PS/2)
INT 1A,4 - Read Real Time Clock Date (XT 286,AT,PS/2)
INT 1A,5 - Set Real Time Clock Date (XT 286,AT,PS/2)
INT 1A,6 - Set Real Time Clock Alarm (XT 286,AT,PS/2)
INT 1A,7 - Disable Real Time Clock Alarm (XT,AT,PS/2)
INT 1A,8 - Set RTC Activated Power On Mode (convertible)
INT 1A,9 - Read RTC Alarm Time and Status (convertible,PS/2)
INT 1A,A - Read System Day Counter (PS/2)

INT 1A,B - Set System Day Counter (PS/2)
INT 1A,80 - Setup Sound Multiplexer (PCjr only)

INT 1B - BIOS Ctrl-Break Handler Address
INT 1C - System Timer Tick (User Routine)

INT 1D - Video Initialization Parameter Table Vector
INT 1E - Disk Initialization Parameter Table Vector
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INT 1F - Graphics Display Character Bit Map Table

DOS Interrupt Summary
INT 20 - Program Terminate
INT 21 - DOS Function Dispatcher
For more information, see the following topics:

INT 21,0 - Program Terminate
INT 21,1 - Keyboard Input with Echo

INT 21,2 - Display Output
INT 21,3 - Wait for Auxiliary Device Input

INT 21,4 - Auxiliary Output
INT 21,5 - Printer Output
INT 21,6 - Direct Console I/O
INT 21,7 - Direct Console Input Without Echo

INT 21,8 - Console Input Without Echo
INT 21,9 - Print String
INT 21,A - Buffered Keyboard Input
INT 21,B - Check Standard Input Status
INT 21,C - Clear Keyboard Buffer and Invoke Keyboard Function

INT 21,D - Disk Reset
INT 21,E - Select Disk
INT 21,F - Open a File Using FCB

INT 21,10 - Close a File Using FCB
INT 21,11 - Search for First Entry Using FCB
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INT 21,12 - Search for Next Entry Using FCB

INT 21,13 - Delete File Using FCB
INT 21,14 - Sequential Read Using FCB
INT 21,15 - Sequential Write Using FCB

INT 21,16 - Create a File Using FCB
INT 21,17 - Rename a File Using FCB

INT 21,19 - Get Current Default Drive
INT 21,1A - Set Disk Transfer Address (DTA)

INT 21,1B - Get Allocation Table Information
INT 21,1C - Get Allocation Table Info for Specified Drive
INT 21,1F - Get Pointer to Current Drive Parameter Table (Undocumented)

INT 21,21 - Random Read Using FCB
INT 21,22 - Random Write Using FCB

INT 21,23 - Get File Size Using FCB
INT 21,24 - Set Relative Record Field in FCB

INT 21,25 - Set Interrupt Vector
INT 21,26 - Create New Program Segment Prefix

INT 21,27 - Random Block Read Using FCB
INT 21,28 - Random Block Write Using FCB

INT 21,29 - Parse a Filename for FCB
INT 21,2A - Get Date

INT 21,2B - Set Date
INT 21,2C - Get Time
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INT 21,2D - Set Time

INT 21,2E - Set/Reset Verify Switch
INT 21,2F - Get Disk Transfer Address (DTA)

INT 21,30 - Get DOS Version Number
INT 21,31 - Terminate Process and Remain Resident
INT 21,32 - Get Pointer to Drive Parameter Table (Undocumented)

INT 21,33 - Get/Set System Values (Ctl-Break/Boot Drive)
INT 21,34 - Get Address to DOS Critical Flag INDOS
INT 21,35 - Get Interrupt Vector
INT 21,36 - Get Disk Free Space
INT 21,37 - Get/Set Switch Character (Undocumented, DOS 2.
INT 21,38 - Get/Set Country Dependent Information

INT 21,39 - Create Subdirectory (mkdir)
INT 21,3A - Remove Subdirectory (rmdir)
INT 21,3B - Change Current Directory (chdir)

INT 21,3C - Create File Using Handle
INT 21,3D - Open File Using Handle
INT 21,3E - Close File Using Handle
INT 21,3F - Read From File or Device Using Handle

INT 21,40 - Write To File or Device Using Handle
INT 21,41 - Delete File

INT 21,42 - Move File Pointer Using Handle
INT 21,43 - Get/Set File Attributes
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INT 21,44 - I/O Control for Devices (IOCTL)

INT 21,44,0 / IOCTL,0 - Get Device Information
INT 21,44,1 / IOCTL,1 - Set Device Information
Device Data Word
INT 21,44,2 / IOCTL,2 - Read From Character Device

INT 21,44,3 / IOCTL,3 - Write to Character Device
INT 21,44,4 / IOCTL,4 - Read from Block Device
INT 21,44,5 / IOCTL,5 - Write to Block Device
INT 21,44,6 / IOCTL,6 - Get Input Status
INT 21,44,7 / IOCTL,7 - Get Output Status
INT 21,44,8 / IOCTL,8 - Device Removable Query
INT 21,44,9 / IOCTL,9 - Device Local or Remote Query
INT 21,44,A / IOCTL,A - Handle Local or Remote Query

INT 21,44,B / IOCTL,B - Set Sharing Retry Count
INT 21,44,C / IOCTL,C - Generic I/O for Handles
INT 21,44,D / IOCTL,D - Generic I/O for Block Devices
INT 21,44,E / IOCTL,E - Get Logical Drive

INT 21,44,F / IOCTL,F - Set Logical Drive
INT 21,45 - Duplicate File Handle
INT 21,46 - Force Duplicate File Handle
INT 21,47 - Get Current Directory

INT 21,48 - Allocate Memory
INT 21,49 - Free Allocated Memory
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INT 21,4A - Modify Allocated Memory Block (SETBLOCK)

INT 21,4B - EXEC/Load and Execute Program
INT 21,4C - Terminate Process With Return Code

INT 21,4D - Get Return Code of Sub-process
INT 21,4E - Find First Matching File
INT 21,4F - Find Next Matching File
INT 21,50 - Set Current Process ID (Undocumented DOS 2.
INT 21,51 - Get Current Process ID (Undocumented DOS 2.
INT 21,52 - Get Pointer to DOS "INVARS" (Undocumented)

DOS 3.
DOS 3.
DOS 4.
INT 21,53 - Generate Drive Parameter Table (Undocumented)
INT 21,54 - Get Verify Setting
INT 21,55 - Create New PSP (Undocumented)

INT 21,56 - Rename File
INT 21,57 - Get/Set File Date and Time Using Handle
INT 21,58 - Get/Set Memory Allocation Strategy (Undocumented, DOS 3.
INT 21,59 - Get Extended Error Information (DOS 3.

INT 21,5A - Create Temporary File (DOS 3.
INT 21,5B - Create File (DOS 3.

INT 21,5C - Lock/Unlock File Access (DOS 3.
INT 21,5D - Critical Error Information (Undocumented, DOS 3.
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INT 21,5E AL=0 Get Machine Name (DOS 3.

INT 21,5E AL=01 Set Machine Name (DOS 3.
INT 21,5E AL=02 Set Printer Setup (DOS 3.
INT 21,5E AL=03 Get Printer Setup (DOS 3.

INT 21,5E AL=04 Set Printer Mode (DOS 3.
INT 21,5E AL=05 Get Printer Mode (DOS 3.
INT 21,5F AL=00 Get Redirection Mode (DOS 3.

INT 21,5F AL=01 Set Redirection Mode (DOS 3.
INT 21,5F AL=02 Get Redirection List Entry (DOS 3.

INT 21,5F AL=03 Redirect Device (DOS 3.
INT 21,5F AL=04 Cancel Device Redirection (DOS 3.
INT 21,5F AL=05 Get Redirection List Extended Entry (DOS 4.

INT 21,5F AL=06 Get Redirection List (DOS 4.
INT 21,60 - Get Fully Qualified File Name (Undocumented 3.
INT 21,62 - Get PSP address (DOS 3.
INT 21,63 - Get Lead Byte Table (MSDOS 2.
INT 21,63 - Get Lead Byte Table (Asian DOS 3.
INT 21,64 - Set Device Driver Look Ahead (Undocumented)

INT 21,65 - Get Extended Country Information (DOS 3.
INT 21,66 - Get/Set Global Code Page (DOS 3.
INT 21,67 - Set Handle Count (DOS 3.

INT 21,68 - Flush Buffer Using Handle
INT 21,69 - Get/Set Disk Serial Number (Undocumented DOS 4+)
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INT 21,6C - Extended Open/Create (DOS 4.

INT 21,F8 - Set OEM Int 21 Handler (functions F9-FF, Undocumented)
INT 22 - Program Terminate
INT 23 - Control-Break Exit Address

INT 24 - Critical Error Handler
INT 25 - Absolute Disk Read
Control Block Format (DOS 4.

INT 26 - Absolute Disk Write
Control Block Format (DOS 4.
INT 27 - Terminate and Stay Resident
INT 28 - DOS Idle Loop / Scheduler (Undocumented)

INT 29 - DOS Fast Character I/O (Undocumented 2.
INT 2A - DOS Network Critical Section and NETBIOS

INT 2A,0 - Network Installation Query
INT 2A,1 - Execute NETBIOS Request With No Error Retry

INT 2A,3 - Check if Direct I/O Allowed
INT 2A,4 - Execute NETBIOS Request
INT 2A,5 - Get Network Resource Information

INT 2A,6 - Network Print Stream Control
INT 2A,80 - Begin DOS Critical Section
INT 2A,81 - End DOS Critical Section

INT 2A,82 - End DOS Critical Sections 0 thru 7
INT 2A,84 - Keyboard Busy Loop
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INT 2A,87 - Critical Section

INT 2E - Execute Command Using Base Level Command Interpreter (Undocumented DOS 2.
INT 2F - DOS Multiplex Interrupt
INT 2F,0 - DOS Multiplex Interrupt - Get Installed State
INT 2F,1 - Multiplex Interrupt - Submit file

INT 2F,2 - Multiplex Interrupt - Cancel file
INT 2F,3 - Multiplex Interrupt - Cancel all files
INT 2F,4 - Multiplex Interrupt - Pause / return status

INT 2F,5 - Multiplex Interrupt - End of Status
INT 2F,6 - PRINT.
INT 2F,8 - DRIVER.
INT 2F,2E - Setup Error Code Translation Tables (undoc.
INT 2F,80 - PRINT.
INT 33 - Mouse Function Calls
Mouse functions can be broken down into the following classes:

INT 33,0 - Mouse Reset/Get Mouse Installed Flag
INT 33,1 - Show Mouse Cursor
INT 33,2 - Hide Mouse Cursor
INT 33,3 - Get Mouse Position and Button Status

INT 33,4 - Set Mouse Cursor Position
INT 33,5 - Get Mouse Button Press Information

INT 33,6 - Get Mouse Button Release Information
INT 33,7 - Set Mouse Horizontal Min/Max Position
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INT 33,8 - Set Mouse Vertical Min/Max Position

INT 33,9 - Set Mouse Graphics Cursor
INT 33,A - Set Mouse Text Cursor
INT 33,B - Read Mouse Motion Counters
INT 33,C - Set Mouse User Defined Subroutine and Input Mask
INT 33,D - Mouse Light Pen Emulation On
INT 33,E - Mouse Light Pen Emulation Off

INT 33,F - Set Mouse Mickey Pixel Ratio
INT 33,10 - Mouse Conditional OFF
INT 33,13 - Set Mouse Double Speed Threshold

INT 33,14 - Swap Interrupt Subroutines
INT 33,15 - Get Mouse Driver State and Memory Requirements

INT 33,16 - Save Mouse Driver State
INT 33,17 - Restore Mouse Driver State
INT 33,18 - Set alternate subroutine call mask and address
INT 33,19 - Get User Alternate Interrupt Address

INT 33,1A - Set Mouse Sensitivity
INT 33,1B - Get Mouse Sensitivity
INT 33,1C - Set Mouse Interrupt Rate (InPort only)

INT 33,1D - Set Mouse CRT Page
INT 33,1E - Get Mouse CRT Page

INT 33,1F - Disable Mouse Driver
INT 33,20 - Enable Mouse Driver
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INT 33,21 - Reset Mouse Software

INT 33,22 - Set Language for Messages
INT 33,23 - Get Language Number
INT 33,24 - Get Driver Version, Mouse Type & IRQ Number
INT 4A - RTC Alarm Handler Vector
INT 67 - Expanded Memory Specification
INT 67,40 - Get EMM Status (LIM EMS 3.
INT 67,41 - Get Page Frame Base Address (LIM EMS 3.

INT 67,42 - Get Page Counts (LIM EMS 3.
INT 67,43 - Get Handle and Allocate Pages (LIM EMS 3.
INT 67,44 - Map Logical Page Into Physical Page Window (LIM EMS)
INT 67,45 - Release Handle and Memory Pages (LIM EMS)
INT 67,46 - Get EMM Version (LIM EMS)
INT 67,47 - Save Page Map Context (LIM EMS 3.
INT 67,48 - Restore Page Map Context (LIM EMS 3.

INT 67,49 - Get I/O Port Addresses (LIM EMS 3.
INT 67,4A - Get Logical to Physical Page Mapping (LIM EMS 3.
INT 67,4B - Get Handle Count (LIM EMS)

INT 67,4C - Get Page Count for Handle
INT 67,4D - Get Page Count for All Handles (LIM EMS)
INT 67,4E - Get/Set Page Map Context (LIM EMS 3.

INT 67,4F - Get/Set Partial Page Map (LIM EMS 4.
INT 67,50 - Map/Unmap Multiple Handle Pages (LIM EMS 4.
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INT 67,51 - Reallocate Pages (LIM EMS 4.

INT 67,52 - Get/Set Handle Attributes
INT 67,53 Get/Set Handle Name
INT 67,54 - Get Handle Directory (LIM EMS 4.
INT 67,55 - Alter Page Map and Jump (LIM EMS 4.

INT 67,56 - Alter Page Map and Call (LIM EMS 4.
INT 67,57 - Move/Exchange Memory Region (LIM EMS 4.
INT 67,58 - Get Mappable Physical Address Array (LIM EMS 4.
INT 67,59 - Get Expanded Memory Hardware Information (LIM EMS 4.
INT 67,5A - Allocate Standard/Raw Pages (LIM EMS 4.

INT 67,5B - Alternate Map Register Set (LIM EMS 4.
INT 67,5C - Prepare Expanded Memory for Warm Boot (LIM EMS 4.
INT 67,5D - Enable/Disable OS Functions (LIM EMS 4.

INT 67,60 - LIM EMS Get Physical Window Array
INT 70 - Real Time Clock Interrupt (XT 286,AT,PS/2)
SERIAL DATA TRANSFER SCHEMES

Serial Communications
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Serial transmission is often preferred over parallel transmission, even though it has a lower
transfer rate, due to its simplicity, low cost and ease of use. Many peripherals also do not require
the high data rates of a parallel interface.
Baud rate
The number of changes/symbols transmitted, per second. When there are only two states, this is
equal to the Bit rate.
Bit rate
The number of bits transferred per second.

Data rate
The rate at which meaningful information is sent - the bit rate less the overhead of start and stop
bits.
Asynchronous Serial Data Transmission
The asynchronous serial interface is so called because the transmitted and received data are not
synchronised over any extended period of time and therefore no special means of synchronising
the clocks at the transmitter and receiver is necessary. The fundamental problem lies in how to
split the data stream into individual bits and how to then reconstruct the original data. The format
of the data on a serial data link is in fact simple, and is shown in Figure below. Data is grouped
and transferred in characters, where one character is a unit comprising 7 or 8 bits of information
plus 2 to 4 control bits. The idle state is referred to as the mark level and traditionally
corresponds to a logical 1 level. A character is transmitted by placing the line in the space
level (logical 0) for one period T, then the information is sent bit by bit, with each bit T seconds
long, then the transmitter calculates the parity bit and transmits it and finally one or two stop bits
are sent by returning the line to mark level.
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Format of Asynchronous Serial Data
The data word length may be 7 or 8 bits with odd, even, or no parity bits plus either 1 or 2 stop
bits. This allows for 12 different possible formats for serial transmission. Also, there are at least
7 different commonly used values for the bit period T. Thus, connecting two devices via a serial
link may be difficult due to all the available options.
At the receiving end, the receiver monitors the link, looking for the start bit, and once detected,
the receiver waits until the end of the start bit and then samples the next N bits at their centres
using a locally generated clock. Once the character has been assembled from the received bits,
the parity is checked, and if the calculated parity does not agree with the received parity bit, a
parity error flag is set to indicate a transmission error. The most critical aspect is the receiver
timing. The falling edge of the start bit triggers the receiver's local clock, which samples each
incoming bit at its nominal centre. Suppose the receiver clock waits T/2 seconds from the falling
edge of a start bit and samples the incoming data every T seconds thereafter until the stop bit has
been sampled. Let us assume that the receiver clock is running slow, so that a sample is taken
every T+dt seconds. The first bit of the data is thus sampled at (T+dt)/2 + (T+dt) seconds after
the falling edge of the start bit. The stop bit is thus sampled at time (T+dt)/2 + N(T+dt), where N
is the number of bits in the character following the start bit. The total accumulated error in
sampling is thus (T+dt)/2 + N(T+dt) - (T/2+NT), or (2N+1)dt/2 seconds. This situation is shown
in Figure below.
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Effect of Unsynchronised Transmitter and Receiver Clocks
For correct operation, the stop bit is sampled within T/2 seconds of its centre.
Thus, if N=9 for a 7-bit character with one stop bit and one parity bit, the maximum permissible
error is 100/19 = 5%. Fortunately, today's clocks are all crystal controlled and the error between
two clocks of the same frequency is often less than a fraction of a percent.
The most obvious disadvantage of asynchronous serial transfer is the need for start, stop and
parity bits for each transmitted character. If 7-bit characters are used, the overall efficiency is
only 7/(7+3) = 70%. Another problem is when asynchronous transfer is used to, for example,
dump binary data onto a storage device: If the data is arranged in 8-bit bytes and all 256 values
represent valid binary data it is difficult to embed control characters (e.g. tape start or stop)
within the data stream because the same character must be used both for pure data and control
purposes.
Synchronous Serial Data Transmission
The type of asynchronous serial data link described in previous sections is widely used to link
processors to relatively slow peripherals such as printers and terminals. Where information must
be transferred, for example, between individual computers in a network, synchronous serial data
transmission is more popular. In synchronous serial data transmission, the information is
transmitted continuously without gaps between adjacent groups of bits. Note that synchronous
data links are often used to transmit entire blocks of data instead of ASCII-encoded characters.
As this type of link involves long streams of data, the clocks at the receiving and transmitting
end must be permanently synchronised. Of course, one could simply add a clock line to the link
where the transmitter's clock signal is passed to the receiver. However, this requires an additional
line and is thus an unpopular choice. A better solution is to encode the data in such a way that the
synchronising signal is included in the data signal. The figure below shows one of the many
methods which may be used. In this case the data is phase-encoded (or Manchester encoded) by
combining the clock signal with the data signal. A logical one is thus represented by a positive
transition in the centre of the bit and a logical zero by a negative transition. At the receiver, the
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data signal may easily be split into the clock and pure data components. Integrated circuits that
perform this modulation and demodulation are readily available.
A Phase-Encoded Synchronous Serial Bit Stream
Having divided the incoming data stream into individual data elements (i.e. bits), the next step is
to group the bits into meaningful units. The incoming data must be examined for recognisable bit
groups which signify the beginning of a block of data, the end of it or some other control
character.
Parity
There may well be noise on a communications line, and it is helpful to have some check that the
correct information has arrived. One common test is Parity. Send a parity bit set so that the
number of 1 bits sent (data + parity) is odd.
Parity is normally taken as odd, because a single pulse on the line, taken as a start bit, records as
a bad byte.
The parity check will detect one erroneous bit in each byte. There are more serious methods of
encoding data that can send messages down noisy lines, and recover from erroneous bits.
A Universal Asynchronous Receiver Transmitter (UART)

Serial information is normally transmitted and received by a Universal Asynchronous Receiver
Transmitter (UART). The programming interface for a UART usually has four registers:
Transmit control - baud rate, parity, send now
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Transmit data - the byte to be sent
Receive control - byte available, parity check,
Receive data
8251 (USART)
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The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication. As a peripheral device of a microcomputer system, the 8251 receives
parallel data from the CPU and transmits serial data after conversion. This device also receives
serial data from the outside and transmits parallel data to the CPU after conversion.
Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver

Transmitter)
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The 8251 functional configuration is programmed by software. Operation between the 8251 and
a CPU is executed by program control. Table 1 shows the operation between a CPU and the
device.
Table 1 Operation between a CPU and 8251
Control Words
There are two types of control word.
1. Mode instruction (setting of function)

2. Command (setting of operation)
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait
for write" at either internal reset or external reset. That is, the writing of a control word after
resetting will be recognized as a "mode instruction."
Items set by mode instruction are as follows:
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)

Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)

Number of synchronous characters (Synchronous mode)
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The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous
mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a
function will be set because the writing of sync characters constitutes part of mode instruction.
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2) Command
Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters.
Items to be set by command are as follows:
Transmit Enable/Disable
Receive Enable/Disable
DTR, RTS Output of data.
Resetting of error flag.

Sending to break characters
Internal resetting
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Hunt mode (synchronous mode)
Status Word
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It is possible to see the internal status of the 8251 by reading a status word. The bit configuration
of status word is shown in Fig. 5.
Pin Description
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the CPU and
sends status words and received data to CPU.
RESET (Input terminal)
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A "High" on this input forces the 8251 into "reset status." The device waits for the writing of
"mode instruction." The min. reset width is six clock inputs during the operating status of CLK.
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is independent of RXC or
TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at
Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data and
control words from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data and status
words from the 8251.
C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words and status
words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high,
command word or status word will be accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the CPU
accesses. Note: The device wont be in "standby status"; only setting CS = High.
TXD (output terminal)
This is an output terminal for transmitting data from which serial-converted data is sent out. The
device is in "mark status" (high level) after resetting or during a status when transmit is disabled.
It is also possible to set the device in "break status" (low level) by a command.
TXRDY (output terminal)
This is an output terminal which indicates that the 8251is ready to accept a transmitted data
character. But the terminal is always at low level if CTS = high or the device was set in "TX
disable status" by a command. Note: TXRDY status word indicates that transmit data character is
receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be
reset by the leading edge or WR signal.
TXEMPTY (Output terminal)
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This is an output terminal which indicates that the 8251 has transmitted all the characters and had
no data character. In "synchronous mode," the terminal is at high level, if transmit data
characters are no longer remaining and sync characters are automatically transmitted. If the CPU
writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the
transmitter is disabled by setting CTS "High" or command, data written before disable will be
sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that
data is not sent out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to
Timing Chart of Transmitter Control and Flag Timing)
TXC (Input terminal)
This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous
mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64
the TXC. The falling edge of TXC sifts the serial data out of the 8251.
RXD (input terminal)
This is a terminal which receives serial data.

RXRDY (Output terminal)
This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the
CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the
CPU reads a data character before the next one is received completely, the preceding data will be
lost. In such a case, an overrun error flag status word will be set.
RXC (Input terminal)
This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous
mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the
RXC.
SYNDET/BD (Input or output terminal)
This is a terminal whose function changes according to mode. In "internal synchronous mode."
this terminal is at high level, if sync characters are received and synchronized. If a status word is
read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A
"High" on this input forces the 8251 to start receiving data characters.
In "asynchronous mode," this is an output terminal which generates "high level"output upon the
detection of a "break" character if receiver data contains a "low-level" space between the stop
bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset
is active, the terminal will be output at low level.
DSR (Input terminal)
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This is an input port for MODEM interface. The input status of the terminal can be recognized
by the CPU reading status words.
DTR (Output terminal)
This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.
CTS (Input terminal)
This is an input terminal for MODEM interface which is used for controlling a transmit circuit.
The terminal controls data transmission if the device is set in "TX Enable" status by a command.
Data is transmitable if the terminal is at low level.
RTS (Output terminal)
This is an output port for MODEM interface. It is possible to set the status RTS by a command.
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Line Receiver (MC1489)
The *MC1489 (aka 75189) is used as a level translator to invert the positive logic
signals from the UART into NRZi to be transmitted. The data signal from the UART (pin
25) is input on pin 1 of the MC1489 and the output comes from pin 3 of the MC1489. This
output is sent, via an RS-232 cable, to the Receive Data line of the computer (pin 3 of DTE).
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It would have been more appropriate to use the MC1488, Line Driver, since it is the chip
that is typically used to perform the function of TTL-to-RS232 conversion. I couldn't find
this chip in the lab's supply cabinet, so the MC1489 was used, which still inverts the input
and provides an output that can drive a short RS232 cable.
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Introduction to high speed serial communication standards and USB

The Electronics Industries Association (EIA) standard RS-232-C as of 1969 defines:
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Electrical signal characteristics such as voltage levels, signaling rate, timing and slewrate of signals, voltage withstand level, short-circuit behavior, and maximum load
capacitance.
Interface mechanical characteristics, pluggable connectors and pin identification.
Functions of each circuit in the interface connector.
Standard subsets of interface circuits for selected telecom applications.
The standard does not define such elements as
character encoding (for example, ASCII, Baudot code or EBCDIC)

the framing of characters in the data stream (bits per character, start/stop bits, parity)
protocols for error detection or algorithms for data compression
bit rates for transmission, although the standard says it is intended for bit rates lower than
20,000 bits per second. Many modern devices support speeds of 115,200 bit/s and above
power supply to external devices.
Details of character format and transmission bit rate are controlled by the serial port hardware,
often a single integrated circuit called a UART that converts data from parallel to asynchronous
start-stop serial form. Details of voltage levels, slew rate, and short-circuit behavior are typically
controlled by a line-driver that converts from the UART's logic levels to RS-232 compatible
signal levels, and a receiver that converts from RS-232 compatible signal levels to the UART's
logic levels
Limitations of the standard
Because the application of RS-232 has extended far beyond the original purpose of
interconnecting a terminal with a modem, successor standards have been developed to address
the limitations. Issues with the RS-232 standard include:
The large voltage swings and requirement for positive and negative supplies increases
power consumption of the interface and complicates power supply design. The voltage
swing requirement also limits the upper speed of a compatible interface.
Single-ended signaling referred to a common signal ground limits the noise immunity and
transmission distance.
Multi-drop connection among more than two devices is not defined. While multi-drop
"work-arounds" have been devised, they have limitations in speed and compatibility.
Asymmetrical definitions of the two ends of the link make the assignment of the role of a
newly developed device problematic; the designer must decide on either a DTE-like or
DCE-like interface and which connector pin assignments to use.
The handshaking and control lines of the interface are intended for the setup and
takedown of a dial-up communication circuit; in particular, the use of handshake lines for
flow control is not reliably implemented in many devices.
No method is specified for sending power to a device. While a small amount of current
can be extracted from the DTR and RTS lines, this is only suitable for low power devices
such as mice.
While the standard recommends a 25-way connector and its pinout, the connector is large
by current standards
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Standard details
In RS-232, user data is sent as a time-series of bits. Both synchronous and asynchronous
transmissions are supported by the standard. In addition to the data circuits, the standard defines
a number of control circuits used to manage the connection between the DTE and DCE. Each
data or control circuit only operates in one direction, that is, signaling from a DTE to the
attached DCE or the reverse. Since transmit data and receive data are separate circuits, the
interface can operate in a full duplex manner, supporting concurrent data flow in both directions.
The standard does not define character framing within the data stream, or character encoding.
Voltage levels
Diagrammatic oscilloscope trace of voltage levels for an uppercase ASCII "K" character (0x4b)
with 1 start bit, 8 data bits, 1 stop bit
The RS-232 standard defines the voltage levels that correspond to logical one and logical zero
levels. Valid signals are plus or minus 3 to 15 volts. The range near zero volts is not a valid RS232 level; logic one is defined as a negative voltage, the signal condition is called marking, and
has the functional significance of OFF. Logic zero is positive, the signal condition is spacing,
and has the function ON. The standard specifies a maximum open-circuit voltage of 25 volts;
signal levels of 5 V,10 V,12 V, and 15 V are all commonly seen depending on the power
supplies available within a device. RS-232 drivers and receivers must be able to withstand
indefinite short circuit to ground or to any voltage level up to 25 volts. The slew rate, or how
fast the signal changes between levels, is also controlled.
Because the voltage levels are higher than logic levels typically used by integrated circuits,
special intervening driver circuits are required to translate logic levels. These also protect the
device's internal circuitry from short circuits or transients that may appear on the RS-232
interface, and provide sufficient current to comply with the slew rate requirements for data
transmission.
Because both ends of the RS-232 circuit depend on the ground pin being zero volts, problems
will occur when connecting machinery and computers where the voltage between the ground pin
on one end, and the ground pin on the other is not zero. This may also cause a hazardous ground
loop.
Unused interface signals terminated to ground will have an undefined logic state. Where it is
necessary to permanently set a control signal to a defined state, it must be connected to a voltage
source that asserts the logic 1 or logic 0 level. Some devices provide test voltages on their
interface connectors for this purpose.
Connectors
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RS-232 devices may be classified as Data Terminal Equipment (DTE) or Data Communications
Equipment (DCE); this defines at each device which wires will be sending and receiving each
signal. The standard recommended but did not make mandatory the D-subminiature 25 pin
connector. In general and according to the standard, terminals and computers have male
connectors with DTE pin functions, and modems have female connectors with DCE pin
functions. Other devices may have any combination of connector gender and pin definitions.
Many terminals were manufactured with female terminals but were sold with a cable with male
connectors at each end; the terminal with its cable satisfied the recommendations in the standard.
Presence of a 25 pin D-sub connector does not necessarily indicate an RS-232-C compliant
interface. For example, on the original IBM PC, a male D-sub was an RS-232-C DTE port (with
a non-standard current loop interface on reserved pins), but the female D-sub connector was used
for a parallel Centronics printer port. Some personal computers put non-standard voltages or
signals on some pins of their serial ports.
The standard specifies 20 different signal connections. Since most devices use only a few
signals, smaller connectors can often be used. For example, the 9 pin DE-9 connector was used
by most IBM-compatible PCs since the IBM PC AT, and has been standardized as TIA-574.
More recently, modular connectors have been used. Most common are 8P8C connectors.
Standard EIA/TIA 561 specifies a pin assignment, but the "Yost Serial Device Wiring Standard"
invented by Dave Yost (and popularized by the Unix System Administration Handbook) is
common on Unix computers and newer devices from Cisco Systems. Many devices don't use
either of these standards. 10P10C connectors can be found on some devices as well. Digital
Equipment Corporation defined their own DECconnect connection system which was based on
the Modified Modular Jack connector. This is a 6 pin modular jack where the key is offset from
the center position. As with the Yost standard, DECconnect uses a symmetrical pin layout which
enables the direct connection between two DTEs. Another common connector is the DH10
header connector common on motherboards and add-in cards which is usually converted via a
cable to the more standard 9 pin DE-9 connector (and frequently mounted on a free slot plate or
other part of the housing).
Pinouts
The following table lists commonly-used RS-232 signals and pin assignments.
Signal
Name
Origin
Abbrevation DTE DCE
DB-25
DE-9
EIA/TIA 561 Yost
(TIA-574)
Common Ground
Protective Ground
PG
Transmitted Data
TxD
Received Data
RxD
20
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4,5
Data Terminal Ready DTR
Data Set Ready
DSR
Request To Send
RTS
Clear To Send
CTS
Carrier Detect
DCD
Ring Indicator
RI
22
The signals are named from the standpoint of the DTE. The ground signal is a common return for
the other connections; it appears on two pins in the Yost standard but is the same signal. The
DB-25 connector includes a second "protective ground" on pin 1. Connecting this to pin 7 (signal
reference ground) is a common practice but not recommended.
Use of a common ground is one weakness of RS-232: if the two devices are far enough apart or
on separate power systems, the ground will degrade between them and communications will fail,
which is a difficult condition to trace.
Note that EIA/TIA 561 combines DSR and RI[5][6], and the Yost standard combines DSR and
DCD.
Signals
Commonly-used signals are:
Transmitted Data (TxD)

Data sent from DTE to DCE.
Received Data (RxD)
Data sent from DCE to DTE.
Request To Send (RTS)
Asserted (set to logic 0, positive voltage) by DTE to prepare DCE to receive data. This
may require action on the part of the DCE, e.g. transmitting a carrier or reversing the
direction of a half-duplex channel. For the modern usage of "RTS/CTS handshaking," see
the section of that name.
Ready To Receive (RTR)
Asserted by DTE to indicate to DCE that DTE is ready to receive data. If in use, this
signal appears on the pin that would otherwise be used for Request To Send, and the
DCE assumes that RTS is always asserted; see RTS/CTS handshaking for details.
Clear To Send (CTS)
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Asserted by DCE to acknowledge RTS and allow DTE to transmit. This signaling was
originally used with half-duplex modems and by slave terminals on multidrop lines: The
DTE would raise RTS to indicate that it had data to send, and the modem would raise
CTS to indicate that transmission was possible. For the modern usage of "RTS/CTS
handshaking," see the section of that name.
Data Terminal Ready (DTR)
Asserted by DTE to indicate that it is ready to be connected. If the DCE is a modem, this
may "wake up" the modem, bringing it out of a power saving mode. This behaviour is
seen quite often in modern PSTN and GSM modems. When this signal is de-asserted, the
modem may return to its standby mode, immediately hanging up any calls in progress.
Data Set Ready (DSR)
Asserted by DCE to indicate the DCE is powered on and is ready to receive commands or
data for transmission from the DTE. For example, if the DCE is a modem, DSR is
asserted as soon as the modem is ready to receive dialing or other commands; DSR is not
dependent on the connection to the remote DCE (see Data Carrier Detect for that
function). If the DCE is not a modem (e.g. a null modem cable or other equipment), this
signal should be permanently asserted (set to 0), possibly by a jumper to another signal.
Data Carrier Detect (DCD)
Asserted by DCE when a connection has been established with remote equipment.
Ring Indicator (RI)
Asserted by DCE when it detects a ring signal from the telephone line.
Cables
The standard does not define a maximum cable length but instead defines the maximum
capacitance that a compliant drive circuit must tolerate. A widely-used rule-of-thumb indicates
that cables more than 50 feet (15 metres) long will have too much capacitance, unless special
cables are used. By using low-capacitance cables, full speed communication can be maintained
over larger distances up to about 1,000 feet.[7] For longer distances, other signal standards are
better suited to maintain high speed.
Since the standard definitions are not always correctly applied, it is often necessary to consult
documentation, test connections with a breakout box, or use trial and error to find a cable that
works when interconnecting two devices. Connecting a fully-standard-compliant DCE device
and DTE device would use a cable that connects identical pin numbers in each connector (a socalled "straight cable"). "Gender changers" are available to solve gender mismatches between
cables and connectors. Connecting devices with different types of connectors requires a cable
that connects the corresponding pins according to the table above. Cables with 9 pins on one end
and 25 on the other are common. Manufacturers of equipment with 8P8C connectors usually
provide a cable with either a DB-25 or DE-9 connector (or sometimes interchangeable
connectors so they can work with multiple devices). Poor-quality cables can cause false signals
by crosstalk between data and control lines (such as Ring Indicator).
Conventions
For functional communication through a serial port interface, conventions of bit rate, character
framing, communications protocol, character encoding, data compression, and error detection,
not defined in RS 232, must be agreed to by both sending and receiving equipment. For example,
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consider the serial ports of the original IBM PC. This implementation used an 8250 UART using
asynchronous start-stop character formatting with 7 or 8 data bits per frame, usually ASCII
character coding, and data rates programmable between 75 bits per second and 115,200 bits per
second. Data rates above 20,000 bits per second are out of the scope of the standard, although
higher data rates are sometimes used by commercially manufactured equipment. In the particular
case of the IBM PC, baud rates were programmable with arbitrary values, so that a PC could be
connected to, for example, MIDI music controllers (31,250 bits per second) or other devices not
using the rates typically used with modems. Since most devices do not have automatic baud rate
detection, users must manually set the baud rate (and all other parameters) at both ends of the
RS-232 connection.
RTS/CTS handshaking
In older versions of the specification, RS-232's use of the RTS and CTS lines is asymmetric: The
DTE asserts RTS to indicate a desire to transmit to the DCE, and the DCE asserts CTS in
response to grant permission. This allows for half-duplex modems that disable their transmitters
when not required, and must transmit a synchronization preamble to the receiver when they are
re-enabled. This scheme is also employed on present-day RS-232 to RS-485 converters, where
the RS-232's RTS signal is used to ask the converter to take control of the RS-485 bus - a
concept that doesn't otherwise exist in RS-232. There is no way for the DTE to indicate that it is
unable to accept data from the DCE.
A non-standard symmetric alternative, commonly called "RTS/CTS handshaking," was
developed by various equipment manufacturers: CTS indicates permission from the DCE for the
DTE to send data to the DCE (and is controlled by the DCE independent of RTS), and RTS
indicates permission from the DTE for the DCE to send data to the DTE. This was eventually
codified in version RS-232-E (actually TIA-232-E by that time) by defining a new signal, "RTR
(Ready to Receive)," which is CCITT V.24 circuit 133. TIA-232-E and the corresponding
international standards were updated to show that circuit 133, when implemented, shares the
same pin as RTS (Request to Send), and that when 133 is in use, RTS is assumed by the DCE to
be ON at all times.[8]
Thus, with this alternative usage, one can think of RTS asserted (logic 0) meaning that the DTE
is indicating it is "ready to receive" from the DCE, rather than requesting permission from the
DCE to send characters to the DCE.
3-wire and 5-wire RS-232
A minimal "3-wire" RS-232 connection consisting only of transmit data, receive data, and
ground, is commonly used when the full facilities of RS-232 are not required. Even a two-wire
connection (data and ground) can be used if the data flow is one way (for example, a digital
postal scale that periodically sends a weight reading, or a GPS receiver that periodically sends
position, if no configuration via RS-232 is necessary). When only hardware flow control is
required in addition to two-way data, the RTS and CTS lines are added in a 5-wire version.
Seldom used features
The EIA-232 standard specifies connections for several features that are not used in most
implementations. Their use requires the 25-pin connectors and cables, and of course both the
DTE and DCE must support them.
Signal rate selection
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The DTE or DCE can specify use of a "high" or "low" signaling rate. The rates as well as which
device will select the rate must be configured in both the DTE and DCE. The prearranged device
selects the high rate by setting pin 23 to ON.
Loopback testing
Many DCE devices have a loopback capability used for testing. When enabled, signals are
echoed back to the sender rather than being sent on to the receiver. If supported, the DTE can
signal the local DCE (the one it is connected to) to enter loopback mode by setting pin 18 to ON,
or the remote DCE (the one the local DCE is connected to) to enter loopback mode by setting pin
21 to ON. The latter tests the communications link as well as both DCE's. When the DCE is in
test mode it signals the DTE by setting pin 25 to ON.
A commonly used version of loopback testing doesn't involve any special capability of either
end. A hardware loopback is simply a wire connecting complementary pins together in the same
connector (see loopback).
Loopback testing is often performed with a specialized DTE called a Bit Error Rate Tester (see
Bit Error Rate Test).
Timing signals
Some synchronous devices provide a clock signal to synchronize data transmission, especially at
higher data rates. Two timing signals are provided by the DCE on pins 15 and 17. Pin 15 is the
transmitter clock, or send timing (ST); the DTE puts the next bit on the data line (pin 2) when
this clock transitions from OFF to ON (so it is stable during the ON to OFF transition when the
DCE registers the bit). Pin 17 is the receiver clock, or receive timing (RT); the DTE reads the
next bit from the data line (pin 3) when this clock transitions from ON to OFF.
Alternatively, the DTE can provide a clock signal, called transmitter timing (TT), on pin 24 for
transmitted data. Again, data is changed when the clock transitions from OFF to ON and read
during the ON to OFF transition. TT can be used to overcome the issue where ST must traverse a
cable of unknown length and delay, clock a bit out of the DTE after another unknown delay, and
return it to the DCE over the same unknown cable delay. Since the relation between the
transmitted bit and TT can be fixed in the DTE design, and since both signals traverse the same
cable length, using TT eliminates the issue. TT may be generated by looping ST back with an
appropriate phase change to align it with the transmitted data. ST loop back to TT lets the DTE
use the DCE as the frequency reference, and correct the clock to data timing.
Secondary channel
Data can be sent over a secondary channel (when implemented by the DTE and DCE devices),
which is equivalent to the primary channel. Pin assignments are described in following table:
Signal
7 (same as primary)
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Common Ground
Pin
Secondary Transmitted Data (STD) 14

Secondary Received Data (SRD)
16
Secondary Request To Send (SRTS) 19

Secondary Clear To Send (SCTS)
13
Secondary Carrier Detect (SDCD)
12
Related standards
Other serial signaling standards may not interoperate with standard-compliant RS-232 ports. For
example, using the TTL levels of near +5 and 0 V puts the mark level in the undefined area of
the standard. Such levels are sometimes used with NMEA 0183-compliant GPS receivers and
depth finders.
A 20 mA current loop uses the absence of 20 mA current for high, and the presence of current in
the loop for low; this signaling method is often used for long-distance and optically isolated
links. Connection of a current-loop device to a compliant RS-232 port requires a level translator.
Current-loop devices can supply voltages in excess of the withstand voltage limits of a compliant
device. The original IBM PC serial port card implemented a 20 mA current-loop interface, which
was never emulated by other suppliers of plug-compatible equipment.
Other serial interfaces similar to RS-232:
RS-422 (a high-speed system similar to RS-232 but with differential signaling)

RS-423 (a high-speed system similar to RS-422 but with unbalanced signaling)
RS-449 (a functional and mechanical interface that used RS-422 and RS-423 signals - it
never caught on like RS-232 and was withdrawn by the EIA)
RS-485 (a descendant of RS-422 that can be used as a bus in multidrop configurations)
MIL-STD-188 (a system like RS-232 but with better impedance and rise time control)
EIA-530 (a high-speed system using RS-422 or RS-423 electrical properties in an EIA232 pinout configuration, thus combining the best of both; supersedes RS-449)
TIA-574 (standardizes the 9-pin D-subminiature connector pinout for use with EIA-232
electrical signalling, as originated on the IBM PC/AT)
SpaceWire (high-speed serial system designed for use on board spacecraft)
Programs on serial communication using USART

Instruction sequence for 8251 initialisation:
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MOV DX,0FFF2H ;point at command register address

MOV AL,00H ;send 0s to guarantee device is
OUT DX,AL
;in command register format
MOV CX,2
;before the reset command is issued
D0:LOOP D0
;and delay after sending
OUT DX,AL
;each command instruction
MOV CX,2
D1:LOOP D1
OUT DX,AL
MOV CX,2
D1:LOOP D1
MOV AL,40H
OUT DX,AL
MOV CX,2
D3:LOOP D3
;sent internal reset command to

;return device to idle state
;load delay constant
;and delay
MOV AL,11001110B ;load mode control word and

OUT DX,AL
;send it
// MODE WORD //
MOV CX,2
D4:LOOP D4
;and delay
MOV AL,00110111B ;load command word and send it

OUT DX,AL
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// COMMAND WORD//
Instruction sequence for transmitting data:
MOV DX,OFFF2H ;point at control register

TEST2:IN AL DX
;read status
AND AL,10000001B ;and check status of data set ready and transmit ready
CMP AL,10000001B ;Is it ready
JNE TEST1
;continue to poll if not ready
MOV DX,0FFF0H ;otherwise point at data address
MOV AL,DATA_TO_SEND ;load data to send
OUT DX,AL
;and send it
Instruction sequence for receiving data:
MOV DX,0FFF2H
TEST2:IN AL,DX
AND AL,00000001B
JZ TEST2
MOV DX,0FFF2H
IN AL,DX
;point at control register

;
;and check status of RxRdy
;continue to poll if not ready
;otherwise point at data
;address and get data
ARITHMETIC INSTRUCTIONS
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ADDITION INSTRUCTIONS:
ADD
ADC
INC
AAA
DAA
SUBTRACTION INSTRUCTIONS:
SUB
SBB
DEC
NEG
CMP
AAS
DAS
MULTIPLICATION INSTRUCTIONS:
MUL
IMUL
AAM
DIVISION INSTRUCTIONS:
DIV
IDIV
AAD
CBW
CWD
G.Vjaya Santhi,Asst.Prof
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ADD Instruction - These instructions add a number from source to a number from some
destination and put the result in the specified destination. The add with carry instruction ADC,
also add the status of the carry flag into the result. The source and destination must be of same
type , means they must be a byte location or a word location.If you want to add a byte to a word,
you must copy the byte to a word location and fill the upper byte of the word with zeroes before
adding.
ADC Instruction - Add with carry.
EXAMPLE:
ADD AL,74H
ADC CL,BL
ADD DX, BX
ADD DX, [SI]
ADD CL, BL
ADD CL, BL
;Add immediate number 74H to

; content of AL
;Add contents of BL plus
;carry status to contents of CL.
;Results in CL
;Add contents of BX to contents
;of DX
;Add word from memory at
;offset [SI] in DS to contents of DX
; Addition of Un Signed numbers
;CL = 01110011 =115 decimal
;+ BL = 01001111 = 79 decimal
;Result in CL = 11000010 = 194 decimal
; Addition of Signed numbers
;CL = 01110011 = + 115 decimal
;+ BL = 01001111 = +79 decimal
;Result in CL = 11000010 = - 62 decimal
; Incorrect because result is too large to fit in 7 bits.
INC Instruction - INC instruction adds one to the operand and sets the flag according to the
result. INC instruction is treated as an unsigned binary number.
Example:
; AX = 7FFFh
INC AX
;After this instruction AX = 8000h
INC BL
; Add 1 to the contents of BL register
INC CL
; Add 1 to the contents of CX register.
AAA Instruction - AAA converts the result of the addition of two valid unpacked BCD digits
to a valid 2-digit BCD number and takes the AL register as its implicit operand. Two operands of
the addition must have its lower 4 bits contain a number in the range from 0-9.The AAA
instruction then adjust AL so that it contains a correct BCD digit. If the addition produce carry
(AF=1), the AH register is incremented and the carry CF and auxiliary carry AF flags are set to
1. If the addition did not produce a decimal carry, CF and AF are cleared to 0 and AH is not
altered. In both cases the higher 4 bits of AL are cleared to 0.AAA will adjust the result of the
two ASCII characters that were in the range from 30h (0) to 39h(9).This is because the
lower 4 bits of those character fall in the range of 0-9.The result of addition is not a ASCII
character but it is a BCD digit.
Example:
;Clear AH for MSD
;BCD 6 in AL
;Add BCD 5 to digit in AL
;AH=1, AL=1 representing BCD 11.
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MOV AH,0
MOV AL,6
ADD AL,5
AAA
DAA Instruction - Decimal Adjust Accumulator

DAA :If lower nibble of AL > 9 or AF = 1 then:AL = AL + 6 and AF = 1
If AL > 9Fh or CF = 1 then: AL = AL + 60h and CF = 1
Example:
MOV AL, 0Fh
; AL = 0Fh (15)
DAA
; AL = 15h
SUB Instruction - Subtract destination from source: SBB destination, source

SBB Instruction - SUBB instruction subtracts op2 from op1, then subtracts 1
from op1 is CF flag is set and result is stored in op1 and it is used to set the flag.
Example:
SUB CX, BX
SUBB CH, AL
;CX BX . Result in CX
; Subtract contents of AL and
;contents CF from contents of CH .
;Result in CH
SUBB AX, 3427H ;Subtract immediate number
;from AX
Example:
Subtracting unsigned number
; CL = 10011100 = 156 decimal
; BH = 00110111 = 55 decimal
SUB CL, BH
; CL = 01100101 = 101 decimal
; CF, AF, SF, ZF = 0, OF, PF = 1
Subtracting signed number
; CL = 00101110 = + 46 decimal
; BH = 01001010= + 74 decimal
SUB CL, BH ;CL = 11100100 = - 28 decimal
;CF = 1, AF, ZF =0,
;SF = 1 result negative
DEC Instruction - Decrement destination register or memory :DEC destination.

Example:
DEC AX
;decrements the content in AX by one
NEG Instruction - NEG performs the twos complement subtraction of the operand from zero
and sets the flags according to the result.
;AX = 2CBh
NEG AX
;after executing NEG result AX =FD35h.
Example:
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NEG AL
;Replace number in AL with its 2s complement
NEG BX
;Replace word in BX with its 2s complement
NEG BYTE PTR[BX]
; Replace byte at offset BX in
; DS with its 2s complement
CMP Instruction-Compares two operands result is not stored anywhere, flags are set (OF, SF,
ZF, AF, PF, CF) according to result.
Example:
MOV AL, 5
MOV BL, 5
CMP AL, BL
; AL = 5, ZF = 1 (so equal!)
AAS Instruction - AAS converts the result of the subtraction of two valid unpacked BCD digits
to a single valid BCD number and takes the AL register as an implicit operand. The two
operands of the subtraction must have its lower 4 bit contain number in the range from 0 to 9
.The AAS instruction then adjust AL so that it contain a correct BCD digit.
MOV AX,0901H
;BCD 91
SUB AL, 9
;Minus 9
AAS
; Give AX =0802 h (BCD 82)
(a)
;AL =0011 1001 =ASCII 9
;BL=0011 0101 =ASCII 5
SUB AL, BL
;(9 - 5) Result :
;AL = 00000100 = BCD 04,CF = 0
AAS
;Result :
;AL=00000100 =BCD 04
;CF = 0 NO Borrow required
(b)
;AL = 0011 0101 =ASCII 5
;BL = 0011 1001 = ASCII 9
SUB AL, BL
;( 5 - 9 ) Result :
;AL = 1111 1100 = - 4
; in 2s complement CF = 1
AAS
;Results :
;AL = 0000 0100 =BCD 04
;CF = 1 borrow needed
MUL Instruction - This instruction multiplies an unsigned multiplication of the accumulator by

the operand specified by op. The size of op may be a register or memory operand .
MUL op
;AL = 21h (33 decimal)

;BL = A1h(161 decimal )
MUL BL
;AX =14C1h (5313 decimal) since AH0,
;CF and OF will set to 1.
MUL BH
; AL times BH, result in AX
MUL CX
;AX times CX, result high word in DX,
;low word in AX.
IMUL Instruction - This instruction performs a signed multiplication.
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Example:
;In this form the accumulator is the multiplicand and op is

IMUL op
the multiplier. op may be a register or a memory operand.
IMUL op1, op2 ;In this form op1 is always be a register operand and op2
may be a register or a memory operand.
Example:
IMUL BH
;Signed byte in AL times multiplied by
;signed byte in BH and result in AX .
Example:
; 69 * 14
; AL = 01000101 = 69 decimal
; BL = 00001110 = 14 decimal
IMUL BL
;AX = 03C6H = + 966 decimal
;MSB = 0 because positive result
; - 28 * 59
; AL = 11100100 = - 28 decimal
;BL = 00001110 = 14 decimal
IMUL BL
;AX = F98Ch = - 1652 decimal
; MSB = 1 because negative result
AAM Instruction - AAM converts the result of the multiplication of two valid unpacked BCD
digits into a valid 2-digit unpacked BCD number and takes AX as an implicit operand.
To give a valid result the digits that have been multiplied must be in the range of 0 9 and the
result should have been placed in the AX register. Because both operands of multiply are
required to be 9 or less, the result must be less than 81 and thus is completely contained in AL.
AAM unpacks the result by dividing AX by 10, placing the quotient (MSD) in AH and the
remainder (LSD) in AL.
Example:
MOV AL, 5
MOV BL, 7
MUL BL
;Multiply AL by BL , result in AX
AAM
;After AAM, AX =0305h (BCD 35)
DIV Instruction - Unsigned divide-Div source
DIV Instruction-When a double word is divided by a word, the most significant word of
the double word must be in DX and the least significant word of the double word must be
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in AX. After the division AX will contain the 16 bit result (quotient ) and DX will contain a 16
bit remainder. Again , if an attempt is made to divide by zero or quotient is too large to fit in AX
( greater than FFFFH ) the 8086 will do a type of 0 interrupt .
Example:
DIV CX
; (Quotient) AX= (DX:AX)/CX
: (Reminder) DX=(DX:AX)%CX
For DIV the dividend must always be in AX or DX and AX, but
the source of the divisor can be a register or a memory location specified by one of the 24
addressing modes.
If you want to divide a byte by a byte, you must first put the dividend byte in AL and fill AH
with all 0s . The SUB AH,AH instruction is a quick way to do.
If you want to divide a word by a word, put the dividend word in AX and fill DX with all 0s.
The SUB DX,DX instruction does this quickly.
Example:
; AX = 37D7H = 14, 295 decimal
; BH = 97H = 151 decimal
DIV BH ;AX / BH
; AX = Quotient = 5EH = 94 decimal
; AH = Remainder = 65H = 101 decimal
IDIV Instruction - Divide by signed byte or word IDIV source

IDIV Instruction - This instruction is used to divide a signed word by a signed byte or to divide
a signed double word by a signed word.
Example:
IDIV BL
;Signed word in AX is divided by signed byte in BL
AAD Instruction - ADD converts unpacked BCD digits in the AH and AL

register into a single binary number in the AX register in preparation for a division
operation.
Before executing AAD, place the Most significant BCD digit in the AH register and Last
significant in the AL register. When AAD is executed, the two BCD digits are combined into a
single binary number by setting AL=(AH*10)+AL and clearing AH to 0.
Example:
MOV AX,0205h
;The unpacked BCD number 25
AAD
;After AAD , AH=0 and
;AL=19h (25)
After the division AL will then contain the unpacked BCD quotient and AH will contain the
unpacked BCD remainder.
Example:
;AX=0607 unpacked BCD for 67 decimal
;CH=09H
AAD
;Adjust to binary before division
;AX=0043 = 43H =67 decimal
DIV CH
;Divide AX by unpacked BCD in CH
;AL = quotient = 07 unpacked BCD
;AH = remainder = 04 unpacked BCD
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CBW Instruction - CBW converts the signed value in the AL register into an equivalent 16 bit
signed value in the AX register by duplicating the sign bit to the left. This instruction copies the
sign of a byte in AL to all the bits in AH. AH is then said to be the sign extension of AL.
Example:
; AX = 00000000 10011011 = - 155 decimal
CBW
; Convert signed byte in AL to signed word in AX.
; Result in AX = 11111111 10011011
; = - 155 decimal
into an equivalent 32 bit signed value in DX: AX register pair by duplicating the sign bit
to the left. The CWD instruction sets all the bits in the DX register to the same sign bit of the AX
register. The effect is to create a 32- bit signed result that has same integer value as the original
16 bit operand.
Example:
Assume AX contains C435h. If the CWD instruction is executed, DX
will contain FFFFh since bit 15 (MSB) of AX was 1. Both the original value of AX
(C435h) and resulting value of DX : AX (FFFFC435h) represents the same signed
number.
Example:
;DX = 00000000 00000000
;AX = 11110000 11000111 = - 3897 decimal
CWD
;Convert signed word in AX to signed double
;word in DX:AX
;Result DX = 11111111 11111111
;AX = 11110000 11000111 = -3897 decimal .
BIT MANIPULATION INSTRUCTIONS
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LOGICAL INSTRUCTIONS:
NOT
AND
OR
XOR
TEST
SHIFT INSTRUCTIONS:
SHL / SAL
SHR
SAR
ROTATE INSTRUCTIONS:
ROL
ROR
RCL
RCR
NOT Instruction - NOT perform the bitwise complement of op and stores the result back into
op.
NOT op
Example :
NOT BX
;Complement contents of BX register.
;DX =F038h
NOT DX
;after the instruction DX = 0FC7h
AND Instruction - This Performs a bitwise Logical AND of two operands. The result of the
operation is stored in the op1 and used to set the flags.
AND op1, op2
To perform a bitwise AND of the two operands, each bit of the result is set to 1 if and only if the
corresponding bit in both of the operands is 1, otherwise the bit in the result I cleared to 0 .
Example:
AND BH, CL
;AND byte in CL with byte in BH
;result in BH
AND BX,00FFh
;AND word in BX with immediate
;00FFH. Mask upper byte, leave
;lower unchanged
AND CX,[SI]
; AND word at offset [SI] in data
;segment with word in CX
;register . Result in CX register .
;BX = 10110011 01011110
AND BX,00FFh
;Mask out upper 8 bits of BX
;Result BX = 00000000 01011110

;CF =0 , OF = 0, PF = 0, SF = 0 ,
;ZF = 0
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OR Instruction - OR instruction perform the bit wise logical OR of two operands .Each bit of
the result is cleared to 0 if and only if both corresponding bits in each operand are 0, other wise
the bit in the result is set to 1.
OR op1, op2
Examples :
OR AH, CL
;CL ORed with AH, result in AH.
;CX = 00111110 10100101
OR CX,FF00h
;OR CX with immediate FF00h
;result in CX = 11111111 10100101
;Upper byte are all 1s lower bytes
;are unchanged.
XOR Instruction - XOR performs a bit wise logical XOR of the operands specified by op1 and
op2. The result of the operand is stored in op1 and is used to set the flag.
XOR op1, op2
Example : ( Numerical )
; BX = 00111101 01101001
;CX = 00000000 11111111
XOR BX, CX
;Exclusive OR CX with BX
;Result BX = 00111101 10010110
TEST Instruction - This instruction ANDs the contents of a source byte or word with the
contents of specified destination word. Flags are updated but neither operand is changed . TEST
instruction is often used to set flags before a condition jump instruction
Examples:
TEST AL, BH
;AND BH with AL. no result is
;stored . Update PF, SF, ZF
TEST CX, 0001H ;AND CX with immediate
;number
;no result is stored, Update PF,
;SF
Example :
;AL = 01010001
TEST Al, 80H
;AND immediate 80H with AL to
;test f MSB of AL is 1 or 0
;ZF = 1 if MSB of AL = 0
;AL = 01010001 (unchanged)
;PF = 0 , SF = 0
;ZF = 1 because ANDing produced is 00
SAR Instruction - SAR instruction shifts the bits in the operand specified by op1 towards right
by count specified in op2.As bit is shifted out a copy of old MSB is taken in MSB .MSB position
and LSB is shifted to CF.
Example:
SAR op1, op2

(1)
SAR AL, 1
; AL = 00011101 = +29 decimal, CF = 0

;Shift signed byte in AL towards right
;( divide by 2 )
;AL = 00001110 = + 14 decimal, CF = 1
(2)
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;BH = 11110011 = - 13 decimal, CF = 1

;Shifted signed byte in BH to right
;BH = 11111001 = - 7 decimal, CF = 1
SAR BH, 1
SHR Instruction - SHR instruction shifts the bits in op1 to right by the number of times
specified by op2 .
Example:
(1)
SHR BP, 1
; Shift word in BP by 1 bit position to right
; and 0 is kept to MSB
(2)
MOV CL, 03H
;Load desired number of shifts into CL
SHR BYTE PYR[BX] ;Shift bytes in DS at offset BX and
;rotate 3 bits to right and keep 3 0s in MSB
(3)
;SI = 10010011 10101101 , CF = 0
SHR SI, 1
; Result: SI = 01001001 11010110
; CF = 1, OF = 1, SF = 0, ZF = 0
SAL / SHL Instruction - SAL instruction shifts the bits in the operand specified by op1 to its
left by the count specified in op2. As a bit is shifted out of LSB position a 0 is kept in LSB
position. CF will contain MSB bit.
SAL op1,op2
Example:
;CF = 0, BX = 11100101 11010011
SAL BX, 1
;Shift BX register contents by 1 bit
;position towards left
;CF = 1, BX = 11001011 1010011
RCL Instruction - RCL instruction rotates the bits in the operand specified by op1 towards left
by the count specified in op2.The operation is circular, the MSB of operand is rotated into a
carry flag and the bit in the CF is rotated around into the LSB of operand.
RCR op1, op2
Example:
CLC
;put 0 in CF
RCL AX, 1
;save higher-order bit of AX in CF
RCL DX, 1
;save higher-order bit of DX in CF
ADC AX, 0
; set lower order bit if needed.
Example :
;Word in DX of 1 bit is moved to left, and
RCL DX, 1
RCL BH, 1
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MOV CL, 2
RCL AX, CL
;MSB of word is given to CF and

;CF to LSB.
; CF=0, BH = 10110011
;Result : BH =01100110
;CF = 1, OF = 1 because MSB changed
;CF =1,AX =00011111 10101001
;Load CL for rotating 2 bit position
;Result: CF =0, OF undefined
;AX = 01111110 10100110
RCR Instruction - RCR instruction rotates the bits in the operand specified by op1 towards
right by the count specified in op2. RCR op1, op2
Example: ( 1)
RCR BX, 1
;Word in BX is rotated by 1 bit towards

;right and CF will contain MSB bit and
;LSB contain CF bit .
( 2)
RCR BL, 1
;CF = 1, BL = 00111000
;Result: BL = 10011100, CF =0
;OF = 1 because MSB is changed to 1.
ROL Instruction - ROL instruction rotates the bits in the operand specified by op1 towards left
by the count specified in op2. ROL moves each bit in the operand to next higher bit position. The
higher order bit is moved to lower order position. Last bit rotated is copied into carry flag.
ROL op1, op2
Example: ( 1 )
ROL AX, 1
;Word in AX is moved to left by 1 bit
;and MSB bit is to LSB, and CF
;CF =0 ,BH =10101110
ROL BH, 1
;Result: CF ,Of =1 , BH = 01011101
Example : ( 2 )
;BX = 01011100 11010011
;CL = 8 bits to rotate
ROL BH, CL
;Rotate BX 8 bits towards left
;CF =0, BX =11010011 01011100
ROR Instruction - ROR instruction rotates the bits in the operand op1 towards right by count
specified in op2. The last bit rotated is copied into CF.
ROR op1, op2
Example:
(1)
ROR BL, 1
;Rotate all bits in BL towards right by 1
;bit position, LSB bit is moved to MSB
;and CF has last rotated bit.
(2)
ROR BX, 1
;CF =0, BX = 00111011 01110101

;Rotate all bits of BX of 1 bit position
;towards right and CF =1,
BX = 10011101 10111010
Example ( 3 )
;CF = 0, AL = 10110011,
; Load CL
;Rotate all bits of AL towards right
;by 4 bits, CF = 0 ,AL = 00111011
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MOV CL, 04H

ROR AL, CL
STRING INSTRUCTIONS
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REP
REPE / REPZ
REPNE / REPNZ
MOVS / MOVSB / MOVSW
COMPS / COMPSB / COMPSW
SCAS / SCASB / SCASW
LODS / LODSB / LODSW
STOS / STOSB / STOSW
REP/REPE/REPZ/REPNE/REPNZ - (Prefix) Repeat String instruction until specified

condition exist
REP- repeats the string instructions until CX=0.
REPE/REPZ- Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1
(result is Equal), maximum CX times.
REPNE/REPNZ- Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF
= 0 (result is Equal), maximum CX times.
MOVS / MOVSB / MOVSW- Copy byte at DS:[SI] to ES:[DI]. Update SI and DI.
ES:[DI] = DS:[SI]
if DF = 0 then
o
o
SI = SI + 1or 2
DI = DI + 1 or 2
else
o
o
SI = SI 1 or 2
DI = DI 1 or 2
Example:
LEA SI, a1
LEA DI, a2
MOV CX, 5
REP MOVSB
COMPS / COMPSB / COMPSWSI = SI 1 or 2

DI = DI 1 0r 2
DS:[SI] - ES:[DI]
SCAS / SCASB / SCASW-Compare words: AX /AL from ES:[DI].

ES:[DI] AX/AL
If DF=0 DI+ 1 or 2 else DI 2 or 1
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LODS / LODSB / LODSW- Load word or byte at DS:[SI] into AX/AL. Update SI
AX = DS:[SI]
if DF = 0 then
o SI = SI + 2 or 1
else
SI = SI 2 or 1
STOS / STOSB / STOSW - Store word or byte in AX/AL into ES:[DI]. Update DI
ES:[DI] = AX
if DF = 0 then
o DI = DI + 2 or 1
else
DI = DI 2 or 1
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PROGRAM EXECUTION TRANSFER INSTRUCTIONS

UNCONDITIONAL TRANSFER INSTRUCTIONS:
CALL
RET
JMP
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CONDITIONAL TRANSFER INSTRUCTIONS:

JA / JNBE
JAE / JNB
JB / JNAE
JBE / JNA
JC
JE / JZ
JG / JNLE
JGE / JNL
JL / JNGE
JLE / JNG
JNC
JNE / JNZ
JNO
JNP / JPO
JNS
JO JP / JPE
JS
ITERATION CONTROL INSTRUCTIONS:
LOOP
LOOPE / LOOPZ
LOOPNE / LOOPNZ
JCXZ
INTERRUPT INSTRUCTIONS:
INT
INTO
IRET
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CALL Instruction - This Instruction is used to transfer execution to a

subprogram or procedure. There are two basic types of CALL s : Near and Far.
A Near CALL is a call to a procedure which is in the same code segment as the CALL
instruction .
When 8086 executes the near CALL instruction it decrements the stack pointer by two and
copies the offset of the next instruction after the CALL on the stack. This offset saved on the
stack is referred as the return address, because this is the address that execution will returns to
after the procedure executes. A near CALL instruction will also load the instruction pointer with
the offset of the first instruction in the procedure.
A RET instruction at the end of the procedure will return execution to the instruction after the
CALL by coping the offset saved on the stack back to IP.
A Far CALL is a call to a procedure which is in a different from that which contains the CALL
instruction . When 8086 executes the Far CALL instruction it decrements the stack pointer by
two again and copies the content of CS register to the stack. It then decrements the stack pointer
by two again and copies the offset contents offset of the instruction after the CALL to the stack.
Finally it loads CS with segment base of the segment which contains the procedure and IP with
the offset of the first instruction of the procedure in segment. A RET instruction at end of
procedure will return to the next instruction after the CALL by restoring the saved CS and IP
from the stack.
;Direct within-segment ( near or intrasegment )
CALL MULTO ;MULTO is the name of the procedure.
The assembler determines displacement of MULTO from the instruction after the CALL
and codes this displacement in as part of the instruction .
;Indirect within-segment ( near or intrasegment )
CALL BX ; BX contains the offset of the first instruction of the procedure .Replaces
contents of word of IP with contents of register BX.
CALL WORD PTR[BX] ;Offset of first instruction of procedure is in two memory
addresses in DS .Replaces contents of IP with contents of word memory location in DS
pointed to by BX.
;Direct to another segment- far or intersegment.
CALL SMART ;SMART is the name of the Procedure

SMART PROC FAR ; Procedure must be declare as an far
RET Instruction Return execution from procedure to calling program.
JMP Instruction - Unconditional jump to - specified destination

Unconditional Jump. Transfers control to another part of the program. 4-byte address may be
entered in this form: 1234h:5678h, first value is a segment second value is an offset
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JA / JNBE - This instruction performs the Jump if above (or) Jump if not below or equal
operations according to the condition, if CF and ZF = 0 .
Example: ( 1 )
CMP AX, 4371H
;Compare by subtracting 4371H
;from AX
JA RUN_PRESS
;Jump to label RUN_PRESS if
;AX above 4371H
(2)
CMP AX, 4371H
;Compare ( AX 4371H)
JNBE RUN_PRESS ;Jump to label RUN_PRESS if
;AX not below or equal to 4371H
JAE / JNB / JNC - This instructions performs the Jump if above or equal,Jump if not below,
Jump if no carry operations according to the condition, if CF = 0.
Examples:
1. CMP AX, 4371H ;Compare ( AX 4371H)
JAE RUN
;Jump to the label RUN if AX is
;above or equal to 4371H .
2. CMP AX, 4371H ;Compare ( AX 4371H)
JNB RUN_1
;Jump to the label RUN_1 if AX
;is not below than 4371H
3. ADD AL, BL
; Add AL, BL. If result is with in JNC OK
;acceptable range, continue
JB/JC/JNAE Instruction - This instruction performs the Jump if below (or) Jump if carry (or)
Jump if not below/ equal operations according to the condition,if CF = 1
Example:
1.CMP AX, 4371H ;Compare ( AX 4371H )
JB RUN_P
;Jump to label RUN_P if AX is
;below 4371H
2.ADD BX, CX
;Add two words and Jump to
JC ERROR
; label ERROR if CF = 1
JBE/JNA Instruction - This instruction performs the Jump if below orequal (or) Jump if not
above operations according to the condition, if CF and ZF = 1
Example:
CMP AX, 4371H
;Compare ( AX 4371H )
JBA RUN
;Jump to label RUN if AX is
;below or equal to 4371H
CMP AX, 4371H
;Compare ( AX 4371H )
JNA RUN_R
;Jump to label RUN_R if AX is
;not above than 4371H
JE/JZ Instruction Instruction - This instruction performs the Jump if equal (or) Jump if zero
operations according to the condition if ZF = 1
Example:
NXT:CMP BX, DX
;Compare ( BX DX )
;Jump to DONE if BX = DX,

;Else subtract Ax
;Increment counter
;Check again
;Copy count to AX
;read data from port 8FH
;Subtract minimum value
; Jump to label if result of
;subtraction was 0
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JE DONE
SUB BX, AX
INC CX
JUMP NXT
DONE: MOV AX, CX
Example:
IN AL, 8FH
SUB AL, 30H
JZ STATR
JG/JNLE Instruction - This instruction performs the Jump if greater (or) Jump if not less than
or equal operations according to the condition if ZF =0 and SF = OF
Example:
CMP BL, 39H
;Compare by subtracting
;39H from BL
JG NEXT1
;Jump to label if BL is
;more positive than 39H
CMP BL, 39H
;39H from BL
JNLE NEXT2
;Jump to label if BL is not
;less than or equal 39H
JGE/JNL Instruction - This instruction performs the Jump if greater than or equal / Jump if
not less than operation according to the condition if SF = OF
Example:
;Compare by the
CMP BL, 39H
;subtracting 39H from BL
JGE NEXT11
;Jump to label if BL is
;more positive than 39H
; or equal to 39H
CMP BL, 39H
;39H from BL
JNL NEXT22
;Jump to label if BL is not
;less than 39H
JL/JNGE Instruction - This instruction performs the Jump if less than /Jump if not greater than
or equal operation according to the condition, if SF OF
Example:
CMP BL, 39H
;from BL
JL AGAIN
;Jump to the label if BL is more
;negative than 39H
CMP BL, 39H
;from BL
JNGE AGAIN1
; Jump to the label if BL is not
;more positive than 39H or
;not equal to 39H
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JLE/JNG Instruction - This instruction performs the Jump if less than or equal / Jump if not
greater operation according to the condition, if ZF=1 and SF OF
Example:
CMP BL, 39h
; Compare by subtracting 39h
;from BL
JLE NXT1
;Jump to the label if BL is more
;negative than 39h or equal to 39h
CMP BL, 39h
;Compare by subtracting 39h
;from BL
JNG AGAIN2
; Jump to the label if BL is not
;more positive than 39h
JNE/JNZ Instruction - This instruction performs the Jump if not equal / Jump if not zero
operation according to the condition, if ZF=0
Example:
NXT: IN AL, 0F8H
;Read data value from port
CMP AL, 72
;Compare ( AL 72 )
JNE NXT
;Jump to NXT if AL 72
IN AL, 0F9H
;Read next port when AL = 72
MOV BX, 2734H
; Load BX as counter
NXT_1:ADD AX, 0002H ;Add count factor to AX
DEC BX
;Decrement BX
JNZ NXT_1
; Repeat until BX = 0
JNO Instruction This instruction performs the Jump if no overflow operation according to
the condition, if OF=0
Example:
ADD AL, BL
; Add signed bytes in AL and BL
JNO DONE
;Process done if no overflow MOV AL, 00H
;Else load error code in AL
DONE: OUT 24H, AL
; Send result to display
JNP/JPO Instruction This instruction performs the Jump if not parity /Jump if parity odd
operation according to the condition, if PF=0
Example:
IN AL, 0F8H
;Read ASCII char from UART
OR AL, AL
;Set flags
JPO ERROR1
;If even parity executed, if not
;send error message
JNS Instruction - This instruction performs the Jump if not signed (Jump if positive) operation
according to the condition, if SF=0
Example:
;Decrement counter
DEC AL
JNS REDO
; Jump to label REDO if counter has not
;decremented to FFH
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JO Instruction - This instruction performs Jump if overflow operation according to the

condition OF = 0
Example:
ADD AL, BL
;Add signed bits in AL and BL
JO ERROR
; Jump to label if overflow occur
;in addition
MOV SUM, AL
; else put the result in memory
;location named SUM
JPE/JP Instruction - Jump if parity even/ Jump if parity
JPE/JP Instruction - This instruction performs the Jump if parity even / Jump if parity
operation according to the condition, if PF=1
Example:
IN AL, 0F8H
;Read ASCII char from UART
OR AL, AL ;Set flags
JPE ERROR2
;odd parity is expected, if not
;send error message
JS Instruction - This instruction performs the Jump if sign operation according to the
condition, if SF=1
Example:
ADD BL, DH
;Add signed bytes DH to BL
JS JJS_S1
;Jump to label if result is
;negative
LOOP Instruction - Loop to specified label until CX = 0

LOOPE /LOOPZ Instruction - loop while CX 0 and ZF = 1
LOOPNE /LOOPNZ Instruction - loop while CX 0 and ZF = 0
JCXZ Instruction - This instruction performs the Jump if CX register is zero.
If CX does not contain all zeros, execution will simply proceed to the next instruction.
Example:
JCXZ SKIP_LOOP ;If CX = 0, skip the process
NXT: SUB [BX], 07H
;Subtract 7 from data value
INC BX
; BX point to next value
LOOP NXT
; Loop until CX = 0
SKIP_LOOP
;Next instruction
INT Instruction - Interrupt program
INTO Instruction - Interrupt on overflow.
IRET Instruction - Interrupt return
PROCESS CONTROL INSTRUCTIONS
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FLAG SET / CLEAR INSTRUCTIONS:

STC
CLC
CMC
STD
CLD
STI
CLI
EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS:

HLT
WAIT
ESC
LOCK
NOP
STD Instruction - Set the direction flag to 1
STI Instruction - Set interrupt flag ( IF)
STC Instruction - Set the carry flag to 1
CLC Instruction - Clear the carry flag
CLD Instruction - Clear direction flag
CLI Instruction - Clear interrupt flag
CMC Instruction - Complement the carry flag
HALT Instruction - The HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only way to get the processor out of the halt
state are with an interrupt signal on the INTR pin or an interrupt signal on NMI pin or a reset
signal on the RESET input.
WAIT Instruction - When this WAIT instruction executes, the 8086 enters an idle condition.
This will stay in this state until a signal is asserted on TEST input pin or a valid interrupt signal
is received on the INTR or NMI pin.
FSTSW STATUS ; copy 8087 status word to memory
FWAIT
; wait for 8087 to finish before; doing next 8086 instruction
MOV AX, STATUS ;copy status word to AX to
;check bits
In this code we are adding up of FWAIT instruction so that it will stop the execution of
the command until the above instruction is finishes its work .so that you are not loosing
data and after that you will allow to continue the execution of instructions.
ESC Instruction - Escape instruction is used to pass instruction to a coprocessor such as the
8087 math coprocessor which shares the address and data bus with an 8086. Instruction for the
coprocessor are represented by a 6 bit code embedded in the escape instruction. As the 8086
fetches instruction byte, the coprocessor also catches these bytes from data bus and puts them in
its queue. The coprocessor treats all of the 8086 instruction as an NOP. When 8086 fetches an
ESC instruction , the coprocessor decodes the instruction and carries out the action specified by
the 6 bit code. In most of the case 8086 treats ESC instruction as an NOP.
LOCK Instruction - Assert bus lock signal
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NOP Instruction - This instruction simply uses up the three clock cycles and increments the
instruction pointer to point to the next instruction. NOP does not change the status of any flag.
The NOP instruction is used to increase the delay of a delay loop.
Introduction
It was electricity in the beginning....The people were happy because they did not know that it
was all around them and could be utilized. That was good. Then Faraday came and a stone has
started to roll slowly...
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The first machines using a new sort of energy appeared soon. A long time has passed since then
and just when the people finally got used to them and stopped paying attention to what a new
generation of specialists were doing, someone came to an idea that electrons could be a very
convenient toy being closed in a glass pipe. It was just a good idea at first, but there was no
return. Electronics was born and the stone kept on rolling down the hill faster and faster...
A new science - new specialists. Blue coats were replaced with white ones and people who knew
something about electronics appeared on the stage. While the rest of humanity were passively
watching in disbelief what was going on, the plotters split in two groups - software-oriented
and hardware-oriented. Somewhat younger than their teachers, very enthusiastic and full of
ideas, both of them kept on working but separate ways. While the first group was developing
constantly and gradually, the hardware-oriented people, driven by success, threw caution to the
wind and invented transistors.
Up till that moment, the things could be more or less kept under control, but a broad publicity
was not aware of what was going on, which soon led to a fatal mistake! Being naive in belief that
cheap tricks could slow down technology development and development of the world and
retrieve the good all days, mass market opened its doors for the products of Electronics Industry,
thus closing a magic circle. A rapid drop in prices made these components available for a great
variety of people. The stone was falling freely...
The first integrated circuits and processors appeared soon, which caused computers and other
products of electronics to drop down in price even more. They could be bought everywhere.
Another circle was closed! Ordinary people got hold of computers and computer era has begun...
While this drama was going on, hobbyists and professionals, also split in two groups and
protected by anonymity, were working hard on their projects. Then, someone suddenly put a
question: Why should not we make a universal component? A cheap, universal integrated circuit
that could be programmed and used in any field of electronics, device or wherever needed?
Technology has been developed enough as well as the market. Why not? So it happened, body
and spirit were united and the first integrated circuit was designed and called the
MICROCONTROLLER.
What are microcontrollers and what are they used for?
Like all good things, this powerful component is basically very simple. It is made by mixing
tested and high- quality "ingredients" (components) as per following receipt:
1.
The simplest computer processor is used as the "brain" of the future system.
2.
Depending on the taste of the manufacturer, a bit of memory, a few A/D converters,
timers, input/output lines etc. are added
All that is placed in some of the standard packages.
A simple software able to control it all and which everyone can easily learn about has
been developed.
3.
4.
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On the basis of these rules, numerous types of microcontrollers were designed and they quickly
became man's invisible companion. Their incredible simplicity and flexibility conquered us a
long time ago and if you try to invent something about them, you should know that you are
probably late, someone before you has either done it or at least has tried to do it.
The following things have had a crucial influence on development and success of the
microcontrollers:
Powerful and carefully chosen electronics embedded in the microcontrollers can

independently or via input/output devices (switches, push buttons, sensors, LCD displays, relays
etc.), control various processes and devices such as industrial automation, electric current,
temperature, engine performance etc.
Very low prices enable them to be embedded in such devices in which, until recent time
it was not worthwhile to embed anything. Thanks to that, the world is overwhelmed today with
cheap automatic devices and various smart appliences.
Prior knowledge is hardly needed for programming. It is sufficient to have a PC (software
in use is not demanding at all and is easy to learn) and a simple device (called the programmer)
used for loading raedy-to-use programs into the microcontroller.
So, if you are infected with a virus called electronics, there is nothing left for you to do but to
learn how to use and control its power.
How does the microcontroller operate?
Even though there is a large number of different types of microcontrollers and even more
programs created for their use only, all of them have many things in common. Thus, if you learn
to handle one of them you will be able to handle them all. A typical scenario on the basis of
which it all functions is as follows:
1.
Power supply is turned off and everything is stillthe program is loaded into the
microcontroller, nothing indicates what is about to come
2.
Power supply is turned on and everything starts to happen at high speed! The control
logic unit keeps everything under control. It disables all other circuits except quartz crystal to
operate. While the preparations are in progress, the first milliseconds go by.
3.
Power supply voltage reaches its maximum and oscillator frequency becomes stable.
SFRs are being filled with bits reflecting the state of all circuits within the microcontroller. All
pins are configured as inputs. The overall electronics starts operation in rhythm with pulse
sequence. From now on the time is measured in micro and nanoseconds.
4.
Program Counter is set to zero. Instruction from that address is sent to instruction decoder
which recognizes it, after which it is executed with immediate effect.
The value of the Program Counter is incremented by 1 and the whole process is
repeated...several million times per second.
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5.
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Architecture 0f 8051
What is what in the microcontroller?
As you can see, all the operations within the microcontroller are performed at high speed and
quite simply, but the microcontroller itself would not be so useful if there are not special circuits
which make it complete. In continuation, we are going to call your attention to them.
Read Only Memory (ROM)
Read Only Memory (ROM) is a type of memory used to permanently save the program being
executed. The size of the program that can be written depends on the size of this memory. ROM
can be built in the microcontroller or added as an external chip, which depends on the type of the
microcontroller. Both options have some disadvantages. If ROM is added as an external chip, the
microcontroller is cheaper and the program can be considerably longer. At the same time, a
number of available pins is reduced as the microcontroller uses its own input/output ports for
connection to the chip. The internal ROM is usually smaller and more expensive, but leaves
more pins available for connecting to peripheral environment. The size of ROM ranges from
512B to 64KB.
Random Access Memory (RAM)
Random Access Memory (RAM) is a type of memory used for temporary storing data and
intermediate results created and used during the operation of the microcontrollers. The content of
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this memory is cleared once the power supply is off. For example, if the program performes an
addition, it is necessary to have a register standing for what in everyday life is called the sum .
For that purpose, one of the registers in RAM is called the "sum" and used for storing results of
addition. The size of RAM goes up to a few KBs.
Electrically Erasable Programmable ROM (EEPROM)
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The EEPROM is a special type of memory not contained in all microcontrollers. Its contents may
be changed during program execution (similar to RAM ), but remains permanently saved even
after the loss of power (similar to ROM). It is often used to store values, created and used during
operation (such as calibration values, codes, values to count up to etc.), which must be saved
after turning the power supply off. A disadvantage of this memory is that the process of
programming is relatively slow. It is measured in miliseconds.
Special Function Registers (SFR)
Special function registers are part of RAM memory. Their purpose is predefined by the
manufacturer and cannot be changed therefore. Since their bits are physically connected to
particular circuits within the microcontroller, such as A/D converter, serial communication
module etc., any change of their state directly affects the operation of the microcontroller or
some of the circuits. For example, writing zero or one to the SFR controlling an input/output port
causes the appropriate port pin to be configured as input or output. In other words, each bit of
this register controls the function of one single pin.

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Program Counter
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Program Counter is an engine running the program and points to the memory address containing
the next instruction to execute. After each instruction execution, the value of the counter is
incremented by 1. For this reason, the program executes only one instruction at a time just as it is
written. Howeverthe value of the program counter can be changed at any moment, which
causes a jump to a new memory location. This is how subroutines and branch instructions are
executed. After jumping, the counter resumes even and monotonous automatic counting +1, +1,
+1
Central Processor Unit (CPU)
As its name suggests, this is a unit which monitors and controls all processes within the
microcontroller and the user cannot affect its work. It consists of several smaller subunits, of
which the most important are:
Instruction decoder is a part of the electronics which recognizes program instructions

and runs other circuits on the basis of that. The abilities of this circuit are expressed in the
"instruction set" which is different for each microcontroller family.
Arithmetical Logical Unit (ALU) performs all mathematical and logical operations upon
data.
Accumulator is an SFR closely related to the operation of ALU. It is a kind of working
desk used for storing all data upon which some operations should be executed (addition, shift
etc.). It also stores the results ready for use in further processing. One of the SFRs, called the
Status Register, is closely related to the accumulator, showing at any given time the "status" of a
number stored in the accumulator (the number is greater or less than zero etc.).
Input/output ports (I/O Ports)
In order to make the microcontroller useful, it is necessary to connect it to peripheral devices.

Each microcontroller has one or more registers (called a port) connected to the microcontroller
pins.

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Why do we call them input/output ports? Because it is possible to change a pin function
according to the user's needs. These registers are the only registers in the microcontroller the
state of which can be checked by voltmeter!
Oscillator
Even pulses generated by the oscillator enable harmonic and synchronous operation of all
circuits within the microcontroller. It is usually configured as to use quartz-crystal or ceramics
resonator for frequency stabilization. It can also operate without elements for frequency
stabilization (like RC oscillator). It is important to say that program instructions are not executed
at the rate imposed by the oscillator itself, but several times slower. It happens because each
instruction is executed in several steps. For some microcontrollers, the same number of cycles is
needed to execute any instruction, while it's different for other microcontrollers. Accordingly, if
the system uses quartz crystal with a frequency of 20MHz, the execution time of an instruction is
not expected 50nS, but 200, 400 or even 800 nS, depending on the type of the microcontroller!

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Timers/Counters
Most programs use these miniature electronic "stopwatches" in their operation. These are
commonly 8- or 16-bit SFRs the contents of which is automatically incremented by each coming
pulse. Once the register is completely loaded, an interrupt is generated!
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If these registers use an internal quartz oscillator as a clock source, then it is possible to measure
the time between two events (if the register value is T1 at the moment measurement has started,
and T2 at the moment it has finished, then the elapsed time is equal to the result of subtraction
T2-T1 ). If the registers use pulses coming from external source, then such a timer is turned into
a counter.
This is only a simple explanation of the operation itself. Its somehow more complicated in
practice.

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Power Supply Circuit
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There are two things worth attention concerning the microcontroller power supply circuit:
Brown out is a potentially dangerous state which occurs at the moment the microcontroller is
being turned off or when power supply voltage drops to the lowest level due to electric noise. As
the microcontroller consists of several circuits which have different operating voltage levels, this
can cause its out of control performance. In order to prevent it, the microcontroller usually has a
circuit for brown out reset built-in. This circuit immediately resets the whole electronics when
the voltage level drops below the lower limit.
Reset pin is usually referred to as Master Clear Reset (MCLR) and serves for external reset of
the microcontroller by applying logic zero (0) or one (1) depending on the type of the
microcontroller. In case the brown out is not built in the microcontroller, a simple external circuit
for brown out reset can be connected to this pin.
Serial communication

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Parallel connections between the microcontroller and peripherals established over I/O ports are
the ideal solution for shorter distances up to several meters. However, in other cases, when it is
necessary to establish communication between two devices on longer distances it is obviously
not possible to use parallel connections. Then, serial communication is the best solution.
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Today, most microcontrollers have several different systems for serial communication built in as
a standard equipment. Which of them will be used depends on many factors of which the most
important are:

How many devices the microcontroller has to exchange data with?

How fast the data exchange has to be?
What is the distance between devices?
Is it necessary to send and receive data simultaneously?
One of the most important things concerning serial communication is the Protocol which should
be strictly observed. It is a set of rules which must be applied in order that devices can correctly
interpret data they mutually exchange. Fortunately, the microcontrollers automatically take care
of this, so the work of the programmer/user is reduced to a simple write (data to be sent) and read
(received data).

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Pin configuration of 8051
Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.
Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying
logic zero to this pin, the program starts execution from the beginning.
Pins 10-17: Port 1 Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:
Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication
output.
Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication
clock output.
Pin 12: INT0 Interrupt 0 input.
Pin 13: INT1 Interrupt 1 input.
Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.
Pin 16: WR Write to external (additional) RAM.

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Pin 17: RD Read from external RAM.
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Pins 18-19:X0,X1 Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins. Instead of it, miniature ceramics
resonators can also be used for frequency stability. Later versions of microcontrollers operate at
a frequency of 0 Hz up to over 50 Hz.
Pin 20: GND Ground.
Pin 21-28: PORT2 If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte,
i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is
not used, which means that not all eight port bits are used for its addressing, the rest of them are
not available as inputs/outputs.
Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.
Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the
external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and
uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous
logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by
means of only one additional (and cheap) integrated circuit. In other words, this port is used for
both data and address transmission.
Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that even there
is a program written to the microcontroller, it will not be executed. Instead, the program written
to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will
use both memories, first internal then external (if exists).
Pin 32-39: PORT1 Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin
is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).
Pin 40: Vcc +5V power supply.

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Memory Organization
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The 8051 has two types of memory and these are Program Memory and Data Memory. Program
Memory (ROM) is used to permanently save the program being executed, while Data Memory
(RAM) is used for temporarily storing data and intermediate results created and used during the
operation of the microcontroller. Depending on the model in use (we are still talking about the
8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM
is used. However
All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb
memory. It is neither a mistake nor a big ambition of engineers who were working on basic core
development. It is a matter of smart memory organization which makes these microcontrollers a
real programmers goody.
Program Memory
The first models of the 8051 microcontroller family did not have internal program memory. It
was added as an external separate chip. These models are recognizable by their label beginning
with 803 (for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even
though such an amount of memory is sufficient for writing most of the programs, there are
situations when it is necessary to use additional memory as well. A typical example are so called
lookup tables. They are used in cases when equations describing some processes are too
complicated or when there is no time for solving them. In such cases all necessary estimates and
approximates are executed in advance and the final results are put in the tables (similar to
logarithmic tables).
How does the microcontroller handle external memory depends on the EA pin logic state:

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EA=0 In this case, the microcontroller completely ignores internal program memory and
executes only the program stored in external memory.
EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the
program stored in external memory.
In both cases, P0 and P2 are not available for use since being used for data and address
transmission. Besides, the ALE and PSEN pins are also used.
Data Memory
As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the
8051 family includes many registers such as hardware counters and timers, input/output ports,
serial data buffers etc. The previous models had 256 RAM locations, while for the later models
this number was incremented by additional 128 registers. However, the first 256 memory
locations (addresses 0-FFh) are the heart of memory common to all the models belonging to the
8051 family. Locations available to the user occupy memory space with addresses 0-7Fh, i.e.
first 128 registers. This part of RAM is divided in several blocks.
The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to
accessing any of these registers, it is necessary to select the bank containing it. The next memory

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block (address 20h-2Fh) is bit- addressable, which means that each bit has its own address (07Fh). Since there are 16 such registers, this block contains in total of 128 bits with separate
addresses (address of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is 7Fh).
The third group of registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not have any
special functions or features.
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Additional RAM
In order to satisfy the programmers constant hunger for Data Memory, the manufacturers
decided to embed an additional memory block of 128 locations into the latest versions of the
8051 microcontrollers. However, its not as simple as it seems to be The problem is that
electronics performing addressing has 1 byte (8 bits) on disposal and is capable of reaching only
the first 256 locations, therefore. In order to keep already existing 8-bit architecture and
compatibility with other existing models a small trick was done.
What does it mean? It means that additional memory block shares the same addresses with
locations intended for the SFRs (80h- FFh). In order to differentiate between these two
physically separated memory spaces, different ways of addressing are used. The SFRs memory
locations are accessed by direct addressing, while additional RAM memory locations are
accessed by indirect addressing.

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Memory expansion
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In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is possible to add
two external memory chips with capacity of 64Kb each. P2 and P3 I/O ports are used for their
addressing and data transmission.
From the users point of view, everything works quite simply when properly connected because
most operations are performed by the microcontroller itself. The 8051 microcontroller has two
pins for data read RD#(P3.7) and PSEN#. The first one is used for reading data from external
data memory (RAM), while the other is used for reading data from external program memory
(ROM). Both pins are active low. A typical example of memory expansion by adding RAM and
ROM chips (Hardware architecture), is shown in figure above.
Even though additional memory is rarely used with the latest versions of the microcontrollers,
we will describe in short what happens when memory chips are connected according to the
previous schematic. The whole process described below is performed automatically.

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When the program during execution encounters an instruction which resides in external
memory (ROM), the microcontroller will activate its control output ALE and set the first 8 bits
of address (A0-A7) on P0. IC circuit 74HCT573 passes the first 8 bits to memory address pins.
A signal on the ALE pin latches the IC circuit 74HCT573 and immediately afterwards 8
higher bits of address (A8-A15) appear on the port. In this way, a desired location of additional
program memory is addressed. It is left over to read its content.
Port P0 pins are configured as inputs, the PSEN pin is activated and the microcontroller
reads from memory chip.
Similar occurs when it is necessary to read location from external RAM. Addressing is
performed in the same way, while read and write are performed via signals appearing on the
control outputs RD (is short for read) or WR (is short for write).

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Special Function Registers (SFRs)-1
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Special Function Registers (SFRs) are a sort of control table used for running and monitoring the
operation of the microcontroller. Each of these registers as well as each bit they include, has its
name, address in the scope of RAM and precisely defined purpose such as timer control,
interrupt control, serial communication control etc. Even though there are 128 memory locations
intended to be occupied by them, the basic core, shared by all types of 8051 microcontrollers,
has only 21 such registers. Rest of locations are intensionally left unoccupied in order to enable
the manufacturers to further develop microcontrollers keeping them compatible with the
previous versions. It also enables programs written a long time ago for microcontrollers which
are out of production now to be used today.
A Register (Accumulator)
A register is a general-purpose register used for storing intermediate results obtained during
operation. Prior to executing an instruction upon any number or operand it is necessary to store it
in the accumulator first. All results obtained from arithmetical operations performed by the ALU
are stored in the accumulator. Data to be moved from one register to another must go through the
accumulator. In other words, the A register is the most commonly used register and it is

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impossible to imagine a microcontroller without it. More than half instructions used by the 8051
microcontroller use somehow the accumulator.
B Register
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Multiplication and division can be performed only upon numbers stored in the A and B registers.
All other instructions in the program can use this register as a spare accumulator (A).
R Registers (R0-R7)
This is a common name for 8 general-purpose registers (R0, R1, R2 ...R7). Even though they are
not true SFRs, they deserve to be discussed here because of their purpose. They occupy 4 banks
within RAM. Similar to the accumulator, they are used for temporary storing variables and
intermediate results during operation. Which one of these banks is to be active depends on two
bits of the PSW Register. Active bank is a bank the registers of which are currently used.
The following example best illustrates the purpose of these registers. Suppose it is necessary to
perform some arithmetical operations upon numbers previously stored in the R registers:
(R1+R2) - (R3+R4). Obviously, a register for temporary storing results of addition is needed.
This is how it looks in the program:

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; Means: move number from R3 into accumulator

; Means: add number from R4 to accumulator (result remains in accumulator)
; Means: temporarily move the result from accumulator into R5
; Means: move number from R1 to accumulator
; Means: add number from R2 to accumulator
; Means: subtract number from R5 (there are R3+R4)
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MOV A,R3
ADD A,R4
MOV R5,A
MOV A,R1
ADD A,R2
SUBB A,R5
Program Status Word (PSW) Register:
PSW register is one of the most important SFRs. It contains several status bits that reflect the
current state of the CPU. Besides, this register contains Carry bit, Auxiliary Carry, two register
bank select bits, Overflow flag, parity bit and user-definable status flag.
P - Parity bit. If a number stored in the accumulator is even then this bit will be automatically
set (1), otherwise it will be cleared (0). It is mainly used during data transmit and receive via
serial communication.
- Bit 1. This bit is intended to be used in the future versions of microcontrollers.
OV Overflow occurs when the result of an arithmetical operation is larger than 255 and cannot
be stored in one register. Overflow condition causes the OV bit to be set (1). Otherwise, it will be
cleared (0).
RS0, RS1 - Register bank select bits. These two bits are used to select one of four register
banks of RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four banks
of RAM.
RS1
RS2
Space
in
RAM
Bank0
00h07h
Bank1
08h0Fh
Bank2
10h17h

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Bank3
18h1Fh
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F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.
CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and shift
instructions.
Data Pointer Register (DPTR)
DPTR register is not a true one because it doesn't physically exist. It consists of two separate
registers: DPH (Data Pointer High) and (Data Pointer Low). For this reason it may be treated as a
16-bit register or as two independent 8-bit registers. Their 16 bits are primarly used for external
memory addressing. Besides, the DPTR Register is usually used for storing data and
intermediate results.
Stack Pointer (SP)

Register
A value stored in the Stack Pointer points to the first free stack address and permits stack
availability. Stack pushes increment the value in the Stack Pointer by 1. Likewise, stack pops
decrement its value by 1. Upon any reset and power-on, the value 7 is stored in the Stack Pointer,

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which means that the space of RAM reserved for the stack starts at this location. If another value
is written to this register, the entire Stack is moved to the new memory location.
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P0, P1, P2, P3 - Input/Output

Registers
If neither external memory nor serial communication system are used then 4 ports with in total of
32 input/output pins are available for connection to peripheral environment. Each bit within these
ports affects the state and performance of appropriate pin of the microcontroller. Thus, bit logic
state is reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a pin
reflects the state of appropriate port bit.
As mentioned, port bit state affects performance of port pins, i.e. whether they will be configured
as inputs or outputs. If a bit is cleared (0), the appropriate pin will be configured as an output,
while if it is set (1), the appropriate pin will be configured as an input. Upon reset and power-on,
all port bits are set (1), which means that all appropriate pins will be configured as inputs.

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Timer T0
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As seen in figure below, the timer T0 consists of two registers TH0 and TL0 representing a low
and a high byte of one 16-digit binary number.
Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of
will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register
(high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal
number 232.
Formula used to calculate values in these two registers is very simple:

TH0 256 + TL0 = T
Matching the previous example it would be as follows:
3 256 + 232 = 1000

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Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of
exceeding this value, the timer will be automatically cleared and counting starts from 0. This
condition is called an overflow. Two registers TMOD and TCON are closely connected to this
timer and control its operation.
TMOD Register (Timer Mode)
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The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure
below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to
the timer 1. There are 4 operational modes and each of them is described herein.
Bits of this register have the following function:
(P3.3):

GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin
1 - Timer 1 operates only if the INT1 bit is set.

0 - Timer 1 operates regardless of the logic state of the INT1 bit.
C/T1 selects pulses to be counted up by the timer/counter 1:
1 - Timer counts pulses brought to the T1 pin (P3.5).
0 - Timer counts pulses from internal oscillator.
T1M1,T1M0 These two bits select the operational mode of the Timer 1.
T1M0
Mode
Description
13-bit timer
16-bit timer
8-bit autoreload
Split mode
T1M1

GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):
T0M1,T0M0 These two bits select the oprtaional mode of the Timer 0.
Timer Control (TCON) Register

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TCON register is also one of the registers whose bits are directly in control of timer operation.
Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control to be discussed later.
TF1 bit is automatically set on the Timer 1 overflow.

TR1 bit enables the Timer 1.
1 - Timer 1 is enabled.
0 - Timer 1 is disabled.
TR0 bit enables the timer 0.
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PCON
register
The purpose of the Register PCON bits is:
SMOD Baud rate is twice as much higher by setting this bit.

GF1 General-purpose bit (available for use).

PD By setting this bit the microcontroller enters the Power Down mode.
IDL By setting this bit the microcontroller enters the Idle mode.


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Serial Port Control (SCON) Register

SM0 - Serial port mode bit 0 is used for serial port mode selection.
SM1 - Serial port mode bit 1.
SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit.
When set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It
should be cleared in mode 0.
REN - Reception Enable bit enables serial reception when set. When cleared, serial
reception is disabled.
TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of
transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.
RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th
bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is
sent. It's a signal to the processor that the line is available for a new byte transmite. It must be
cleared from within the software.
RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte
is received and should be read quickly prior to being replaced by a new data. This bit is also
cleared from within the software.
As seen, serial port mode is selected by combining the SM0 and SM2 bits:
SM1
Mode
Description
Baud Rate
8-bit Shift
Register
1/12 the quartz

frequency
8-bit UART
Determined by
the timer 1
SM0
9-bit UART
1/32 the quartz

frequency (1/64
the quartz
frequency)
9-bit UART
Determined by
the timer 1

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Addressing Modes
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While operating, the processor processes data as per program instructions. Each instruction
consists of two parts. One part describes WHAT should be done, while the other explains HOW
to do it. The latter part can be a data (binary number) or the address at which the data is stored.
Two ways of addressing are used for all 8051 microcontrollers depending on which part of
memory should be accessed:
Direct Addressing
On direct addressing, the address of memory location containing data to be read is specified in
instruction. The address may contain a number being changed during operation (variable). For
example:
Since the address is only one byte in size (the largest number is 255), only the first 255 locations
of RAM can be accessed this way. The first half of RAM is available for use, while another half
is reserved for SFRs.
MOV A,33h
; Means: move a number from address 33 hex. to accumulator
Indirect Addressing
On indirect addressing, a register containing the address of another register is specified in

instruction. Data to be used in the program is stored in the letter register. For example:
Indirect addressing is only used for accessing RAM locations available for use (never for
accessing SFRs). This is the only way of accessing all the latest versions of the microcontrollers
with additional memory block (128 locations of RAM). Simply put, when the program
encounters instruction including @ sign and if the specified address is higher than 128 ( 7F
hex.), the processor knows that indirect addressing is used and skips memory space reserved for
SFRs.
MOV A,@R0
; Means: Store the value from the register whose address is in the R0 register
into accumulator
On indirect addressing, registers R0, R1 or Stack Pointer are used for specifying 8-bit addresses.
Since only 8 bits are available, it is possible to access only registers of internal RAM this way
(128 locations when speaking of previous models or 256 locations when speaking of latest
models of microcontrollers). If an extra memory chip is added then the 16-bit DPTR Register
(consisting of the registers DPTRL and DPTRH) is used for specifying address. In this way it is
possible to access any location in the range of 64K

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Instruction Set-1
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The process of writing program for the microcontroller mainly consists of giving instructions
(commands) in the specific order in which they should be executed in order to carry out a
specific task. As electronics cannot understand what for example an instruction if the push
button is pressed- turn the light on means, then a certain number of simpler and precisely
defined orders that decoder can recognise must be used. All commands are known as
INSTRUCTION SET. All microcontrollers compatibile with the 8051 have in total of 255
instructions, i.e. 255 different words available for program writing.
At first sight, it is imposing number of odd signs that must be known by heart. However, It is not
so complicated as it looks like. Many instructions are considered to be different, even though
they perform the same operation, so there are only 111 truly different commands. For example:
ADD A,R0, ADD A,R1, ... ADD A,R7 are instructions that perform the same operation (additon
of the accumulator and register). Since there are 8 such registers, each instruction is counted
separately. Taking into account that all instructions perform only 53 operations (addition,
subtraction, copy etc.) and most of them are rarely used in practice, there are actually 20-30
abbreviations to be learned, which is acceptable.
Types of instructions
Depending on operation they perform, all instructions are divided in several groups:

Branch Instructions
Logic Instructions
Bit-oriented Instructions
The first part of each instruction, called MNEMONIC refers to the operation an instruction
performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of
operation being executed. For example:
INC
R1 Means:
Increment
register
R1
(increment
register
R1);
LJMP LAB5 - Means: Long Jump LAB5 (long jump to the address marked as LAB5);
JNZ LOOP - Means: Jump if Not Zero LOOP (if the number in the accumulator is not 0, jump to
the address marked as LOOP);
The other part of instruction, called OPERAND is separated from mnemonic by at least one
whitespace and defines data being processed by instructions. Some of the instructions have no
operand, while some of them have one, two or three. If there is more than one operand in an
instruction, they are separated by a comma.
For example:

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RET return from a subroutine;
JZ TEMP - if the number in the accumulator is not 0, jump to the address marked as TEMP;
ADD A,R3 - add R3 and accumulator;
CJNE A,#20,LOOP - compare accumulator with 20. If they are not equal, jump to the address
marked as LOOP;
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Arithmetic instructions
Arithmetic instructions perform several basic operations such as addition, subtraction, division,
multiplication etc. After execution, the result is stored in the first operand. For example:
ADD A,R1 - The result of addition (A+R1) will be stored in the accumulator.
Description
Byte
Cycle
ADD A,Rn
Adds the register to the accumulator
ADD
A,direct
Adds the direct byte to the accumulator
ADD
A,@Ri
Adds the indirect

accumulator
ADD
A,#data
Adds the immediate

accumulator
ADDC
A,Rn
Adds the register to the accumulator

with a carry flag
ADDC
A,direct
Adds the direct byte to the accumulator

with a carry flag
ADDC
A,@Ri
Adds the indirect RAM

accumulator with a carry flag
to
the
ADDC
A,#data
Adds the immediate data

accumulator with a carry flag
to
the
SUBB
A,Rn
Subtracts the register

accumulator with a borrow
from
the
SUBB
A,direct
Subtracts the direct byte from the

SUBB
A,@Ri
Subtracts the indirect RAM from the

SUBB
Subtracts the immediate data from the
Mnemonic
RAM
to
the
data
to
the

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INC A
Increments the accumulator by 1
INC Rn
Increments the register by 1
INC Rx
Increments the direct byte by 1
INC @Ri
Increments the indirect RAM by 1
DEC A
Decrements the accumulator by 1
DEC Rn
Decrements the register by 1
DEC Rx
Decrements the direct byte by 1
DEC @Ri
Decrements the indirect RAM by 1
INC DPTR
Increments the Data Pointer by 1
MUL AB
Multiplies A and B
DIV AB
Divides A by B
DA A
Decimal adjustment of the accumulator

according to BCD code
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A,#data


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Branch Instructions
There are two kinds of branch instructions:
Unconditional jump instructions: upon their execution a jump to a new location from where the
program continues execution is executed.
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Conditional jump instructions: a jump to a new program location is executed only if a specified
condition is met. Otherwise, the program normally proceeds with the next instruction.
Branch Instructions
Description
Byte
Cycle
ACALL
addr11
Absolute subroutine call
LCALL
addr16
Long subroutine call
RET
Returns from subroutine
RETI
Returns from interrupt subroutine
AJMP addr11
Absolute jump
LJMP addr16
Long jump
SJMP rel
Short jump (from 128 to +127

locations relative to the following
instruction)
JC rel
Jump if carry flag is set. Short jump.
JNC rel
Jump if carry flag is not set. Short jump.
JB bit,rel
Jump if direct bit is set. Short jump.
JBC bit,rel
Jump if direct bit is set and clears bit.

Short jump.
JMP
@A+DPTR
Jump indirect relative to the DPTR
JZ rel
Jump if the accumulator is zero. Short

jump.
JNZ rel
Jump if the accumulator is not zero.

Short jump.
Mnemonic


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Compares direct byte to the accumulator

and jumps if not equal. Short jump.
CJNE
A,#data,rel
Compares immediate data to the

accumulator and jumps if not equal.
Short jump.
CJNE
Rn,#data,rel
Compares immediate data to the register

and jumps if not equal. Short jump.
CJNE
@Ri,#data,rel
Compares immediate data to indirect

register and jumps if not equal. Short
jump.
DJNZ Rn,rel
Decrements register and jumps if not 0.

Short jump.
DJNZ Rx,rel
Decrements direct byte and jump if not

0. Short jump.
NOP
No operation
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CJNE
A,direct,rel

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Data transfer instructions move the content of one register to another. The register the content of
which is moved remains unchanged. If they have the suffix X (MOVX), the data is exchanged
with external memory.
Description
Byte
Cycle
MOV A,Rn
Moves the register to the accumulator
MOV
A,direct
Moves the direct byte to the

accumulator
MOV A,@Ri
Moves the indirect RAM to the

accumulator
MOV A,#data
Moves the immediate data to the

accumulator
MOV Rn,A
Moves the accumulator to the register
MOV
Rn,direct
Moves the direct byte to the register
MOV
Rn,#data

register
MOV
direct,A
Moves the accumulator to the direct

byte
MOV
direct,Rn
Moves the register to the direct byte
MOV
direct,direct
Moves the direct byte to the direct byte
MOV
direct,@Ri
Moves the indirect RAM to the direct

byte
MOV
direct,#data
Moves the immediate data to the direct

byte
MOV @Ri,A
Moves the accumulator to the indirect

RAM
MOV
Moves the direct byte to the indirect
Mnemonic

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RAM
MOV
@Ri,#data

indirect RAM
MOV
DPTR,#data
Moves a 16-bit data to the data pointer
MOVC
A,@A+DPTR
Moves the code byte relative to the

DPTR to the accumulator
(address=A+DPTR)
MOVC
A,@A+PC
Moves the code byte relative to the PC

to the accumulator (address=A+PC)
MOVX
A,@Ri
Moves the external RAM (8-bit address)

to the accumulator
3-10
MOVX
A,@DPTR
Moves the external RAM (16-bit

address) to the accumulator
3-10
MOVX
@Ri,A
Moves the accumulator to the external

RAM (8-bit address)
4-11
MOVX
@DPTR,A
Moves the accumulator to the external

RAM (16-bit address)
4-11
PUSH direct
Pushes the direct byte onto the stack
POP direct
Pops the direct byte from the stack/td>
XCH A,Rn
Exchanges the register with the

accumulator
XCH A,direct
Exchanges the direct byte with the

accumulator
XCH A,@Ri
Exchanges the indirect RAM with the

accumulator
XCHD
A,@Ri
Exchanges the low-order nibble indirect

RAM with the accumulator
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@Ri,direct

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Logic Instructions
Logic instructions perform logic operations upon corresponding bits of two registers. After
execution, the result is stored in the first operand.
Logic Instructions
Description
Byte
Cycle
ANL A,Rn
AND register to accumulator
ANL
A,direct
AND direct byte to accumulator
ANL
A,@Ri
AND indirect RAM to accumulator
ANL
A,#data
AND immediate data to accumulator
ANL
direct,A
AND accumulator to direct byte
ANL
direct,#data
AND immediae data to direct register
ORL A,Rn
OR register to accumulator
ORL
A,direct
OR direct byte to accumulator
ORL
A,@Ri
OR indirect RAM to accumulator
ORL
direct,A
OR accumulator to direct byte
ORL
direct,#data
OR immediate data to direct byte
XRL A,Rn
Exclusive OR register to accumulator
XRL
A,direct
Exclusive OR direct byte to accumulator
XRL
A,@Ri
Exclusive OR indirect RAM to

accumulator
XRL
A,#data
Exclusive OR immediate data to

accumulator
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Mnemonic

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Exclusive OR accumulator to direct byte
XORL
direct,#data
Exclusive OR immediate data to direct

byte
CLR A
Clears the accumulator
CPL A
Complements the accumulator (1=0,

0=1)
SWAP A
Swaps nibbles within the accumulator
RL A
Rotates bits in the accumulator left
RLC A
Rotates bits in the accumulator left

through carry
RR A
Rotates bits in the accumulator right
RRC A
Rotates bits in the accumulator right

through carry
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XRL
direct,A

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Similar to logic instructions, bit-oriented instructions perform logic operations. The difference is
that these are performed upon single bits.
Description
Byte
Cycle
CLR C
Clears the carry flag
CLR bit
Clears the direct bit
SETB C
Sets the carry flag
SETB bit
Sets the direct bit
CPL C
Complements the carry flag
CPL bit
Complements the direct bit
ANL C,bit
AND direct bit to the carry flag
ANL C,/bit
AND complements of direct bit to the

carry flag
ORL C,bit
OR direct bit to the carry flag
ORL C,/bit
OR complements of direct bit to the

carry flag
MOV C,bit
Moves the direct bit to the carry flag
MOV bit,C
Moves the carry flag to the direct bit
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Mnemonic

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Here is a list of the operands and their meanings:
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A - accumulator;
Rn - is one of working registers (R0-R7) in the currently active RAM memory bank;
Direct - is any 8-bit address register of RAM. It can be any general-purpose register or a SFR
(I/O port, control register etc.);
@Ri - is indirect internal or external RAM location addressed by register R0 or R1;
#data - is an 8-bit constant included in instruction (0-255);
#data16 - is a 16-bit constant included as bytes 2 and 3 in instruction (0-65535);
addr16 - is a 16-bit address. May be anywhere within 64KB of program memory;
addr11 - is an 11-bit address. May be within the same 2KB page of program memory as the first
byte of the following instruction;
rel - is the address of a close memory location (from -128 to +127 relative to the first byte of the
following instruction). On the basis of it, assembler computes the value to add or subtract from
the number currently stored in the program counter;
bit - is any bit-addressable I/O pin, control or status bit; and
C - is carry flag of the status register (register PSW).

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Microcontroller Memory Expansion
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Some recent microcontrollers, such as the Microchip PIC range, have been designed to be
configured to access external memory and I/O.
The above diagram shows a microcontroller with two ports, A and B. If these two ports are also
used for external data and address bus, the microcontroller can be configured for microprocessor
mode.

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Port A is now used as part of the address bus, with port B used for both the remaining address
bus signals and the data bus. So port B pins form part of the address bus, while, a little later, they
are the data bus. This is a common arrangement, called a multiplexed address/data bus
configuration. It uses less pins than would be needed for separate address and data bus
connections.
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In order to obtain the multiplexed address and data signals from the port B pins, an external data
latch is required. This is used to hold the address bits, when the port B pins change to become the
data bus. The purpose of the address strobe is to latch the address bits into the data latch at the
right moment, before the port B pins change to become the data bus.
The above diagram illustrates the basic arrangement of a multiplexed Address/Data bus. It is
similar to that used for the intel 80X86 processor. The basic address/data multiplexed timing is
illustrated below.

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Note that the address remains fixed until the next address strobe, also that the memory read
(when the read line is asserted) and the memory write (when the write line is asserted) take place
towards the end of the data waveform.

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Timer in different modes-1
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As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the
frequency of this oscillator is precisely defined and very stable, pulses it generates are always of
the same width, which makes them ideal for time measurement. Such crystals are also used in
quartz watches. In order to measure time between two events it is sufficient to count up pulses
coming from this oscillator. That is exactly what the timer does. If the timer is properly
programmed, the value stored in its register will be incremented (or decremented) with each
coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12
quartz oscillator periods, which means that by embedding quartz with oscillator frequency of
12MHz, a number stored in the timer register will be changed million times per second, i.e. each
microsecond.
The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their
main purpose is to measure time and count external events. Besides, they can be used for
generating clock pulses to be used in serial communication, so called Baud Rate.
Timer T0
As seen in figure below, the timer T0 consists of two registers TH0 and TL0 representing a low
and a high byte of one 16-digit binary number.
Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of
will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register
(high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal
number 232.

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Formula used to calculate values in these two registers is very simple:

TH0 256 + TL0 = T
Matching the previous example it would be as follows:
3 256 + 232 = 1000
Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of
exceeding this value, the timer will be automatically cleared and counting starts from 0. This
condition is called an overflow. Two registers TMOD and TCON are closely connected to this
timer and control its operation.
TMOD Register (Timer Mode)
The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure
below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to
the timer 1. There are 4 operational modes and each of them is described herein.
Bits of this register have the following function:

(P3.3):
GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin

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T1M0
Mode
Description
13-bit timer
16-bit timer
8-bit autoreload
Split mode
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T1M1
GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):

T0M1
T0M0
Mode
Description
13-bit timer
16-bit timer
8-bit autoreload
Split mode
Timer 0 in mode 0 (13-bit timer)
This is one of the rarities being kept only for the purpose of compatibility with the previuos
versions of microcontrollers. This mode configures timer 0 as a 13-bit timer which consists of all
8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits. How
does it operate? Each coming pulse causes the lower register bits to change their states. After
receiving 32 pulses, this register is loaded and automatically cleared, while the higher byte (TH0)
is incremented by 1. This process is repeated until registers count up 8192 pulses. After that,
both registers are cleared and counting starts from 0.

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Timer 0 in mode 1 (16-bit timer)
Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and
TL0. That's why this is one of the most commonly used modes. Timer operates in the same way
as in mode 0, with difference that the registers count up to 65 536 as allowable by the 16 bits.

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Timer in different modes-2

Timer 0 in mode 2 (Auto-Reload Timer)
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Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for
counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0)
register.
The following example shows the advantages of this mode. Suppose it is necessary to constantly
count up 55 pulses generated by the clock.
If mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and
constantly check whether an overflow has occured, i.e. whether they reached the value 255.
When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure. The
same procedure is automatically performed by the microcontroller if set in mode 2. In fact, only
the TL0 register operates as a timer, while another (TH0) register stores the value from which the
counting starts. When the TL0 register is loaded, instead of being cleared, the contents of TH0
will be reloaded to it. Referring to the previous example, in order to register each 55th pulse, the
best solution is to write the number 200 to the TH0 register and configure the timer to operate in
mode 2.

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Timer 0 in Mode 3 (Split Timer)
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Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In
other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two
independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit
timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1. In
addition, all the control bits of 16-bit Timer 1 (consisting of the TH1 and TL1 register), now
control the 8-bit Timer 1. Even though the 16-bit Timer 1 can still be configured to operate in
any of modes (mode 1, 2 or 3), it is no longer possible to disable it as there is no control bit to do
it. Thus, its operation is restricted when timer 0 is in mode 3.
The only application of this mode is when two timers are used and the 16-bit Timer 1 the
operation of which is out of control is used as a baud rate generator.
Timer Control (TCON) Register

TCON register is also one of the registers whose bits are directly in control of timer operation.
Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control to be discussed later.

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TR1 bit enables the Timer 1.
TR0 bit enables the timer 0.
How to use the Timer 0 ?
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In order to use timer 0, it is first necessary to select it and configure the mode of its operation.
Bits of the TMOD register are in control of it:
Referring to figure above, the timer 0 operates in mode 1 and counts pulses generated by internal
clock the frequency of which is equal to 1/12 the quartz frequency.
Turn on the timer:

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The TR0 bit is set and the timer starts operation. If the quartz crystal with frequency of 12MHz is
embedded then its contents will be incremented every microsecond. After 65.536 microseconds,
the both registers the timer consists of will be loaded. The microcontroller automatically clears
them and the timer keeps on repeating procedure from the beginning until the TR0 bit value is
logic zero (0).
How to 'read' a timer?
Depending on application, it is necessary either to read a number stored in the timer registers or
to register the moment they have been cleared.
- It is extremely simple to read a timer by using only one register configured in mode 2 or 3. It is
sufficient to read its state at any moment. That's all!
- It is somehow complicated to read a timer configured to operate in mode 2. Suppose the lower
byte is read first (TL0), then the higher byte (TH0). The result is:
TH0 = 15 TL0 = 255
Everything seems to be ok, but the current state of the register at the moment of reading was:
TH0 = 14 TL0 = 255
In case of negligence, such an error in counting (255 pulses) may occur for not so obvious but
quite logical reason. The lower byte is correctly read (255), but at the moment the program
counter was about to read the higher byte TH0, an overflow occurred and the contents of both
registers have been changed (TH0: 1415, TL0: 2550). This problem has a simple solution.
The higher byte should be read first, then the lower byte and once again the higher byte. If the

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number stored in the higher byte is different then this sequence should be repeated. It's about a
short loop consisting of only 3 instructions in the program.
There is another solution as well. It is sufficient to simply turn the timer off while reading is
going on (the TR0 bit of the TCON register should be cleared), and turn it on again after reading
is finished.
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Timer 0 Overflow Detection
Usually, there is no need to constantly read timer registers. It is sufficient to register the moment
they are cleared, i.e. when counting starts from 0. This condition is called an overflow. When it
occurrs, the TF0 bit of the TCON register will be automatically set. The state of this bit can be
constantly checked from within the program or by enabling an interrupt which will stop the main
program execution when this bit is set. Suppose it is necessary to provide a program delay of
0.05 seconds (50 000 machine cycles), i.e. time when the program seems to be stopped:
First a number to be written to the timer registers should be calculated:
Then it should be written to the timer registers TH0 and TL0:

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When enabled, the timer will resume counting from this number. The state of the TF0 bit, i.e.
whether it is set, is checked from within the program. It happens at the moment of overflow, i.e.
after exactly 50.000 machine cycles or 0.05 seconds.

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Programs on timers
Programming for timer in mode 1:
To generate a square wave on port 2.1 pin:

ORG 0000H
MOV TMOD, #01H
HERE :CPL P1.2
ACALL DELAY
SJMP HERE
DELAY: MOV TH0, #0FFH
MOV TL0, #0F0H

SETB TR0
TARGET : JNB P1.2,TARGET

CLR TR0
CLR TF0
RET

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Programming for timer in mode 2:
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To generate a square wave on port 2.1 pin:

ORG 0000H
MOV TMOD, #02H

MOV TH0, # 0F0H
HERE :CPL P1.2
ACALL DELAY
SJMP HERE
DELAY:SETB TR0
TARGET : JNB P1.2,TARGET

CLR TR0
CLR TF0
RET

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UART (Universal Asynchronous Receiver and Transmitter)
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One of the microcontroller features making it so powerful is an integrated UART, better known
as a serial port. It is a full-duplex port, thus being able to transmit and receive data
simultaneously and at different baud rates. Without it, serial data send and receive would be an
enormously complicated part of the program in which the pin state is constantly changed and
checked at regular intervals. When using UART, all the programmer has to do is to simply select
serial port mode and baud rate. When it's done, serial data transmit is nothing but writing to the
SBUF register, while data receive represents reading the same register. The microcontroller takes
care of not making any error during data transmission.
Serial port must be configured prior to being used. In other words, it is necessary to determine
how many bits is contained in one serial word, baud rate and synchronization clock source.
The whole process is in control of the bits of the SCON register (Serial Control).
In mode 0, serial data are transmitted and received through the RXD pin, while the TXD pin
output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least
significant bit (LSB bit) is sent/received first.

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TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this
process starts after any instruction being performed upon this register. When all 8 bits have been
sent, the TI bit of the SCON register is automatically set.
RECEIVE - Data receive through the RXD pin starts upon the two following conditions are
met: bit REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have
been received, the RI bit of the SCON register is automatically set indicating that one byte
receive is complete.
Since there are no START and STOP bits or any other bit except data sent from the SBUF
register in the pulse sequence, this mode is mainly used when the distance between devices is
short, noise is minimized and operating speed is of importance. A typical example is I/O port
expansion by adding a cheap IC (shift registers 74HC595, 74HC597 and similar).

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Mode 1
In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the
following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1).
The START bit is only used to initiate data receive, while the STOP bit is automatically written
to the RB8 bit of the SCON register.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
transmission is indicated by setting the TI bit of the SCON register.
RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The
following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the
SCON register. The RI bit is automatically set upon data reception is complete.

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The Baud rate in this mode is determined by the timer 1 overflow.

Mode 2
In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a
START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit
(always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit
usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the same
register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
transmission is indicated by setting the TI bit of the SCON register.

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RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The
following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the
SCON register. The RI bit is automatically set upon data reception is complete.
Mode 3
Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is
variable.
The parity bit is the P bit of the PSW register. The simplest way to check correctness of the
received byte is to add a parity bit to it. Simply, before initiating data transmit, the byte to
transmit is stored in the accumulator and the P bit goes into the TB8 bit in order to be a part of
the message. The procedure is opposite on receive, received byte is stored in the accumulator
and the P bit is compared with the RB8 bit. If they are the same- everything is OK!
Baud Rate
Baud Rate is a number of sent/received bits per second. In case the UART is used, baud rate
depends on: selected mode, oscillator frequency and in some cases on the state of the SMOD bit
of the SCON register. All the necessary formulas are specified in the table:
Baud
Rate
Mode
0
Fosc. /
12
Mode
BitSMOD
BitSMOD

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Fosc. /
32
Fosc. /
64
1
0
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Mode
2
Fosc.
16 12
(256TH1)
Mode
3
Fosc.
16 12
(256TH1)
Timer 1 as a clock generator
Timer 1 is usually used as a clock generator as it enables various baud rates to be easily set. The
whole procedure is simple and is as follows:
First, enable Timer 1 overflow interrupt.

Configure Timer T1 to operate in auto-reload mode.
Depending on needs, select one of the standard values from the table and write it to the
TH1 register. That's all.
Baud
Rate
Fosc. (MHz)
11.0592
12
14.7456
150
40 h
30 h
00 h
300
A0 h
98 h
80 h
75 h
52 h
600
D0 h
CC h
C0 h
BB h
A9 h
1200
E8 h
E6 h
E0 h
DE h
D5 h
2400
F4 h
F3 h
F0 h
EF h
EA h
F3 h
EF h
EF h

4800
4800
FA h
F8 h
9600
FD h
FC h
9600
19200
16
20
F5 h
FC h
0
F5 h
FD h
Bit
SMOD
1
1

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FE h
76800
FF h
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38400

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Interrupts of 8051
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Interrupts
- An interrupt is the occurrence of an event that causes a temporary suspension of a
program while the condition is serviced by another program
- The program or routine that deals with the interrupt is the interrupt service routine (ISR)
or interrupt handler
- Interrupts allow a system to respond asynchronously to an event and deal with the event
while another program is executing
- An interrupt driven system gives the illusion of doing many things simultaneously
- Of course, the CPU cannot execute more than one instruction at a time - it can only
temporarily suspend execution of one program, execute another, and then return to the
first program
- In a way, interrupts are like subroutines, except that one does not know when the
interrupt code will be executed
Interrupt Handling
- When an interrupt occurs, CPU:
finishes the instruction it is currently executing
stores the PC on the stack
saves the current status of all interrupts internally
fetches the ISR address for the interrupt from IVT (interrupt vector table), stores it into
PC and jumps to that address
executes the ISR until it reaches the RETI instruction
upon RETI, the CPU pops back the old PC from the stack and continues with whatever
it was doing before the interrupt occurred.
Interrupts v. Pooling
Polling:
-CPU monitors all served devices continuously, looking for a service request flag
- Whenever it sees a request, it serves the device and then keeps polling
-CPU is always busy with polling doing the while any request loop
Interrupts:
-If and when a device is ready and needs attention, it informs the CPU
- CPU drops whatever it was doing and serves the device and then returns back to its
original task
- CPU is always free, when not serving any interrupts
Interrupt Sources
- 2 external (INT0 and INT1)
- 2 Timers (TF0 and TF1)
- 1 Serial (SI)

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Interrupt Enable Register
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- IE enables interrupts individually and globally

- EX0/EX1: Enable external interrupt 0/1
- ET0/ET1: Enable Timer 0/1 interrupt
- ES: Enable serial interrupt
- EA: Global Interrupt enable
Putting a 1 in a bit enables its interrupt
Putting a 0 masks that interrupt
Interrupt Flags
- IE0/IE1 in TCON - For External Interrupts
- TF0/TF1 in TCON - For Timer Interrupts
- T1/R1 in SCON - For Serial Interrupts
Interrupt Priority
- The 8051 implements 2 types of interrupt priority.

- User Defined Priority
- Using the IP register, the user can group interrupts into two levels high and low.
- An interrupt is assigned a high priority level by setting its bit in the IP register to 1. If
the bit is set to 0, the interrupt gets a low priority.
- Automatic Priority
- Within each priority level, a strict order is observed.
- Interrupts are ordered as follows: INT0, TF0, INT1, TF1, SO.
Interrupt Priorities Register
- Sets which Interrupt will have priority should 2 occur simultaneously, or if another is
being serviced the higher priority will be processed first.
- Putting a 1 in a bit assigns its interrupt to the high priority level.
Pending Interrupts
- If an interrupt occurs while it is disabled, or while a higher priority interrupt is active, it
becomes pending.
- As soon as the interrupt is enabled, it will cause a call.
- It is also possible to cancel it by software by clearing the appropriate bit in the register.

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Interrupt Vectors
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- Each interrupt will cause execution to branch to a unique location.

- External 0: 0003H
- Timer 0: 000BH
- External 1: 0013H
- Timer 1: 001BH
- Serial Port: 0023H
Service Routines
- Each vector has 8 bytes for a routine. The interrupt code may all be contained here
(Small ISR).
- From the vector location execution may branch to a much larger routine elsewhere in
memory (Large ISR)
External Interrupts
- Occur as a result of a low level or negative edge on INT0 and INT1.

- Set up using TCON
IT0/IT1:
1 = Negative edge triggered

0 = Level Triggered
IE0/IE1: 1 = Condition occurred
- Enabled using IE
EX1/0 = 1, EA = 1
- IEx is cleared by hardware when the CPU vectors to the ISR if the
interrupt is transition-activated
- If the interrupt is level activated, then IEx flag has to be cleared by
user software
Timer Interrupts
- Occur as a result of Timer 0/1 overflowing.

TF0/1: 1 = Condition occurred
- Enabled using IE
ET0/1 = 1, EA = 1

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Serial Interrupts
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- Occurs on the condition a serial byte was transmitted or received.

RI = 1
TI = 1
- Enabled using IE
ES = 1, EA = 1

Programs on serial communication

Program to transfer A continuously:
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MOV TMOD , #20H ;load TMOD with 20h to select timer 1 in mode 2
;programming
MOV TH1, #-3H
; to set the baud rate to 9600bps
MOV SCON,#50H ;to select serial programming in mode 0
SETB TR1
;start the timer
AGAIN:MOV SBUF , # A ;load SBUF with the ascii character of A
HERE:JNB TI,HERE
;continuosly monitor the transmit interrupt flag to check
;that the byte is transmitted or not
CLR TI
;clear the flag to transmit next byte
SJMP AGAIN
;jump to required label to repeat the process again
Program to receive the byte continuously:
MOV TMOD , #20H ;load TMOD with 20h to select timer 1 in mode 2
;programming
MOV TH1, #-3H
; to set the baud rate to 9600bps
MOV SCON,#50H ;to select serial programming in mode 0
SETB TR1
;start the timer
HERE:JNB TI,HERE
;continuosly monitor the transmit interrupt flag to check
;that the byte is transmitted or not
;load the value of SBUF into Accumulator
;the byte received is send to port 1
;clear the flag to receive next byte
;jump to required label to repeat the process again
MOV A,SBUF
MOV P1,A
CLR RI
SJMP HERE
Passing parameters to procedures-1
Program on passing parameters to procedures through registers:
DW
DW
STACK SEGMENT
STACK DW
TOP_STACK
STACK ENDS
0BH
LABEL
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DATA SEGMENT
FACT_INPUT
FACT_OUTPUT
DATA ENDS
0016H
2
DUP(0)
DUP(0)
WORD
CODE SEGMENT
ASSUME CS:CODE,DS:DATA,SS:STACK
START:MOV AX,DATA
MOV DS,AX
MOV AX,STACK
MOV SS,AX
MOV SP,OFFSET TOP_STACK
MOV AX,0001H
MOV CX,FACT_INPUT
CALL FACTORIAL
MOV FACT_OUTPUT,AX
MOV FACT_OUTPUT+2,DX
HLT
FACTORIAL PROC NEAR

PUSHF
BACK:MUL CX
LOOP BACK
POPF
RET
FACTORIAL ENDP
CODE ENDS
END START
Program on passing parameters to procedures through pointers:

DATA SEGMENT
FACT_INPUT
FACT_OUTPUT
DATA ENDS
DW
DW
STACK SEGMENT
STACK DW
TOP_STACK
STACK ENDS
0BH
LABEL
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0016H
2
DUP(0)
DUP(0)
WORD
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,STACK
MOV SS,AX
MOV SI,OFFSET FACT_INPUT
MOV DI,OFFSET FACT_OUTPUT
MOV AX,0001H
CALL FACTORIAL
HLT
FACTORIAL PROC NEAR

PUSHF
MOV CX,[SI]
BACK:MUL CX
LOOP BACK
MOV [DI],AX
MOV [DI + 2],DX
POPF
RET
FACTORIAL ENDP
CODE ENDS
END START
Passing parameters to procedures-2
Program on passing parameters to procedures through memory location:
DW
DW
STACK SEGMENT
STACK DW
TOP_STACK
STACK ENDS
0BH
LABEL
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DATA SEGMENT
FACT_INPUT
FACT_OUTPUT
DATA ENDS
0016H
2
DUP(0)
DUP(0)
WORD
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,STACK
MOV SS,AX
CALL FACTORIAL
HLT
FACTORIAL PROC NEAR

PUSHF
MOV AX,0001H
MOV CX,FACT_INPUT
BACK:MUL CX
LOOP BACK
POPF
MOV FACT_OUTPUT,AX
MOV FACT_OUTPUT+2,DX
RET
FACTORIAL ENDP
CODE ENDS
END START
Program on passing parameters to procedures through stack:

DATA SEGMENT
FACT_INPUT
FACT_OUTPUT
DATA ENDS
DW
DW
STACK SEGMENT
STACK DW
TOP_STACK
STACK ENDS
0BH
LABEL
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0016H
2
DUP(0)
DUP(0)
WORD
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,STACK
MOV SS,AX
MOV AX,FACT_INPUT
PUSH AX
CALL FACTORIAL
POP AX
HLT
FACTORIAL PROC NEAR

PUSHF
MOV BP,SP
MOV CX,[BP+04]
MOV AX,0001H
BACK:MUL CX
LOOP BACK
MOV [BP+04],AX
POPF
RET
FACTORIAL ENDP
CODE ENDS
END START
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Microprocessors and Interfacing

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Microprocessors and Interfacing

* For more details visit - www.worldwebsites8.blogspot.com &/ www.yoursww8.tk | Admin: N.Rajeev *

Microprocessors and Interfacing

* For more details visit - www.worldwebsites8.blogspot.com &/ www.yoursww8.tk | Admin: N.Rajeev *

Microprocessors and Interfacing

* For more details visit - www.worldwebsites8.blogspot.com &/ www.yoursww8.tk | Admin: N.Rajeev *

Microprocessors and Interfacing

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8085 Internal Architecture and Instruction set

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Arithmetic Logic Unit

The 8085/8080A-programming model includes six registers, one accumulator, and

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Program Counter (PC)

Stack Pointer (SP)

Memory Address Register

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General Purpose Registers

2. 8085 System Bus

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3. 8085 Pin description.

The following describes the function of each pin:

A6 - A1s (Output 3 State)

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AD0 - 7 (Input/Output 3state)

Data Bus Status. Encoded status of the bus cycle:

S1 can be used as an advanced R/W status.

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INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

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RESET OUT (Output)

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4. 8085 Functional Description

HALT, WRITE, READ, FETCH

Interrupt and Serial l/O

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Basic System Timing

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5. The 8085 Programming Model

Stack Pointer (SP)

Program Counter (PC)

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Program Counter (PC)

Stack Pointer (SP)

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6. The 8085 Addressing Modes

Data is provided through the registers.

7. Instruction Set Classification

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Data Transfer (Copy) Operations

1. Copy the contents of the register B into

3. Between a memory location and a 3. From a memory location 2000H to register

These instructions perform arithmetic operations such as addition, subtraction,

Addition - Any 8-bit number, or the contents of a register or the contents of a

Increment/Decrement - The 8-bit contents of a register or a memory location can be

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AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of