Академический Документы
Профессиональный Документы
Культура Документы
Features
Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
consumption
Up to 0.5ms instruction cycle with 8MHz system
clock at VDD=5V
output channel, with prescaler and 8-bit programmable timer counter, and supports active low or
active high output
Watchdog Timer
General Description
The device are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for
A/D applications that interface directly to analog signals,
such as those from sensors.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, HALT
Rev. 1.00
November 1, 2005
HT46R12
Block Diagram
In te rru p t
C ir c u it
T M R 0 C
T M R 0
P F D 0
IN T C
T M R 1 C
T M R 1
P F D 1
S ta c k
P ro g ra m
R O M
P ro g ra m
C o u n te r
M P
U
X
P P G 0 C
P P G T 0
P P G
P C
S T A T U S
A L U
Y S
T M R 0
fS
X
fS
Y S
Y S
/4
/4
W D T O S C
fS
P r e s c a le r
P o rt C
P C C
S h ifte r
T im in g
G e n e ra to r
fS
D a ta
M e m o ry
M U X
In s tr u c tio n
D e c o d e r
P r e s c a le r
T M R 1
U
W D T
In s tr u c tio n
R e g is te r
P C
P C
P C
P C
0 /C
1 /C
2 /C
3 /C
0 V
0 V
0 O
1 O
Y S
IN
IN
U
U
4 -C h a n n e l
A /D C o n v e rte r
O S C 2
O S
R E
V D
V S
S
C 1
P B
A C C
H A L T
E N /D IS
P o rt B
P B C
L V R
P A
P P G 0 C
P P G
P P G
P o rt A
P A C
P B 0 /A N 0 ~ P B 3 /A N 3
P A
P A
P A
P A
P A
0 ~ P
3 /P
4 /T
5 , P
7 /T
A 2
F D
M R 0
A 6
M R 1
Pin Assignment
P B 1 /A N 1
1
2 4
P B 2 /A N 2
P B 0 /A N 0
2
2 3
P B 3 /A N 3
P A 3 /P F D
3
2 2
P A 4 /T M R 0
P A 2
4
2 1
P A 5
P A 1
5
2 0
P A 6
P A 0
6
1 9
P A 7 /T M R 1
C 1 V IN +
7
1 8
O S C 2
O S C 1
C 1 V IN 8
1 7
P C 3 /C 1 O U T
9
1 6
V D D
P C 2 /C 0 O U T
1 0
1 5
R E S
V S S
1 1
1 4
P P G
P C 1 /C 0 V IN +
1 2
1 3
P C 0 /C 0 V IN -
H T 4 6 R 1 2
2 4 S K D IP -A /S O P -A
Rev. 1.00
November 1, 2005
HT46R12
Pin Description
Pin Name
PA0~PA2
PA3/PFD
PA4/TMR0
PA5, PA6
PA7/TMR1
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
I/O
Options
Description
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt
trigger input with or without pull-high resistor (determined by pull-high options: bit
option). The PA3, PA4 and PA7 are pin-shared with PFD, TMR0 and TMR1 respectively.
Pull-high
I/O
PC0/C0VINPC1/C0VIN+
PC2/C0OUT
PC3/C1OUT
C1VINC1VIN+
I/O
Pull-high
I/O or
Comparator
PPG
Programmable pulse generator output pin, the pin is floating when the power is
first turned on. The PPG0 output level (active low or active high) can be selected via configuration option.
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
RES
VDD
VSS
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
November 1, 2005
HT46R12
D.C. Characteristics
Ta=25C
Test Conditions
Symbol
Parameter
VDD
IDD1
IDD2
Min.
Typ.
Max.
Unit
Conditions
VDD
fSYS=4MHz
2.2
5.5
fSYS=8MHz
3.3
5.5
Operating Current
(Crystal OSC)
3V
No load, fSYS=4MHz
ADC disable
0.6
1.5
mA
mA
Operating Current
(RC OSC)
3V
0.8
1.5
mA
2.5
mA
mA
mA
10
mA
mA
mA
Operating Voltage
5V
5V
No load, fSYS=4MHz
ADC disable
IDD3
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
3V
Standby Current
(WDT Disabled)
3V
VIL1
0.3VDD
VIH1
0.7VDD
VDD
VIL2
0.4VDD
VIH2
0.9VDD
VDD
VLVR
2.7
3.3
IOL
3V
VOL=0.1VDD
mA
VOL=0.1VDD
10
20
mA
3V
VOH=0.9VDD
-2
-4
mA
5V
VOH=0.9VDD
-5
-10
mA
3V
20
60
100
kW
5V
10
30
50
kW
ISTB2
IOH
RPH
5V
No load, fSYS=8MHz
ADC disable
No load, system HALT
5V
No load, system HALT
5V
Pull-high Resistance
VAD
VDD
EAD
0.5
LSB
IADC
3V
0.5
mA
1.5
mA
VOS
-10
10
mV
VI
0.2
VDD-0.8
Rev. 1.00
5V
November 1, 2005
HT46R12
A.C. Characteristics
Ta=25C
Test Conditions
Symbol
Parameter
fSYS
fTIMER
tWDTOSC
System Clock
Timer I/P Frequency
(TMR0/TMR1)
Min.
Typ.
Max.
Unit
Conditions
VDD
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
2.2V~5.5V
4000
kHz
3.3V~5.5V
8000
kHz
3V
45
90
180
ms
5V
32
65
130
ms
ms
1024
*tSYS
tRES
tSST
tINT
ms
tAD
ms
tADC
76
tAD
tADCS
32
tAD
tCOMP
ms
Power-up or Wake-up
from HALT
Note: *tSYS=1/fSYS
Rev. 1.00
November 1, 2005
HT46R12
Functional Description
Execution Flow
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manages the program transfer by
loading the address corresponding to each instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are in-
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
Comparator 0 Interrupt
Comparator 1 Interrupt
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
Rev. 1.00
November 1, 2005
HT46R12
Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, interrupt entries, and is organized into
204814 bits, addressed by the program counter and table pointer.
Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 010H.
Location 000H
Location 014H
Location 014H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 014H
Location 004H
Location 004H is reserved for the Comparator 0 interrupt service program. If the Comparator 0 output pin is
activated, and If the interrupt is enabled and the stack
is not full, the program begins execution at location
004H.
Table location
Location 008H
Location 008H is reserved for the Comparator 1 interrupt service program. If the Comparator 1 output pin is
activated, and if the interrupt is enabled and the stack
is not full, the program begins execution at location
008H.
0 0 0 H
0 0 4 H
C o m p a r a to r 0 In te r r u p t S u b r o u tin e
0 0 8 H
0 0 C H
0 1 0 H
C o m p a r a to r 1 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 4 H
A /D
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 7
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
Rev. 1.00
November 1, 2005
HT46R12
00H. The general purpose data memory, addressed
from 28H to 7FH is used for data and control information
under instruction commands.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
Rev. 1.00
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
S p e c ia l P u r p o s e
D a ta M e m o ry
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
IN T C 1
1 F H
2 0 H
P P G 0 C
2 1 H
P P G T 0
2 2 H
2 3 H
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
7 F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(8 8 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
November 1, 2005
HT46R12
Indirect Addressing Register
Accumulator
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Interrupt
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
The ALU not only saves the results of a data operation but
also changes the status register.
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a
rotate through carry instruction.
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow
from the high nibble into the low nibble in subtraction, otherwise AC is cleared.
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set
by executing the HALT instruction.
TO
6, 7
November 1, 2005
HT46R12
(C1F; bit 5 of the INTC0), which is caused by a falling
edge transition from the Comparator 1 output. After the
interrupt is enabled, and the stack is not full, and the
C1F bit is set, a subroutine call to location 08H occurs.
The related interrupt request flag (C1F) is reset, and the
EMI bit is cleared to disable further maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 6 of the INTC0), caused by a timer
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
0CH will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further interrupts.
The Comparator 0 output Interrupt is initialized by setting the Comparator 0 output Interrupt request flag
(C0F; bit 4 of the INTC0), which is caused by a falling
edge transition from the Comparator 0 output. After the
interrupt is enabled, and the stack is not full, and the
C0F bit is set, a subroutine call to location 04H occurs.
The related interrupt request flag (C0F) is reset, and the
EMI bit is cleared to disable further maskable interrupts.
The Comparator 1 output Interrupt is initialized by setting the Comparator 1 output Interrupt request flag
Bit No.
Label
Function
EMI
EC0I
EC1I
ET0I
C0F
C1F
T0F
Bit No.
Label
Function
ET1I
EADI
2, 3
T1F
ADF
6, 7
Rev. 1.00
10
November 1, 2005
HT46R12
V
During the execution of an interrupt subroutine, other interrupt acknowledge are held until the RETI instruction
is executed or the EMI bit and the related interrupt control
bit are set to 1 (if the stack is not full). To return from the
interrupt subroutine, RET or RETI may be invoked.
RETI will set the EMI bit to enable an interrupt service,
but RET will not.
O S C 1
C r y s ta l O s c illa to r
08H
0CH
10H
14H
O S C 2
R C
O s c illa to r
04H
Once an internal WDT oscillator (RC oscillator with a period of 65ms/@5V normally) is selected, it is divided by
213, 214 , 215 or 216 (by options) to get the WDT time-out
period. The minimum WDT time-out period is about
600ms. This time-out period may vary with temperature,
VDD and process variations. By selection the WDT options, longer time-out periods can be realized. If the
WDT time-out is selected to fS/216, the maximum
time-out period is about 4.7s.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
Rev. 1.00
fS Y S /4
N M O S O p e n D r a in
System Oscillator
Priority Vector
O S C 1
O S C 2
D D
11
November 1, 2005
HT46R12
S y s te m
C lo c k /4
W D T
O S C
M a s k
o p tio n
s e le c t
fs
fs/2
D iv id e r
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
T im e - o u t R e s e t
fs/2 1 6
fs/2 1 5
fs/2 1 4
fs/2 1 3
Watchdog Timer
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after wake-up. If the
wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
unchanged.
WDT will be cleared and recounted again (if the WDT
Rev. 1.00
12
November 1, 2005
HT46R12
Reset
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Timer/Event Counter
Off
PPG Timer
Off
PPG output
Floating
Input/Output Ports
Input mode
Stack Pointer
RESET Conditions
V
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Note:
H A L T
O S C 1
S T
S S T T im e - o u t
C h ip
R e s e t
R E S
V D D
tS
W a rm
W D T
R E S
* Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
R e s e t
Reset Configuration
Rev. 1.00
13
November 1, 2005
HT46R12
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PCC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
INTC1
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
PPG0C
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PPGT0
Program
Counter
TBLP
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Note:
Rev. 1.00
14
November 1, 2005
HT46R12
Timer/Event Counter
Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may come from an external source or an internal clock source. An internal clock source comes from
fSYS. The Timer/Event Counter 1 contains an 8-bit programmable count-up counter and the clock may come
from an external source or an internal clock source. An
internal clock source comes from fSYS/4. The external
clock input allows the user to count external events,
measure time intervals or pulse widths, or to generate
an accurate time base.
The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an
external (TMR0, TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
internal selected clock source. The pulse width measurement mode can be used to count the high or low
level duration of the external signal (TMR0, TMR1), and
the counting is based on the internal selected clock
source.
In the event count or timer mode, the timer/event counter 0/1 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (T0F; bit 6 of the INTC0, T1F; bit 4 of the
INTC1).
Rev. 1.00
15
November 1, 2005
HT46R12
fS
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
D a ta b u s
T 0 P S C 2 ~ T 0 P S C 0
(1 /1 ~ 1 /1 2 8 )
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
P F D 0
Timer/Event Counter 0
fS
Y S
D a ta b u s
/4
T 1 M 1
T 1 M 0
T M R 1
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 1 E
8 - b it T im e r /E v e n t
C o u n te r (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T 1 M 1
T 1 M 0
T 1 O N
O v e r flo w
T o In te rru p t
P F D 1
Timer/Event Counter 1
P F D 0
P F D 1
M
U
T
X
P F D
P A 3 D a ta C T R L
P F D S o u r c e O p tio n
Bit No.
0
1
2
Label
T0PSC0
T0PSC1
T0PSC2
T0E
T0ON
6
7
T0M0
T0M1
Function
Define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable the timer counting
(0=disable; 1=enable)
Unused bit, read as 0
Define the operating mode (T0M1, T0M0)
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR0C (0EH) Register
Rev. 1.00
16
November 1, 2005
HT46R12
Bit No.
Label
0~2
T1E
T1ON
6
7
T1M0
T1M1
Function
Unused bit, read as 0
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting
(0= disable; 1= enable)
Unused bit, read as 0
Define the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
C 0 IN T
C 1 IN T
P C 1 /C 0 V IN +
D a ta b u s
C 0 V O
P C 0 /C 0 V IN -
P r e lo a d R e g is te r
P C 2 /C 0 O U T
P P G M o d e
C o n tro l
C 1 V IN +
C 1 V IN -
R e lo a d
P P G 0 T im e r O n /O ff
P P G 0 T im e r
C 1 V O
O v e r flo w
P P G 0 T im e r O ff
P 0 L E V ( O p tio n )
P C 3 /C 1 O U T
P P G 0 O u tp u t
P P G
P 0 fs
C M P 1 E N
C M P 0 E N
P r e s c a le r
fS
P 0 P S C 2
P 0 P S C 1
P 0 P S C 0
Y S
17
November 1, 2005
HT46R12
PPG0C control register
Bit No.
PPG0C (20H)
P0ST
P0RSEN
P0SPEN
P0PSC2
P0PSC1
P0PSC0
CMP1EN
CMP0EN
POR value
Description
Disable the Comparator 0. PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins.
CMP1EN
Description
The bits 4~2 of the PPG0 control register (PPG0C) can be used to define the pre-scaling stages of the PPG0 timer
counter clock.
PPG0C: PPG0 timer prescaler rate bits
P0PSC2
P0PSC1
P0PSC0
P0fS=fSYS
P0fS=fSYS/2
P0fS=fSYS/4
P0fS=fSYS/8
P0fS=fSYS/16
P0fS=fSYS/32
P0fS=fSYS/64
P0fS=fSYS/128
Rev. 1.00
18
November 1, 2005
HT46R12
The P0SPEN is the PPG0 timer OFF enable or disable bit using C0VO trigger input, if this bit is enabled, the PPG0
stopping input can be triggered by C0VO or PC2 falling edge. The P0RSEN is the PPG0 restarting enable or disable
bit using C1VO trigger input, if this bit is enabled, the PPG0 timer restarting input can be trigger by C1VO or PC3 falling edge. User can read the status of C0VO or C1VO by setting the PC2 or PC3 to be an input pin when comparator 0
or comparator 1 is enabled.
P0SPEN
Description
P0RSEN
Description
The P0ST is a software trigger bit, if this bit is set to 1, the PPG0 timer will start counting and this bit will be cleared
when the PPG timer overflow occurs, if this bit is cleared to 0, the PPG0 timer will stop counting, when the PPG
timer is counting and if a falling edge generates from C1VO, PC3 or a software control bit (P0ST) is set, the PPG0
timer counter is not affected, the trigger from C1V0, PC3 or P0ST is not useful. The P0ST can also be used as a status bit of PPG0 timer output.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control
register must write 1. The input source also depends
on the control register. If the control register bit is 1,
the input will read the pad state. If the control register bit
is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write
instruction.
Rev. 1.00
19
November 1, 2005
HT46R12
V
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
P U
P A
P A
P A
P A
P A
P B
P C
P C
P C
P C
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
Q
C K
W r ite D a ta R e g is te r
D D
0 ~ P
3 /P
4 /T
5 ~ P
7 /T
0 /A
0 /C
1 /C
2 /C
3 /C
A 2
F D
M R
A 6
M R
N 0
0 V
0 V
0 O
1 O
0
1
~ P
IN
IN
U
U
T
B 3 /A N 3
S
M
(P A 0 ) P A 3
(P P G 1 ) P F D
M
R e a d D a ta R e g is te r
S y s te m
U
X
E N
(P F D )
X
W a k e - u p ( P A o n ly )
O P 0 ~ O P 7
T M R 0 fo r P A 4 O n ly
T M R 1 fo r P A 7 O n ly
Input/Output Ports
Logical
Input
PA3
Note:
I/P
O/P
(Normal) (Normal)
I/P
(PFD)
Logical
Output
Note:
O/P
(PFD)
Logical
PFD
Input (Timer on)
A/D Converter
PFD
Frequency
OFF
OFF
ON
ON
PFD
fTMR/[2(M-N)]
Rev. 1.00
20
November 1, 2005
HT46R12
sion has started. In order to ensure that A/D conversion
is completed, the START should remain at 0 until the
EOCB is cleared to 0 (end of A/D conversion).
PB3
PB2
PB1
PB0
PB3
PB2
PB1
AN0
PB3
PB2
AN1
AN0
PB3
AN2
AN1
AN0
AN3
AN2
AN1
AN0
Port B Configuration
Once a PB line is selected as an analog input, the I/O
functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered on. The
EOCB bit (bit6 of the ADCR) is end of A/D conversion
flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the
conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D converBit No.
Label
Function
0
1
2~6
TEST
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption
EOCB
START Starts the A/D conversion. (010= start; 01= Reset A/D converter and set EOCB to 1)
ADCR (26H) Register
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL (24H)
D0
ADRH (25H)
D8
D7
D6
D5
D4
D3
D2
D1
Note:
Rev. 1.00
21
November 1, 2005
HT46R12
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
Rev. 1.00
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
22
November 1, 2005
HT46R12
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 7 6 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
d o n 't c a r e
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
L V R
3 .0 V
2 .2 V
tained for more than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and do not perform a reset function.
0 .9 V
O P R
5 .5 V
D D
5 .5 V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained for over 1ms, after 1ms delay, the device enters the
reset mode.
Rev. 1.00
23
November 1, 2005
HT46R12
Options
The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper system function.
Options
OSC type selection.
This option is to determine if an RC or crystal oscillator is chosen as system clock.
WDT source selection.
There are three types of selection: On-chip RC oscillator, instruction clock or disable the WDT.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear
the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed,
then WDT can be cleared.
WDT time-out period selection.
There are four types of selection: fS/213, fS/214, fS/215 and fS/216
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
chip from a HALT.
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PA0~PA7,
can be independently selected.
Pull-high selection.
This option is to decide whether a pull-high resistance is viable or not in the input mode of the I/O ports. PB0~PB3,
can be independently selected
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports.
PC0~PC3, can be independently selected
I/O pins share with other function selections.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
PFD selection.
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are generated by the timer overflow signals of the Timer/Event Counter 0, Timer/Event
Counter 1 respectively.
Low voltage reset selection.
Enable or disable LVR function.
PPG0 output level selection; P0LEV.
This option is to determine the PPG output level. Active Low or Active High selection. Disable this bit to 0, the PPG
output will be defined as an active high output, Enable this bit to 1, the PPG output will be defined as an active low
output
PPG0 timer start counting synchronized with clock; P0TSYN.
This option is to determine the PPG0 timer start counting is synchronized with input clock or not.
Rev. 1.00
24
November 1, 2005
HT46R12
Application Circuits
V
D D
0 .0 1 m F *
P A 0 ~ P A 2
V D D
P A 3 /P F D
1 0 0 k W
P A 4 /T M R 0
0 .1 m F
R E S
4 7 0 p F
P A 5 ~ P A 6
1 0 k W
P A 7 /T M R 1
R
P B 0 /A N 0
P B 3 /A N 3
O S C
V S S
fS
C 1
P C 0 /C 0 V IN P C 1 /C 0 V IN +
O S C 1
R 1
P C 3 /C 1 O U T
S e e R ig h t S id e
H T 4 6 R 1 2
Y S
/4
O S C 2
O S C 1
C 2
P C 2 /C 0 O U T
O S C 2
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 1
0 .1 m F *
O S C
C ir c u it
D D
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
O S C
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
* Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.00
25
November 1, 2005
HT46R12
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
1
1(1)
1
None
None
None
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Rev. 1.00
26
November 1, 2005
HT46R12
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
27
November 1, 2005
HT46R12
Instruction Definition
ADC A,[m]
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ACC+[m]+C
Affected flag(s)
TO
OV
AC
ADCM A,[m]
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ACC+[m]+C
Affected flag(s)
TO
OV
AC
ADD A,[m]
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ACC+[m]
Affected flag(s)
TO
OV
AC
ADD A,x
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ACC+x
Affected flag(s)
TO
OV
AC
ADDM A,[m]
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ACC+[m]
Affected flag(s)
Rev. 1.00
TO
OV
AC
28
November 1, 2005
HT46R12
AND A,[m]
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
Affected flag(s)
TO
OV
AC
AND A,x
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
Affected flag(s)
TO
OV
AC
ANDM A,[m]
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
Affected flag(s)
TO
OV
AC
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Affected flag(s)
TO
OV
AC
CLR [m]
Description
Operation
[m] 00H
Affected flag(s)
Rev. 1.00
TO
OV
AC
29
November 1, 2005
HT46R12
CLR [m].i
Description
Operation
[m].i 0
Affected flag(s)
TO
OV
AC
CLR WDT
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT 00H
PDF and TO 0
Affected flag(s)
TO
OV
AC
CLR WDT1
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT 00H*
PDF and TO 0*
Affected flag(s)
TO
OV
AC
0*
0*
CLR WDT2
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT 00H*
PDF and TO 0*
Affected flag(s)
TO
OV
AC
0*
0*
CPL [m]
Description
Each bit of the specified data memory is logically complemented (1s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] [m]
Affected flag(s)
Rev. 1.00
TO
OV
AC
30
November 1, 2005
HT46R12
CPLA [m]
Description
Each bit of the specified data memory is logically complemented (1s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC [m]
Affected flag(s)
TO
OV
AC
DAA [m]
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
Affected flag(s)
TO
OV
AC
DEC [m]
Description
Operation
[m] [m]-1
Affected flag(s)
TO
OV
AC
DECA [m]
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC [m]-1
Affected flag(s)
Rev. 1.00
TO
OV
AC
31
November 1, 2005
HT46R12
HALT
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Affected flag(s)
TO
OV
AC
INC [m]
Description
Operation
[m] [m]+1
Affected flag(s)
TO
OV
AC
INCA [m]
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC [m]+1
Affected flag(s)
TO
OV
AC
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Affected flag(s)
TO
OV
AC
MOV A,[m]
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC [m]
Affected flag(s)
Rev. 1.00
TO
OV
AC
32
November 1, 2005
HT46R12
MOV A,x
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC x
Affected flag(s)
TO
OV
AC
MOV [m],A
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ACC
Affected flag(s)
TO
OV
AC
NOP
No operation
Description
Operation
Affected flag(s)
TO
OV
AC
OR A,[m]
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
Affected flag(s)
TO
OV
AC
OR A,x
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ACC OR x
Affected flag(s)
TO
OV
AC
ORM A,[m]
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
33
November 1, 2005
HT46R12
RET
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Affected flag(s)
TO
OV
AC
RET A,x
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Affected flag(s)
TO
OV
AC
RETI
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Affected flag(s)
TO
OV
AC
RL [m]
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
Affected flag(s)
TO
OV
AC
RLA [m]
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
34
November 1, 2005
HT46R12
RLC [m]
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
Affected flag(s)
TO
OV
AC
RLCA [m]
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
Affected flag(s)
TO
OV
AC
RR [m]
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
Affected flag(s)
TO
OV
AC
RRA [m]
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
TO
OV
AC
RRC [m]
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
35
November 1, 2005
HT46R12
RRCA [m]
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
TO
OV
AC
SBC A,[m]
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ACC+[m]+C
Affected flag(s)
TO
OV
AC
SBCM A,[m]
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ACC+[m]+C
Affected flag(s)
TO
OV
AC
SDZ [m]
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
TO
OV
AC
SDZA [m]
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
36
November 1, 2005
HT46R12
SET [m]
Description
Operation
[m] FFH
Affected flag(s)
TO
OV
AC
SET [m]. i
Description
Operation
[m].i 1
Affected flag(s)
TO
OV
AC
SIZ [m]
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Affected flag(s)
TO
OV
AC
SIZA [m]
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
TO
OV
AC
SNZ [m].i
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i0
Affected flag(s)
Rev. 1.00
TO
OV
AC
37
November 1, 2005
HT46R12
SUB A,[m]
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ACC+[m]+1
Affected flag(s)
TO
OV
AC
SUBM A,[m]
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ACC+[m]+1
Affected flag(s)
TO
OV
AC
SUB A,x
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ACC+x+1
Affected flag(s)
TO
OV
AC
SWAP [m]
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 [m].7~[m].4
Affected flag(s)
TO
OV
AC
SWAPA [m]
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 [m].7~[m].4
ACC.7~ACC.4 [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
OV
AC
38
November 1, 2005
HT46R12
SZ [m]
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
OV
AC
SZA [m]
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
OV
AC
SZ [m].i
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
OV
AC
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
Affected flag(s)
TO
OV
AC
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
39
November 1, 2005
HT46R12
XOR A,[m]
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
Affected flag(s)
TO
OV
AC
XORM A,[m]
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
Affected flag(s)
TO
OV
AC
XOR A,x
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
Affected flag(s)
Rev. 1.00
TO
OV
AC
40
November 1, 2005
HT46R12
Package Information
24-pin SKDIP (300mil) Outline Dimensions
2 4
1 3
1 2
H
C
D
E
Symbol
Rev. 1.00
a
G
Dimensions in mil
Min.
Nom.
Max.
1235
1265
255
265
125
135
125
145
16
20
50
70
100
295
315
345
360
15
41
November 1, 2005
HT46R12
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
394
419
290
300
14
20
590
614
92
104
50
32
38
12
10
42
November 1, 2005
HT46R12
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
C
B
T 1
SOP 24W
Symbol
Description
Dimensions in mm
3301.0
621.5
13.0+0.5
-0.2
2.00.5
T1
24.8+0.3
-0.2
T2
Reel Thickness
30.20.2
Rev. 1.00
43
November 1, 2005
HT46R12
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
K 0
A 0
SOP 24W
Symbol
Description
Dimensions in mm
24.00.3
Cavity Pitch
12.00.1
Perforation Position
1.750.1
11.50.1
Perforation Diameter
1.55+0.1
D1
1.5+0.25
P0
Perforation Pitch
4.00.1
P1
2.00.1
A0
Cavity Length
10.90.1
B0
Cavity Width
15.90.1
K0
Cavity Depth
3.10.1
Rev. 1.00
0.350.05
21.3
44
November 1, 2005
HT46R12
Rev. 1.00
45
November 1, 2005