FSK Demodulation on DSP

Milan Brejl
Motorola Czech Systems Laboratories,
1. mje 1009, 756 61 Ronov p.Radh., Czech Republic,
E-mail: Milan.Brejl@motorola.com

Abstract: The article discusses FSK [1] demodulation algorithms suitable for an

implementation on a DSP. The algorithms are based on direct DFT (Discrete

Fourier Transformation) values computation. Their behavior in different noisy
environments is simulated. The implementation of this algorithm on a power-line
modem application is briefly described.
I. INTRODUCTION
The power of today's digital signal processors [2] enables implementation of digital
modulation/demodulation algorithms in software. Advanced demodulation techniques require
significantly higher computational power but also bring great improvement to the error ratio in
noisy environments.
The subject of this article is a discussion about FSK demodulation algorithms that are
designed for maximal noise proof and with respect to implementation on a DSP.
II. THEORY
DFT computes the continuous frequency function of a given discrete-time signal. Here,
DFT is used to compute the values F0 and F1 of a frequency function at only two discrete
points - at frequencies f0 and f1. f0 is the frequency of a signal element corresponding to bit 0
and f1 is the frequency of a signal element corresponding to bit 1.
N
1

F0  s
n  b e
j; 0n ,

(1)

F1  s
n  b e
j;1n

(2)

n0
N
1
n0

where

f0
,
(3)
fs
f
; 1  2 1
(4)
fs
and s(n) is the signal element sample, fs is the sampling frequency.
Comparison of F0 and F1 decides if the signal element transfers bit 0 or bit 1. Lets
establish a binary vector MSG as the transmitted message. Then
MSG
j   F1  F0
(5)
where j is the index of the actual signal element and the corresponding bit.
Further solutions are required to establish synchronization to the signal element within
the incoming FSK signal and to suppress the noise influence.
; 0  2

0.3
0.25

0.2
Spectral
Power
Density 0.15
0.1

0.05
0
150

200

250

300
Window No.

350

400

450

Figure 1. The course of |F0|2 (solid line) and |F1|2 (dotted line) - variant 3:1. The data burst starts approx. at the
window No. 300 where the start sequence is recognizable.

In correspondence with the rule of a digital signal minimal frequency differentiation, the
signal element length T is chosen:
1
T
(6)
f1
f 0
to obtain a maximum bit rate. Than
(7)
N  f sT
The incoming signal is windowed by a rectangular window of length N. The rectangular
window shape and the window length N are necessary to accomplish maximum frequency
differentiation.

Lets establish an index i for indexing each signal window and the corresponding
variables.
The computation of F0(i) and F1(i) and consequential comparison is done for each signal
window:
b
i   F1
i   F0
i 
(8)
The approximate beginning of the data burst is set from the signal window where the
instantaneous value SB(i) crosses the doubled value SA(i):
S B
i   2S A
i 
(9)
SB(i) is a short-term sliding average of the sum of F0 and F1. SA(i) is a long-term sliding
average of the sum of F0 and F1. The sliding averages SA(i) and SB(i) are computed in each step
as follows:
S B
i   O B S B
i  1

1  O B >F0
i 
F1
i @ ,
(10)

if S B
i   2S A
i  1 then

S A
i   OA S A
i  1

1  O A >F0
i 
F1
i @
(11)
otherwise SA is not updated: SA(i) = SA(i-1). O and O are Forgetting Factors less than but
close to 1. O > O makes the SA long-term sliding average and SB the short-term one.
In order to achieve synchronization between the window and the signal element, a
synchronization byte is transmitted in the head of each data burst. The synchronization byte is
formed by a bit sequence [1 0 1 0 0 1 0 1]. The transmitter and receiver clocks are supposed to
be precise enough to maintain this synchronization during the whole data burst.

The best fit to the synchronization sequence is computed as the position where the
divergence between sequence b of the F0(i), F1(i) comparison results and the interpolated
synchronization bit sequence is minimal
idx  index of min
SYN 
(12)
where
SYN
i  
b XOR >1100110000110011@
(13)

in the case of a 50% window overlap (in this case the synchronization bit sequence has to be
interpolated 2:1).
Let's discuss three of possible variants of implementing the FSK demodulation algorithm.

Continuous variant
The signal window is moved by 1 sample. The synchronization bit sequence has to be
interpolated in the ratio N:1. Then, the repeated computation of (12) is very strenuous but the
result of synchronization is very precise. After this synchronization, the signal can be
windowed accurately with the signal element positions and each of the F0(i) and F1(i)
comparison results can be directly added to MSG.
Variant 3:1
The incoming signal is windowed with a 33% overlap. The synchronization to the
start-bit sequence sets triplets of windows corresponding to 1 signal element. When 2 or 3 of
the comparison results b(i) within this triplet indicate bit 1, bit 1 is added to the MSG output
sequence. Otherwise, (when 2 or 3 indicate bit 0) bit 0 is added.
Variant 2:1
The incoming signal is windowed with a 50% overlap. The synchronization to the start
bit sequence sets pairs of windows corresponding to 1 signal element. When both of the
comparison results b(i) within this pair indicate the same bit, this one is added to the MSG
output sequence. When each b(i) indicates a different bit, the decision if [1 0] will be resolved
as 1 or 0 in MSG and [0 1] as 0 or 1 is based on the following idea: One of the signal windows
within the pair can overlap the neighbor signal element by a minor but significant part. In a
noisy environment this can cause the b(i) of this window to sometimes indicate that the bit was
transmitted
by
the
0
neighbor signal element
instead
of
the
10
corresponding
signal
element.
The
decision
]
%
[ 20
about which one of the
bit
et
error
windows within the pair is
ar
rate
r
o
the one more significantly
[%]
rr 30
eti
overlapping the neighbor
b
signal element, can be
40
found
from
the
comparison of SYN(idx-1)
50
10
5
0
-5
-10
-15
-20
-25
-30
and
SYN(idx+1).
If
SNR [dB]
SYN(idx-1) > SYN(idx+1)
Figure 2. Bit-error rates of Continues Variant (solid line), Variant 3:1
then [1 0] is resolved as 0
(dotted line) and Variant 2:1 (dashed line) in comparison to quadrature
and [0 1] as 1.
demodulator [3] (dash-dot line).

III. RESULTS
The Figure 2 shows simulation results. Three discussed variants of FSK demodulation
based on DFT and the traditional quadrature demodulation [3] were tested during an escalating
signal-to-noise ratio (SNR). The DFT-base demodulation gives a 15dB rise to the SNR.
IV. DATA RECEPTION ALGORITHM MODEL
The model of the whole data reception algorithm is illustrated in Figure 3.
INITIALIZATION

No start
sequence

No data

synchronization to start sequence

Data burst
received

No data - false
reception

waiting for data burst start

data reception
decimation to out 1/0 sequence

Figure 3. Model of data reception algorithm

V. IMPLEMENTATION
The algorithm is primarily devoted to a power-line modem application with
preconditions f0 = 100 kHz, f1 = 110 kHz, fs = 500 kHz. Power-lines are a very noisy
environment with heavy impulse interference. The data reception and demodulation algorithm
together with a control application (including bit-error checking, communication routines, etc.)
is running on a single low-cost Motorola DSP 56F801 [2].
VI. CONCLUSION
Three FSK demodulation algorithms based on the DFT were described and discussed.
These algorithms together with the described signal detection and synchronization procedures
form the basis for a single-chip modem implementation on a DSP. This approach has the
following important advantages:
N The number of hardware components is reduced to a minimum, replacing them by pieces of
software,
N The frequency of a signal element can be determined by a mathematical computation (DFT)
that is an ultimate solution for a noisy environment, and
N The output of the algorithm is the transferred message - not only a binary signal.
REFERENCES
[1] Fuquin Xiong: Digital Modulation Techniques. Artech House, 2000. ISBN 0-89006-970-0.
[2] DSP 56800 Family Manual, Motorola, Inc., 2000
[3] FSK Modulation and Demodulation With the MSP430 Microcontroller, Application
Report, Texas Instruments Inc., 1998.