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FACULTY OF ENGINEERING AND TECHNOLOGY

MULTIMEDIA UNIVERSITY

LAB SHEET (ASSIGNMENT-1)


DIGITAL SYSTEMS
EEE3156
TRIMESTER 1 (2015/2016)

DS1: Digital System Design Laboratory 1

DS2: Digital System Design Laboratory 2

EEE3156: Digital Systems

EEE3156: Digital Systems


Digital System Design Laboratory
1.

Objective

1. To sharpen students design skills, which after completing the two lab phases, students
will be able to design some digital system blocks based on given specifications.
2. To expose students to the EDA (Electronic Design Automation) tool in designing digital
system. During the course of the design labs, students will be going through digital
systems design flow, from design entry, verification, until implementation on FPGA
development kit.

2.

Introduction

In DS1, students are asked to design and simulate some digital circuits using VHDL
language. In DS2, students are asked to design, simulate, and implement some designs on
FPGA development kit.
Not all the detailed procedures on how to design the system and use the EDA tool are given
in the lab sheet. Students will have to explore themselves in certain extends in the process.
This will also sharpen students design skills and self-learning capability, as engineers are not
procedure-followers.

3.

Introduction to Quartus II

The Altera Quartus II CAD software makes it easy to implement a desired logic circuit by
using a programmable logic device, such as a field-programmable gate array (FPGA) chip. A
typical FPGA CAD flow is illustrated in Figure 1.
It involves the following basic steps:

Design Entry the desired circuit is specified either by using a hardware description
language, such as Verilog or VHDL, or by means of a schematic diagram
Synthesis the CAD Synthesis tool synthesizes the circuit into a netlist that gives the
logic elements (LEs) needed to realize the circuit and the connections between the LEs
Functional Simulation the synthesized circuit is tested to verify its functional
correctness; the simulation does not take into account any timing issues
Fitting the CAD Fitter tool determines the placement of the LEs defined in the netlist
into the LEs in an actual FPGA chip; it also chooses routing wires in the chip to make the
required connections between specific LEs
Timing Analysis propagation delays along the various paths in the fitted circuit are
analyzed to provide an indication of the expected performance of the circuit
Timing Simulation the fitted circuit is tested to verify both its functional correctness
and timing
Programming and Configuration the designed circuit is implemented in a physical
FPGA chip by programming the configuration switches that configure the LEs and
establish the required wiring connections

EEE3156: Digital Systems

Figure 1. Typical CAD flow

3.1

Getting Started

Each logic circuit, or subcircuit, being designed with Quartus II software is called a project.
The software works on one project at a time and keeps all information for that project in a
single directory (folder) in the file system. To begin a new logic circuit design, the first step
is to create a directory to hold its files.
Create a new folder and name it, say as mylab1.

3.2

Starting a New Project

Start the Quartus II software. To start working on a new design we first have to define a new
design project. Select File > New Project Wizard to reach a window that indicates a new
project wizard.

EEE3156: Digital Systems

Set the working directory at the folder you just created. The project must have a name, which
is usually the same as the top-level design entity that will be included in the project. For
example, write apex20k as the name for both the project and the top-level entity.
Click Next twice until you reach a window as shown in Figure 2. Here, we can specify the
type of device in which the designed circuit will be implemented. Choose APEXTM as the
target device family. From the list of available devices, choose the device called
EP20K200EFC484-2X. We will use default settings for the remaining of the wizard, press
Finish to create the new project.

Figure 2. Choose the device family and a specific device.

3.3

Editing VHDL File

To start creating a VHDL design, select File > New from menu and choose VHDL File, and
click OK. This opens the Text Editor window. The first step is to specify a name for the file
that will be created. Select File > Save As to open the pop-up box. Make sure the box
labeled Save as type chooses VHDL File. In the box labeled File name, type apex20k.
Make sure the checkbox Add file to current project is ticked. Click Save.
Most of the commands available in the Text Editor are self-explanatory. The text editor has
syntax highlight and auto text indent features.

EEE3156: Digital Systems

3.3.1 Using VHDL Templates


The syntax of VHDL code is sometimes difficult for a designer to remember. To help with
this issue, the Text Editor provides a collection of VHDL templates. The templates provide
examples of various types of VHDL statements, such as an entity declaration, a process
statement, and assignment statements. It is worthwhile to browse through the templates by
selecting Edit > Insert Template > VHDL to become familiar with this resource.

EEE3156: Digital Systems

4.

Digital System Design Lab 1

4.1

Equipment Required

PC installed with Altera Quartus II software.

4.2

Seven Segment Display Decoder

Given a 4-bit unsigned binary value, decode it into 7-segment display codes. Given that the 7
segments are organized in gfedcba bit order, where the segment orientation is shown in
Figure 3.

a
f g b
e

c
d

Figure 3: 7-segment orientation


Also, the segments are driven by active-low signals:
0 = LED on
1 = LED off
The 7-segment decode table is given in Table 1. The task is to write the VHDL code that
inputs a 4-bit unsigned binary value and outputs a 7-bit decoded value according to the table.
Table 1: 7-Segment Decoder Table
Digit
0
1
2
3
4
5
6
7

gfedcba
1000000
1111001
0100100
0110000
0011001
0010010
0000010
1111000

Digit
8
9
A
b
c
d
E
F

gfedcba
0000000
0010000
0001000
0000011
1000110
0100001
0000110
0001110

EEE3156: Digital Systems

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity apex20k is
port (
Digit : in unsigned(3 downto 0);
LED7SEG : out unsigned(6 downto 0)
);
end apex20k;
architecture apex20k_arch of apex20k is
begin
-- 7 segment display decoder

Libraries and
packages used are
stated here.
Entity body declares
in/out signals of a
design.
Architecture body
defines the function
of a design.
This is a comment
after two dashes.

You need to write the decoders


code here.
end apex20k_arch;
Refer to the VHDL code above, copy the code to the opened VHDL file. You will need to
add the code to implement the 7-segment decoder. Use one of the following methods by
referring to the VHDL templates in Quartus II:

Selected Signal Assignment Statement


Conditional Signal Assignment

4.2.1 Compilation
After writing your code, you may compile your code by selecting Processing > Start
Compilation, or by clicking the toolbar icon . As the compilation moves through various
stages, its progress is reported in the Status window on the left side. This window displays
the compilation progress as a project is being compiled. In the Messages window at the
bottom, various messages are displayed. In case of errors, there will be appropriate messages
given.
When the compilation is finished, a compilation report is produced. A window showing this
report, is also displayed automatically. The window can be closed, and reopened at any time
either by selecting Processing > Compilation Report or by clicking on the icon
.
4.2.2 Errors
Quartus II software displays messages produced during compilation in the Messages window.
If your VHDL design file contains errors, the compilation will be unsuccessful. In this case a
message corresponding to each error found will be displayed in the Messages window.
Double-clicking on an error message will highlight the offending statement in the VHDL
code in the Text Editor window. Similarly, the Compiler may display some warning
messages. Their details can be explored in the same way as in the case of error messages. The

EEE3156: Digital Systems

user can obtain more information about a specific error or warning message by selecting the
message and pressing the F1 function key.
4.2.3 Using the RTL Viewer
Quartus II software includes a tool that can display a schematic diagram of the designed
circuit. The display is at the Register Transfer Level of detail, and the tool is called the RTL
Viewer. Click Tools > RTL Viewer, to reach the viewer.
The RTL viewer can also be opened from the Project Navigator window. Right click on
the apex20k in the Hierarchy view and choose Locate > Locate in RTL Viewer from the
pop-up menu that appears. This causes Quartus II software to display the RTL view of the
circuit.
The RTL viewer is a useful tool. It can be used effectively to facilitate the development of
VHDL code for a circuit that is being designed. It provides a pictorial feedback to the
designer, which gives an indication of the structure of the circuit that the code will produce.
Viewing the pictures makes it easy to spot missing elements, wrong connections, and other
typical errors that one makes early in the design process.
4.2.4 Simulation
Simulation allows you to test a design thoroughly to ensure that it responds correctly in every
possible situation before you program or configure a device. Before running a simulation,
you must specify input vectors as the stimuli for the Quartus II Simulator.
You can create Vector Waveform Files (.vwf) as stimuli for simulation. VWFs describe the
simulation input vectors and simulation outputs as graphical waveforms. To create a VWF,
follow these steps:
1. Choose File > New.
2. To select VWF as the file type, click the Other Files tab and select Vector Waveform
File.
3. Click OK. The Waveform Editor opens, displaying an empty waveform file.
4. To change the end time for the simulation, select Edit > End Time and specify the end
time say as 2000ns.
5. To change the grid size of the display, select Edit > Grid Size and specify the grid size
say as 100ns.
You can complete the VWF by entering the input node waveforms and the desired output
node waveforms. To add the input and output nodes, follow these steps:
1. To find the node names you want to add to the file, right click at the left portion of the
window, select Insert Node or Bus from the pop-up menu.
2. Insert Node or Bus dialog box appears, click on Node Finder button.
3. Node Finder dialog box appears, to find the nodes you want to add to the VWF, set the
Filter as Pins: all and click List.
4. In the Nodes Found list, select the signals desired, for example, Digit and LED7SEG,
and click > button. Selected nodes will appear at the right portion of the dialog.
5. Click OK to exit from the dialogs. Now you should see the selected nodes appearing at
the waveform window.
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You create the input vectors for simulation by specifying the logic levels of the node
waveforms. To edit the input node waveform, first highlight the signal or portion of signal by
dragging the mouse on the waveform window, then use one of the various toolbar buttons
available to edit the waveform. You should explore yourself on various ways of creating
input waveforms using the toolbar. An example is shown in Figure 4. Make sure you save the
VWF file after creating the input vectors.

Figure 4: Input vector waveform


You can then run the simulation by clicking on Start Simulation toolbar . The Simulator
immediately begins to simulate the design using the vector source file. The simulation result
is shown, where you can inspect the output waveforms whether they are correct. To see the
entire waveform, choose View > Fit in Window. You can also use the Zoom tool
or
Full Screen
toolbars to inspect the waveforms in a clearer and larger view area.
Verify that the output values are correct for all the 16 combinations of input signal.
Special note:
Simulator settings can be changed allowing you to control the type of simulation to run, the
time period covered by the simulation, the source of vector stimuli, and other options. To
specify Simulator settings, perform the following steps:
1. Choose Assignments > Settings. The Settings dialog box appears.
2. In the Category list, select Simulator Settings.
3. In the Simulation mode list, you can choose to various simulate modes, by default is
Timing mode.
4. The Simulation input box, is where the simulator gets the input stimuli file. When you
wish to simulate the same design with a different input vectors, change the simulation
input file here.
5. Simulation period allows you to specify the simulation end time. By default, Run
simulation until all vector stimuli are used is selected.

EEE3156: Digital Systems

4.3

1-Digit BCD Up Counter

VHDL code below shows the design of a 1-digit BCD up counter.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity bcdcounter1 is
port (
RST : in std_logic;
Digit1_O : out unsigned(3 downto 0);
CLK : in std_logic
);
end bcdcounter1;
architecture bcdcounter1_arch of bcdcounter1 is
signal Digit1 : unsigned(3 downto 0);
Internal signal
declaration.
begin
-- BCD UP counter
These 2 lines generate
process (CLK,RST)
reset signal for the flipbegin
flops.
if RST = '0' then
Digit1 <= (others=>'0');
With this line, the assigned
elsif rising_edge(CLK) then
signals, Digit1 in this case,
if Digit1 < 9 then
will infer flip-flops.
Digit1 <= Digit1 + 1;
else
Digit1 <= (others=>'0');
end if;
end if;
Output signal cannot be read
end process;
internally, thus internal signal
Digit1_O <= Digit1;
end bcdcounter1_arch;

Digit1 is used internal, and


this line connects the Digit1 to
output as Digit1_O.

Create a new VHDL file named as bcdcounter1.vhd, make sure to add it to the project. Enter
the VHDL code as above. Since earlier the project was set to other design as top-level entity,
you need to change it to this new design. At the Project Navigator window, click the Files
tab, right click on the new VHDL file and click Set as Top-Level Entity. Compile the
design.
After compilation, you may see a warning stating that it found pins functioning as undefined
clocks. Since the new design uses a clock input, the clock frequency should be set for use by
the Fitter and Timing Analyzer to perform their jobs. In this case, set the clock frequency to
say 100 MHz. Invoke Assignments > Timing Analysis Settings. Click on Individual
Clocks button, and click New button in the new dialog appeared. Give the Clock settings

EEE3156: Digital Systems

name as clock and Applies to node as CLK. Set the Required fmax as 100 MHz. Then
rerun the compilation. The warning should be cleared by then.
Create a new vector waveform file and design the input test vectors accordingly so that the
functionality of the counter can be verified. You should change the simulation end time and
grid size accordingly as well. Also, make sure you set the simulation input file to the new vwf
file at the Simulator Settings page as stated in the special note.
Verify that the counter functions correctly, including the reset signal.

4.4

2-Digit BCD Up Counter

Based on the VHDL code of the 1-digit BCD up counter, design a 2-digit BCD up counter.
Your design should now contain 2 output signals: Digit10_O and Digit1_O. Design, compile,
and simulate the new design accordingly.
Tips: Add some nested ifelse statements to create the design.

4.5

2-Digit BCD Up/Down Counter

Based on the VHDL code from the above design, modify it to become a 2-digit BCD
up/down counter, where there is an additional input signal, DIR, which controls the direction
of counter, i.e. 1 for counting up and 0 for counting down. Design, compile, and simulate
the design.
Tips: Similarly, add some nested ifelse statements to create the design.

4.6

BCD Down Counter with Synchronous Load

Based on one of the previous designs, write a 2-digit BCD down counter to count decimal
values. After counting to 00, the counter will stop counting. This time, there are two
additional input signals:

LOAD: A synchronous control signal to cause the BCD counter to reload a new value to
the counter when it is high and start down counting after it goes low.
LOADVALUE: An 8-bit value to be loaded to the counter after the LOAD signal is
asserted.

4.7

ASSIGNMENT 1 (10%): Seven Segment Display Decoder

This is an individual assignment. Based on this lab-sheet, complete the laboratory practice on
4.2. Write a simple report which contain following items. Due date 13th July 2015.
- Brief Introduction
- RTL View and Logic Diagram
- Waveform Results and Discussion
- Conclusion

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5.

Digital System Design Lab 2

In this second lab, you will be using the Altera Nios Development Kit, APEX Edition to
implement designs into the FPGA on this board.

5.1
1.
2.
3.
4.
5.

Equipment Required

PC with LPT port installed with Altera Quartus II software.


Altera Nios Development Kit, APEX Edition
Altera ByteBlaster II download cable
9-V DC power supply
SC1602D LCD Module

5.2

Setting Up the Board

Figure 5: Nios Development Board


1. Connect one end of the ByteBlaster II download cable to the PCs LPT port and the other
end to the JTAG connector (JP3). Pin 1 on JP3 must connect to pin 1 of the download
cable.
2. Connect the 14-pin LCD module ribbon cable to JP12. Pin 1 on JP12 must connect to pin
1 on the LCD module.

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EEE3156: Digital Systems

3. Turn SW8 (Apex JTAG) to CONNECT (left), while SW9 (Max JTAG) and SW10
(PMC JTAG) to BYPASS (right). This is for use during programming the board, where
only the Apex FPGA will be programmed.
4. Connect the 9-V DC power-supply to J1 and plug the other end to an outlet.
5. All the other jumpers and connectors should be left unconnected.
6. Make sure the connections are all correct, and turn on the power. The Altera FPGA is
configured with a reference design. Verify that the following board indicators are
functioning properly:
The LED7 labeled POWER is on.
The LED3 is on, indicating that the FPGA is configured.
2 segments for each 7-segment LED are illuminated.
The first row of the LCD module displays all black squares.
7. Turn off the power. You will only need to use the board after creating a design using
Quartus II.

5.3

Basic I/O Testing

In this section, you will need to establish and test the basic I/O connections from the FPGA to
8-bit DIP switch (SW1), push-button switches (SW4, SW5, SW6, and SW7), dual 7-segment
LED display (D1), and LEDs (LED1 and LED2). To get started, you are provided with the
following code template to work on.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity apex20k is
port (
SW1 : in unsigned(7 downto 0);
SW4 : in std_logic;
SW5 : in std_logic;
SW6 : in std_logic;
SW7 : in std_logic;
LED7SEG1 : out unsigned(7 downto 0); -- For Digit10
LED7SEG2 : out unsigned(7 downto 0); -- For Digit1
LED1 : out std_logic;
LED2 : out std_logic;
CLK : in std_logic
);
end apex20k;
architecture apex20k_arch of apex20k is
signal clkdiv
: unsigned(24 downto 0);
signal CLK1Hz : std_logic;
signal Digit10, Digit1 : unsigned(3 downto 0);
begin
-- Divide the master clock (33.333Mhz)
-- to lower frequency

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process (CLK)
begin
if rising_edge(CLK) then
clkdiv <= clkdiv + 1;
end if;
end process;
-- F=0.9934Hz, T=1.0066s, for LED blinking
CLK1Hz <= clkdiv(24);
-- 7-segment display decoder
You need to write two sets of the 7-segment display decoders here for the two
7-segment displays. Inputs are Digit10 and Digit1 for decoded outputs
LED7SEG1 and LED7SEG2 respectively.
-- Testing
Digit1 <= ...
Digit10 <= ...
LED1 <= ...
LED2 <= ...
LED7SEG1(7) <= ...
LED7SEG2(7) <= ...

Write signal
assignment
statements
for each of
these signals.

end apex20k_arch;
To demonstrate that these I/Os function correctly, design VHDL code to do the following
tasks:
Display the 8-bit DIP switchs binary value in hexadecimal form at the dual 7-segment
display.
Connect SW6 and SW7 to LED2 and LED1 respectively. Make LED turns on when
switch is pressed. Note that the switches are active low, the APEX device will see a logic0 when each switch is pressed. The LEDs are active high. Each LED will light-up when
the APEX device drives a logic-1 on its controlling output.
Make DP (decimal point) LEDs at the 7-segment displays blink with 1Hz frequency when
SW5 and SW4 is pressed respectively. The DP LEDs are LED7SEG1(7) and
LED7SEG2(7) signals that are grouped together with the other 7 segments.
In the code template, a clock divider is provided to obtain the desired 1Hz frequency,
CLK1Hz, from the input frequency. You need to write some signal assignment statements to
accomplish the tasks. You may need to use some logical operators like not, and, or, nand,
nor, xor, xnor, to form expressions. You may combine with the use of conditional signal
assignment as well at your choice. Simulate the design if you are not confident with the
correctness of the code.
5.3.1 Preparing to Program the APEX Device
After developing the code, you need to do a number of things as described below before you
can proceed to program and test on the real hardware. Edit the clock setting of signal CLK to
33.333MHz, this is the oscillator frequency of the board.

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Make sure the device selected is EP20K200EFC484-2X, since you are going to program
your design into the device. This can be checked at the Project Navigator windows
Hierarchy tab. If the wrong device is selected, right click on the device name and click
Device, then choose the correct device.
Attention! The next very important thing to perform is pin assignment. This is to link the I/O
signals in VHDL code to the actual pins on the FPGA, where these pins are connected to
various components on the board. Before you can do this, you need to invoke the toolbar icon
, Start Analysis & Synthesis. The compiler checks the design files for syntax and
semantic errors, synthesizes the logic, and generates a project database. By this, the I/O pin
information will be obtained by the tool. You can then invoke Assignments > Pins to start
assigning pins. The I/O signals used in the VHDL code are listed. Double click on the
Location column next to the CLK signal, scroll down the list of pins and select PIN_L6.
This is the pin where the oscillator is connected.
Table 2: Pin assignment
Node Name
CLK
LED1
LED2
LED7SEG1[0]
LED7SEG1[1]
LED7SEG1[2]
LED7SEG1[3]
LED7SEG1[4]
LED7SEG1[5]
LED7SEG1[6]
LED7SEG1[7]
LED7SEG2[0]
LED7SEG2[1]
LED7SEG2[2]
LED7SEG2[3]
LED7SEG2[4]

Location
PIN_L6
PIN_T18
PIN_T19
PIN_R11
PIN_U11
PIN_Y7
PIN_V8
PIN_Y17
PIN_V18
PIN_V17
PIN_D18
PIN_R10
PIN_T11
PIN_U8
PIN_W18
PIN_Y18

Node Name
LED7SEG2[5]
LED7SEG2[6]
LED7SEG2[7]
SW1[0]
SW1[1]
SW1[2]
SW1[3]
SW1[4]
SW1[5]
SW1[6]
SW1[7]
SW4
SW5
SW6
SW7

Location
PIN_U18
PIN_W17
PIN_C18
PIN_Y10
PIN_U12
PIN_P11
PIN_V10
PIN_U10
PIN_T10
PIN_U9
PIN_V9
PIN_Y9
PIN_T9
PIN_Y8
PIN_W9

** You must double check to ensure all the pins assigned are correct! Wrong pin
assignment might damage the board after programming.
After finished assigning the pins, compile the project. Check for errors or warnings.
5.3.2 Program the Device
After a successful compilation, you can download configuration data into the device through
the ByteBlaster II download cable.
If this is the first time the computer is setup for programming Altera devices. You need to
install driver for the download cable. Follow steps involved for various different operating
systems and download cables accordingly as detailed in the following web site:
http://www.altera.com/support/software/drivers/
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To program the device, follow these steps:


1. Select Tools > Programmer, or click the toolbar icon . The Programmer window
automatically lists the apex20k.sof file as the current programming file.
2. In the Mode list of the Programmer window, select JTAG.
3. If at the right of the Hardware Setup button shows No Hardware, click the
Hardware Setup button. A dialog box appears.
4. Click Add Hardware. In the Hardware type list, select ByteBlasterMV or
ByteBlaster II.
5. Click OK and then click Close to exit from the hardware setup dialogs.
6. Check the Program/Configure checkbox.
7. Save the settings by selecting File > Save.
8. Now you can start configuring the device, turn on the power supply for the board.
9. Click Start Button. If all the hardware and software setups are correct, you should see the
progress bar moves to 100%, indicating a successful configuration has been done.
Now you may check the functionality of your design on the board. Press the push-button
switches (SW4 to SW7) and change the DIP switch positions, but do not press on SW2 and
SW3, the configuration would be reset back to reference design. Observe how the LEDs and
7-segment displays respond. Verify whether they react correctly as described in the tasks
given.

5.4

2-Digit BCD Up/Down Counter

Based on the code above and adding the code that you have developed from lab 1, implement
a 2-digit BCD up/down counter on the board. Use SW1(0) as the direction signal input. The
counting rate should be in seconds.

5.5

LCD Display

In this section, you will need to use the LCD module to display a string of characters, Hello
world.
You are supplied with the VHDL module of an LCD driver, which is also listed in Appendix.
The I/O signals of the LCD driver and their functions are listed in Table 3, and the timing
diagram of the operation is shown in Figure 6.
Table 3: LCD driver I/O signal description
Signal
clock
reset

Dir.
in
in

char

in

address

in

enable

in

Function
Clock input, connects to 33.333MHz main clock.
Active high asynchronous reset input. When asserted, the LCD module
is reinitialized and cleared.
8-bit character code to be displayed. The character codes for common
alphanumeric characters are the same as ASCII codes.
7-bit address lines should be supplied together with char signal to
indicate the location. The address is from x"00" ~ x"0F" for first line,
and x"40" ~ x"4F" for second line.
At the ready state, pulse high the signal to display a new character.
char and address signals will be latched by the driver.

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EEE3156: Digital Systems

ready

out

lcd_data
lcd_rs
lcd_rw
lcd_enable

out
out
out
out

Active high status signal indicating that the LCD driver is ready to
accept new character.
LCD modules signals should be connected externally to the LCD
module.

Figure 6: LCD Driver Timing Diagram


To use the driver, after resetting the LCD module by asserting the reset signal, wait until the
ready signal goes high before writing to LCD. Assign desired char and address signals and
assert the enable signal. The driver will proceed to write the character to the LCD module.
For writing the next character, user need to wait until the ready signal goes high again, this
would take about 100s.
You should use the LCD driver as a component in your design without altering the LCD
drivers code. You need to do component declaration at the architecture bodys declarative
part, then instantiate it in the architecture bodys definition part. The 4 LCD modules signals
must be brought out to the top-level module as external output signals. You also need to
assign pins to the Apex device according to Table 4.
Table 4: LCD module pin assignment
Node Name
lcd_data[0]
lcd_data[1]
lcd_data[2]
lcd_data[3]
lcd_data[4]
lcd_data[5]
lcd_data[6]
lcd_data[7]
lcd_enable
lcd_rs
lcd_rw

Location
PIN_U21
PIN_P17
PIN_U1
PIN_U2
PIN_T2
PIN_T3
PIN_U4
PIN_U19
PIN_N15
PIN_W20
PIN_R18

** You must double check to ensure all the pins assigned are correct! Wrong pin
assignment might damage the board after programming.
Tips: To create the design, you might use a counter with enable signal to obtain the address,
and use a lookup table to obtain the display character codes with address signal as input.

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6.

Appendix

LCDdriver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity LCDdriver is
generic(
long_delay:
big_delay:
small_delay:
setup_delay:
);

integer
integer
integer
integer

:=
:=
:=
:=

52000;
2000;
1500;
10

-----

delay needed for long instructions


delay needed for slow instructions
delay needed for fast instructions
initial delay

port(
clock: in std_logic;
reset: in std_logic;
char: in std_logic_vector(7 downto 0);
address: in std_logic_vector(6 downto 0);
enable: in std_logic;
ready : out std_logic;
lcd_data: out std_logic_vector(7 downto 0);
lcd_rs: out std_logic;
lcd_rw: out std_logic;
lcd_enable: out std_logic
);
end entity LCDdriver;
-- Architecture Description
architecture Display of LCDdriver is
type state_type is (initial, display, entrymode, clear, waiting,
verify, putchar, newaddr);
signal state: state_type;
signal char_r: std_logic_vector(7 downto 0);
signal address_r: std_logic_vector(6 downto 0);
subtype charcode is std_logic_vector( 7 downto 0 );
-- Clear screen.
constant CLR:
charcode := "00000001";
-- Display ON, without cursor.
constant DON:
charcode := "00001100";
-- Set Entry Mode to increment cursor automatically after each character
-- is displayed.
constant SEM:
charcode := "00000110";
-- Function set for 8-bit data transfer and 2-line display
constant SET:
charcode := "00111100";
begin
lcd_rw<='0';
process (clock,reset)
variable count: integer range 0 to long_delay;
variable initcount: integer range 0 to big_delay;
begin
if reset = '1' then
--active high reset
state <=initial;
count:=0;
initcount:=0;
elsif rising_edge(clock) then
case state is

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EEE3156: Digital Systems

when initial => -- set SET (initalization step)


if initcount < big_delay then --create delay at beginning
initcount :=initcount + 1;
else
lcd_data <=SET; -- send SET instruction
lcd_rs<='0'; -- instruction mode
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
-- when count = small delay, go onto the next state
if count = small_delay then
state<=display;
count:=0;
else-- else increment the count
count:=count+1;
end if;
end if;
when display => -- to set DISPLAY (initalization step)
lcd_data<=DON;
lcd_rs<='0';
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
if count=small_delay then
state<=clear;
count:=0;
else
count:=count+1;
end if;
when clear => -- clear the screen (initalization step)
lcd_data<=CLR;
lcd_rs<='0';
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
if count = long_delay then
state<=entrymode;
count:=0;
else
count:=count+1;
end if;
when entrymode => -- to set ENTRY MODE (initalization step)
lcd_data<=SEM;
lcd_rs<='0';
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
if count=small_delay then
state<=waiting;
count:=0;
else
count:=count+1;
end if;
when waiting => -- wait enable to go high (i.e. next input coming)
if enable='1' then
state<=verify;

18

EEE3156: Digital Systems

char_r <= char;


address_r <= address;
end if;
when verify => -- wait enable to go low (i.e. current input done)
if enable='0' then
state<=newaddr;
else
char_r <= char;
address_r <= address;
end if;
when newaddr=> --set the cursor to next address
lcd_data <= '1' & address_r; --set new address
lcd_rs<='0'; -- set to instruction mode
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
if count=small_delay then
state<=putchar; -- go to display character
count:=0;
else
count:=count+1;
end if;
when putchar=> -- display the character on the LCD
lcd_data <= char_r; --send msg to LCD
lcd_rs<='1'; -- set to data mode
if count < setup_delay then
lcd_enable <= '1'; -- enable LCD
else
lcd_enable <= '0';
end if;
if count=big_delay then
count:=0;
state<=waiting; -- go back to waiting when done
else
count:=count+1;
end if;
end case;
end if;
end process;
ready <= '1' when state=waiting else '0';
end architecture Display;

19