EEE3156

Chapter 1
Hardware & Software
Aspects of Digital Design

Digital Logic Design

Digital Logic
Binary system: 0 & 1, LOW & HIGH.
Basic building blocks: AND, OR, NOT, NAND, NOR.

Digital Logic Design

Digital Logic Design

Example of Combinational Networks

Representations of Design Entries

Representations of Design Entries

Transistor-level circuit diagrams

Representations of Design Entries

Prepackaged building
blocks,
e.g. multiplexer
Equations:
Z = S A + S B

Representations of Design Entries

VHDL (Very High Speed Integrated Circuit
Hardware Description Language)

Representations of Design Entries

State diagrams
State codes:
S0 = 11
S1 = 10
S2 = 01
S3 = 00

Logic Levels
Undefined region is inherent
in digital, not analog.
amplification, weak => strong.
Switching threshold varies with voltage,
temperature, process.

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Design Flow

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Design Flow
Design idea: Features, performance, power,
etc. are concerned.
Functional specification: Functionally describe
design using high-level language like C.
RTL/logic design: Realize design in RTL level or
logic level with clock-cycle accuracy.

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Design Flow
Layout design: Translate design into VLSI IC
layout.
Silicon tapeout: Send design for IC fabrication.
Verification: Along the design flow, design
description is verified for functionality,
equivalence, circuit performance, power
consumption, etc. at different abstraction
levels and accuracy.
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Design Strategies
IC design productivity depends on the
efficiency with which the design may be
converted from concept to architecture, to
logic and memory, to circuit and hence to a
physical layout.
A good design strategy with a good design
system should provide for consistent
descriptions in various abstraction levels.
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Design Strategies
The role of good design strategies is to reduce
complexity, increase productivity, and assure
working product.
Design is a continuous trade-off to achieve
adequate results for:
Performance - speed, power, function,
flexibility
Size of die (hence cost of die)
Time to design
Ease of test generation and testability
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Level of Abstraction

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Design Abstraction

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Register Transfer Level Design

To specify a large digital system with a state
table is very difficult, if not impossible,
because the number of states would be
prohibitively large.
To overcome this difficulty, digital systems are
designed using modular approach.
The system is partitioned into subsystems,
each of which performs some functional task.
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Register Transfer Level Design

A digital system is represented at the register
transfer level (RTL) when it is specified by the
following three components:
The set of registers in the system.
The operations that are performed on the data
stored in the registers.
The control that supervises the sequence of
operations in the system.
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Register Transfer Level Design

Examples of register transfers:
Add content of R2 to R1
R1 R1 + R2
R3 R3 + 1
Increment R3 by 1 (count up)
R4 shr R4
Shift right R4
R5 0
Clear R5 to 0
The addition is done with a binary parallel
adder, the incrementing with a counter, and
the shift with a shift register.
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Implementation platforms
The programmable logic device families:

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Standard Chips
Standard chips have predefined logic and are
normally easier to manufacture and smaller in
size.
A 7400-series chip

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ASIC
Chips designed for a particular, limited
product or application are called ApplicationSpecific Integrated Circuit.
ASICs generally reduce the total component
and manufacturing cost of a product by
reducing chip count, physical size, and power
consumption, and the often provide higher
performance.
ASICs can be divided into Custom ICs,
Standard-Cell Chip, Gate Arrays and PLDs.
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Custom Chips
Chips that provide the largest number of logic
gates and the highest speed.
Custom chip is created from scratch, and the
designer has full flexibility to decide the size of
the chip, the number of transistors the chip
contains, the placement of each transistor on
the chip, and the way they are connected
together.
A custom chip requires a large amount of
design effort and therefore it is expensive.
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Cell-Based Chips
Some of the design effort incurred for a custom
chip can be avoided by using a technology
known as standard cells.

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Gate Arrays

A sea-of-gates gate array

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Gate Arrays
f1

An example of a logic function in a gate array

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Programmable Logic Devices (PLDs)

There are a few major programmable logic
architecture available today. Each architecture
typically has vendor-specific sub-variants within
each type. The major types include:
Simple Programmable Logic Devices (SPLDs)
Complex Programmable Logic Devices (CPLDs)
Field Programmable Gate Arrays (FPGAs)

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Simple Programmable Logic Device

SPLDs are the smallest and consequently the
least-expensive form of programmable logic.
These were the first chips that could be used
to implement a flexible digital logic design in
hardware.
Other names of this class of device are
Programmable Logic Array (PLA) and
Programmable Array Logic (PAL).
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Programmable Logic Array (PLA)

Based on the idea that logic functions can be
realized in sum-of-product form, a PLA
comprises a collection of AND gates that feeds
a set of OR gates.
As shown in the figure, PLAs inputs x1, xn
pass through a set of buffers (which provide
both the true value and complement of each
input) into a circuit block called an AND plane,
or AND array.
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Programmable Logic Array (PLA)

Gate Level Diagram of a PLA

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Programmable Array Logic (PAL)

Historically, the programmable switches in PLA
presented two difficulties for manufacturers of
these devices:
they were hard to fabricate correctly, and
they reduced the speed-performance of the circuit.

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Programmable Array Logic (PAL)

These drawbacks led to the development of a
similar device in which the AND plane is
programmable, but the OR plane is fixed.
Such a chip is known as a programmable array
logic (PAL) device.
Because they are simpler to manufacture, and
thus less expensive than PLAs, and offer better
performance, PALs have become popular in
practical applications.
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PLA and PAL

PLA

PAL

Customary schematic for PLA and PAL

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Complex Programmable Logic Device

CPLDs are similar to SPLDs except that they
are significantly higher capacity.
A typical CPLD is the equivalent of two to 64
SPLDs.
A CPLD typically contains from tens to a few
hundred macrocells.

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Complex Programmable Logic Device

A section of CPLD

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Complex Programmable Logic Device

Structure of a complex programmable logic device

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Field Programmable Gate Arrays

A field programmable gate array (FPGA) is a
programmable logic device that supports
implementation of relatively large logic
circuits.
FPGAs are quite different from SPLDs and
CPLDs because FPGAs do not contain AND or
OR planes. Instead, FPGAs provide logic blocks
for implementation of the required functions.
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Field Programmable Gate Arrays

It contains three main type of resources: logic
blocks, I/O blocks for connecting to the pins of
the package, and interconnection wires and
switches.
The logic blocks are arranged in a two
dimensional array, and the interconnection
wires are organized as horizontal and vertical
routing channels between rows and columns
of logic blocks.
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Field Programmable Gate Arrays

The routing channels contain wires and
programmable switches that allow the logic
blocks to be interconnected in many ways.
Programmable connections also exist between
the I/O blocks and the interconnection wires.

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Field Programmable Gate Arrays

General structure of a FPGA

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Field Programmable Gate Arrays

The most commonly used logic block is a
lookup table (LUT), which contains storage
cells that are used to implement a small logic
function.
Each cell is capable of holding a single logic
value, either 0 or 1. The stored value is
produced as the output of the storage cell.
LUTs of various sizes may be created, where
the size is defined by the number of inputs.
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Field Programmable Gate Arrays

A two-input lookup table (LUT)

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Field Programmable Gate Arrays

A section of a programmed FPGA

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Computer-Aided Digital Design Tools

To design a logic circuit, a number of
Computer-Aided Design (CAD) tools are
needed.
They are usually packaged together into a CAD
system, which typically includes tools for the
following tasks:
design entry
synthesis and optimization
physical design
simulation
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Design Entry
The starting point of designing a logic circuit is
to describe what the circuit suppose to do and
the formulation of its general structure into a
CAD system, which is called design entry.
There are three design entry methods using:
truth tables
schematic capture (schematic diagram)
source code in hardware description language
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Synthesis and Optimization

Synthesis is a process of generating a logic
circuit from the description of design entry.
If truth tables are used for design entry, then
the synthesis tools generate expressions for
the logic functions represented by the truth
tables.
For schematic capture case, the synthesis
tools produce a set of logic equations
representing the circuit from the schematic
diagram.
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Synthesis and Optimization

When VHDL source code is used, a set of logic
expressions that describe the logic functions
needed to realize the circuit is produced.
Synthesis CAD tools perform this process
automatically.
However, the synthesis tools also handle many
other tasks like translating, or compiling,
VHDL code into a network of logic gates.
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Synthesis and Optimization

Initial logic expressions produced by the
synthesis tools are not likely to be in an
optimal form.
It is difficult for user to manually produce
optimal results, especially for large circuits.
Hence, one of the most important tasks of the
synthesis tools is to manipulate the users
design to automatically produce an equivalent
but better circuit. This step is called logic
synthesis, or logic optimization.
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Physical Design
This task decides how each logic function,
represented by an expression, should be
implemented using whatever physical
resources that are available in the technology
and be realized into a specific hardware form.
It involves two steps called technology
mapping, followed by layout synthesis, or
physical design.
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Simulation
Once the design entry and synthesis are
completed, it is useful to verify that the designed
circuit functions as expected.
To perform this task, the simulator requires two
types of information:
the users initial design which is represented by the
logic equations generated during synthesis.
The user specifies valuations of the circuits inputs
that should be applied to these equations during
simulation.
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Simulation
For each valuation, the simulator evaluates
the outputs produced by the equations. The
output of the simulation is provided either in
truth-table form or as timing diagram.
Then the user examines this output to verify
that the circuit operates as required.
Time needed for the signals to propagate
through the logic gates is assumed negligible.
For accurate timing details, timing simulator
can be applied.
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